Bonding apparatus, bonding method, and method for manufacturing semiconductor device

Abstract

The improved performance bonding apparatus of the embodiments includes a first and second stage, a first gauge, a stress generator, and a controller. The first gauge is capable of gauging an alignment mark disposed on a first substrate held by the first stage. The stress generator is capable of applying a stress to the first stage. The controller performs a bonding process. The bonding process includes an alignment process for each of the first and second substrates. The controller generates a focus map for each amount of deformation of the first stage based on the amount of deformation of the first stage by the stress generator and a shape of the first substrate held by the first stage after deformation. The controller uses a focus setting based on the focus map corresponding to the amount of deformation applied to the first stage when the first gauge gauges the alignment mark disposed on the first substrate held by the first stage in the alignment process for the first substrate.

Description

[0001] Citation of relevant applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2022-96807, filed on June 15, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The embodiments relate to bonding apparatus, bonding method, and method of manufacturing semiconductor device. Background Technology

[0004] Three-dimensional stacking technology is known to be used to stack semiconductor circuit substrates in three dimensions. Summary of the Invention

[0005] One implementation improves the performance of the coupling device.

[0006] The bonding apparatus of this embodiment includes a first worktable, a second worktable, a first measuring instrument, a second measuring instrument, a stress generator, and a controller. The first worktable is capable of holding a first substrate. The second worktable is disposed opposite to the first worktable and is capable of holding a second substrate. The first measuring instrument is capable of measuring alignment marks disposed on the first substrate held on the first worktable. The second measuring instrument is capable of measuring alignment marks disposed on the second substrate held on the second worktable. The stress generator is capable of applying stress to the first worktable. The controller performs a bonding process. The bonding process includes respective alignment processes for the first and second substrates, bonding the first and second substrates together. The controller generates a focus map for each deformation of the first worktable based on the deformation amount of the first worktable after deformation by the stress generator and the shape of the first substrate held on the deformed first worktable. In the alignment process of the first substrate, when the first measuring instrument measures the alignment marks disposed on the first substrate held on the first worktable, the controller uses a focus setting based on the focus map, which corresponds to the deformation amount applied to the first worktable.

[0007] Based on the above configuration, the performance of the joining device can be improved. Attached Figure Description

[0008] Figure 1 It is a schematic diagram showing the outline of the manufacturing process of a semiconductor device.

[0009] Figure 2 This is a schematic diagram illustrating an example of the configuration of alignment marks on a wafer used in the manufacturing process of a semiconductor device.

[0010] Figure 3 This is a schematic diagram showing an example of the shape of alignment marks disposed on a chip and the signal waveform.

[0011] Figure 4 This is a block diagram illustrating an example of the configuration of the coupling device in the first embodiment.

[0012] Figure 5 This is a schematic diagram illustrating an example of the joining process of the joining device according to the first embodiment.

[0013] Figure 6 This is a flowchart illustrating an example of a method for manufacturing a deformable model used in the joining device of the first embodiment.

[0014] Figure 7 This is a schematic diagram illustrating a specific example of a method for manufacturing a deformable model used in the joining device of the first embodiment.

[0015] Figure 8 This is a flowchart detailing an example of the alignment process of the lower wafer (LW) included in the bonding process of the bonding apparatus of the first embodiment.

[0016] Figure 9 This is a schematic diagram illustrating a specific example of a method for measuring alignment marks in the alignment process of the lower wafer (LW) included in the bonding process of the bonding apparatus of the first embodiment.

[0017] Figure 10 This is a flowchart illustrating a modified example of a method for manufacturing a modified model used in the joining device of the first embodiment.

[0018] Figure 11 This is a schematic diagram illustrating an example of the relationship between the optical axis and the signal waveform during alignment processing.

[0019] Figure 12 This is a schematic diagram illustrating an example of the detailed configuration of the camera included in the coupling device of the second embodiment.

[0020] Figure 13 This is a flowchart illustrating an example of a method for manufacturing a deformable model used in the joining device of the second embodiment.

[0021] Figure 14 This is a schematic diagram illustrating a specific example of a method for measuring alignment marks in the alignment process of the lower wafer included in the bonding process of the bonding apparatus of the second embodiment.

[0022] Figure 15 This is a flowchart illustrating an example of the joining process of the joining device in the second embodiment.

[0023] Figure 16 This is a schematic diagram illustrating an example of a measured image of the alignment marks of the lower wafer in the bonding apparatus of the second embodiment, and a patterned signal waveform.

[0024] Figure 17 This is a block diagram illustrating an example of the configuration of a memory device according to the third embodiment.

[0025] Figure 18 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array provided in the memory device of the third embodiment.

[0026] Figure 19 This is a perspective view showing an example of the structure of the memory device according to the third embodiment.

[0027] Figure 20 This is a top view showing an example of the planar layout of the memory cell array provided by the memory device of the third embodiment.

[0028] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device of the third embodiment.

[0029] Figure 22 This is an example of the cross-sectional structure of the memory pillars of the memory device according to the third embodiment, along... Figure 21 A cross-sectional view of the XXII-XXII line.

[0030] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the third embodiment. Detailed Implementation

[0031] Hereinafter, embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual. The dimensions, scales, etc., of each drawing are not necessarily the same as reality. Construction details are appropriately omitted. The shading added to the drawings is not necessarily related to the raw materials or characteristics of the constituent elements. In this specification, constituent elements having substantially the same function and construction are given the same reference numerals. Numbers, etc., attached to the reference numerals are referred to by the same reference numerals and are used to distinguish similar elements from each other.

[0032] The semiconductor device described in this specification is formed by bonding two semiconductor circuit substrates, each having semiconductor circuits formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. Hereinafter, the semiconductor circuit substrate is referred to as a "wafer." The apparatus for performing the exposure process is referred to as an "exposure apparatus." The process of bonding two wafers is referred to as a "bonding process." The apparatus for performing the bonding process is referred to as a "bonding apparatus." During the bonding process, the wafer positioned on the upper side is referred to as the "upper wafer UW." During the bonding process, the wafer positioned on the lower side is referred to as the "lower wafer LW." The group of the two bonded wafers, namely the upper wafer UW and the lower wafer LW, is referred to as the "bonded wafer BW." In this specification, the "surface of the wafer (front side)" corresponds to the surface side of the wafer, corresponding to the side on which the semiconductor circuits are formed by the preceding process described later. The "back side of the wafer" corresponds to the side opposite to the surface of the wafer. The X and Y directions are intersecting directions, parallel to the surface of the wafer (horizontal direction). The Z direction is a direction intersecting both the X and Y directions, vertically perpendicular to the surface of the wafer (vertical direction). In this specification, "up and down" is defined based on the direction along the Z-direction.

[0033] [0] Overview of Semiconductor Device Manufacturing Methods

[0034] Figure 1 This is a schematic diagram illustrating an outline of a semiconductor device manufacturing process. See below for reference. Figure 1 The general process flow of the semiconductor device manufacturing method described in this specification is explained.

[0035] First, the wafers are allocated into lots (“lot allocation”). A lot can contain multiple wafers. For example, lots may be classified as containing upper wafers (UW) and lower wafers (LW). Then, pre-processing is performed on the lots containing upper wafers (UW) and the lots containing lower wafers (LW) respectively, forming semiconductor circuits on the upper wafers (UW) and the lower wafers (LW). Pre-processing includes a combination of “exposure processing”, “overlay (alignment control) measurement”, and “processing”.

[0036] Exposure processing, for example, involves irradiating a resist-coated wafer with light that has passed through the mask, thereby transferring the mask pattern onto the wafer. The area where the mask pattern is transferred through a single exposure corresponds to an "exposure zone (shot)". An "exposure zone (shot)" corresponds to a defined area in the exposure processing. During exposure processing, exposures of the exposure zone (shot) are repeated with staggered exposure positions. That is, the exposure processing is performed in a step-and-repeat manner. The layout of multiple exposure zones (shots) in the upper wafer (UW) and the lower wafer (LW) is set identically.

[0037] Furthermore, during the exposure process, the configuration and shape of each exposure area (shot) can be corrected based on the measurement results of the alignment marks (described later) and various correction values. As a result, the overlap position of the pattern formed during the exposure process and the pattern formed on the wafer substrate is adjusted (aligned). Hereinafter, the correction value used for alignment at the overlap position, i.e., the control parameter used to suppress overlap offset, will be referred to as the "alignment correction value." The alignment correction value can be represented by a combination of various components, including offset (displacement) components in the X and Y directions, magnification components, orthogonality components, etc. In this specification, the overlap offset component of the magnification component generated within the wafer plane will be referred to as the "wafer magnification."

[0038] Exposure OL measurement is a process that measures the overlap offset between the pattern formed by the exposure process and the pattern on the substrate that becomes the exposure process. The overlap offset measurement results obtained by exposure OL measurement can be used to determine the rework of the exposure process and / or to calculate alignment correction values ​​for subsequent batches. Processing is the process of processing (e.g., etching) the wafer using a mask formed by the exposure process. Once processing is complete, the mask used is removed, and the next process is performed.

[0039] Once the preprocessing steps for the associated upper wafer (UW) and lower wafer (LW) batches are completed, a bonding process is performed. In this bonding process, the bonding apparatus positions the surfaces of the upper wafer (UW) and the lower wafer (LW) opposite each other. Furthermore, the bonding process adjusts the overlap position of the patterns formed on the surfaces of the upper wafer (UW) and the lower wafer (LW). Then, the bonding apparatus bonds the surfaces of the upper wafer (UW) and the lower wafer (LW) together to form a bonded wafer (BW).

[0040] Overlay (alignment control) measurement is performed on the bonded wafers (BWs) formed through the bonding process. Overlay OL measurement is a process that measures the overlap offset between the pattern formed on the surface of the upper wafer (UW) and the pattern formed on the surface of the lower wafer (LW). The overlap offset measurement results obtained through overlay OL measurement can be used for calculating alignment correction values ​​applied in subsequent batch exposure processes. The measurement results of alignment marks formed on the wafer are used in the alignment of the exposure apparatus and bonding apparatus at the overlap position during the exposure and bonding processes.

[0041] Figure 2 This is a schematic diagram illustrating an example of the configuration of alignment marks AM on the lower wafer (LW) used in a semiconductor device manufacturing process. Additionally, although the diagram is omitted, the configuration of alignment marks AM on the upper wafer (UW) is, for example, the same as that on the lower wafer (LW). Figure 2 As shown, during the bonding process, the bonding apparatus measures alignment marks AM_C, AM_L, and AM_R at at least three points respectively disposed on the lower wafer LW and the upper wafer UW.

[0042] Alignment mark AM_C is positioned near the center of the wafer. The bonding device, for example, can adjust the overlap of the shift components based on the measurement results of the alignment marks AM_C for the lower wafer (LW) and upper wafer (UW). Alignment marks AM_L and AM_R are positioned on one and the other side of the outer periphery of the wafer, respectively. The bonding device, for example, can adjust the overlap of the rotational components (orthogonality components common in the X and Y directions) based on the measurement results of the alignment marks AM_L and AM_R for the lower wafer (LW) and upper wafer (UW). Furthermore, the bonding device can have the function of deforming the stage holding the wafer. By holding the wafer on the deformed stage, the bonding device can correct the wafer magnification. The bonding device can, for example, use the alignment correction value of the wafer magnification used in the exposure process, or the value of the wafer magnification calculated based on the measurement results of exposure OL, as the correction value for the wafer magnification. In this way, the bonding device can correct the overlap misalignment in the bonding surface (surface) of the lower wafer (LW) and upper wafer (UW).

[0043] Figure 3 This is a schematic diagram illustrating an example of the configuration of alignment marks AM disposed on a chip and the signal waveform. Figure 3 (A) shows an example of the configuration of the alignment mark AM. Figure 3As shown in (A), the alignment mark AM includes, for example, patterns AP1 to AP4. Patterns AP1 and AP2 each have portions extending along the Y direction and are arranged along the X direction. Patterns AP3 and AP4 each have portions extending along the X direction and are arranged along the Y direction. For example, the X-direction coordinates of the alignment mark AM are calculated based on the measurement results of patterns AP1 and AP2, and the Y-direction coordinates of the alignment mark AM are calculated based on the measurement results of patterns AP3 and AP4.

[0044] Figure 3 (B) indicates along Figure 3 The signal waveform in the X direction of alignment mark AM shown in (A) includes the measurement results of patterns AP1 and AP2. Figure 3 As shown in (B), the signal waveform includes signal SP1 corresponding to pattern AP1 and signal SP2 corresponding to pattern AP2. Each signal SP can be identified by detecting the edge portion of the signal waveform, etc. In this example, the signal strength of signals SP1 and SP2 is higher than that of the other portions. The X coordinate of the alignment mark AM is, for example, the coordinate corresponding to the middle of the centroid portion of each of signals SP1 and SP2. Similarly, the Y coordinate of the alignment mark AM can be calculated using patterns AP3 and AP4. In addition, the configuration of the alignment mark AM can be other than other configurations, and the method for calculating the position of the alignment mark AM can also be other calculation methods.

[0045] [1] First implementation method

[0046] In the bonding apparatus 1 of the first embodiment, the focus setting during alignment is changed based on the deformation of the stage holding the lower wafer LW during the bonding process. The details of the bonding apparatus 1 of the first embodiment will be described below.

[0047] [1-1] Composition

[0048] Figure 4 This is a block diagram illustrating an example of the configuration of the coupling device 1 in the first embodiment. For example... Figure 4 As shown, the joining device 1 includes, for example, a control device 10, a storage device 11, a conveying device 12, a communication device 13, and a joining unit 14.

[0049] The control device 10 is a computer or similar device that controls the overall operation of the coupling device 1. The control device 10 controls the storage device 11, the transport device 12, the communication device 13, and the coupling unit 14. Although not shown in the figures, the control device 10 includes a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). The CPU is a processor that executes various programs related to the control of the coupling device. The ROM is a non-volatile storage medium that stores the control programs for the coupling device. The RAM is a volatile storage medium that serves as the operating area for the CPU. The control device 10 can also be referred to as a "controller".

[0050] Storage device 11 is a storage medium for storing data, programs, etc. Storage device 11 may store, for example, a bonding process (recipe) 110 and a deformation model 111. The bonding process 110 is a table recording the settings for the bonding process. The bonding process 110 is prepared for each processing step and batch. The bonding process settings include information about the alignment mark AM used, the focus setting during the measurement of the alignment mark AM, etc. The focus setting is applied to the control of the camera used for alignment. The deformation model 111 contains information for estimating the optimal focus BF when measuring the alignment mark AM of the lower wafer LW based on the deformation amount of the lower stage 140 (described later). Although not shown in the figure, storage device 11 can store multiple deformation models 111 associated with alignment correction values. Details about the deformation model 111 will be described later. Alternatively, storage device 11 may also be included in control device 10.

[0051] The transport device 12 is an apparatus equipped with a transport arm capable of transporting wafers, a transfer device for temporarily holding multiple wafers, and the like. For example, the transport device 12 transports the upper wafer UW and lower wafer LW received from the preprocessing unit of the bonding process to the bonding unit 14. Furthermore, after the bonding process, the transport device 12 transports the bonding wafer BW received from the bonding unit 14 to the outside of the bonding apparatus 1. The transport device 12 may also be equipped with a mechanism for reversing the wafer's orientation.

[0052] The communication device 13 is a communication interface that can connect to the network NW. The bonding device 1 can operate based on the control of the terminal on the network NW, or it can have the server on the network store the action log, or it can perform bonding processing based on the information stored in the server.

[0053] The joining unit 14 is a collection of components used in the joining process. The joining unit 14 includes, for example, a lower worktable 140, a stress device 141, a camera 142, an upper worktable 143, a pressing pin 144, and a camera 145.

[0054] The lower stage 140 has the function of holding the lower wafer LW. The lower stage 140 includes, for example, a wafer chuck that holds the wafer by vacuum adsorption. The lower stage 140 is configured, for example, to be able to move horizontally based on a measurement result of the position of the lower stage 140 measured by a laser interferometer. The stress device 141 has the function of applying stress to the lower stage 140, thereby deforming the lower wafer LW via the lower stage 140. The amount of scaling of the lower wafer LW held on the lower stage 140 varies depending on the amount of deformation of the lower stage 140 caused by the stress device 141. Specifically, the lower stage 140 adsorbs the lower wafer LW, causing the outer periphery of the lower wafer LW to fall onto the lower stage 140 and be held. Thus, the lower wafer LW adsorbed on the lower stage 140 extends (deforms) along the shape of the deformed lower stage 140. Moreover, the amount of extension (i.e., scaling) of the lower wafer LW varies depending on the amount of deformation of the lower stage 140. Camera 142 is positioned on the lower stage 140 and is a photographing mechanism used for measuring the alignment mark AM on the upper wafer UW.

[0055] The upper stage 143 has the function of holding the upper wafer UW. The upper stage 143 includes, for example, a wafer chuck that holds the wafer by vacuum suction. Furthermore, the upper stage 143 is configured to be positioned above the lower stage 140 and is movable in the vertical direction. The lower stage 140 and the upper stage 143 are configured to allow the lower wafer LW held on the lower stage 140 to be positioned opposite the upper wafer UW held on the upper stage 143. The pressing pin 144 is driven vertically based on the control of the control device 10 and is capable of pressing a pin on the upper surface of the center portion of the upper wafer UW held on the upper stage 143. The camera 145 is disposed on the side of the upper stage 143 and is an imaging mechanism for measuring the alignment mark AM of the lower wafer LW.

[0056] Furthermore, the process of deforming and holding the lower wafer LW on the lower worktable 140 can be achieved either by adsorbing the lower wafer LW after the lower worktable 140 has deformed, or by deforming the lower worktable 140 after the lower wafer LW has been adsorbed. The upper worktable 143 may also have the same mechanism for deforming and holding the wafer as the lower worktable 140.

[0057] exist Figure 4 In this context, the lower and upper surfaces of the lower wafer LW, held on the lower stage 140, correspond to the back surface and the front surface of the lower wafer LW, respectively. Figure 4In this assembly, the lower and upper surfaces of the upper wafer UW held on the upper stage 143 correspond to the front and back surfaces of the upper wafer UW, respectively. The bonding device 1 adjusts (aligns) the overlap of the displacement and rotation components by adjusting the relative positions of the lower stage 140 and the upper stage 143. Furthermore, the bonding device 1 adjusts (corrects) the wafer magnification of the lower wafer LW held on the deformed lower stage 140 by deforming the lower stage 140 using the stress device 141.

[0058] Additionally, the joining device 1 may also include a vacuum pump used in vacuum adsorption performed by the lower worktable 140 and the upper worktable 143. The stress device 141 may also be referred to as a "stress generator". The camera 142 may also be referred to as an alignment sensor having the function of measuring the position of the upper worktable 143. The camera 145 may also be referred to as an alignment sensor having the function of measuring the position of the lower worktable 140. Cameras 142 and 145 may each have a moving part that is driven and adjusts the focus along the vertical (optical axis) direction.

[0059] Furthermore, the aforementioned "pretreatment apparatus for bonding processing" is an apparatus that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and the lower wafer LW in a manner suitable for bonding before the bonding process. In short, the pretreatment apparatus first performs plasma treatment on the surfaces of the upper wafer UW and the lower wafer LW to modify their surfaces. During plasma treatment, oxygen ions or nitrogen ions are generated based on oxygen or nitrogen as the treatment gas under a specified reduced pressure atmosphere, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. Afterward, the pretreatment apparatus supplies pure water to the surfaces of the upper wafer UW and the lower wafer LW. Then, hydroxyl groups are attached to the surfaces of the upper wafer UW and the lower wafer LW to hydrophilize them. In the bonding process, the upper wafer UW and the lower wafer LW, having undergone this surface modification and hydrophilization, are used. The bonding apparatus 1 can also be combined with the pretreatment apparatus to form a bonding system.

[0060] [1-2] Manufacturing methods for semiconductor devices

[0061] Hereinafter, an example of a specific process using the bonding device 1 will be described as a method for manufacturing a semiconductor device according to the first embodiment. That is, the semiconductor device is manufactured using the bonding method (bonding process) of the first embodiment described below.

[0062] [1-2-1] Overview of the jointing process

[0063] Figure 5 This is a schematic diagram showing the outline of the joining process of the joining device 1 in the first embodiment. Figure 5(A) to (H) show the states of the joining unit 14 during the joining process. Hereinafter, refer to... Figure 5 A summary of the joining process is provided.

[0064] Figure 5 (A) shows the state of the bonding unit 14 before the bonding process. The bonding device 1 starts the bonding process when it receives the execution instruction for the bonding process and establishes the associated upper wafer UW and lower wafer LW group.

[0065] If the joining process begins, the lower worktable 140 will be deformed. Figure 5 (B): Deformation of the lower worktable). Specifically, the control device 10 controls the stress device 141 based on the alignment correction value, causing the lower worktable 140 to deform. The alignment correction value referenced by the control device 10 can be obtained from an external server or calculated based on an alignment correction value obtained from the exposure device or the server. Furthermore, depending on the alignment correction value, the state can also be as follows: in Figure 5 During the processing of (B), the stress device 141 does not apply stress to the lower worktable 140, and the lower worktable 140 does not deform.

[0066] Next, the UW chip is loaded ( Figure 5 (C): Upper wafer loading. Specifically, the control device 10 causes the transport device 12 to transport the upper wafer UW to the upper worktable 143. Moreover, the control device 10 holds the upper wafer UW on the upper worktable 143 by vacuum adsorption. In addition, the surface of the upper wafer UW loaded onto the bonding device 1 is modified and hydrophilized by a pretreatment device.

[0067] Next, the alignment process of the upper wafer UW is performed. Figure 5 (D): Upper wafer alignment). Specifically, the control device 10 uses the camera 142 to measure the alignment marks AM_C, AM_L and AM_R on the upper wafer UW, and calculates the coordinates of these alignment marks AM.

[0068] Next, the lower chip LW is loaded ( Figure 5 (E): Lower wafer loading. Specifically, the control device 10 causes the transport device 12 to transport the lower wafer LW to the lower worktable 140. Furthermore, the control device 10 holds the lower wafer LW on the lower worktable 140 by vacuum suction. At this time, when the stress device 141 does not apply stress to the lower worktable 140, the lower wafer LW is held on the lower worktable 140 in a flat state. On the other hand, when the stress device 141 applies stress to the lower worktable 140, the lower wafer LW deforms along the shape of the lower worktable 140 after being deformed by the stress device 141. Additionally, the surface of the lower wafer LW loaded into the bonding device 1 is modified and hydrophilized by a pretreatment device.

[0069] Next, the alignment process for the lower wafer (LW) will be performed. Figure 5 (F): Lower wafer alignment). Specifically, the control device 10 uses the camera 145 to measure the alignment marks AM_C, AM_L, and AM_R of the lower wafer LW, and calculates the coordinates of these alignment marks AM. When measuring the alignment marks AM_C, AM_L, and AM_R of the lower wafer LW, a pre-made deformable model 111 is used.

[0070] Next, perform origin alignment for cameras 142 and 145. Figure 5 (G): Camera origin alignment). Specifically, the control device 10 controls the positions of the lower worktable 140 and the upper worktable 143, and inserts a common target 146 between the optical axes of camera 142 and camera 145. Then, based on the measurement results of cameras 142 and 145 on the common target 236, the control device 10 aligns the origins of cameras 142 and 145.

[0071] Next, the joining sequence is executed ( Figure 5 (H): Joining sequence). Specifically, firstly, the control device 10 adjusts the relative position of the lower stage 140 and the upper stage 143 based on the alignment results of the upper wafer UW and the lower wafer LW, as well as the alignment results of the origins of cameras 142 and 145. Then, the control device 10 moves the position of the upper stage 143 closer to the lower stage 140 and adjusts the spacing between the upper wafer UW and the lower wafer LW. Then, the control device 10 presses the center of the upper wafer UW by lowering the pressing pin 144, so that the surface of the upper wafer UW contacts the surface of the lower wafer LW.

[0072] Subsequently, the control device 10 releases the upper stage 143 from holding the upper wafer UW (vacuum adsorption) from the inside out. The upper wafer UW then falls onto the lower wafer LW, and the surfaces of the upper wafer UW and lower wafer LW are bonded. Specifically, van der Waals forces (intermolecular forces) are generated between the bonding surfaces of the modified upper wafer UW and the modified lower wafer LW, bonding the contact portions of the upper wafer UW and lower wafer LW. Then, because the bonding surfaces of the upper wafer UW and lower wafer LW are hydrophilized, hydrogen bonds are formed between the hydrophilic groups at the contact portions of the upper wafer UW and lower wafer LW, resulting in a more stable bond between the contact portions of the upper wafer UW and lower wafer LW.

[0073] [1-2-2] How to make deformable model 111

[0074] Figure 6 This is a flowchart illustrating an example of a method for manufacturing the deformed model 111 used in the joining device of the first embodiment. Hereinafter, refer to... Figure 6 The process of manufacturing the deformable model 111 in the joining device 1 of the first embodiment will be described.

[0075] First, a wafer with alignment mark AM is prepared (S101). The structure of the wafer prepared in S101, including the portion with alignment mark AM, is the same as that of the lower wafer LW during the bonding process. That is, in the process of S101, it is preferable to prepare a wafer that will be used as the object for manufacturing the deformable model 111. As the object for manufacturing the deformable model 111, any wafer that can be deformed by the bonding device 1 during the bonding process can be used, and it can be either the upper wafer UW or the lower wafer LW.

[0076] Next, the control device 10 confirms the bonding process 110 (S102). The bonding process 110 during the fabrication of the deformed model 111 includes: information on the coordinates of multiple alignment marks AM in the wafer prepared in S101 and the setting of the deformation amount of the lower stage 140.

[0077] Next, the control device 10 deforms the lower worktable 140 by the m-th deformation amount (S103). "m" is an integer greater than or equal to 2. "m" is, for example, used as... Figure 6 The initial values ​​for the series of processes shown are set to "1". The control device 10 applies the m-th deformation amount to the lower worktable 140 by causing the stress device 141 to apply stress corresponding to the m-th deformation amount to the lower worktable 140. In this example, the first deformation amount corresponds to the uncorrected state of the stress device 141. The deformation amount of the wafer is expressed, for example, by the height of the central portion of the wafer, based on the height of the outer periphery. The unit of deformation amount is, for example, micrometers (μm). Furthermore, the deformation amount of the wafer can also be expressed by the magnitude of the stress applied to the wafer by the stress device 141. The unit of stress is, for example, megapascals (MPa).

[0078] Next, the control device 10 loads the wafer (S104). In this example, based on the control of the control device 10, the lower wafer LW is transported to the lower stage 140 and vacuum-adhered to the lower stage 140. At this time, the lower wafer LW is deformed based on the shape of the lower stage 140 after being deformed by the stress device 141. In addition, if the stress device 141 is not corrected, the lower wafer LW is held in a flat state.

[0079] Next, the control device 10 uses the camera 145 to measure the height of multiple points within the wafer surface (S105). In this example, "multiple points" correspond to multiple alignment marks AM, and "height" corresponds to the position of the optimal focal point. Specifically, in the process of S105, the control device 10 controls the horizontal position of the lower stage 140 to align the optical axis of the camera 145 on the upper stage 143 with the position of the alignment marks AM on the lower wafer LW. Moreover, the camera 145 measures each alignment mark AM with a predetermined focal range and a predetermined focal step size. Then, based on the measurement results of the camera 145, the control device 10 determines the optimal focal point (height) for each alignment mark AM.

[0080] Next, the control device 10 unloads the wafer (S106). In this example, the transport device 12 receives the wafer LW after the vacuum adsorption of the lower stage 140 has been released.

[0081] Next, the control device 10 determines whether "m = M" (S107) is satisfied. "M" corresponds to the number of deformable models 111 produced that correspond to the deformation amount of the wafer (i.e., the correction value of the wafer magnification). In addition, the process of S107 can also be described as the process by which the control device 10 determines whether there are any wafer deformation amounts that have not been measured in S105.

[0082] If the condition "m = M" is not met in the S107 process (S107: No), the control device 10 increments "m" (S108) and proceeds to the S103 process. That is, while the deformation amount of the lower stage 140, i.e., the deformation amount of the lower wafer LW adsorbed on the lower stage 140, is changed in the S103 process, the control device 10 executes the S104 and S105 processes. By repeating the S103 to S108 processes, the control device 10 is able to generate information on the optimal focus associated with each deformation amount. In addition, the S108 process can also be described as the process by which the control device 10 selects the setting of the deformation amount of the wafer for which the measurement result of S105 has not been obtained.

[0083] In the processing of S107, if "m = M" is satisfied (S107: Yes), the control device 10, based on the measurement results of S105, creates multiple deformation models 111 that are associated with the settings of multiple deformation amounts respectively (S109). Specifically, the control device 10 creates a deformation model 111 associated with the first deformation amount based on the measurement results of S105 in the first deformation amount. Similarly, the control device 10 creates multiple deformation models 111 that are associated with the second to Mth deformation amounts respectively. In addition, since the deformation model 111 is calculated based on the optimal focal position (height) of each alignment mark AM, it can also be called "focal mapping". The deformation model 111 is calculated, for example, by using the value of the optimal focal point of each alignment mark AM to perform a polynomial approximation.

[0084] Furthermore, for the deformation model 111 corresponding to the deformation amount not measured in the S105 process, the control device 10 can infer it based on the deformation model 111 using a deformation amount value close to that of the deformation model, or it can infer it based on the deformation model 111 with multiple conditions constituting that deformation amount. Moreover, by using the deformation model 111 associated with the deformation amount of the lower stage 140, the control device 10 can calculate the height of the alignment mark AM in the coordinates of the lower wafer LW vacuum-adhered to the lower stage 140. If the S109 process is completed, the control device 10 ends. Figure 6 The series of processes shown.

[0085] (A specific example of how to create Deformation Model 111)

[0086] Figure 7 This is a schematic diagram illustrating a specific example of a method for manufacturing a modified model 111 used in the joining device of the first embodiment. Figure 7 The measured image of the lower wafer (LW) on the lower stage 140, along with the focus setting and optimal focus calculation results, are shown for each deformation amount of the lower stage 140. The first deformation amount when m=1 corresponds to the state where the wafer magnification is uncorrected relative to the lower stage 140. The second deformation amount when m=2 corresponds to the state after the lower stage 140 is deformed by the stress device 141. The third deformation amount when m=3 corresponds to the state after the lower stage 140 is further deformed by the stress device 141 compared to the second deformation amount. Figure 7 The numbers at coordinates (1), (2), and (3) shown correspond to an example of the measurement sequence. Furthermore, coordinates (1), (2), and (3) correspond, for example, to alignment marks AM_C, AM_L, and AM_R, respectively.

[0087] When the deformation of the lower stage 140 is the first deformation (without correction), the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a flat state. That is, the camera 145 on the upper stage 143 photographs the alignment mark AM of the lower wafer LW, which is positioned in a flat state, under conditions based on a predetermined focus setting. In this case, the optimal focus BF, determined based on the measurement of the alignment mark AM at coordinates (1), (2), and (3), can be approximately equal in position (height). Therefore, the deformation model 111 associated with the first deformation can be an approximation that represents approximately equal values ​​regardless of the coordinates.

[0088] When the deformation amount of the lower stage 140 is the second deformation amount, the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a deformed convex shape. That is, the camera 145 on the upper stage 143 takes a picture of the alignment mark AM of the lower wafer LW, which is in a deformed convex shape, based on a predetermined focus setting. In this case, the position of the optimal focus BF in coordinates (1) at the center is higher than the position of the optimal focus BF in coordinates (2) and (3) at the outer periphery. Therefore, the deformation model 111 associated with the second deformation amount can be an approximation in which the value increases as it gets closer to the center of the wafer.

[0089] When the deformation amount of the lower stage 140 is the third deformation amount, the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a state where it is deformed into a convex shape to a greater extent than in the case of the second deformation amount. That is, the camera 145 on the upper stage 143 takes a picture of the alignment mark AM of the lower wafer LW, which is in a state of greater deformation into a convex shape than in the case of the second deformation amount, based on a predetermined focus setting. In this case, the position of the optimal focus BF at coordinates (1), (2), and (3) can be higher than the position of the optimal focus BF at coordinates (1), (2), and (3) in the second deformation amount, respectively. Therefore, the deformation model 111 associated with the third deformation amount can be an approximation in which the value is higher the closer to the center of the wafer compared to the case of the second deformation amount.

[0090] When creating the deformable model 111, it is preferable to set the focal range FR of the alignment mark AM at each of the measured coordinates (1), (2), and (3) to a relatively wide range. The focal range FR corresponds to the range of the position (height) of the alignment mark AM at the measurement point of the alignment mark AM. During the measurement of the alignment mark AM, multiple shots are taken within the focal range FR based on a preset focal step size. The "relatively wide range" described here refers to a focal setting that includes the optimal focal point BF regardless of the deformation amount of the lower stage 140 in each coordinate. By setting the focal range FR to a relatively wide range, it is possible to suppress the remeasurement of the focal point when the optimal focal point BF is not detected within the focal range FR.

[0091] [1-2-3] Alignment process of the lower wafer LW

[0092] Figure 8 This refers to the alignment process of the lower wafer LW included in the bonding process of the bonding apparatus 1 in the first embodiment. Figure 5 A flowchart detailing an example of (F) is provided below. Figure 8 The alignment process of the lower wafer LW in the bonding apparatus 1 of the first embodiment will be described.

[0093] After the alignment process of the lower wafer (LW) in the first embodiment begins, the control device 10 first calculates the focal position (height) of each measurement coordinate based on the deformation model 111 corresponding to the deformation amount of the lower stage 140 (S111). In other words, in the S111 process, the control device 10 selects (uses) the deformation model 111 associated with the correction value of the wafer magnification applied to the lower wafer (LW) to calculate the focal position of each measurement coordinate. Furthermore, in the S111 process, the control device 10 infers (calculates) the optimal focal point based on the deformation model 111 of the lower wafer (LW) in the area where the camera 145 performs focus calibration.

[0094] Next, the control device 10 searches for the optimal focus in coordinates (1) within a narrower focus range than that generated when the deformable model 111 was generated, including the focus position calculated in coordinates (1) during the processing of S111 (S112). The optimal focus in coordinates (1) is determined through the processing of S112.

[0095] Next, the control device 10 measures the alignment mark AM_C by setting the optimal focus determined in S112 (S113).

[0096] Next, the control device 10 searches for the optimal focus in coordinates (2) within a narrower focus range than that generated during the processing of the deformable model 111, including the focus position calculated in coordinates (2) during the processing of S111 (S114). The optimal focus in coordinates (2) is determined through the processing of S114.

[0097] Next, the control device 10 measures the alignment mark AM_L by setting the optimal focus determined in S114 (S115).

[0098] Next, the control device 10 searches for the optimal focus in coordinates (3) within a narrower focus range than that generated when the deformable model 111 was generated, including the focus position calculated in coordinates (3) during the processing of S111. The optimal focus in coordinates (3) is determined through the processing of S116.

[0099] Next, the control device 10 measures the alignment mark AM_L by setting the optimal focus determined in S116 (S117).

[0100] Next, based on the measurement results of S113, S115, and S117, the control device 10 adjusts the position of the lower stage 140 (S118). If the processing of S118 is completed, the control device 10 completes the alignment process of the lower wafer LW and enters the next process in the bonding process.

[0101] Furthermore, in the joining device 1 of the first embodiment, the processing of each of S112 and S113, the processing of S114 and S115, and the processing of S116 and S117 can also be integrated. In addition, the joining device 1 of the first embodiment can determine the focus setting such as the focus range FR and the focus step based at least on the deformation model 111 corresponding to the deformation amount of the lower worktable 140.

[0102] (A specific example of the measurement method for alignment mark AM)

[0103] Figure 9 This is a schematic diagram illustrating a specific example of a method for measuring the alignment mark AM in the alignment process of the lower wafer LW included in the bonding process of the bonding apparatus 1 of the first embodiment. Figure 9 The measurement images, focus settings, and optimal focus calculation results of the lower wafer LW on the lower stage 140 are shown according to each deformation amount of the lower stage 140. The measurement images for the first deformation amount (uncorrected), the second deformation amount, and the third deformation amount are compared with those obtained using... Figure 7 The content is the same. In Figure 9 and Figure 7 The focus settings differ for each deformation quantity.

[0104] like Figure 9 As shown, when the deformation of the lower worktable 140 is the first deformation (without correction), the focal range FR of each measured coordinate is set to include the optimal focal point BF shown by the deformation model 111 corresponding to the first deformation, and is narrower than when the deformation model 111 is generated. Furthermore, in the focal setting associated with the first deformation, the positions of the focal range FR in coordinates (1), (2), and (3) are set to approximately the same height.

[0105] When the deformation of the lower worktable 140 is the second deformation amount, the focal range FR of each measured coordinate is set to include the optimal focal point BF shown by the deformation model 111 corresponding to the second deformation amount, and is narrower than when the deformation model 111 is generated. Furthermore, in the focal setting associated with the second deformation amount, the position of the focal range FR in coordinates (1), (2), and (3) is shifted to a higher position than the focal setting associated with the first deformation amount. Moreover, based on the deformation model 111 associated with the second deformation amount, the position of the focal range FR in coordinate (1) is shifted to a higher position compared to coordinates (2) and (3).

[0106] When the deformation of the lower worktable 140 is the third deformation amount, the focal range FR of each measured coordinate is set to include the optimal focal point BF represented by the deformation model 111 corresponding to the third deformation amount, and is narrower than when the deformation model 111 is generated. Furthermore, in the focal setting associated with the third deformation amount, the position of the focal range FR in coordinates (1), (2), and (3) is set to be shifted to a higher side compared to the focal setting associated with the second deformation amount. Moreover, based on the deformation model 111 associated with the third deformation amount, the position of the focal range FR in coordinate (1) is set to be shifted to a higher side compared to coordinates (2) and (3).

[0107] [1-3] Effects of the first embodiment

[0108] The joining device 1 according to the first embodiment described above can improve the performance of the joining device. Hereinafter, the effects of the first embodiment will be described in detail.

[0109] When confirming the position of the stage holding the wafer, the bonding device 1 measures the alignment mark AM on the wafer. At this time, the bonding device 1 performs focus calibration, for example, by driving the camera 145 body or the lens within the camera 145 up and down. In addition, as a function of the bonding device 1, it is known to have a function of correcting the wafer magnification by deforming the lower stage 140.

[0110] If the wafer magnification is corrected in the bonding apparatus 1, the position of the optimal focus of the alignment mark AM changes due to the deformation of the lower stage 140. As a countermeasure, a wider focus calibration range (focus range) is considered to enable the detection of the optimal focus of the alignment mark AM even when the wafer magnification changes. However, if the focus range is set wider, the measurement time of the alignment mark AM becomes longer, and the productivity of the bonding apparatus decreases.

[0111] Therefore, the bonding apparatus 1 of the first embodiment pre-fabricates a deformation model 111 that correlates the deformation amount of the lower stage 140 with the trend within the wafer surface at the optimal focal position of the lower wafer LW. Furthermore, the bonding apparatus 1 performs alignment processing of the lower wafer LW using the focal setting based on the deformation amount of the lower stage 140 and the deformation model 111 of the wafer. For example, the bonding apparatus 1 predicts the optimal focal position of the measured coordinates in advance based on the deformation amount of the lower stage 140, thereby enabling a narrower focal range during alignment processing compared to the focal range during calibration.

[0112] As a result, the bonding device 1 of the first embodiment can shorten the measurement time of the alignment mark AM and improve the productivity of the bonding device 1. That is, the bonding device 1 of the first embodiment can improve the performance of the bonding device.

[0113] Furthermore, the joining device 1 of the first embodiment can also set a narrower focus range FR and a more refined focus step size than when the deformable model 111 was manufactured. With a more refined focus step size, the measurement time for the alignment mark AM increases with the number of shots taken by the camera 145. On the other hand, by refining the focus step size, the detection accuracy of the optimal focus position can be improved. In other words, in the focus setting based on the deformable model 111, the joining device 1 of the first embodiment can adjust the balance between productivity and focus accuracy by allowing the user to select the focus range FR and the focus step size.

[0114] [1-4] Variations of the first embodiment

[0115] In use Figure 6 In the manufacturing method of the deformable model 111 described herein, the process of reloading the wafer can be omitted when changing the deformation amount of the lower worktable 140. Figure 10 This is a flowchart illustrating a modified example of the method for manufacturing the modified model 111 used in the coupling device 1 of the first embodiment. Hereinafter, refer to... Figure 10 The process of manufacturing the modified model 111 in the modified example of the first embodiment will be described.

[0116] First, prepare a wafer with alignment mark AM (S101). Next, confirm bonding process 110 (S102). Next, load the wafer (S104). Next, deform the lower stage 140 by the m-th deformation amount (S103). Next, use camera 145 to measure the height of multiple points within the wafer surface (S105). Next, determine whether "m = M" is satisfied (S107).

[0117] If the condition “m = M” is not met in the process of S107 (S107: No), “m” is incremented (S108), and the processes of S103 and S105 are executed. That is, while the wafer is vacuum-adsorbed on the lower stage 140, the deformation of the lower stage 140 is changed, and the height of multiple points on the wafer surface is measured.

[0118] If the condition "m = M" is met in process S107 (S107: Yes), the wafer is unloaded (S106). Then, based on the measurement results of S105, a deformed model 111 of the wafer is created, which is associated with the deformation amount of the lower stage 140 (S109). If process S109 is completed, the process ends. Figure 10 The series of processes shown.

[0119] As explained above, the order of processes used to create the deformable model 111 can be changed, or some processes can be omitted. In this case, the joining device 1 can also create the deformable model 111 in the same way as in the first embodiment.

[0120] [2] Second implementation method

[0121] In the second embodiment of the bonding apparatus 1, during the alignment process of the lower wafer (LW) during the bonding process, the optical axis setting of the camera 145 is changed based on the deformation amount and measured coordinates of the lower stage 140. The details of the bonding apparatus 1 of the second embodiment will be described below.

[0122] [2-1] On the relationship between the optical axis and the signal waveform during alignment processing

[0123] Figure 11 It is a schematic diagram showing the relationship between the optical axis and the signal waveform during alignment processing. Figure 11 The measured images of the lower wafer LW and the signal waveform of pattern AP on the lower worktable 140 are shown in the case of no deformation on the lower worktable 140 and the case of deformation on the lower worktable 140, respectively. Figure 11 The coordinates (1), (2), and (3) shown correspond, for example, to alignment marks AM_C, AM_L, and AM_R, respectively. In the signal waveform, "DF" corresponds to the defocused case, and "BF" corresponds to the optimal focus.

[0124] With the lower stage 140 remaining undeformed, the lower wafer LW, vacuum-adsorbed onto the lower stage 140, is held in a flat state. In this case, the optical axis of the camera 145 on the upper stage 143 is tilted perpendicular to the surface of the lower wafer LW. In this case, the signal waveform of a pattern AP is symmetrical in any of the alignment marks AM_C, AM_L, and AM_R. With the signal waveform symmetrical, changes in the center of gravity of the signal waveform can be suppressed even when defocusing in either the positive or negative direction. Therefore, the control device 10 can detect the optimal focus BF based on the signal strength.

[0125] On the other hand, when the lower stage 140 is deformed, the lower wafer LW, which is vacuum-adsorbed onto the lower stage 140, is held in a state where it is deformed into a convex shape along the lower stage 140. In this case, the angle formed by the optical axis of the camera 145 of the upper stage 143 and the surface of the lower wafer LW is further away from the center portion of the lower wafer LW (coordinate (1)) and further away from a right angle. Therefore, in the measurement of the alignment mark AM_L in coordinate (2) and the measurement of the alignment mark AM_R in coordinate (3), the alignment mark AM is measured from the tilt direction. As a result, the signal waveforms of the alignment marks AM_L and AM_R can become asymmetrical.

[0126] If the signal waveform is asymmetrical, the detection accuracy of the alignment mark AM deteriorates. Specifically, between the defocus DFp in the positive direction and the defocus DFm in the negative direction, the centroid position of the signal waveform of a pattern AP changes in opposite directions. As a result, the control device 10 is more likely to misdetect the peak value of the signal waveform, and the coordinates of the alignment mark AM calculated based on the measurement results may be offset. Therefore, the joining device 1 of the second embodiment has the function of adjusting the optical axis of the camera 145 according to each measured coordinate.

[0127] [2-2] Composition of Camera 145

[0128] Figure 12 This is a schematic diagram illustrating an example of the detailed configuration of the camera 145 included in the coupling device 1 of the second embodiment. Figure 12 The alignment mark AM of the lower wafer LW, which is the object of measurement for camera 145, is also shown. For example... Figure 12 As shown, the camera 145 includes, for example, a light source 150, an optical element 151, a lens unit 152, a support 153, and a light-receiving part 154.

[0129] Light source 150 is a semiconductor element capable of emitting laser light. Hereinafter, the laser light emitted by light source 150 is also referred to as emitted light EL. Camera 145 may have multiple light sources, and the wavelength of emitted light EL may be differentiated according to the configuration of the object being measured (alignment mark AM).

[0130] Optical element 151 is, for example, a semi-reflective mirror. Optical element 151 reflects the laser light (emitted light EL) emitted from light source 150 toward lens unit 152. In addition, optical element 151 allows laser light passing through lens unit 152 to pass through.

[0131] Lens unit 152 is an optical system that guides emitted light EL to the object being measured (e.g., the lower wafer LW). Lens unit 152 guides the reflected light RL, after the emitted light EL illuminating the lower wafer LW is reflected by the surface of the lower wafer LW, to the light-receiving part 154 via optical element 151. The optical axis of lens unit 152 corresponds to the optical axis of camera 145.

[0132] The support portion 153 supports the lens unit 152 and has a mechanism for adjusting the tilt of the optical axis of the lens unit 152. In addition, in the camera 145, the relative positions of the light source 150, the optical element 151, and the light-receiving portion 154 with respect to the lens unit 152 can also be changed according to the tilt of the optical axis of the lens unit 152 after the support portion 153 is changed.

[0133] The light-receiving part 154 is a sensor capable of detecting the reflected light RL. The light-receiving part 154 is disposed, for example, on the optical axis of the lens unit 152. The light-receiving part 154 only needs to be disposed at a position where the reflected light RL can be detected.

[0134] The other configurations of the coupling device 1 in the second embodiment are the same as those in the first embodiment. Furthermore, the camera 145 can also be configured in other ways. For example, the arrangement of the light source 150 and the light-receiving part 154 in the camera 145 can be interchanged.

[0135] [2-3] Manufacturing methods for semiconductor devices

[0136] Hereinafter, an example of a specific process using the bonding device 1 will be described as a method for manufacturing a semiconductor device according to the second embodiment. That is, a semiconductor device is manufactured using the bonding method (bonding process) of the second embodiment described below. In addition, the general outline of the bonding process in the bonding device 1 of the second embodiment is the same as that of the first embodiment.

[0137] [2-3-1] Method for correcting the optical axis

[0138] Figure 13 This is a flowchart illustrating an example of a method for correcting the optical axis used in the coupling device 1 of the second embodiment. Hereinafter, refer to... Figure 13 The process of the optical axis correction method in the bonding device 1 of the second embodiment will be described.

[0139] First, compared with the first embodiment, Figure 6The fabrication method for the deformable model 111 described herein is the same, and processes S101 to S109 are performed. Specifically, first, a wafer with alignment mark AM is prepared (S101). Next, the bonding process 110 is verified (S102). Next, the lower stage 140 is deformed by the m-th deformation amount (S103). Next, the wafer is loaded (S104). Next, the height of multiple points within the wafer surface is measured using camera 145 (S105). Next, the wafer is unloaded (S106). Next, it is determined whether "m = M" is satisfied (S107). If "m = M" is not satisfied in process S107 (S107: No), "m" is incremented (S108), and process S103 is performed. If "m = M" is satisfied in process S107 (S107: Yes), multiple deformable models 111 are fabricated based on the measurement results of S105 and are associated with the settings of multiple deformation amounts (S109).

[0140] Upon completion of process S109, the control device 10 generates a relationship table of optical axis correction values ​​for each coordinate within the wafer surface using the corresponding deformation model 111, according to the settings of each of the multiple deformation values ​​(S201). The relationship table of optical axis correction values ​​contains information relating the measured coordinates to the optical axis correction values. The optical axis correction values ​​are set such that the optical axis of the camera 145 is perpendicular to the orientation of the lower wafer LW surface calculated based on the deformation model 111 in each measured coordinate. In other words, the optical axis of the camera 145 is set to be orthogonal to the tilt of the lower wafer LW surface in the measured coordinates calculated based on the deformation model 111. The optical axis correction value can be represented by the rotation amount of the lens unit 152 from its default state or by the control parameters of the support portion 153.

[0141] Next, the control device 10 corrects the positional relationship (relative position) between the lower worktable 140 and the camera 145 based on the optical axis correction amount (S202). In the S202 process, the control device 10 adjusts the position of the camera 145 so that the corrected optical axis in each measurement coordinate is aligned with the position of the corresponding alignment mark AM. In other words, the position of the camera 145 is adjusted so that the vertical axis from the surface of the alignment mark AM is aligned with the optical axis of the camera 145. Furthermore, in the S202 process, the correction amount for the positional relationship between the lower worktable 140 and the camera 145 can also be recorded in the relationship table created in S201. After the S202 process is completed, the control device 10 terminates. Figure 13 The series of processes shown.

[0142] (A specific example of the measurement method for alignment mark AM)

[0143] Figure 14This is a schematic diagram illustrating a specific example of a method for measuring the alignment mark AM in the alignment process of the lower wafer LW included in the bonding process of the bonding apparatus 1 of the second embodiment. Figure 14 An example of a corrected image of the optical axis and a corrected image of the positional relationship between the lower stage 140 and the camera 145 is shown. The outlines of the first to third deformation amounts and coordinates (1) to (3) are the same as in the first embodiment. The double-dotted lines shown in the corrected image of the optical axis indicate the tilt of the optical axis in each measured coordinate.

[0144] With the deformation of the lower stage 140 being the first deformation (without correction), the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a flat state. In this case, the tilt of the optical axis of the camera 145 during the measurement of the alignment marks AM of coordinates (1), (2), and (3) is set to be approximately the same (e.g., vertical). At this time, the positional relationship between the lower stage 140 and the camera 145 is controlled such that the coordinates represented by the bonding process 110 are consistent with the actual measurement coordinates.

[0145] When the deformation of the lower stage 140 is the second deformation amount, the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a deformed convex shape. In this case, the tilt of the optical axis of the camera 145 during the measurement of the alignment marks AM at coordinates (2) and (3) is set to tilt outward relative to coordinate (1) (i.e., in the direction in which the reflected light RL leaves the center of the lower wafer LW). At this time, for example, in the measurement of the alignment mark AM_R at coordinate (3), the positional relationship between the lower stage 140 and the camera 145 is controlled to be shifted outward by a length L1 from the coordinates represented by the bonding process 110.

[0146] When the deformation amount of the lower stage 140 is the third deformation amount, the lower wafer LW vacuum-adhered to the lower stage 140 is held in a state where it is deformed into a convex shape to a greater extent than in the case of the second deformation amount. In this case, the tilt of the optical axis of the camera 145 during the measurement of the alignment marks AM at coordinates (2) and (3) is set to be tilted outward relative to coordinate (1) compared to the case of the second deformation amount. At this time, for example, in the measurement of the alignment mark AM_R at coordinate (3), the positional relationship between the lower stage 140 and the camera 145 is controlled to be shifted outward from the coordinates represented by the bonding process 110 by a length L2 greater than the length L1.

[0147] [2-3-2] Alignment process of the lower wafer LW

[0148] Figure 15 This is a flowchart illustrating an example of the alignment process of the lower wafer (LW) included in the bonding process of the bonding apparatus 1 according to the second embodiment. Hereinafter, refer to... Figure 15 The alignment process of the lower wafer LW in the bonding apparatus 1 of the second embodiment will be described.

[0149] If the alignment process of the lower wafer (LW) in the second embodiment begins, the control device 10 first calculates the optical axis correction amount for each measurement coordinate based on the relationship between the optical axis correction amount corresponding to the deformation amount of the lower stage 140 (S211). In other words, in the S211 process, the control device 10 selects (uses) the relationship between the optical axis correction amount established with the correction value of the wafer magnification applied to the lower wafer (LW) and calculates the optical axis correction amount for each measurement coordinate. Through the S211 process, the control device 10 corrects the tilt of the optical axis based on the deformation model 111 of the lower wafer (LW) in the area where the camera 145 performs focus calibration.

[0150] Next, the control device 10 calculates the correction amount of the positional relationship between the lower worktable 140 and the camera 145 in each measurement coordinate based on the calculated optical axis correction amount of each measurement coordinate (S212).

[0151] Next, the control device 10 determines the optical axis and position of the camera 145 based on the optical axis correction amount calculated in coordinate (1) during the processing in S211 and the correction amount of the positional relationship between the lower worktable 140 and the camera 145, and searches for the optimal focus in coordinate (1) (S213). The optimal focus in coordinate (1) is determined through the processing in S213.

[0152] Next, the control device 10 measures the alignment mark AM_C (S214) with the optimal focus set in S213.

[0153] Next, the control device 10 determines the optical axis and position of the camera 145 based on the optical axis correction amount calculated in coordinate (2) during the processing in S211 and the correction amount of the positional relationship between the lower worktable 140 and the camera 145, and searches for the optimal focus in coordinate (2) (S215). The optimal focus in coordinate (2) is determined through the processing in S215.

[0154] Next, the control device 10 measures the alignment mark AM_L (S216) with the optimal focus set as determined in S215.

[0155] Next, the control device 10 determines the optical axis and position of the camera 145 based on the optical axis correction amount calculated in coordinate (3) during the processing in S211 and the correction amount of the positional relationship between the lower worktable 140 and the camera 145, and searches for the optimal focus in coordinate (3) (S217). The optimal focus in coordinate (3) is determined through the processing in S217.

[0156] Next, the control device 10 measures the alignment mark AM_R (S218) with the optimal focus set as determined in S217.

[0157] Next, based on the measurement results of S214, S216, and S218, the control device 10 adjusts the position of the lower stage 140 (S219). If the processing of S219 is completed, the control device 10 completes the alignment process of the lower wafer LW and enters the next process in the bonding process.

[0158] Furthermore, in the joining device 1 of the second embodiment, the processes of each of S213 and S214, S215 and S216, and S217 and S218 can also be integrated. Alternatively, the processes of S112, S114, and S116 of the first embodiment can be combined with the processes of S213, S215, and S217 respectively. The joining device 1 of the second embodiment only needs to correct the optical axis according to each measured coordinate, at least based on the deformation model 111 corresponding to the deformation amount of the lower worktable 140.

[0159] (Specific examples of the focus action in the joining process)

[0160] Figure 16 This is a schematic diagram showing the relationship between the optical axis and the signal waveform during the alignment process in the joining device 1 of the second embodiment. Figure 16 The measurement image of the alignment mark AM of the lower wafer LW and the signal waveform of a pattern AP are shown according to each deformation of the lower stage 140. The optical axis settings and use of the camera 145 for the first to third deformations are also described. Figure 15 The descriptions are the same.

[0161] like Figure 16 As shown, when the deformation of the lower stage 140 is the first deformation (without correction), the lower wafer LW, vacuum-adsorbed on the lower stage 140, is held in a flat state. Therefore, the optical axis of the camera 145 in each measurement coordinate is set to be perpendicular to the surface of the lower wafer LW. In this case, the signal waveform of a pattern AP in each coordinate of the upper stage 143 is approximately symmetrical.

[0162] Furthermore, in the bonding apparatus 1 of the second embodiment, when the deformation amount of the lower stage 140 is the second or third deformation amount, the optical axis of the camera 145 in each measurement coordinate is also set to be perpendicular to the surface of the lower wafer LW. Therefore, when the deformation amount of the lower stage 140 is the second or third deformation amount, the signal waveform of a pattern AP in each measurement coordinate of the upper stage 143 is also approximately symmetrical.

[0163] [2-4] Effects of the second embodiment

[0164] As explained above, if the lower stage 140 is deformed to correct the wafer magnification, the optical axis of the camera 145 may shift during the alignment process. Furthermore, the measurement results during the alignment process may change.

[0165] In contrast, the joining device 1 of the second embodiment has a mechanism for adjusting the optical axis of the camera 145 during alignment processing based on the amount of deformation of the lower worktable 140. For example, by deforming the lower worktable 140 and adjusting the optical axis of the camera 145, the joining device 1 of the second embodiment can maintain the symmetry of the signal waveform even if defocus occurs in any of the measured coordinates.

[0166] As a result, the joining device 1 of the second embodiment can improve the measurement accuracy of the alignment process and improve the overlap accuracy in the joining process. Therefore, the joining device 1 of the second embodiment can improve the performance of the joining device.

[0167] [3] Third implementation method

[0168] The third embodiment relates to a specific example of a semiconductor device to which the manufacturing methods for semiconductor devices described in the first and second embodiments can be applied. Hereinafter, a memory device 2, which is a NAND flash memory, will be described as a specific example of a semiconductor device.

[0169] [3-1] Composition

[0170] [3-1-1] Composition of memory device 2

[0171] Figure 17 This is a block diagram illustrating an example of the configuration of the memory device 2 according to the third embodiment. For example... Figure 17 As shown, the memory device 2 includes, for example, a memory interface (memory I / F) 20, a sequencer 21, a memory cell array 22, a driver module 23, a line decoder module 24, and a sense amplifier module 25.

[0172] Memory I / F 20 is a hardware interface for connecting to an external memory controller. Memory I / F 20 communicates according to the interface standard between memory device 2 and the memory controller. Memory I / F 20, for example, supports the NAND interface standard.

[0173] The sequencer 21 is a control circuit that controls the overall operation of the memory device 2. Based on the instructions received via the memory I / F 20, the sequencer 21 controls the driver module 23, the line decoder module 24, and the sense amplifier module 25 to perform read operations, write operations, erase operations, etc.

[0174] The memory cell array 22 is a storage circuit containing a collection of multiple memory cells. The memory cell array 22 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Blocks BLK are used, for example, as units for data erasure. Furthermore, the memory cell array 22 includes multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. Each memory cell is identified based on the address of the identified word line WL and the address of the identified bit line BL.

[0175] Driver module 23 is a driver circuit that generates the voltages used in read, write, and erase operations. Driver module 23 is connected to line decoder module 24 via multiple signal lines. Driver module 23 can change the voltages applied to the multiple signal lines based on the page address received via memory I / F 20.

[0176] The row decoder module 24 is a decoder that decodes the row address received via the memory I / F 20. The row decoder module 24 selects a block BLK based on the decoding result. Furthermore, the row decoder module 24 transmits voltages applied to multiple signal lines to multiple wirings (word lines WL, etc.) located on the selected block BLK.

[0177] The sensing amplifier module 25 is a sensing circuit that senses data read from the selected block BLK based on the voltage of the bit line BL during the read operation. The sensing amplifier module 25 sends the read data to the memory controller via the memory I / F 20. Furthermore, during the write operation, the sensing amplifier module 25 can apply a voltage corresponding to the data being written to each memory cell according to each bit line BL.

[0178] [3-1-2] Circuit configuration of memory cell array 22

[0179] Figure 18 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 22 provided in the memory device 2 of the third embodiment. Figure 18 This shows one of the multiple block BLKs contained in the storage cell array 22. For example... Figure 18 As shown, block BLK contains, for example, string units SU0 to SU3.

[0180] Each string unit (SU) contains multiple NAND strings (NS). Each NAND string (NS) is associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Different column addresses are assigned to each bit line BL0 to BLm. Each bit line BL is shared among multiple blocks (BLK) by NAND strings (NS) that have been assigned the same column address. Each NAND string (NS) contains, for example, memory cell transistors MT0 to MT7 and selection transistors STD and STS.

[0181] Each memory cell transistor MT includes a control gate and a charge accumulation layer, storing data non-volatilely. Memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of memory cell transistors MT0 to MT7 are respectively connected to word lines WL0 to WL7. Each word line WL0 to WL7 is configured according to each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string cell SU is, for example, called a "cell unit CU". When each memory cell transistor MT stores 1 bit of data, the cell unit CU stores "1 page of data". The cell unit CU can have a storage capacity of more than 2 pages of data, corresponding to the number of bits of data stored by the memory cell transistor MT.

[0182] Select transistors STD and STS are used to select the serial cell SU. The drain of select transistor STD is connected to the associated bit line BL. The source of select transistor STD is connected to one end of the serially connected memory cell transistors MT0 to MT7. The gates of the select transistors STD contained in serial cells SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3. The drain of select transistor STS is connected to the other end of the serially connected memory cell transistors MT0 to MT7. The source of select transistor STS is connected to the source line SL. The gate of select transistor STS is connected to the select gate line SGS. The source line SL is shared, for example, in multiple blocks BLK.

[0183] [3-1-3] Construction of memory device 2

[0184] Hereinafter, an example of the construction of the memory device 2 according to the third embodiment will be described. In addition, in the third embodiment, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction of the semiconductor substrate (wafer) used in the formation of the memory device 2 relative to the surface.

[0185] Figure 19 This is a perspective view showing an example of the construction of the memory device 2 according to the third embodiment. For example... Figure 19 As shown, memory device 2 includes a memory chip MC and a CMOS chip CC. The lower surface of the memory chip MC corresponds to the surface of the lower wafer LW. The upper surface of the CMOS chip CC corresponds to the surface of the upper wafer UW. The memory chip MC includes, for example, a storage region MR, lead-out regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes, for example, a sensing amplification region SR, a peripheral circuit region PER1, transmission regions XR1 and XR2, and a pad region PR2.

[0186] The memory region MR includes a memory cell array 22. Lead-out regions HR1 and HR2 include wiring for connections between the stacked wiring of the memory chip MC and the row decoder module 24 of the CMOS chip CC. Pad region PR1 includes pads for connections between the memory device 2 and the memory controller. Lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. Pad region PR1 is adjacent to the memory region MR and lead-out regions HR1 and HR2 in the Y direction, respectively.

[0187] The sensing amplification region SR contains a sensing amplifier module 25. The peripheral circuit region PERI contains a sequencer 21, a driver module 23, etc. The transmission regions XR1 and XR2 contain a line decoder module 24. The pad region PR2 contains a memory I / F 20. The sensing amplification region SR and the peripheral circuit region PERI are arranged adjacently in the Y direction and overlap with the memory region MR. The transmission regions XR1 and XR2 sandwich the sensing amplification region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively. The pad region PR2 overlaps with the pad region PR1 of the memory chip MC.

[0188] The memory chip MC has multiple bonding pads BP at the bottom of each of the memory region MR, lead-out regions HR1 and HR2, and pad region PR1. The bonding pads BP of the memory region MR are connected to associated bit lines BL. The bonding pads BP of the lead-out regions HR are connected to associated wiring (e.g., word lines WL) in the stacked wiring provided in the memory region MR. The bonding pads BP of the pad region PR1 are connected to pads (not shown) located on the upper surface of the memory chip MC. The pads on the upper surface of the memory chip MC are used, for example, for the connection between the memory device 2 and the memory controller.

[0189] The CMOS chip CC has multiple bonding pads BP on the upper parts of the sensing amplification region SR, the peripheral circuit region PERI, the transmission regions XR1 and XR2, and the pad region PR2. The bonding pads BP of the sensing amplification region SR overlap with the bonding pads BP of the memory region MR. The bonding pads BP of the transmission regions XR1 and XR2 overlap with the bonding pads BP of the lead-out regions HR1 and HR2, respectively. The bonding pads BP of the pad region PR1 overlap with the bonding pads BP of the pad region PR2.

[0190] The memory device 2 has a structure that bonds the lower surface of a memory chip MC to the upper surface of a CMOS chip CC. Two bonding pads BP, which are opposite each other between the memory chip MC and the CMOS chip CC, are electrically connected by bonding among a plurality of bonding pads BP provided in the memory device 2. Thus, the circuitry within the memory chip MC and the circuitry within the CMOS chip CC are electrically connected via the bonding pads BP. The group of two bonding pads BP opposite each other between the memory chip MC and the CMOS chip CC can be either boundary-bounded or integrated.

[0191] (Planar layout of storage cell array 22)

[0192] Figure 20 This is a top view showing an example of the planar layout of the memory cell array 22 provided in the memory device 2 of the third embodiment. Figure 20 This displays the region containing a block BLK within the storage region MR. For example... Figure 20 As shown, memory device 2 includes, for example, multiple slits SLT, multiple slits SHE, multiple memory pillars MP, multiple bit lines BL, and multiple contacts CV. In the memory region MR, the planar layout described below is repeatedly configured in the Y direction.

[0193] Each slit SLT has, for example, a structure with embedded insulating components. Each slit SLT insulates adjacent wiring (e.g., word lines WL0-WL7 and select gate lines SGD and SGS) separated by that slit SLT. Each slit SLT has a portion extending along the X direction and transversely cuts the memory region MR and the lead-out regions HR1 and HR2 along the X direction. Multiple slit SLTs are arranged in the Y direction. The region divided by the slit SLT corresponds to the block BLK.

[0194] Each slit SHE has, for example, a structure with embedded insulating components. Each slit SHE insulates the wiring (at least the gate line SGD) adjacent to that slit SLT. Each slit SHE has a portion extending in the X direction that transversely cuts the memory region MR. Multiple slit SHEs are arranged in the Y direction. In this example, three slit SHEs are arranged between adjacent slit SLTs. The multiple regions divided by the slit SLTs and SHEs correspond to the string cells SU0 to SU3, respectively.

[0195] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern, for example, in 19 columns, within the region between two adjacent slots (SLTs). Furthermore, counting from the top of the paper, the memory columns (MPs) in the 5th, 10th, and 15th columns each overlap with a slot (SHE).

[0196] Each bit line BL has a portion extending along the Y direction and transverses the region containing multiple blocks BLK along the Y direction. Multiple bit lines BL are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory column MP for each string cell SU. In this example, two bit lines BL overlap with each memory column MP.

[0197] Each contact CV is located between one of the multiple bit lines BL overlapping the memory cylinder MP and the memory cylinder MP. The contact CV electrically connects the memory cylinder MP and the bit line BL. Additionally, the contact CV between the memory cylinder MP and the bit line BL overlapping the slit SHE is omitted.

[0198] (Cross-sectional view of memory cell array 22)

[0199] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 22 provided in the memory device 2 of the third embodiment. Figure 21 This shows a cross-section along the Y direction within the storage region MR, including the storage column MP and the slot SLT. Additionally, although... Figure 21 In this context, the Z-direction refers to the bottom of the paper, but... Figure 21 In the instructions, the top edge of the paper is referred to as "the upper side," and the bottom edge as "the lower side." For example... Figure 21 As shown, the memory device 2 includes, for example, insulating layers 30-37, conductive layers 40-46, and contacts V1 and V2.

[0200] An insulating layer 30 is disposed, for example, at the bottom layer of a memory chip MC. A conductive layer 40 is disposed on the insulating layer 30. An insulating layer 31 is disposed on the conductive layer 40. Conductive layers 41 and 32 are alternately disposed on the insulating layer 31. An insulating layer 33 is disposed on the top conductive layer 41. Conductive layers 42 and 34 are alternately disposed on the insulating layer 33. An insulating layer 35 is disposed on the top conductive layer 42. Conductive layers 43 and 36 are alternately disposed on the insulating layer 35. An insulating layer 37 is disposed on the top conductive layer 43. A conductive layer 44 is disposed on the insulating layer 37. A contact V1 is disposed on the conductive layer 44. A conductive layer 45 is disposed on the contact V1. A contact V2 is disposed on the conductive layer 45. A conductive layer 46 is disposed on the contact V2. The wiring layers with conductive layers 44, 45 and 46 are respectively referred to as "M0", "M1" and "M2".

[0201] Conductor layers 40, 41, 42, and 43 are formed as plates extending, for example, along the XY plane. Conductor layer 44 is formed as a line extending along the Y direction, for example. Conductor layers 40, 41, and 43 serve as source line SL, select gate line SGS, and select gate line SGD, respectively. Multiple conductor layers 42, starting from conductor layer 40, are sequentially used as word lines WL0 to WL7. Conductor layer 44 serves as bit line BL. Contacts V1 and V2 are pillar-shaped. Conductor layers 44 and 45 are connected via contact V1. Conductor layers 45 and 46 are connected via contact V2. Conductor layer 45 is formed as a line extending along the X direction, for example. Conductor layer 46 is connected to the interface of the memory chip MC and is used as a bonding pad BP. Conductor layer 46 contains, for example, copper.

[0202] The slit SLT has a plate-like portion formed extending along the XZ plane, separating the insulating layers 31-36 and the conductive layers 41-43. Each memory pillar MP extends along the Z direction and penetrates the insulating layers 31-36 and the conductive layers 41-43. Each memory pillar MP includes, for example, a core component 50, a semiconductor layer 51, and a laminated film 52. The core component 50 is an insulator that extends along the Z direction. The semiconductor layer 51 covers the core component 50. The lower part of the semiconductor layer 51 is in contact with the conductive layer 40. The laminated film 52 covers the side surface of the semiconductor layer 51. A contact CV is provided on the semiconductor layer 51. The conductive layer 44 is in contact with the contact CV.

[0203] Additionally, in the illustrated area, the contact CV corresponding to one of the two memory pillars MP is shown. Memory pillars MP not connected to contact CV in this area are connected to contact CV in areas not shown. The portion of the memory pillar MP intersecting with the multiple conductive layers 41 functions as a select transistor STS. The portion of the memory pillar MP intersecting with the conductive layer 42 functions as a memory cell transistor MT. The portion of the memory pillar MP intersecting with the multiple conductive layers 43 functions as a select transistor STD.

[0204] (Cross-sectional structure of storage column MP)

[0205] Figure 22 This is an example of the cross-sectional structure of the memory column MP provided in the memory device 2 of the third embodiment, along... Figure 22 A cross-sectional view of the XXII-XXII line. Figure 22 A cross-section is shown, including the storage column MP and the conductive layer 42, and parallel to the conductive layer 40. (See image.) Figure 22 As shown, the laminated membrane 52 includes, for example, a tunnel insulating membrane 53, an insulating membrane 54, and a block insulating membrane 55.

[0206] The core component 50 is disposed, for example, at the center of the memory column MP. A semiconductor layer 51 surrounds the sides of the core component 50. A tunnel insulating film 53 surrounds the sides of the semiconductor layer 51. An insulating film 54 surrounds the sides of the tunnel insulating film 53. A bulk insulating film 55 surrounds the sides of the insulating film 54. A conductive layer 42 surrounds the sides of the bulk insulating film 55. The semiconductor layer 51 serves as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 53 and the bulk insulating film 55, for example, each contain silicon oxide. The insulating film 54 serves as the charge accumulation layer for the memory cell transistor MT and, for example, contains silicon nitride. Thus, each memory column MP functions as a NAND string NS.

[0207] (Cross-sectional view of memory device 4)

[0208] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 2 according to the third embodiment. Figure 23 This shows a cross-section including the memory region (MR) and the sensing amplification region (SR), that is, a cross-section including the memory chip (MC) and the CMOS chip (CC). Figure 23 As shown, the memory device 4 includes a semiconductor substrate 60, conductive layers GC and 61 to 64, and contacts CS and C0 to C3 in the sensing amplification region SR.

[0209] Semiconductor substrate 60 is a substrate used in the formation of a CMOS chip CC. Semiconductor substrate 60 includes multiple well regions (not shown). Transistors TR are formed, for example, in each of the multiple well regions. The multiple well regions are separated, for example, by STI (Shallow Trench Isolation). A conductive layer GC is provided on semiconductor substrate 60 via a gate insulating film. The conductive layer GC within the sensing amplification region SR serves as the gate electrode of the transistor TR included in the sensing amplifier module 25. Contacts C0 are provided on the conductive layer GC. Two contacts CS are provided on semiconductor substrate 60 corresponding to the source and drain of the transistor TR.

[0210] Conductive layers 61 are provided on contact CS and contact C0 respectively. Contact C1 is provided on conductive layer 61. Conductive layer 62 is provided on contact C1. Conductive layers 61 and 62 are electrically connected via contact C1. Contact C2 is provided on conductive layer 62. Conductive layer 63 is provided on contact C2. Conductive layers 62 and 63 are electrically connected via contact C2. Contact C3 is provided on conductive layer 63. Conductive layer 64 is provided on contact C3. Conductive layers 63 and 64 are electrically connected via contact C3. The wiring layers with conductive layers 61 to 64 are respectively referred to as "D0", "D1", "D2", and "D3".

[0211] The conductive layer 64 is connected to the interface of the CMOS chip CC and is used as a bonding pad BP. The conductive layer 64 in the sensing amplification region SR is bonded to the conductive layer 46 (i.e., the bonding pad BP of the memory chip MC) in the oppositely positioned memory region MR. Moreover, each conductive layer 64 in the sensing amplification region SR is electrically connected to a bit line BL. The conductive layer 64 contains, for example, copper.

[0212] In memory device 2, wiring layer D3 of CMOS chip CC and wiring layer M2 of memory chip MC are adjacent to each other through bonding between memory chip MC and CMOS chip CC. Semiconductor substrate 60 corresponds to the back side of upper wafer UW, and wiring layer D3 corresponds to the surface side of upper wafer UW. Insulator layer 30 corresponds to the back side of lower wafer LW, and wiring layer M2 corresponds to the surface side of lower wafer LW. The semiconductor substrate used in the formation of memory chip MC is removed during processes such as the formation of bonding pads after bonding treatment.

[0213] [3-2] Effects of the third embodiment

[0214] As explained above, the memory device 2 includes, for example, a memory chip MC with a structure comprising memory cells stacked in three dimensions, and a CMOS chip CC containing other control circuitry. Between the memory chip MC and the CMOS chip CC, the memory chip MC tends to exhibit a larger deviation in wafer magnification between wafers. Specifically, since the memory chip MC has a layered memory cell array 22, the deviation in wafer warpage increases, potentially leading to a larger deviation in wafer magnification. On the other hand, the arrangement of the exposure areas (shots) of the CMOS chip CC approximates an ideal grid based on the exposure apparatus. Therefore, when performing the bonding process, it is preferable to assign the wafer with the memory chip MC as the lower wafer (LW) capable of correcting wafer magnification, and the wafer with the CMOS chip CC as the upper wafer (UW). Thus, the first and second embodiments can respectively improve the yield of the memory device 2.

[0215] [4] Other

[0216] In this embodiment, the flowchart used in the description of the actions is only one example. Regarding the actions described using the flowchart, the order of processing can be interchanged to the extent possible, additional processing can be added, and some processing can be omitted. In the above embodiment, the case where the fabrication of the deformable model 111 is performed simultaneously in S109 is illustrated, but the calculation of the deformable model 111 based on the measurement results of S105 can also be performed each time the processing of S105 is completed. Similarly, in the second embodiment, the calculation of the deformable model 111 based on the measurement results of S105 and the fabrication of the relationship between the optical axis correction amount can also be performed each time the processing of S105 is completed. In the above embodiment, the case where alignment correction is applied to the lower wafer LW placed (held) on the lower stage 130 for bonding is illustrated, but it is not limited to this. The alignment correction in the bonding process can be applied to the upper wafer UW placed (held) on the upper stage 133, or to both the upper wafer UW held on the upper stage 133 and the lower wafer LW held on the lower stage 130. In this specification, an MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array) may be used instead of a CPU. Furthermore, the processes described in the embodiments can also be implemented using dedicated hardware. The processes described in the embodiments may combine software-executed processes with hardware-executed processes, or may consist of only one of these methods.

[0217] In various embodiments, the cameras 142 and 145 of the bonding device 1 may also be configured with separate optical systems (microscopes) and light-receiving sensors, as long as they can measure the alignment mark AM. Cameras 142 and 145 may also be referred to as "measuring devices," "measuring instruments," or "alignment cameras," respectively. "Optical axis" may also be referred to as "optical path." In this specification, "overlap offset" may also be referred to as "position offset." In the descriptions of the first and second embodiments, "height" is associated with the position of the focal point. The method for calibrating the focal point is not limited to the method described in the embodiments, and other methods may be used. In the embodiments, the case where the deformable model 111 is fabricated based on the optimal focal point position is illustrated, but the deformable model 111 only needs to at least represent the shape of the surface of the lower wafer LW.

[0218] The configuration described in the third embodiment is merely illustrative, and the configuration of the memory device 4 is not limited thereto. The circuit configuration, planar layout, and cross-sectional structure of the memory device 2 can be appropriately modified according to the design of the memory device 2. For example, in the third embodiment, a case is illustrated where a memory chip MC is provided above a CMOS chip CC, but a CMOS chip CC may also be provided above a memory chip MC. Although a case is illustrated where a memory chip MC is assigned to a lower wafer LW and a CMOS chip CC is assigned to an upper wafer UW, a case is also illustrated where a memory chip MC is assigned to an upper wafer UW and a CMOS chip CC is assigned to a lower wafer LW. When applying the manufacturing methods described in the first and second embodiments, it is preferable to assign a wafer with a larger wafer ratio deviation between wafers as a lower wafer LW. This can suppress overlap misalignment during the bonding process, and thus suppress the occurrence of defects caused by overlap misalignment.

[0219] In this specification, "connection" refers to an electrical connection, excluding the possibility of it being connected via other components. An "electrical connection" can also be connected via an insulator, as long as it can operate in the same manner as the electrical connection itself. "Columnar" refers to a structure formed within a hole during the manufacturing process. "Top view" corresponds, for example, to viewing an object in a vertical direction relative to the surface of the semiconductor substrate 60. "Region" can also be considered as a structure included by the semiconductor substrate 60 of the CMOS chip CC. For example, if the semiconductor substrate 60 is specified to include a memory region MR, the memory region MR is associated with a region above the semiconductor substrate 80. The bonding pad BP can also be referred to as "bonding metal."

[0220] In addition, some or all of the above embodiments may also be described as follows, but are not limited to the following.

[0221] [Postscript 1]

[0222] A bonding apparatus includes: a first stage capable of holding a first substrate; a second stage disposed above the first stage and capable of holding a second substrate; a first measuring device capable of measuring alignment marks disposed on the first substrate held on the first stage; a second measuring device capable of measuring alignment marks disposed on the second substrate held on the second stage; a stress generator capable of applying stress to the first stage; and a controller performing a bonding process for bonding the first substrate and the second substrate, the bonding process including respective alignment processes for the first substrate and the second substrate, the controller generating a focal mapping for each deformation of the first stage based on the deformation amount of the first stage deformed by the stress generator and the shape of the first substrate held on the deformed first stage, and in the alignment process of the first substrate, when the first measuring device measures the alignment marks disposed on the first substrate held on the first stage, the controller corrects the optical axis of the first measuring device based on the optical axis correction amount corresponding to the deformation amount applied to the first stage.

[0223] [Postscript 2]

[0224] As described in Appendix 1, in the alignment process of the first substrate, when the first measuring instrument measures the alignment mark disposed on the first substrate held on the first worktable, the controller corrects the positional relationship between the first worktable and the first measuring instrument based on the optical axis correction amount.

[0225] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and also within the scope of the invention and its equivalents as described in the claims.

Claims

1. A coupling device comprising: The first worktable is capable of holding the first substrate; The second workbench is disposed opposite to the first workbench and is capable of holding the second substrate; The first measuring device is capable of measuring the alignment marks disposed on the first substrate held on the first worktable; The second measuring device is capable of measuring the alignment marks disposed on the second substrate held on the second worktable; A stress generator is capable of applying stress to the first worktable; as well as The controller executes a bonding process to join the first substrate and the second substrate, the bonding process including respective alignment processes for the first substrate and the second substrate. The controller generates a focal mapping for each deformation of the first worktable based on the deformation amount of the first worktable deformed by the stress generator and the shape of the first substrate held in the deformed first worktable. In the alignment process of the first substrate, when the controller causes the first measuring instrument to measure the alignment mark disposed on the first substrate held on the first worktable, the controller uses a focus setting based on a focus mapping, the focus mapping corresponding to the amount of deformation applied to the first worktable.

2. The coupling device as claimed in claim 1, The alignment process of the first substrate includes the measurement of first to third alignment marks disposed on the first substrate. The first alignment mark is disposed at the center of the first substrate, and the second alignment mark and the third alignment mark are respectively disposed on one side and the other side of the outer periphery of the first substrate. In the focus setting based on the focus mapping, the controller sets the focus range when measuring the first alignment mark to be higher than the focus range when measuring the second alignment mark and the third alignment mark respectively. This focus mapping is the focus mapping when the first worktable is deformed by the stress generator.

3. The joining device as described in claim 2, When generating the focus map for each deformation of the first stage, the controller measures the alignment mark using a wider focus range than the focus setting based on the focus map.

4. The coupling device as claimed in claim 1, The controller generates the focus mapping based on the measurement results of the optimal focus held in the first substrate of the deformed first worktable.

5. The coupling device as claimed in claim 1, In the alignment process of the first substrate, when the controller causes the first measuring instrument to measure the alignment mark disposed on the first substrate held on the first worktable, the controller corrects the optical axis of the first measuring instrument based on the optical axis correction amount, which corresponds to the deformation amount applied to the first worktable.

6. The coupling device as claimed in claim 5, In the alignment process of the first substrate, when the first measuring device measures the alignment mark disposed on the first substrate held on the first worktable, the controller corrects the positional relationship between the first worktable and the first measuring device based on the optical axis correction amount.

7. A bonding method for bonding a first substrate and a second substrate, the bonding method comprising alignment processes for the first substrate held on a first worktable and the second substrate held on a second worktable, comprising the following steps: Based on the deformation of the first worktable deformed by the stress generator and the shape of the first substrate remaining on the deformed first worktable, a focal mapping for each deformation of the first worktable is generated; and In the alignment process of the first substrate, when measuring the alignment marks disposed on the first substrate held on the first worktable, a focus setting based on a focus mapping is used, the focus mapping corresponding to the amount of deformation applied to the first worktable.

8. A method for manufacturing a semiconductor device, comprising bonding a first substrate and a second substrate, the method including alignment processes for the first substrate held on a first worktable and the second substrate held on a second worktable, comprising the following steps: Based on the deformation of the first worktable deformed by the stress generator and the shape of the first substrate remaining on the deformed first worktable, a focal mapping for each deformation of the first worktable is generated; and In the alignment process of the first substrate, when measuring the alignment marks disposed on the first substrate held on the first worktable, a focus setting based on a focus mapping is used, the focus mapping corresponding to the amount of deformation applied to the first worktable.

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