L0 BTB Fault-Tolerant Design System and Method Based on Fully Connected Structure

Abstract

This invention relates to the field of branch target buffer fault-tolerant design, and proposes a fault-tolerant design system and method based on a fully connected L0 BTB, comprising: XORing the current instruction address to obtain the XOR checksum of the current instruction address; concatenating the current instruction address and the XOR checksum and writing them simultaneously into two L0 BTBs; accessing both L0 BTBs simultaneously with the current instruction address, and comparing the current instruction address with the target instruction address to determine whether an L0 BTB is hit; if one of the L0 BTBs is hit, setting the enable signal value to 1, obtaining the content of the entry and performing an XOR check on the entry; if the XOR checksum of the entry is the same as the checksum stored in the entry, then the entry is taken as a candidate entry; making a decision based on the obtained candidate entries; if the check result shows that no candidate entry appears, then it is considered that the current instruction address has not hit an L0 BTB.

Description

Technical Field

[0001] This invention relates to the field of branch target buffer fault-tolerant design, and in particular to a L0BTB fault-tolerant design system and method based on a fully connected structure. Background Technology

[0002] Processors may encounter two potential errors during operation. The first is a problem with the chip's hardware circuitry; the second is transient failures caused by external environmental interference, such as high-energy particle impacts. Specifically, the L0 Branch Target Buffer (LTB) in the processor's branch prediction module can be affected by external radiation, such as single-event upsets (SEUs). The first type of error is a permanent, unrecoverable fault caused by the circuitry. The second type of error can be mitigated by adding redundancy techniques to eliminate the effects of transient failures.

[0003] The branch prediction module is one of the key modules in processor design. It predicts the address of the current instruction and sends the prediction result as the target instruction address to the PC register for instruction fetching. The L0 BTB is a crucial part of the branch prediction module. If a table entry flips, it may result in the output of the erroneous entry to the cache module. Even if the cache's fault tolerance design achieves a 100% success rate, it will still lead to an incorrect target instruction. Therefore, fault tolerance design for the L0 BTB helps improve the accuracy of cache instruction fetching and maintains the normal and stable operation of the processor.

[0004] Fault-tolerant design methods for cache and register file are well-established and have been successfully deployed in various processors. However, there is a lack of dedicated research on fault-tolerant design for L0 BTB. Directly applying cache and register file fault-tolerant design methods to L0 BTB can lead to a decrease in hit rate. Therefore, a fault-tolerant design scheme specifically for fully connected L0 BTB architecture is needed. Summary of the Invention

[0005] The purpose of this invention is to provide a fault-tolerant design system and method for L0 BTB based on a fully connected structure. The aim is to reduce the impact of external environmental radiation, such as single-event flips, on L0 BTB through coded logic verification, thereby ensuring the normal operation of the branch prediction module and the normal and stable execution of the cache instruction fetching function.

[0006] The technical solution adopted by this invention to solve its technical problem is as follows:

[0007] On one hand, this invention proposes a fault-tolerant design system based on a fully connected L0 BTB structure, comprising:

[0008] The master-slave redundancy module includes two identical L0 BTB structures, each containing multiple entries. When an L0 BTB prediction target instruction is executed, the prediction result is output through the two L0 BTB structures.

[0009] The verification decision module includes two verification modules and one decision module. The two verification modules correspond to the master module and the slave module, respectively, and are used to verify the prediction results of the two L0 BTB structures. The two verification modules have completely identical structures and both output an enable signal and a verification result. If both the enable signal and the verification result are 1, it means that the entry is a candidate entry. If one of them is 0, the entry is considered not a selectable target entry.

[0010] As a further optimization, the two L0 BTB structures are L0 BTB1 and L0 BTB2, each containing 40 entries.

[0011] As a further optimization, each entry contains the following: current instruction address, target instruction address, enable signal, and XOR check value.

[0012] As a further optimization, when writing table entries, the current address is first passed through an XOR logic to obtain the XOR checksum of the current address, and the current address and the XOR checksum are concatenated and used as input to two L0 BTB structures respectively.

[0013] As a further optimization, when reading an entry, the current instruction address simultaneously accesses two L0 BTB structures. The current instruction address is compared with the target instruction address to determine whether an L0 BTB is hit. If one of the L0 BTBs is hit, the enable signal value is 1, the content of that entry is obtained, and an XOR check is performed on the entry. If the XOR check value of the entry is the same as the check value stored in the entry, the entry is taken as a candidate entry. A decision is made based on the obtained candidate entries. If the check result shows that no candidate entry appears, it is considered that the current instruction address has not hit an L0 BTB.

[0014] On the other hand, the present invention proposes a fault-tolerant design method based on a fully connected L0 BTB structure, applied to the aforementioned fault-tolerant design system based on a fully connected L0 BTB structure, comprising the following steps:

[0015] The XOR checksum of the current instruction address is obtained by performing an XOR operation on the current instruction address.

[0016] The current instruction address and the XOR checksum are concatenated and used as the input to the L0 BTB module;

[0017] Write the concatenated current instruction to both L0 BTB1 and L0 BTB2 simultaneously;

[0018] The current instruction address accesses both L0 BTB1 and L0 BTB2 simultaneously. The current instruction address is compared with the target instruction address to determine whether L0 BTB is hit.

[0019] If one of the L0 BTBs is hit, the enable signal value is 1, the content of the entry is obtained and the entry is XOR checked. If the XOR check value of the entry is the same as the check value stored in the entry, the entry is selected as a candidate entry.

[0020] The decision is made based on the obtained candidate entries. If the verification result shows that no candidate entries have appeared, it is considered that the current instruction address has not hit L0 BTB.

[0021] As a further optimization, when the concatenated current instruction is written to both L0 BTB1 and L0 BTB2 at the same time, a counter is set to determine the placement position of the entry, and the replacement strategy is a first-in-first-out strategy.

[0022] The beneficial effects of this invention are as follows: Through the above-described L0 BTB fault-tolerant design system and method based on a fully connected structure, the master-slave redundancy module ensures that the current instruction address can be matched with the correct entry in two identical L0 BTB structures. The verification decision module verifies the prediction results of the two L0 BTB structures and outputs the correct entry. This significantly reduces the impact of external environmental radiation on the L0 BTB, such as single-event upsets, ensuring the normal operation of the branch prediction module and the normal and stable execution of the cache instruction fetch function. This invention is not only applicable to fully associative L0 BTBs but can also be used in the return address stack (RAS) module of branch prediction, demonstrating the versatility of the proposed solution for various different structures. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall structure of the L0 BTB fault-tolerant design system based on a fully connected structure in Embodiment 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the verification logic in Embodiment 1 of the present invention;

[0025] Figure 3 This is a schematic diagram comparing the access to the register file and BTB structure in Embodiment 1 of the present invention;

[0026] Figure 4 This is a flowchart of the L0 BTB fault-tolerant design method based on a fully connected structure in Embodiment 2 of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1

[0029] This embodiment proposes an L0 BTB fault-tolerant design system based on a fully connected structure. A schematic diagram of its overall structure is shown below. Figure 1 The system includes:

[0030] The master-slave redundancy module includes two identical L0 BTB structures, each containing multiple entries. When predicting the target instruction using L0 BTB, the prediction result is output through the two L0 BTB structures. In this embodiment, the two L0 BTB structures are L0 BTB1 and L0 BTB2, each containing 40 entries. Each entry contains the following information: current instruction address, target instruction address, enable signal, and XOR check value.

[0031] Verification decision module, see Figure 2 It includes two verification modules and one decision module. The two verification modules correspond to the master module and the slave module, respectively, and are used to verify the prediction results of the two L0 BTB structures. The two verification modules have completely identical structures and both output an enable signal and a verification result. If both the enable signal and the verification result are 1, it means that the entry is a candidate entry. If one of them is 0, the entry is considered not a selectable target entry.

[0032] When writing a table entry, the current address is first passed through an XOR logic to obtain the XOR checksum of the current address. The current address and the XOR checksum are then concatenated and used as input to two L0 BTB structures respectively.

[0033] When reading an entry, the current instruction address accesses two L0 BTB structures simultaneously. The current instruction address is compared with the target instruction address to determine whether an L0 BTB is hit. If one of the L0 BTBs is hit, the enable signal value is 1, the content of that entry is obtained, and an XOR check is performed on the entry. If the XOR check value of the entry is the same as the check value stored in the entry, the entry is taken as a candidate entry. A decision is made based on the obtained candidate entries. If the check result shows that no candidate entry appears, it is considered that the current instruction address has not hit an L0 BTB.

[0034] It's worth noting that the L0 BTB module mainly consists of two parts: the first is a master-slave redundancy scheme, and the second contains the verification decision logic. The master-slave redundancy scheme ensures that each table entry has a corresponding correct table entry. For example, if an error occurs in table A, the data in table B can be matched with the corresponding correct table entry.

[0035] For the system described in this embodiment, there are the following two paths:

[0036] Path 1: When reading L0 BTB entries, first access two L0 BTB entries simultaneously to see if a hit occurs. If both entries are hit (i.e., the vld signals are both 0), then output the result directly, indicating that the L0 BTB structure has not been hit.

[0037] Path 2: Access the L0 BTB structure. If more than one entry is hit, it is considered likely to be hit. At this point, a parity check is performed on the hit entries to verify their correctness.

[0038] When writing, parity checks are performed first. The parity check result is added to the table entry content, and the table entry is written to two L0 BTB tables simultaneously.

[0039] For master-slave redundant modules:

[0040] In this implementation, master-slave redundancy provides backup for the L0 BTB structure, and the decision module selects the correct entry content for output. The advantage of this embodiment is that it ensures the success rate of branch prediction. Compared with the protection mechanism of adding ECC codes, the success rate of branch prediction is not reduced by adding fault-tolerant design. Compared with the fault-tolerant scheme using multi-mode redundancy, it effectively reduces area and power consumption issues while ensuring error correction capability.

[0041] To achieve a low entry miss rate in the L0 BTB, this embodiment adopts a master-slave redundancy scheme. First, the differences in working principles between the L0 BTB structure and general-purpose registers are analyzed. Then, the potential problems caused by using ECC encoding and multi-mode redundancy are analyzed. Finally, the structure is described.

[0042] Specifically, for cases where ECC encoding causes L0 BTB structure table entries to be missed:

[0043] In fault tolerance protection for register files, most previous methods used ECC encoding, which achieved good results. However, the structure and working principle of L0 BTB are different from those of register files. Directly using checksums for fault tolerance protection will result in table entry misses, leading to performance loss.

[0044] For a register file, each entry has a specific number; you only need to access a specific entry based on the register number. For example... Figure 3 (a) is a register file containing 32 registers, where the Z symbol indicates a bit flip. The signal Rs_i provides the index of the table entry to be accessed. The unique table entry to be accessed is determined by decoding the register file, the table entry content is output, and fault tolerance verification is performed. Since Rs_i determines the unique table entry to be accessed, the unique table entry can be accessed simply by decoding it according to the index number. If an error occurs in the read L0 BTB table entry (2a7f_XXXX), error correction is performed using a checksum (2a6f_XXXX) to ensure the correct execution of branch prediction.

[0045] The biggest difference between the L0 BTB structure and the general-purpose register file is the absence of the index number Rs_i and decoding logic. The L0 BTB structure requires accessing each entry and then comparing it with each L0 BTB entry using the current instruction address as the tag. If an entry matches, its content is output; otherwise, the output value of vld is 0.

[0046] This presents a serious problem: a flip error in the TAG bit of the L0 BTB structure can cause a matching failure. For example... Figure 3 In (b), 2a6f in the L0 BTB structure is incorrectly flipped to 2a7f. During matching, since (2a6f != 2a7f), the entry cannot be matched, resulting in the entry being lost.

[0047] Using checksums is a good fault-tolerance solution for register files because regardless of whether an entry has been accidentally flipped, the unique entry can be obtained through the Rs_i signal, and error correction can be performed. However, for L0 BTB structures, if the error occurs in the matching address portion, i.e., a bit flip occurs in the TAG, it will cause the entry to be lost. If the design scheme only uses checksums for error correction, it will result in performance loss.

[0048] There are two solutions to this problem: one is to design the L0 BTB structure like the register file, and the other is to add backups. The former is not feasible because the general-purpose register file corresponds to 32 registers and is associated with instructions. Specific registers can be accessed based on instruction requirements. However, for the L0 BTB structure, there is no unique index tag to find entries; the contents of the entries must be retrieved through matching. Therefore, to ensure that every piece of data can be retrieved, backups must be added.

[0049] The goal of this embodiment is to ensure that bit flips in L0 BTB entries do not affect the entry hit rate, i.e., to maintain the L0 BTB hit success rate. The most direct solution to this problem is to add backups. Triple Modular Redundancy (TMR) is commonly used to harden critical components such as triggers. The TMR structure uses a two-out-of-three strategy to achieve system fault tolerance. This strategy follows the principle of majority rule, meaning that if two of the three structures are correct, the correct result can be output. The core idea of ​​TMR is that the same entry will not flip simultaneously in different structures.

[0050] The triple redundancy scheme can solve the problem of lost entries caused by using checksums for fault tolerance. If one entry fails and cannot be matched, but its backup can still be matched, the correct result can still be obtained by voting.

[0051] In general, multi-mode redundancy leads to higher accuracy. However, it also increases area and power consumption. For register file and SRAM structures, multi-mode redundancy inherently introduces significant area and power consumption issues. This problem is even more severe for L0 BTB structures.

[0052] If an L0 BTB accesses only one entry, triple redundancy also only accesses three entries simultaneously. However, for an L0 BTB structure, all entries need to be accessed simultaneously for matching. For an L0 BTB structure with 40 entries, 120 entries need to be accessed simultaneously. For larger L0 BTB structures, the cost of accessing these entries doubles. This leads to significant additional power consumption issues.

[0053] This embodiment employs a master-slave redundancy scheme to address the issue of table entry misses. The premise is that the same table entry in the L0 BTB structure and the backup L0 BTB structure will not simultaneously experience errors; this principle is consistent with triple modular redundancy. For example, the L0 BTB stores table entry A (2a6f_3a5c), and the backup stores its corresponding entry A' (2a6f_3a5c). If the TAG bit in table entry A flips to A (2a7f_3a5c), comparing it using TAG (2a6f) will ensure a successful match for A' in the backup. The correct table entry is then selected for output through verification logic. Similarly, if the target address in table entry A flips to A (2a6f_3a5b), both entries will be matched using TAG (2a6f), and the correct entry is selected for output through verification logic. The logic for flipping in the backup remains consistent with the above. The advantage of master-slave redundancy is that a correct table entry can always be found and output.

[0054] For the verification decision module:

[0055] To output the correct entry, the outputs of L0 BTB1 and L0 BTB2 need to be evaluated. For a general-purpose register file, the output consists of two entries. A verification decision module determines whether a correct entry exists and outputs the correct entry. For the L0 BTB structure, there are eight potential outputs (cases 1-8). As shown in Table 1, these include three cases: no L0 BTB structure hit, one L0 BTB structure hit, and both L0 BTB structures hit. Therefore, a selection circuit is designed to decide on these potential cases.

[0056] This embodiment first uses a structure to determine whether an output entry has been hit. When an entry is hit, the vld signal is 1. An XOR check is performed on the stored address and compared with the saved checksum value. If the comparison value is 1, it indicates that the entry has not been flipped and can be considered a candidate entry. Otherwise, it indicates that the entry has experienced a flipping error.

[0057] The above process can be represented using logical expressions, with Cx indicating whether an entry is valid and whether an error has occurred. First, the XOR value of the target address is compared with the stored checksum, and then ANDed with the enable signal. The output control signal Cx has three cases: both L0 BTB1 and L0 BTB2 are hit and valid; one of L0 BTB1 and L0 BTB2 is hit and valid; and both L0 BTB1 and L0 BTB2 are invalid (case 1). A hit occurs when one of L0 BTB1 or L0 BTB2 is valid; a Cx value of 0 indicates no hit, corresponding to case 1. However, for cases 2-8, further distinction of the entries is necessary. Designing a circuit for each case would be complex and wasteful.

[0058] Research revealed a certain correlation between cases 2 through 8. The core idea in circuit design is to disregard which L0 BTB1 or L0 BTB2 is correct in each case. If only one L0 BTB is valid, that entry is selected as a candidate. If both BTB entries are correct, either one can be chosen as a candidate.

[0059] Set L0 BTB1 as the primary BTB structure. When L0 BTB1 is valid, L0 BTB1 is directly selected as the target. When L0 BTB1 is invalid but L0 BTB2 is valid, L0 BTB2 is selected as the target entry.

[0060] Referring to Table 1, the present invention includes the following cases, where the boxed parts are the flipped bits:

[0061] Table 1

[0062]

[0063] Case 6: Vld1=1, Cx1=1, Vld2=1, Cx2=1, indicating a jump has occurred, and the target instruction address is TA1.

[0064] If both Cx1 and Cx2 are 1, it indicates that the master-slave module contains two potential target entries. One of them is selected as the target entry. To simplify the decision circuit, if a target entry exists in L0 BTB, L0 BTB1 is selected as the output target.

[0065] Case 7: Vld1=1, Cx1=0, Vld2=1, Cx2=1, indicating a jump has occurred, and the target instruction address is TA2.

[0066] Vld1 is 1, but Cx1 is 0. This indicates two potential prediction results: TAG flipping and target instruction address flipping. The table shows that the error was caused by TAG flipping. After XOR verification, an error was found in L0 BTB1, and L0 BTB2 was selected as the target entry.

[0067] Case 8: Vld1 = 1, Cx1 = 1, Vld2 = 1, Cx2 = 0, indicating a jump occurred, with the target instruction address = TA1. Vld2 is 1, but Cx2 is 0. This suggests two potential prediction outcomes: TAG flipping and target instruction address flipping. The table shows that the error was caused by TAG flipping. After XOR verification, an error was found in L0 BTB2, and L0 BTB1 was selected as the target entry.

[0068] Example 2

[0069] Based on Example 1, this example proposes a fault-tolerant design method for L0 BTB based on a fully connected structure, the flowchart of which is shown below. Figure 4 The method includes the following steps:

[0070] S1. Perform an XOR operation on the current instruction address to obtain the XOR checksum of the current instruction address;

[0071] S2. Concatenate the current instruction address and the XOR checksum, and use it as the input to the L0 BTB module;

[0072] S3. Write the concatenated current instruction to both L0 BTB1 and L0 BTB2 simultaneously;

[0073] S4. The current instruction address accesses both L0 BTB1 and L0 BTB2 simultaneously. The current instruction address is compared with the target instruction address to determine whether L0 BTB is hit.

[0074] S5. If one of the L0 BTBs is hit, the enable signal value is 1. Obtain the content of the entry and perform an XOR check on the entry. If the XOR check value of the entry is the same as the check value stored in the entry, then the entry is taken as a candidate entry.

[0075] S6. Make a decision based on the obtained candidate entries. If the verification result shows that no candidate entries have appeared, it is considered that the current instruction address has not hit L0 BTB.

[0076] In this embodiment, when the concatenated current instruction is written to L0 BTB1 and L0 BTB2 at the same time, a counter can be set to determine the placement position of the entry, and the replacement strategy is a first-in-first-out strategy.

[0077] The fault-tolerant design method in this embodiment works on the same principle as the fault-tolerant design system in Embodiment 1, so it will not be described again.

[0078] Example 3

[0079] Based on Embodiments 1 and 2, this embodiment further describes the technical effects of the present invention in conjunction with simulation experiments:

[0080] 1. Simulation conditions and content:

[0081] The hardware platform used in this experiment is: Intel Core i7-7700 CPU (3.6GHz) and 16GB of memory. The simulation software platform is Python 3.6 and Vivado 2019.1.

[0082] Simulation 1: Verifying the Number of Missing L0 BTB Entry Entries. The L0 BTB is used to predict the target instruction address, and its performance is reflected in the number of hit addresses and the number of missing addresses. When a SEU toggle error occurs, entries that could have been hit will not be hit, resulting in missing entries. Simultaneously, if the toggle error occurs at the target address, the PC register will fetch the incorrect instruction address, affecting the cache's instruction fetching results. Therefore, keeping the number of missing L0 BTB entries as low as possible is crucial for the performance of the branch prediction structure.

[0083] Simulation 2: Verifying the fault tolerance capability after adding fault-tolerant design. The addition of fault-tolerant design reduces soft errors caused by SEU, etc. Not only is the fault tolerance capability of L0 BTB verified, but the proposed method is also used to verify the fault tolerance capability of the RAS (Return Address Stack) module in branch prediction, proving the universality of the proposed scheme for various different structures.

[0084] 2. Simulation Result Analysis:

[0085] Table 2

[0086]

[0087] To investigate the impact of external environmental radiation on the normal operation of the processor, a single-event flip (SET) was simulated in LoBTB to examine its effect on branch prediction hits and missing branches. Table 1 shows that experiments were conducted on 10 different traces, each containing 1 million branch instructions.

[0088] First, we statistically analyzed the hit and missing data of these 10 traces under normal conditions through L0 BTB. Then, we designed an error injection scheme for 1% of the missing entries. As shown in Table 1, for a trace with 1 million branch instructions, an average of 572 errors were injected, which is equivalent to injecting one error for every 10,000 branch instructions.

[0089] Flip errors involve two aspects: CA (Current Address) and TA (Target Address). When a flip error occurs at the CA bit, it causes a mismatch between the current address and the CA bit, resulting in a hit loss. Experimental results show that for 10 different traces, injecting an error results in an average of 7 false hits and a reduction in the number of hit entries to 37. Therefore, the actual reduction in hits is the sum of both, averaging 44. The number of missing entries due to flips increases by 32, indicating that single-event flips severely challenge the normal operation of the branch prediction L0 BTB module and affect its prediction performance. Therefore, fault-tolerant design methods must be added to address the impact of harsh external environments such as SEU.

[0090] Table 3

[0091]

[0092] The table above shows the hit and missing data of the table entries using the proposed fault tolerance method. As can be seen from the table, using the same injection error method and injection error ratio, the average number of injected erroneous entries is 572, and the number of times the injected erroneous entries are hit is 2597. This includes false hits due to flip errors and the number of miss hits due to flip errors. Using the proposed L0 BTB fault tolerance design method, the hit problem caused by flip errors is solved, achieving 100% fault tolerance.

[0093] Table 4

[0094]

[0095] In addition to achieving 100% fault tolerance in the L0 BTB module, the proposed method will also be used in the Return Address Stack (RAS) module. Figure 3 The paper demonstrates the difference between the L0 BTB module and the RAS module. The L0 BTB is a fully connected structure that determines the target entry by matching all entries. The RAS module pushes the target entry onto the stack and removes the top element as the target entry. The fault-tolerant design method of L0 BTB can also be deployed in the RAS module. Experimental results show that the method achieves 100% fault tolerance for the RAS module, demonstrating that the method can be deployed on various register structures and exhibiting a certain degree of versatility.

[0096] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A fault-tolerant design system based on a fully connected L0 BTB architecture, characterized in that, include: The master-slave redundancy module includes two identical L0 BTB structures, each containing multiple entries. When an L0 BTB prediction target instruction is executed, the prediction result is output through the two L0 BTB structures. The verification decision module includes two verification modules and one decision module. The two verification modules correspond to the main module and the slave module, respectively, and are used to verify the prediction results of the two L0 BTB structures. The two verification modules have completely identical structures and both output an enable signal and a verification result. If both the enable signal and the verification result are 1, it means that the hit entry is a candidate entry. If one of them is 0, the hit entry is considered not a selectable target entry. When writing entries, the current address is first passed through an XOR logic to obtain the XOR check value of the current instruction address. The current instruction address and the XOR check value are then concatenated and used as input to the two L0 BTB structures respectively. When reading an entry, the current instruction address accesses two L0 BTB structures simultaneously. The current instruction address is compared with the target instruction address to determine whether an L0 BTB is hit. If an entry in one of the L0 BTBs is hit, the enable signal is set to 1, the entry content is retrieved, and an XOR check is performed on the entry. If the XOR check value of the entry is the same as the XOR check value stored in the entry, the entry is taken as a candidate entry. A decision is made based on the obtained candidate entries. If the check result shows that no candidate entry appears, it is considered that the current instruction address has not hit an L0 BTB. The two L0 BTB structures are L0 BTB1 and L0 BTB2, respectively.

2. The L0 BTB fault-tolerant design system based on a fully connected structure according to claim 1, characterized in that, Both L0BTB1 and L0BTB2 contain 40 entries.

3. The L0 BTB fault-tolerant design system based on a fully connected structure according to claim 1, characterized in that, Each entry contains the following information: current instruction address, target instruction address, enable signal, and XOR checksum.

4. A fault-tolerant design method based on a fully connected L0 BTB structure, applied to the fault-tolerant design system based on a fully connected L0 BTB structure as described in any one of claims 1-3, characterized in that, Includes the following steps: The XOR operation is performed on the current instruction address to obtain the XOR check value of the current instruction address. The current instruction address and the XOR checksum are concatenated and used as the input to the L0 BTB module; Write the concatenated current instruction address to both L0 BTB1 and L0 BTB2 simultaneously; The current instruction address accesses both L0 BTB1 and L0 BTB2 simultaneously. The current instruction address is compared with the target instruction address to determine whether L0 BTB is hit. If an entry in one of the L0 BTBs is hit, the enable signal value is 1, the content of the entry is obtained, and an XOR check is performed on the entry. If the XOR check value of the entry is the same as the XOR check value stored in the entry, the entry is taken as a candidate entry. The decision is made based on the obtained candidate entries. If the verification result shows that no candidate entries have appeared, it is considered that the current instruction address has not hit L0 BTB.

5. The L0 BTB fault-tolerant design method based on a fully connected structure according to claim 4, characterized in that, When the concatenated current instruction is written to both L0 BTB1 and L0 BTB2, a counter is set to determine the placement position of the entry, and the replacement strategy is a first-in, first-out strategy.

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