An anti-interference power circuit for a gallium nitride driver

Abstract

The present application discloses an anti-interference power circuit for a gallium nitride driver, comprising a control chip, a driver chip, a power circuit, a sampling signal amplification circuit, a current sampling resistor circuit, and a PWM filter circuit. The output of the control chip is connected to the input of the driver chip via an upper / lower bridge PWM filter circuit, and the output of the driver chip is connected to the power circuit. One output of the upper / lower bridge PWM filter circuit is connected to a signal ground (SGND). Two reference ground planes (VSS) of the driver chip are connected and then connected to the signal ground (SGND), with one reference ground plane (VSS) being connected to the source of a lower bridge arm gallium nitride chip (U2) in the power circuit. The circuit described in the present application ensures the stability between the gate and source of the gallium nitride power chip and ensures the same potential difference between the control chip and the driver chip, thereby avoiding malfunction or damage to the driver.

Description

Technical Field

[0001] The present application relates to the technical field of servo motors, and in particular to an anti-interference power circuit of a gallium nitride driver. Background Art

[0002] With the rapid development of the industrial control industry, industrial robots have been increasingly widely used. As the core component of industrial robots, servo drives are facing increasing market demand. Miniaturized, high-power-density, and efficient servo drives are increasingly favored by the market.

[0003] Currently, the primary power transistors used in low-voltage servo drives internationally are MOSFETs. Full-bridge driver chips are used to drive MOSFETs, but due to their high heat generation, they must be connected in parallel for high-power applications. As gallium nitride (GaN) technology matures, its high power density is gaining widespread market recognition. Numerous international companies are also gradually launching products using GaN as power transistors.

[0004] Compared to traditional MOSFET chips, GaN has no body diode reverse recovery, significantly reducing dead time and switching losses, thereby reducing heat and improving power efficiency. However, precisely because of these advantages, the power density in a small area poses significant challenges to layout and routing. Parasitic parameters are inevitably introduced during the design process. Therefore, in non-isolated, high-current driver circuits based on GaN modules, the driver power side experiences high dv / dt and di / dt, making GaN power devices more sensitive to parasitic parameters of the printed circuit board and power circuit. This can lead to a significant potential difference between the power ground and the control ground, causing driver malfunction or damage. Summary of the Invention

[0005] Based on this, in order to address the above technical issues, an anti-interference power circuit of a gallium nitride driver is provided to solve the problem of driver malfunction or damage caused by high current.

[0006] An anti-interference power circuit of a gallium nitride driver includes a control chip, a driver chip, a power circuit, a sampling signal amplification circuit, a current sampling resistor circuit, and a PWM filter circuit;

[0007] The PWM filter circuit includes an upper bridge arm PWM filter circuit and a lower bridge arm PWM filter circuit;

[0008] The high-side PWM control output signal end of the control chip is connected to the high-side control signal input end HI of the driving chip through the upper bridge arm PWM filter circuit, and the low-side PWM control output signal end is connected to the low-side control signal input end LI of the driving chip through the lower bridge arm PWM filter circuit, and one output end of the upper bridge arm PWM filter circuit and the lower bridge arm PWM filter circuit are respectively connected to the signal ground SGND;

[0009] The power circuit includes an upper arm power circuit and a lower arm power circuit; the upper arm power circuit includes an upper arm gallium nitride power chip U1 and a driving resistor R5, and the lower arm power circuit includes a lower arm gallium nitride power chip U2 and a driving resistor R6;

[0010] The two reference ground planes VSS of the driver chip are connected and then connected to the signal ground SGND, one of the reference ground planes VSS is connected to the source of the lower bridge arm gallium nitride chip U2, the low-side driver output terminal LO is connected to the gate of the lower bridge arm gallium nitride power chip U2 through the driving resistor R6, the high-side driver output terminal HO is connected to the gate of the upper bridge arm gallium nitride power chip U1 through the driving resistor R5, and the high-side driver return terminal HS is directly connected to the source of the upper bridge arm gallium nitride power chip U1;

[0011] The source of the lower bridge arm gallium nitride chip U2 is connected to the input end of the current sampling signal amplifying circuit through the current sampling resistor circuit, and the output end of the sampling signal amplifying circuit is connected to the analog input end of the control chip; an output end of the control chip is connected to the power ground PGND, and an output end of the current sampling resistor circuit is connected to the power ground PGND.

[0012] In the above solution, optionally, the upper arm PWM filter circuit includes: a resistor R1, a resistor R2, and a capacitor C1, the input end of the resistor R1 is connected to the high-side PWM control output signal end of the driver chip, an output end of the resistor R1 is connected to the high-side control signal input end HI of the driver chip, a first branch and a second branch are led out from the node between the output end of the resistor R1 and the high-side control signal input end HI of the driver chip, the first branch is connected in series with the resistor R2 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C1 and connected to the signal ground SGND;

[0013] The lower bridge arm PWM filter circuit includes: a resistor R3, a resistor R4 and a capacitor C2, the input end of the resistor R3 is connected to the low-side PWM control output signal end of the driver chip, and an output end of the resistor R3 is connected to the low-side control signal input end LI of the driver chip. A first branch and a second branch are led out from the node between the output end of the resistor R3 and the low-side control signal input end LI of the driver chip. The first branch is connected in series with the resistor R4 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C2 and connected to the signal ground SGND.

[0014] In the above solution, further optionally, all capacitors and resistors in the PWM filter circuit and the power circuit are set to preset parameters to eliminate interference caused by potential differences between different grounds.

[0015] In the above solution, further optionally, the values ​​of the resistors R1 and R3 are 51Ω, the values ​​of the resistors R2 and R4 are 10kΩ, the values ​​of the resistors R5 and R6 are 5.1Ω, and the values ​​of the capacitors C1 and C2 are 4.7nF.

[0016] In the above solution, optionally, the upper arm power circuit and the lower arm power circuit together form a full-bridge inverter topology structure, which is used to generate a three-phase sinusoidal waveform with an angle of 120° to each other to drive the motor.

[0017] This application has at least the following beneficial effects:

[0018] This application closely connects the VSS level of the driver chip to the source of the gallium nitride chip, connects the control chip and the driver chip through a PWM filter circuit, and controls the output end of the PWM filter circuit and the driver chip to be connected to the signal ground. This ensures the stability between the gate and source of the gallium nitride power chip and makes the potential difference between the control chip and the driver chip the same, thus avoiding the problem of driver malfunction or damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the circuit structure of a gallium nitride driver in the prior art provided in one embodiment of the present application;

[0020] Figure 2 A schematic diagram of the circuit structure of an anti-interference power circuit of a gallium nitride driver provided in one embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0022] See also Figure 1The existing gallium nitride driver includes a control chip, a gallium nitride driver chip 4 and a power circuit. The power circuit includes an upper-arm power circuit 5 and a lower-arm power circuit 6. The upper-arm power circuit 5 includes a driving resistor R5 and an upper-arm gallium nitride power chip U1. The lower-arm power circuit 6 includes a driving resistor R6 and a lower-arm gallium nitride power chip U2. The control chip 1 is directly connected to the driver chip 4. The driver chip 4 is directly connected to the power circuit gallium nitride power chip through the resistor in the power circuit. The output end of the lower-bridge gallium nitride power chip U2 is connected to the lower-bridge sampling resistor 7 and the sampling signal amplifier circuit 8 in sequence. The output end of the sampling signal amplifier circuit 8 is connected to the driver chip 1.

[0023] The control chip is used to send control signals to the driver chip 4 using SVPWM space vector pulse width modulation technology, and at the same time sample the three-phase current after passing through the lower bridge sampling resistor 7 and process it through the amplifier circuit 8. Then, the control chip 1 uses the real-time control algorithm to output the SVPWM signal to the driver chip 1, thereby performing closed-loop control of the output current.

[0024] Therefore, when the driver is operating at full load, its GaN power chip can generate a very high voltage signal at a very high di / dt due to its fast turn-on and turn-off speeds and large output current. If this voltage signal interferes with the control chip 1 or the driver chip 4, the entire circuit will malfunction.

[0025] This application discloses a hardware circuit design for suppressing interference with drive signals at high power levels in a gallium nitride servo drive. This hardware design effectively suppresses interference from the power circuit into the drive circuit in high-power circuits, ensuring stable operation of the drive.

[0026] In one embodiment, see Figure 2 , the present application provides an anti-interference power circuit of a gallium nitride driver, comprising a control chip 1, a driver chip 4, a power circuit, a sampling signal amplifying circuit 8 and a current sampling resistor circuit 7, characterized in that it also includes: a PWM filter circuit;

[0027] The PWM filter circuit includes an upper bridge arm PWM filter circuit 2 and a lower bridge arm PWM filter circuit 3;

[0028] The PWM filter circuit includes an upper bridge arm PWM filter circuit and a lower bridge arm PWM filter circuit;

[0029] The high-side PWM control output signal end of the control chip is connected to the high-side control signal input end HI of the driving chip through the upper bridge arm PWM filter circuit, and the low-side PWM control output signal end is connected to the low-side control signal input end LI of the driving chip through the lower bridge arm PWM filter circuit, and one output end of the upper bridge arm PWM filter circuit and the lower bridge arm PWM filter circuit are respectively connected to the signal ground SGND;

[0030] The power circuit includes an upper arm power circuit and a lower arm power circuit; the upper arm power circuit includes an upper arm gallium nitride power chip U1 and a driving resistor R5, and the lower arm power circuit includes a lower arm gallium nitride power chip U2 and a driving resistor R6;

[0031] The two reference ground planes VSS of the driver chip are connected and then connected to the signal ground SGND, one of the reference ground planes VSS is connected to the source of the lower bridge arm gallium nitride chip U2, the low-side driver output terminal LO is connected to the gate of the lower bridge arm gallium nitride power chip U2 through the driving resistor R6, the high-side driver output terminal HO is connected to the gate of the upper bridge arm gallium nitride power chip U1 through the driving resistor R5, and the high-side driver return terminal HS is directly connected to the source of the upper bridge arm gallium nitride power chip U1;

[0032] The source of the lower bridge arm gallium nitride chip U2 is connected to the input end of the current sampling signal amplifying circuit through the current sampling resistor circuit, and the output end of the sampling signal amplifying circuit is connected to the analog input end of the control chip; an output end of the control chip is connected to the power ground PGND, and an output end of the current sampling resistor circuit is connected to the power ground PGND.

[0033] The gallium nitride driver includes multiple driver chips for driving multiple power circuits, with one driver chip connected to one power circuit. This application employs multiple PWM filter circuits installed between the control chip and the driver chip, with each PWM filter circuit connected to a driver chip. This means one PWM filter circuit is connected to one driver chip, and one driver chip is connected to one power circuit.

[0034] The driver chip 4 amplifies the control signal sent by the control chip 1 to a level that can drive the upper and lower bridge gallium nitride power chips. Because the gate to source of the gallium nitride power chip is very fragile, to avoid interference with the gate, the low-side VSS of the driver chip is tightly connected to the source of the gallium nitride to ensure stability between its gate and source.

[0035] To ensure a tight connection between the source of the high-arm GaN chip and the VSS of the driver chip, the VSS of driver chip 1 is raised to the source voltage of the GaN chip. However, the "ground plane" of the entire circuit is actually the low side of sampling resistor 7. Therefore, the "ground planes" on the control and driver chips are inconsistent. To address this problem, a PWM filtering circuit can effectively resolve this interference issue.

[0036] In the anti-interference power circuit of the above-mentioned GaN driver, the VSS level of the driver chip is closely connected to the source of the GaN chip, the control chip and the driver chip are connected through a PWM filter circuit, and the output of the PWM filter circuit and the driver chip are connected to the signal ground. This not only ensures the stability between the gate and source of the GaN power chip, but also makes the potential difference between the control chip and the driver chip equal, avoiding the problem of driver malfunction or damage.

[0037] In one embodiment, the upper arm PWM filter circuit 2 includes: a resistor R1, a resistor R2, and a capacitor C1, wherein the input end of the resistor R1 is connected to the high-side PWM control output signal end of the driver chip 4, and the output end of the resistor R1 is connected to the high-side control signal input end HI of the driver chip 4. A first branch and a second branch are led out from the node between the output end of the resistor R1 and the high-side control signal input end HI of the driver chip 4, the first branch is connected in series with the resistor R2 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C1 and connected to the signal ground SGND;

[0038] The lower bridge arm PWM filter circuit 3 includes: a resistor R3, a resistor R4 and a capacitor C2, the input end of the resistor R3 is connected to the low-side PWM control output signal end of the driver chip 4, and an output end of the resistor R3 is connected to the low-side control signal input end LI of the driver chip 4. A first branch and a second branch are led out from the node between the output end of the resistor R3 and the low-side control signal input end LI of the driver chip 4. The first branch is connected in series with the resistor R4 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C2 and connected to the signal ground SGND.

[0039] In one embodiment, all capacitors and resistors in the PWM filter circuit and the power circuit are set to preset parameters for absorbing noise.

[0040] In one embodiment, the values ​​of the resistors R1 and R3 are 51Ω, the values ​​of the resistors R2 and R4 are 10 kΩ, the values ​​of the resistors R5 and R6 are 5.1Ω, and the values ​​of the capacitors C1 and C2 are 4.7 nF.

[0041] In one embodiment, the upper arm power circuit and the lower arm power circuit together form a full-bridge inverter topology structure, which is used to generate a three-phase sinusoidal waveform with an angle of 120° to each other to drive the motor.

[0042] The overall hardware design method described in this application can make the entire system run smoothly, which solves the problem that the gate of the gallium nitride chip is fragile and easily interfered with, and also solves the problem of signal instability caused by the inconsistent "ground plane" between the control circuit 1 and the driver chip 4.

[0043] This application focuses on a low-voltage, high-power servo driver based on gallium nitride power devices, which can replace MOSFET solutions. Its power density is much higher than other types of power transistors and can be used to drive joints in AGVs, collaborative robots, and robot dogs.

[0044] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An anti-interference power circuit of a gallium nitride driver, comprising a control chip, a driver chip, a power circuit, a sampling signal amplifying circuit, and a current sampling resistor circuit, characterized in that: Also includes: PWM filter circuit; The PWM filter circuit includes an upper bridge arm PWM filter circuit and a lower bridge arm PWM filter circuit; The high-side PWM control output signal end of the control chip is connected to the high-side control signal input end HI of the driving chip through the upper bridge arm PWM filter circuit, and the low-side PWM control output signal end is connected to the low-side control signal input end LI of the driving chip through the lower bridge arm PWM filter circuit, and one output end of the upper bridge arm PWM filter circuit and the lower bridge arm PWM filter circuit are respectively connected to the signal ground SGND; The power circuit includes an upper arm power circuit and a lower arm power circuit; the upper arm power circuit includes an upper arm gallium nitride power chip U1 and a driving resistor R5, and the lower arm power circuit includes a lower arm gallium nitride power chip U2 and a driving resistor R6; The two reference ground planes VSS of the driver chip are connected and then connected to the signal ground SGND, one of the reference ground planes VSS is connected to the source of the lower bridge arm gallium nitride chip U2, the low-side driver output terminal LO is connected to the gate of the lower bridge arm gallium nitride power chip U2 through the driving resistor R6, the high-side driver output terminal HO is connected to the gate of the upper bridge arm gallium nitride power chip U1 through the driving resistor R5, and the high-side driver return terminal HS is directly connected to the source of the upper bridge arm gallium nitride power chip U1; The source of the lower bridge arm gallium nitride chip U2 is connected to the input end of the current sampling signal amplifying circuit through the current sampling resistor circuit, and the output end of the sampling signal amplifying circuit is connected to the analog input end of the control chip; an output end of the control chip is connected to the power ground PGND, and an output end of the current sampling resistor circuit is connected to the power ground PGND; The upper bridge arm PWM filter circuit includes: a resistor R1, a resistor R2 and a capacitor C1, the input end of the resistor R1 is connected to the high-side PWM control output signal end of the driver chip, an output end of the resistor R1 is connected to the high-side control signal input end HI of the driver chip, a first branch and a second branch are led out from the node between the output end of the resistor R1 and the high-side control signal input end HI of the driver chip, the first branch is connected in series with the resistor R2 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C1 and connected to the signal ground SGND; The lower bridge arm PWM filter circuit includes: a resistor R3, a resistor R4 and a capacitor C2, the input end of the resistor R3 is connected to the low-side PWM control output signal end of the driver chip, an output end of the resistor R3 is connected to the low-side control signal input end L1 of the driver chip, a first branch and a second branch are led out from the node between the output end of the resistor R3 and the low-side control signal input end L1 of the driver chip, the first branch is connected in series with the resistor R4 and then connected to the signal ground SGND, and the second branch is connected in series with the capacitor C2 and connected to the signal ground SGND; The sizes of all capacitors and resistors in the PWM filter circuit and the power circuit are set to preset parameters to eliminate interference caused by potential differences between different ground surfaces; The upper arm power circuit and the lower arm power circuit together form a full-bridge inverter topology structure, which is used to generate a three-phase sinusoidal waveform with an angle of 120 degrees to each other to drive the motor.

2. The anti-interference power circuit of the gallium nitride driver according to claim 1, characterized in that: The values ​​of the resistors R1 and R3 are 51Ω, the values ​​of the resistors R2 and R4 are 10 kΩ, the values ​​of the resistors R5 and R6 are 5.1Ω, and the values ​​of the capacitors C1 and C2 are 4.7 nF.

Images