A silicon piezoresistive pressure sensing chip and a preparation method thereof
By using intelligent stripping technology to fabricate pressure sensing chips on SOI wafers, the problems of leakage current and short lifespan at high temperatures have been solved, resulting in higher temperature resistance and longer service life, while reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN AMPRON TECH CORP
- Filing Date
- 2023-09-22
- Publication Date
- 2026-04-17
AI Technical Summary
Existing piezoresistive pressure sensing chips are prone to leakage current at high temperatures, have a short lifespan, and the pressure-sensitive resistors are easily deformed or corroded, leading to chip failure, and are also costly.
SOI wafers are fabricated using intelligent stripping technology to form a thicker silicon dioxide insulating layer. This layer is then combined with a silicon elastic diaphragm and an ohmic contact metal layer to form a Wheatstone bridge structure, preventing pressure from directly contacting the monocrystalline silicon sensitive resistor.
This improves the chip's high-temperature resistance, prevents leakage current, extends its service life, reduces the risk of failure, and lowers costs.
Smart Images
Figure CN117268624B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of pressure sensor technology, and specifically relates to a silicon piezoresistive pressure sensing chip and its fabrication method. Background Technology
[0002] Currently, in traditional piezoresistive pressure sensing chips, the pressure source, such as the gas or liquid to be measured, directly acts on the single-crystal silicon sensitive resistor, causing deformation to complete the pressure test. In this case, the chip's maximum operating temperature is 125℃, leading to significant leakage current at high temperatures. Furthermore, the pressure-sensitive resistor element used for testing is also prone to deformation or corrosion by certain liquid pressure sources, causing chip failure. To solve this problem, simply improving the durability of the pressure-sensitive resistor to enhance the chip's lifespan and effectiveness is not ideal and would significantly increase development costs.
[0003] SOI wafers incorporate a buried oxide layer between the top silicon layer and the substrate, achieving insulation between them and improving device reliability. Furthermore, the high-temperature characteristics of SOI wafers make them ideal for fabricating high-temperature pressure sensors. High-energy oxygen ion implantation (SIMOX) is the mainstream method for manufacturing SOI materials. It involves implanting oxygen ions into the substrate, where they react with silicon to form a silicon dioxide insulating layer, resulting in the SOI wafer structure. While this method can form a relatively uniform buried oxide layer, its thickness is typically no more than 240 nm, and its high-temperature resistance is generally limited. Moreover, the high implantation energy can easily damage the silicon dioxide insulating layer, causing device failure, thus affecting chip yield and increasing costs. Summary of the Invention
[0004] In order to overcome the above-mentioned shortcomings in the prior art, the purpose of this application is to provide a silicon piezoresistive pressure sensor chip and its fabrication method, so as to overcome the problems of short life, poor high temperature resistance, and serious leakage current when operating at high temperature in existing pressure sensors.
[0005] The technical means adopted in this application to solve the above-mentioned technical problems are:
[0006] This application provides a silicon piezoresistive pressure sensing chip, comprising:
[0007] Conical wafer layer;
[0008] A silicon elastic diaphragm is disposed above the tapered wafer layer;
[0009] A silicon dioxide insulating layer is mounted on top of the silicon elastic diaphragm;
[0010] A capping wafer layer is disposed on the silicon dioxide insulating layer, and a reference pressure cavity is provided between the capping wafer layer and the silicon dioxide insulating layer;
[0011] Pressure-sensitive monocrystalline silicon, wherein the pressure-sensitive monocrystalline silicon is mounted on the silicon dioxide insulating layer and is located inside the reference pressure chamber;
[0012] An ohmic contact metal layer is mounted on the silicon dioxide insulation and is located outside the reference pressure chamber.
[0013] Preferably, the thickness of the ohmic contact metal layer is 0.8μm-1.2μm, the thickness of the pressure-sensitive monocrystalline silicon is 0.32-0.7μm, and the thickness of the silicon dioxide insulating layer is 1-3μm.
[0014] Preferably, the reference pressure chamber is filled with air or a vacuum.
[0015] Preferably, four resistors are disposed on the pressure-sensitive monocrystalline silicon, and the four resistors form a Wheatstone bridge structure.
[0016] Preferably, the resistor has a width of 5μm-15μm and a length of 1000μm-1500μm.
[0017] This application also provides a method for fabricating a silicon piezoresistive pressure sensor chip as described in any of the above claims, comprising the following steps:
[0018] S1: A certain amount of H+ is injected into the silicon wafer covered with an oxide layer to the required depth to obtain a two-layer structure of silicon dioxide insulating layer and silicon substrate with microcavities;
[0019] S2: On the two-layer structure obtained in step S1, it is bonded to another silicon wafer covered with an oxide layer at low temperature to obtain a three-layer structure of upper silicon substrate, silicon dioxide insulating layer and lower silicon substrate.
[0020] S3: On the three-layer structure obtained in step S2, the silicon substrate is annealed and peeled off to the hydrogen implantation position to obtain the SOI wafer structure;
[0021] S4: On the SOI wafer structure obtained in step S3, CMP polishing is used to obtain a smooth SOI wafer structure.
[0022] S5: On the SOI wafer structure obtained in step S4, the pressure-sensitive single crystal silicon of the SOI wafer structure is etched into resistance strips distributed along the crystal orientation using a plasma etching method.
[0023] S6: On the SOI wafer structure obtained in step S5, a square deep trench is etched on the lower silicon wafer using the KOH etching method to obtain a silicon elastic film. In addition, the conical wafer layer is also formed using the KOH etching method.
[0024] S7: On the SOI wafer structure obtained in step S6, the SOI wafer structure is directly bonded to the tapered wafer layer;
[0025] S8: On the SOI wafer structure obtained in step S7, a high-temperature resistant ohmic contact multilayer metal film is obtained on both sides above the SOI wafer structure by using a combination of vacuum sputtering and LIFT-OFF.
[0026] S9: On the SOI wafer structure obtained in step S8, the capping wafer is bonded to the SOI wafer structure using a glass paste method to form a reference pressure cavity. Finally, the silicon piezoresistive pressure sensor chip is obtained by dicing.
[0027] Preferably, in step S2, the thickness of the silicon dioxide insulating layer is 1–3 μm.
[0028] Compared with existing technologies, the SOI wafer obtained by the intelligent stripping technology in this application has a relatively thicker silicon dioxide layer, which makes the chip have higher high temperature resistance. In addition, the silicon elastic diaphragm can prevent pressure from directly contacting the single crystal silicon sensitive resistor, which would cause chip failure due to long-term use. This structure can effectively solve the problems of short chip life and aging.
[0029] Typical pressure sensor chips can operate at a maximum temperature of 125°C, but the silicon piezoresistive pressure sensor chip with intelligent SOI wafer stripping described in this application can withstand operating temperatures up to 225°C, effectively preventing leakage current, protecting the diaphragm, and reducing the occurrence of failures. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the silicon piezoresistive pressure sensor chip of this application.
[0032] Figure 2 A schematic diagram of the structure of SOI wafers prepared using the smart stripping technology of this application.
[0033] Figure 3A schematic diagram of the structure of SOI wafers prepared using existing high-energy oxygen injection technology.
[0034] Figure 4 This is a schematic diagram of the structure of an existing piezoresistive pressure sensor chip.
[0035] Marker explanation:
[0036] 1. Silicon dioxide insulating layer; 2. Pressure-sensitive monocrystalline silicon; 3. Reference pressure chamber; 4. Cover wafer layer; 5. Ohmic contact metal layer; 6. Silicon elastic diaphragm; 7. Tapered wafer layer; 8. Pressure chamber under test; 9. Silicon dioxide layer; 10. Monocrystalline silicon layer; 11. Silicon substrate; 12. Pressure-sensitive resistor; 13. Substrate; 14. Lead; 15. Wire. Detailed Implementation
[0037] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0038] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Similar reference numerals and letters denote similar items in the following figures; therefore, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0039] like Figure 1As shown, this embodiment provides a silicon piezoresistive pressure sensing chip, including a tapered wafer layer 7, a silicon elastic diaphragm 6, a silicon dioxide insulating layer 1, a capping wafer layer 4, a pressure-sensitive monocrystalline silicon 2, and an ohmic contact metal layer 5; the silicon elastic diaphragm 6 is disposed above the tapered wafer layer 7; the silicon dioxide insulating layer 1 is mounted above the silicon elastic diaphragm 6; the capping wafer layer 4 is disposed on the silicon dioxide insulating layer 1, and a reference pressure cavity 3 is formed between the capping wafer layer 4 and the silicon dioxide insulating layer 1; the pressure-sensitive monocrystalline silicon 2 is mounted on the silicon dioxide insulating layer 1, and the pressure-sensitive monocrystalline silicon 2 is located inside the reference pressure cavity 3; the ohmic contact metal layer 5 is mounted on the silicon dioxide insulating layer, and the ohmic contact metal layer 5 is located outside the reference pressure cavity 3.
[0040] The silicon elastic diaphragm 6 can prevent the pressure source under test from directly contacting the pressure-sensitive monocrystalline silicon 2, thereby extending the service life of the pressure sensing chip.
[0041] The portion surrounded by the capping wafer layer 4 and the silicon dioxide insulating layer 1 is the reference pressure chamber 3, and the portion that enters through the conical wafer layer 7 and contacts the silicon elastic diaphragm 6 is the pressure chamber to be tested 8.
[0042] like Figure 2 As shown, the thickness of the ohmic contact metal layer 5 is 0.8μm-1.2μm, the thickness of the pressure-sensitive single-crystal silicon 2 is 0.32-0.7μm, and the thickness of the silicon dioxide insulating layer 1 is 1-3μm. The biggest advantage of this structure is that it can form a relatively thick silicon dioxide insulating layer 1, which also improves the high-temperature resistance of the chip.
[0043] like Figure 3 As shown, Figure 3 This diagram illustrates the structure of an SOI wafer fabricated using high-energy oxygen injection technology. The single-crystal silicon layer 10 has a thickness of 0.1 μm-0.3 μm, the silicon dioxide layer 9 has a thickness of 0.2 μm-0.5 μm, and the bottom layer is a silicon substrate 11. This technology is very expensive, and the resulting SOI structure has relatively thin insulating and top silicon layers, resulting in generally lower high-temperature resistance compared to SOI wafers fabricated using smart lift-off technology. Figure 3 The silicon dioxide layer 9 is the silicon dioxide insulating layer 1 of this application.
[0044] The silicon piezoresistive pressure sensing chip uses intelligent stripping technology to prepare the silicon dioxide insulating layer 1 of the SOI wafer, which is 2-6 times thicker than the silicon dioxide layer 9 prepared by high-energy oxygen ion implantation technology and can withstand higher temperatures.
[0045] In some preferred embodiments of this application, the reference pressure chamber 3 is filled with air or a vacuum. Depending on the actual situation, if the pressure chip is used for gauge pressure measurement, the reference pressure chamber 3 is filled with air; if the pressure chip is used for absolute pressure measurement, the reference pressure chamber 3 is filled with a vacuum.
[0046] exist Figure 4 middle, Figure 4 This diagram illustrates the structure of a typical piezoresistive pressure sensor chip. It includes pin 14, wire 15, pressure-sensitive resistor 12, and substrate 13. In this type of chip, the pressure source (gas or liquid) directly acts on the piezoresistive resistor to measure the pressure. However, in this case, the resistive element used for testing is prone to deformation or corrosion by certain liquids, leading to failure, short lifespan, and low durability.
[0047] In some preferred embodiments of this application, four resistors are disposed on the pressure-sensitive monocrystalline silicon 2, forming a Wheatstone bridge structure. The resistor strips are located at the edge of the silicon elastic diaphragm 6. When external pressure is applied to the silicon elastic diaphragm 6 through the pressure chamber 8, the stress at the edge changes from negative to positive. Utilizing the longitudinal and lateral piezoresistive effects of silicon resistors, by placing two pairs of resistors at the horizontal and vertical edges of the elastic diaphragm respectively, the resistance values of the two sets of resistors will change in opposite directions, forming a full-bridge circuit.
[0048] In some preferred embodiments of this application, the resistor has a width of 5μm-15μm and a length of 1000μm-1500μm.
[0049] This application also provides a method for fabricating a silicon piezoresistive pressure sensor chip as described in any of the above claims, comprising the following steps:
[0050] S1: A certain amount of H+ is injected into the silicon wafer covered with oxide layer to the required depth to obtain a two-layer structure of silicon dioxide insulating layer 1 and silicon substrate 11 with microcavities;
[0051] S2: On the two-layer structure obtained in step S1, it is bonded at low temperature to another silicon wafer covered with an oxide layer to obtain a three-layer structure of upper silicon substrate 11, silicon dioxide insulating layer 1, and lower silicon substrate 11.
[0052] S3: On the three-layer structure obtained in step S2, the silicon substrate 11 is annealed and peeled off to the hydrogen implantation position to obtain the SOI wafer structure.
[0053] S4: On the SOI wafer structure obtained in step S3, CMP polishing is used to obtain a smooth SOI wafer structure.
[0054] S5: On the SOI wafer structure obtained in step S4, the pressure-sensitive single crystal silicon 2 of the SOI wafer structure is etched into resistance strips distributed along the crystal orientation using a plasma etching method.
[0055] S6: On the SOI wafer structure obtained in step S5, a square deep groove is etched on the lower silicon wafer using the KOH etching method to obtain the silicon elastic film 6. In addition, the conical wafer layer 7 is also formed using the KOH etching method.
[0056] S7: On the SOI wafer structure obtained in step S6, the SOI wafer structure is directly bonded to the tapered wafer layer 7;
[0057] S8: On the SOI wafer structure obtained in step S7, a high-temperature resistant ohmic contact multilayer metal film is obtained on both sides above the SOI wafer structure by using a combination of vacuum sputtering and LIFT-OFF.
[0058] S9: On the SOI wafer structure obtained in step S8, the capping wafer is bonded to the SOI wafer structure using a glass paste method to form a reference pressure cavity 3. Finally, the silicon piezoresistive pressure sensor chip is obtained by dicing.
[0059] In some preferred embodiments of this application, in step S2, the thickness of the silicon dioxide insulating layer 1 is 1 to 3 μm.
[0060] Compared with the prior art, the SOI wafer obtained by the intelligent stripping technology in this application has a relatively thicker silicon dioxide layer 9, which makes the chip have higher high temperature resistance. In addition, the silicon elastic diaphragm 6 can prevent pressure from directly contacting the single crystal silicon sensitive resistor, which would cause the chip to break and fail after long-term use. This structure can effectively solve the problems of short chip life and aging.
[0061] Typical pressure sensor chips can operate at a maximum temperature of 125°C, but the silicon piezoresistive pressure sensor chip with intelligent SOI wafer stripping described in this application can withstand operating temperatures up to 225°C, effectively preventing leakage current, protecting the diaphragm, and reducing the occurrence of failures.
[0062] The above description is merely a specific embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should also be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A silicon piezoresistive pressure sensing chip, characterized in that, include: Conical wafer layer; A silicon elastic diaphragm is disposed above the tapered wafer layer; A silicon dioxide insulating layer is mounted on top of the silicon elastic diaphragm; A capping wafer layer is disposed on the silicon dioxide insulating layer, and a reference pressure cavity is provided between the capping wafer layer and the silicon dioxide insulating layer; Pressure-sensitive monocrystalline silicon, wherein the pressure-sensitive monocrystalline silicon is mounted on the silicon dioxide insulating layer and is located inside the reference pressure chamber; An ohmic contact metal layer is mounted on the silicon dioxide insulation and is located outside the reference pressure chamber; The thickness of the ohmic contact metal layer is 0.8μm-1.2μm, the thickness of the pressure-sensitive monocrystalline silicon is 0.32-0.7μm, and the thickness of the silicon dioxide insulating layer is 1-3μm.
2. The silicon piezoresistive pressure sensing chip according to claim 1, characterized in that, The reference pressure chamber is filled with air or a vacuum.
3. The silicon piezoresistive pressure sensing chip according to claim 1, characterized in that, Four resistors are disposed on the pressure-sensitive monocrystalline silicon, and the four resistors form a Wheatstone bridge structure.
4. The silicon piezoresistive pressure sensing chip according to claim 3, characterized in that, The resistor has a width of 5μm-15μm and a length of 1000μm-1500μm.
5. A method for fabricating a silicon piezoresistive pressure sensing chip as described in any one of claims 1-4, characterized in that, Including the following steps: S1: A certain amount of H+ is injected into the silicon wafer covered with an oxide layer to the required depth to obtain a two-layer structure of silicon dioxide insulating layer and silicon substrate with microcavities; S2: On the two-layer structure obtained in step S1, it is bonded to another silicon wafer covered with an oxide layer at low temperature to obtain a three-layer structure of upper silicon substrate, silicon dioxide insulating layer and lower silicon substrate. S3: On the three-layer structure obtained in step S2, the silicon substrate is annealed and peeled off to the hydrogen implantation position to obtain the SOI wafer structure; S4: On the SOI wafer structure obtained in step S3, CMP polishing is used to obtain a smooth SOI wafer structure. S5: On the SOI wafer structure obtained in step S4, the pressure-sensitive single crystal silicon of the SOI wafer structure is etched into resistance strips distributed along the crystal orientation using a plasma etching method. S6: On the SOI wafer structure obtained in step S5, a square deep trench is etched on the lower silicon wafer using the KOH etching method to obtain a silicon elastic film. In addition, the tapered wafer layer is also formed using the KOH etching method. S7: On the SOI wafer structure obtained in step S6, the SOI wafer structure is directly bonded to the tapered wafer layer; S8: On the SOI wafer structure obtained in step S7, a high-temperature resistant ohmic contact multilayer metal film is obtained on both sides above the SOI wafer structure by using a combination of vacuum sputtering and LIFT-OFF. S9: On the SOI wafer structure obtained in step S8, the capping wafer is bonded to the SOI wafer structure using a glass paste method to form a reference pressure cavity. Finally, the silicon piezoresistive pressure sensor chip is obtained by dicing.
6. The preparation method according to claim 5, characterized in that, In step S2, the thickness of the silicon dioxide insulating layer is 1–3 μm.
Citation Information
Patent Citations
High-temperature pressure sensor chip and preparation method thereof
CN112174085A