A four-stage pipelined stack processor

Abstract

The present invention provides a four-stage pipeline stack processor, which mainly includes four core modules: an instruction fetch stage, a decode stage, an execution stage, and a write-back stage. The instruction fetch stage module fetches the corresponding instruction from the instruction storage port according to the value of the program counter; the decode stage module decodes the instruction and extracts the immediate value, operand, and function code according to the instruction code; the execution stage module is responsible for performing corresponding arithmetic and logical operations, accessing the data storage port, determining the stack write enable, obtaining the stack pre-write value, calculating the stack pointer value, and performing pipeline flushing; and the write-back stage module is responsible for reading and writing the stack and updating the value of the top element and the stack pointer. Compared with traditional single-cycle stack processors, this processor achieves efficient instruction parallel processing capabilities, effectively improves the main frequency, and balances resource utilization and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of embedded microprocessors, in particular to a four-stage pipeline stack processor. Background Art

[0002] As computer applications continue to expand and develop, demands for processor performance, programmability, and flexibility are increasing. However, traditional embedded microprocessors typically employ register-based designs. While these designs offer advantages like high performance and out-of-order performance, they are difficult to design and manufacture due to the complexity of their instruction sets. In contrast, the J1 instruction set is currently used by many stack-based processors due to its simplicity, clarity, and ease of understanding and implementation.

[0003] However, despite their compact structure and high coupling, stack processors lack multi-stage pipeline processing, which limits the processor's operating frequency. Pipelining technology is a key means of improving processor performance. Currently, stack processors employing pipeline technology include two-stage and three-stage stack processors. However, these stack processors all employ a Harvard architecture, resulting in inefficient resource utilization. The shallower pipelines also result in a limited increase in frequency.

[0004] Therefore, there is an urgent need for a processor with improved main frequency and resource utilization. Summary of the Invention

[0005] In response to the problems of low main frequency and resource utilization of existing stack processors, the present invention provides a four-stage pipeline stack processor. The processor combines the characteristics of the stack processor and adopts the J1 instruction set and multi-stage pipeline structure, which is conducive to improving resource utilization and processor main frequency.

[0006] The present invention is achieved through the following solutions:

[0007] A four-stage pipeline stack processor comprising:

[0008] A memory including two ports, one for instruction storage and the other for data storage;

[0009] An instruction fetch module, configured to fetch corresponding instructions from an instruction storage port of the memory;

[0010] A decoding module, configured to extract corresponding immediate values, operands and function codes according to the instruction code corresponding to the corresponding instruction fetched by the instruction fetch module;

[0011] an execution-level module, configured to perform corresponding arithmetic and logical operations based on the immediate values, operands, and function codes extracted by the decoding-level module, access the data storage port of the memory, determine whether stack write is enabled, obtain a stack pre-write value, calculate a stack pointer value, and determine whether instructions that can generate jump behavior are eligible for pipeline flushing.

[0012] The write-back level module is used to receive the parameters passed by the execute / write-back pipeline register, determine the write enable of the data stack and the return stack, perform read and write operations, and update the value of the top element of the stack and the stack pointer;

[0013] Pipeline registers are used to temporarily store passed parameters to achieve parallel execution of instructions;

[0014] There are corresponding pipeline register connections between the instruction fetch level module, decoding level module, execution level module, and write-back level module, namely the instruction fetch / decoding pipeline register, decoding / execution pipeline register, and execution / write-back pipeline register.

[0015] Further, in the four-stage pipeline stack processor as described above, the instruction fetch stage module includes a program counter;

[0016] The program counter is used to give the instruction address of the current clock cycle according to the jump flag signal and the value of the program counter in the previous clock cycle; the instruction fetch module is used to fetch the corresponding instruction from the instruction storage port of the memory according to the value of the program counter;

[0017] The program counter is connected to the memory, and the memory is connected to the instruction fetch / decode pipeline register.

[0018] Furthermore, in the four-stage pipeline stack processor described above, the decoding stage module includes:

[0019] a multiplexer for receiving an instruction inputted by the instruction fetch / decode pipeline register, judging the instruction according to the instruction code type corresponding to the instruction, and outputting a unique selection value;

[0020] An instruction information extraction register is used to receive the instruction input from the instruction fetch / decode pipeline register, extract the immediate value, operand and function code of the instruction, and then store them and wait for the next clock cycle to be transmitted to the execution level module;

[0021] The outputs of the instruction fetch / decode pipeline register are respectively connected to the inputs of the multiplexer and the instruction information extraction register, and the outputs of the multiplexer and the instruction information extraction register are both connected to the input of the decode / execute pipeline register.

[0022] Furthermore, in the four-stage pipeline stack processor described above, the execution stage module includes:

[0023] an arithmetic logic unit, configured to receive a selection value of the decode / execute pipeline register and perform different arithmetic logic operations according to different selection values; the arithmetic logic operations include: addition, subtraction, multiplication, division, AND, OR, and NOT;

[0024] A stack operation unit, configured to determine the type of instruction and perform corresponding stack operations based on the selection value passed by the decode / execute pipeline register; the corresponding stack operations include: determining the data stack, returning a write enable signal of the stack, obtaining a stack pre-write value, and calculating a stack pointer value;

[0025] a control unit for determining whether a jump occurs based on a jump instruction; if the jump instruction selection value is valid and satisfies the jump condition, generating a jump flag signal and a jump address; and when the next clock cycle arrives, transmitting the jump flag signal to the instruction fetch / decode pipeline register, the decode / execute pipeline register, and the program counter, while also transmitting the jump address to the program counter; and the instruction fetch / decode pipeline register and the decode / execute pipeline register that receive the jump signal perform a no-operation to achieve pipeline flushing;

[0026] a memory access circuit, configured to determine whether a write enable signal of a data storage port of the memory is set high; if the write enable signal ram_wen is set high, then writing the next top element N of the data stack to the data storage port whose address is the top element T of the data stack; if the write enable signal ram_wen is set low, then performing no operation;

[0027] The output of the decoding / execution pipeline register is connected to the input of the arithmetic logic unit, the stack operation unit, the control unit, and the memory access circuit respectively;

[0028] The outputs of the arithmetic logic unit and the stack operation unit are both connected to the input of the execute / write-back pipeline register;

[0029] The output of the arithmetic logic unit is also connected to the input of the memory.

[0030] Furthermore, in the four-stage pipeline stack processor described above, the write-back stage module includes: a data stack, a return stack;

[0031] The data stack is used for temporarily storing variables and passing subroutine parameters;

[0032] The return stack is used to store the subroutine return address;

[0033] The output of the execute / write-back pipeline register is connected to the input of the data stack, return stack, and stack operation unit respectively;

[0034] The output of the data stack is connected to the input of the arithmetic logic unit and the memory respectively;

[0035] The output of the return stack is connected to the input of the arithmetic logic unit.

[0036] Furthermore, in the four-stage pipeline stack processor described above, the memory size is 32KB, and is addressed in word units, with a total of 16,384 units.

[0037] Furthermore, in the four-stage pipeline stack processor described above, the data stack and the return stack have the same size, a bit width of 16 bits, and a stack depth of 32 bits;

[0038] The top element of the data stack is T, the next top element is N, and the top element of the return stack is R.

[0039] Furthermore, in the four-stage pipeline stack processor described above, the immediate value includes the lower 15 bits of the Literal instruction;

[0040] The operands include jump addresses of Jump, ConditionalJump, and Call instructions;

[0041] The function code includes a stack function code and a mixed function code; the stack function code is used to adjust the stack top pointers of the parameter stack and the return stack; the mixed function code is used to execute some necessary functional operations.

[0042] Furthermore, in the four-stage pipeline stack processor described above, the multiplexer is a 5-to-1 multiplexer, which outputs a corresponding selection value sel according to the instruction code op of the received instruction, wherein the four types of instructions, Literal, Jump, ConditionalJump, and Call, have constant selection values; the selection value of ALU instructions depends on the value of the T' bit area of the ALU instructions; there are 16 selection values for ALU instructions, and only 1 selection value for other types of instructions.

[0043] Furthermore, in the four-stage pipeline stack processor as described above, the operands of the arithmetic logic unit include: the top element T of the data stack, the next top element N, the top element R of the return stack, and the output value [T]_ex of the decode / execute pipeline register (106);

[0044] The arithmetic logic unit reads the data in the data storage port of the memory, the reading address is the top element T of the data stack, the read data is [T], and after passing through the decoding / execution pipeline register, the final output value is [T]_ex;

[0045] The arithmetic logic unit transfers the execution result of the arithmetic logic operation to the execution / write-back pipeline register.

[0046] Compared with the prior art, the present invention has the following beneficial technical effects:

[0047] The four-stage pipeline stack processor provided by the present invention improves the resource utilization of the processor by designing the memory as a dual-port, one port for instruction storage and the other port for data storage; at the same time, the present invention divides the pipeline into four stages: instruction fetch, decoding, execution, and write back, and each stage executes in parallel. The four-stage pipeline stack processor is used to achieve the integration of multi-stage pipeline technology and the stack processor, thereby effectively improving the processor main frequency.

[0048] In addition, the four-stage pipeline stack processor provided by the present invention solves the pipeline risk problem, thereby making the execution process of the pipeline stack processor more stable, specifically:

[0049] Through memory, instructions and data share a memory, using dual-port RAM structure, taking advantage of memory characteristics to avoid pipeline structural risk problems;

[0050] Through the execution level module, data reading and writing operations are placed at the execution level, avoiding the data hazard problem of the pipeline.

[0051] The control unit performs a pipeline flush operation after encountering a jump instruction. Before the jump target instruction is executed, all operations executed in the pipeline are empty, thus avoiding pipeline control risk problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is the overall architecture diagram of the four-stage pipeline stack processor provided by the present invention;

[0053] Figure 2 1 is a schematic diagram illustrating the execution of a stack operation unit of a four-stage pipeline stack processor provided by the present invention;

[0054] Figure 3 This is a flow chart of the control unit processing of the four-stage pipeline stack processor provided by the present invention;

[0055] Figure 4 It is a pipeline flushing schematic diagram of the four-stage pipeline stack processor provided by the present invention;

[0056] Reference numerals:

[0057] 101-Program counter, 102-Memory, 103-Instruction fetch / decode pipeline register, 104-Decode multiplexer, 105-Instruction information extraction register, 106-Decode / execute pipeline register, 107-Arithmetic logic unit, 108-Stack operation unit, 109-Control unit, 110-Memory access circuit, 111-Execute / write-back pipeline register, 112-Data stack, 113 Return stack. DETAILED DESCRIPTION

[0058] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention are described clearly and completely below. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0059] The four-stage pipeline stack processor provided by the present invention is a four-stage pipeline J1 stack processor, which adopts the J1 instruction set. The instruction inst in the J1 instruction set has a word length of 16 bits and is divided into five categories of instructions: Literal, Jump, Conditional Jump, Call, and ALU.

[0060] Among them, the instruction code op of the Literal instruction is the 15th bit of the instruction, while the instruction code op of the Jump, Conditional Jump, Call, and ALU instructions is the 13th to 15th bits of the instruction.

[0061] Literal instructions are used to pass immediate values, where bits 0-14 are used to indicate the size of the immediate value, with a value range of 0-32767.

[0062] The Jump class instruction and ConditionalJump class belong to the jump class instruction. The Jump class instruction is a direct jump, and the ConditionalJump class instruction is a conditional jump. When the top element T of the parameter stack is 0, the jump occurs, otherwise there is no jump;

[0063] The Call instruction is a call instruction, which also belongs to the jump instruction. The instruction has two actions: one is to store the address of the instruction next to the Call instruction in the return stack, and the other is to jump to the target address;

[0064] The ALU instructions are used to perform arithmetic and logical operations, stack pointer adjustments, and other functional operations;

[0065] The three most significant bits of the four types of instructions, Jump, ConditionalJump, Call, and ALU, i.e., bits 13-15, are the instruction code. For Jump, ConditionalJump, and Call instructions, the remaining 13 bits are the jump target address, with a jump range of 0 to 8191. For ALU instructions, the remaining 13 bits are divided into different bit areas, each of which performs a different function.

[0066] In ALU instructions, when the 12th bit of the instruction is 1, the Return signal is set high, which will generate a jump behavior. The function is to assign the top element R of the return stack as the jump target address to the program counter PC. ALU instructions with the Return signal set high also belong to jump instructions, which match the Call instructions and are equivalent to the return operation of the Call instructions.

[0067] Jump, Conditional Jump, Call instructions, and ALU instructions with the Return signal set high are all jump instructions and can generate jumps. Bits 0-12 of Jump, Conditional Jump, and Call instructions represent the jump target address, and the jump range is 0-8191. Jump instructions are direct jumps, while Conditional Jump instructions are indirect jumps. The jump occurs when the top element T of the parameter stack is 0; otherwise, no jump occurs. Call instructions involve two actions: one is to store the address of the instruction following the Call instruction in the return stack, and the other is to jump to the target address. ALU instructions with the Return signal set high use the top element R of the return stack as the jump target address.

[0068] Bits 0-12 of ALU instructions are divided into multiple bit areas, each of which performs a different function.

[0069] Figure 1 This is the overall architecture diagram of the four-stage pipeline stack processor provided by the present invention, such as Figure 1 As shown, the pipeline of this four-stage pipeline stack processor is divided into four stages: instruction fetch, decode, execute, and writeback. The overall architecture includes an instruction fetch module, a decode module, an execute module, a writeback module, memory 102, a data stack 112, and a return stack 113. The instruction fetch module includes a program counter 101. The decode module includes a decode multiplexer 104 and an instruction information extraction register 105. The execute module includes an arithmetic logic unit 107, a stack operation unit 108, a control unit 109, and a memory access circuit 110.

[0070] The memory 102 includes two ports, one port is used for instruction storage and the other port is used for data storage; the instruction fetch module is used to fetch corresponding instructions from the instruction storage port of the memory 102.

[0071] The decoding module is used to extract the corresponding immediate value, operand and function code according to the instruction code corresponding to the corresponding instruction fetched by the instruction fetch module.

[0072] The execution level module is used to perform corresponding arithmetic and logical operations based on the immediate values, operands and function codes extracted by the decoding level module, access the data storage port of the memory 102, determine the stack write enable, obtain the stack pre-write value, calculate the stack pointer value, and at the same time determine the instructions that can generate jump behavior. If the requirements are met, the pipeline is flushed.

[0073] The write-back level module is used to receive the parameters passed by the execution / write-back pipeline register 111, determine the write enable of the data stack and the return stack, perform read and write operations, and update the value of the top element of the stack and the stack pointer.

[0074] There are corresponding pipeline register connections between the instruction fetch level module, decoding level module, execution level module, and write-back level module, namely the instruction fetch / decoding pipeline register 103, the decoding / execution pipeline register 106, and the execution / write-back pipeline register 111. The function of the pipeline register is to temporarily store the passed parameters.

[0075] The program counter 101 is used to provide the instruction address of the current clock cycle according to the jump flag signal and the value of the program counter in the previous clock cycle.

[0076] The instruction fetch module is used to fetch corresponding instructions from the instruction storage port of the memory 102 according to the value of the program counter 101 .

[0077] The multiplexer 104 is used to receive the instruction input from the instruction fetch / decode pipeline register 103, make a judgment based on the instruction code type corresponding to the instruction, and output a unique selection value.

[0078] The instruction information extraction register 105 is used to receive the instruction input by the instruction fetch / decode pipeline register 103, extract the immediate value, operand and function code of the instruction, and then store them and wait for the next clock cycle to be input to the execution level module.

[0079] The logic unit 107 is used to receive the selection value of the decoding / execution pipeline register 106 and perform different arithmetic and logical operations according to different selection values; the arithmetic and logical operations include: addition, subtraction, multiplication, division, AND, OR, and NOT.

[0080] The stack operation unit 108 is used to determine the type of instruction and perform corresponding stack operations based on the selection value passed by the decoding / execution pipeline register 106; the corresponding stack operations include determining the write enable signals of the data stack and the return stack, obtaining the stack pre-write value, and calculating the value of the stack pointer.

[0081] The control unit 109 is used to determine whether a jump occurs based on a jump instruction. If the jump instruction selection value is valid and meets the jump condition, a jump flag signal and a jump address are generated. When the next clock cycle arrives, the jump flag signal is transmitted to the instruction fetch / decode pipeline register 103, the decode / execute pipeline register 106 and the program counter 101, and the jump address is also transmitted to the program counter 101. The instruction fetch / decode pipeline register 103 and the decode / execute pipeline register 106 that receive the jump signal perform a no-operation to achieve pipeline flushing.

[0082] The memory access circuit 110 is used to determine whether the write enable signal of the data storage port of the memory 102 is set high; if the write enable signal ram_wen is set high, the next top element N of the data stack is written to the data storage port whose address is the top element T of the data stack; if the write enable signal ram_wen is set low, no operation is performed.

[0083] The write-back level module includes: a data stack 112 and a return stack 113; the data stack 112 is used for temporarily storing variables and subroutine parameter transfer; the return stack 113 is used for storing subroutine return addresses.

[0084] The output of the program counter 101 is connected to the input of the memory 102, the output of the memory 102 is connected to the input of the instruction fetch / decode pipeline register 103, the output of the instruction fetch / decode pipeline register 103 is respectively connected to the inputs of the decoding multiplexer 104 and the instruction information extraction register 105, the outputs of the decoding multiplexer 104 and the instruction information extraction register 105 are both connected to the input of the decoding / execution pipeline register 106, the output of the decoding / execution pipeline register 106 is respectively connected to the inputs of the arithmetic logic unit 107, the stack operation unit 108, the control unit 109, and the memory access circuit 110; the outputs of the arithmetic logic unit 107 and the stack operation unit 108 are both connected to the input of the execution / write-back pipeline register 111; the output of the arithmetic logic unit 107 is also connected to the input of the memory 102. The output of the control unit 109 is connected to the inputs of the decode / execute pipeline register 106, the instruction fetch / decode pipeline register 103, and the program counter 101. The output of the memory access circuit 110 is connected to the input of the memory 102. The output of the execute / write-back pipeline register 111 is connected to the inputs of the data stack 112, the return stack 113, and the stack operation unit 108. The output of the data stack 112 is connected to the inputs of the arithmetic logic unit 107 and the memory 102. The output of the return stack 113 is connected to the input of the arithmetic logic unit 107.

[0085] Furthermore, the memory 102 is logically a dual-port RAM, wherein one port is used for instruction storage and the other port is used for data storage. The size of the RAM is 32KB, each unit size is 2 bytes, and the RAM has 16384 units.

[0086] Furthermore, the program counter 101 contains selection logic. If the jump flag signal jump_flag is received, the value of pc is set to the jump address jump_addr. Otherwise, the value of pc is incremented by 1 to obtain the address of the instruction fetch. The program counter 101 fetches the instruction inst from the instruction storage port of the memory 102 as the instruction address. inst is stored in the instruction fetch / decode pipeline register 103 and is sent to the next level of the pipeline at the next clock cycle. The value of the program counter 101 is passed to the instruction storage port, which is used as the instruction address to fetch the corresponding instruction. The instruction storage port is only readable and cannot be written.

[0087] The decode multiplexer 104 is a 5-to-1 multiplexer that outputs a corresponding select value sel based on the instruction code op of the received instruction. The four instruction types (literal, jump, conditional jump, and call) have constant select values, while the select value for ALU instructions depends on the value of the T' bit field of the ALU instruction. ALU instructions have 16 select values, while other instruction types have only one. The instruction information extraction register 105 extracts information from the received instruction, including the immediate value of the literal instruction and the function code and operands of the ALU instruction. This extracted information is stored in the decode / execute pipeline register 106.

[0088] The operands of the arithmetic logic unit 107 include the top element T and the next top element N of the data stack, the top element R of the return stack, and the output value [T]_ex of the decoding / execution pipeline register 106. According to different selection values sel_ex, the arithmetic logic unit 107 performs different arithmetic logic operations, including a series of operations such as addition, subtraction, multiplication, division, and, or, and not. Among them, the data read operation requires reading the data in the data storage port. The read address is the top element T of the data stack, and the read data is [T]. After passing through the decoding / execution pipeline register 106, the final output value is [T]_ex. The execution result of the arithmetic logic operation is passed to the execution / write-back pipeline register 111.

[0089] The memory access circuit 110 is used to determine the write enable signal ram_wen of the data storage port. If the write enable signal ram_wen is set high, the data stack next top element N is written to the data storage port whose address is the data stack top element T. If the write enable signal ram_wen is set low, no operation is performed.

[0090] The stack operation unit 108 mainly performs a series of operations on the stack. According to the selection value sel_ex passed by the decode / execute pipeline register 106, it determines the type of instruction and performs the corresponding stack operation. The specific operations are as follows: Figure 2 As shown:

[0091] If the selected value is a Literal instruction, the data stack write enable is set high, and the pre-written data is the top element T of the data stack; the return stack write enable is set low, and the pre-written data is 0; the data stack top pointer is incremented by 1; the return stack top pointer remains unchanged;

[0092] If the selected value is a Jump instruction, the data stack write enable is set low, and the pre-written data is 0; the return stack write enable is set low, and the pre-written data is 0; the data stack top pointer remains unchanged; the return stack top pointer remains unchanged;

[0093] If the selected value is a ConditionalJump instruction, the data stack write enable is set low, and the pre-written data is 0; the return stack write enable is set low, and the pre-written data is 0; the data stack top pointer is decremented by 1; the return stack top pointer remains unchanged;

[0094] If the selected value is a Call instruction, the data stack write enable is set low and the pre-written data is 0; the return stack write enable is set high and the pre-written data is pc+1; the data stack top pointer remains unchanged; the return stack top pointer is incremented by 1;

[0095] If the selected value is an ALU type instruction, the data stack write enable depends on the second bit T→N signal of the mixed function code mix_ex[2:0]. If the T→N signal is set high, the data stack write enable is set high, and the pre-written data is the top element T of the data stack, otherwise it is all 0; the return stack write enable depends on the first bit T→R signal of the mixed function code mix_ex[2:0]. If the T→R signal is set high, the return stack write enable is set high, and the pre-written data is the top element R of the return stack, otherwise it is all 0; the data stack top pointer and the return stack top pointer depend on the stack function code value. The stack function code stack_ex[3:0] has a total of 4 bits, of which the upper two bits stack_ex[3:2] are used to adjust the return stack top pointer, and the lower two bits stack_ex[1:0] are used to adjust the data stack top pointer. Among them, the value 01 represents the stack top pointer plus 1, and 11 represents the stack top pointer minus 1.

[0096] The control unit 109 is used to determine whether a jump occurs. If the jump instruction selection value is valid and meets the jump condition, a jump flag signal jump_flag and a jump address jump_addr are generated. When the next clock cycle comes, the jump flag signal jump_flag is transmitted to the instruction fetch / decode pipeline register, the decode / execute pipeline register and the program counter, and the jump address jump_addr is also transmitted to the program counter.

[0097] The control unit 109 processes the flow chart as shown in FIG. Figure 3 As shown:

[0098] First, determine whether it is a Jump instruction. If it is a Jump instruction, set the jump flag signal high, and the jump address is the jump target address of the Jump instruction. If it is not a Jump instruction, determine whether it is a ConditionalJump instruction. If so, determine whether the top element T of the stack is 0. If T is 0, set the jump flag signal high, and the jump address is the jump target address of the ConditionalJump instruction. If T is not 0, set the jump flag signal low, and the jump address is 0. If it is not a ConditionalJump instruction, continue to determine whether it is a Call instruction. If so, set the jump flag signal high, and the jump address is the jump target address of the Call instruction. If not, determine whether it is an ALU instruction. If it is an ALU instruction, determine the jump flag signal and jump address based on whether the Return signal is high. If the Return signal is high, set the jump flag signal high, and the jump address is the top element R of the return stack. If the Return signal is set low, the jump flag signal is set low and the jump address is 0.

[0099] The four-stage pipeline stack processor provided by the present invention performs no operations on the pipeline register that receives the jump signal, while the program counter PC outputs the jump target address. In this way, from the instruction fetch of the jump instruction to the instruction fetch of the jump target instruction, the two instructions taken in the middle perform no operations, which can ensure the correctness of the instruction execution, thereby realizing the flushing of the pipeline.

[0100] The data stack 112 and return stack 113 have a width of 16 bits and a depth of 32 bits. After receiving a write enable signal from the decode / execute pipeline register 106, if the stack write enable is valid, the data stack 112 and return stack 113 perform a write operation on the stack, writing the top element values of the data stack and return stack to T_wb and R_wb, respectively. Simultaneously, the decode / execute pipeline register 106 sends the updated top-of-stack pointer to the stack operation unit 108.

[0101] The execution process of the four-stage pipeline stack processor provided by the present invention is as follows: first, the program counter output value pc is sent as an address to the memory instruction storage port, from which the instruction inst is taken out. At the same time, the top element T of the stack is also sent as an address to the memory data storage port, and the data [T] is taken out. Inst and [T] are stored in the instruction fetch / decode pipeline register 103. When the next clock cycle comes, it enters the decoding stage, and is processed by the decoding multiplexer 104 and the instruction information extraction register 105 to decode the selected value, immediate value, operand and function. Code, temporarily store this information in the decoding / execution pipeline register 106, wait until the next clock cycle comes, enter the execution level pipeline stage, perform corresponding arithmetic and logical operations, stack operations, jump operations according to the selection value sel_ex, perform data write operations according to the data storage port write enable ram_wen, and temporarily store the result after execution in the execution / write back pipeline register 111. Wait until the next clock cycle comes, enter the write back level pipeline stage, if the stack write enable is set high, write to the stack, and update the stack top pointer and the stack top element at the same time.

[0102] In a four-stage pipeline stack processor, the dual-port RAM allows instructions and data to be accessed simultaneously, avoiding pipeline structure hazard problems. Read and write operations are integrated into the execution level module to solve data hazard problems. Pipeline control hazard problems are solved using pipeline flushing technology, which is implemented by the control unit. The specific implementation is as follows: Figure 4 As shown:

[0103] When a jump instruction is read in the instruction fetch phase, the control unit 109 determines whether the jump condition is met during the jump instruction execution phase. If so, the corresponding jump flag signal jump_flag and jump address jump_addr are generated. The jump flag signal jump_flag will be transmitted to the instruction fetch / decode pipeline register 103 and the decode / execute pipeline register 106. After the instruction fetch / decode pipeline register 103 and the decode / execute pipeline register 106 receive the jump flag signal, a no-op operation of the Noop instruction is executed in the next clock cycle. Therefore, instruction 1 performs a no-op operation in the execution phase, and instruction 2 performs a no-op operation in the decode phase, which are equivalent to Noop instructions. At the same time, the jump flag signal jump_flag and the jump address jump_addr are also transmitted to the program counter 101, thereby obtaining the jump target instruction.

[0104] In summary, the four-stage pipeline stack processor provided by the present invention has simple control logic and strong coupling, while having a high main frequency and balancing resource utilization and power consumption. It should be pointed out that the above is only a preferred embodiment of the present invention and cannot be used to limit the scope of the present invention.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A four-stage pipeline stack processor, characterized in that: include: A memory (102), comprising two ports, one port for instruction storage and the other port for data storage; An instruction fetch module, configured to fetch a corresponding instruction from an instruction storage port of the memory (102); A decoding module, configured to extract corresponding immediate values, operands and function codes according to the instruction code corresponding to the corresponding instruction fetched by the instruction fetch module; An execution level module is used to perform corresponding arithmetic and logical operations based on the immediate value, operand and function code extracted by the decoding level module, access the data storage port of the memory (102), determine whether the stack write is enabled, obtain the stack pre-write value, calculate the stack pointer value, and determine the instructions that can generate jump behavior. If the instructions meet the requirements, the pipeline is flushed; A write-back level module is used to receive parameters passed by the execution / write-back pipeline register (111), determine the write enable of the data stack and the return stack, perform read and write operations, and update the value of the top element of the stack and the stack pointer; Pipeline registers are used to temporarily store passed parameters to achieve parallel execution of instructions; There are corresponding pipeline register connections between the instruction fetch level module, the decoding level module, the execution level module, and the write-back level module, namely the instruction fetch / decoding pipeline register (103), the decoding / execution pipeline register (106), and the execution / write-back pipeline register (111); The instruction fetch stage module includes a program counter (101); The program counter (101) is used to provide the instruction address of the current clock cycle according to the jump flag signal and the value of the program counter in the previous clock cycle; the instruction fetch module is used to fetch the corresponding instruction from the instruction storage port of the memory (102) according to the value of the program counter (101); The program counter (101) is connected to the memory (102), and the memory (102) is connected to the instruction fetch / decode pipeline register (103); The execution level module includes: an arithmetic logic unit (107) for receiving a selection value of the decoding / execution pipeline register (106) and performing different arithmetic logic operations according to different selection values; the arithmetic logic operations include: addition, subtraction, multiplication, division, AND, OR, and NOT; A stack operation unit (108) is used to determine the type of instruction and perform corresponding stack operations according to the selection value transmitted by the decoding / execution pipeline register (106); the corresponding stack operations include determining the write enable signals of the data stack and the return stack, obtaining the stack pre-write value, and calculating the value of the stack pointer; A control unit (109) is used to determine whether a jump occurs according to a jump instruction. If the jump instruction selection value is valid and the jump condition is satisfied, a jump flag signal and a jump address are generated. When the next clock cycle arrives, the jump flag signal is transmitted to the instruction fetch / decode pipeline register (103), the decode / execute pipeline register (106) and the program counter (101). At the same time, the jump address is also transmitted to the program counter (101). The instruction fetch / decode pipeline register (103) and the decode / execute pipeline register (106) that receive the jump signal perform a no-operation to achieve pipeline flushing. A memory access circuit (110) is used to determine whether a write enable signal of a data storage port of the memory (102) is set high; if the write enable signal ram_wen is set high, then the next top element N of the data stack is written to the data storage port whose address is the top element T of the data stack; if the write enable signal ram_wen is set low, then no operation is performed; The output of the decoding / execution pipeline register (106) is respectively connected to the input of the arithmetic logic unit (107), the stack operation unit (108), the control unit (109), and the memory access circuit (110); The outputs of the arithmetic logic unit (107) and the stack operation unit (108) are both connected to the input of the execution / write-back pipeline register (111); the output of the arithmetic logic unit (107) is also connected to the input of the memory (102); The output of the control unit (109) is connected to the input of the program counter (101).

2. The four-stage pipeline stack processor according to claim 1, wherein: The decoding level module includes: A multiplexer (104) is used to receive the instruction input from the instruction fetch / decode pipeline register (103), make a judgment based on the instruction code type corresponding to the instruction, and output a unique selection value; An instruction information extraction register (105) is used to receive the instruction inputted by the instruction fetch / decode pipeline register (103), extract the immediate value, operand and function code of the instruction, and then store them and wait for the next clock cycle to be inputted into the execution level module; The output of the instruction fetch / decode pipeline register (103) is connected to the input of the multiplexer (104) and the instruction information extraction register (105) respectively, and the output of the multiplexer (104) and the instruction information extraction register (105) are both connected to the input of the decode / execute pipeline register (106).

3. The four-stage pipeline stack processor according to claim 1, wherein: The write-back level module includes: a data stack (112), a return stack (113); The data stack (112) is used for temporarily storing variables and passing subroutine parameters; The return stack (113) is used to store the subroutine return address; The output of the execute / write-back pipeline register (111) is connected to the input of the data stack (112), the return stack (113), and the stack operation unit (108) respectively; The output of the data stack (112) is connected to the input of the arithmetic logic unit (107) and the memory (102) respectively; The output of the return stack (113) is connected to the input of the arithmetic logic unit (107).

4. The four-stage pipeline stack processor according to claim 1, wherein: The memory (102) has a size of 32KB and is addressed in word units, with a total of 16,384 units.

5. The four-stage pipeline stack processor according to claim 4, wherein: The data stack (112) is the same size as the return stack (113), with a bit width of 16 bits and a stack depth of 32; The top element of the data stack (112) is T, the next top element is N, and the top element of the return stack is R.

6. The four-stage pipeline stack processor according to claim 3, wherein: The immediate value includes the lower 15 bits of the Literal instruction; The operands include jump addresses of Jump, ConditionalJump, and Call instructions; The function code includes a stack function code and a mixed function code; the stack function code is used to adjust the stack top pointer of the parameter stack and the return stack; The mixed function code is used to execute some necessary functional operations.

7. The four-stage pipeline stack processor according to claim 2, wherein: The multiplexer (104) is a 5-to-1 multiplexer, which outputs a corresponding selection value sel according to the instruction code op of the received instruction, wherein the four types of instructions, Literal, Jump, Conditional Jump, and Call, have constant selection values; the selection value of ALU instructions depends on the value of the T' bit area of the ALU instructions; the selection values of ALU instructions are 16, and the selection values of other types of instructions are only 1.

8. The four-stage pipeline stack processor according to claim 1, wherein: The operands of the arithmetic logic unit (107) include: the top element T of the data stack, the next top element N, the top element R of the return stack, and the output value [T]_ex of the decode / execute pipeline register (106); The arithmetic logic unit (107) reads data from the data storage port of the memory (102), the read address is the top element T of the data stack, the read data is [T], and after passing through the decoding / execution pipeline register (106), the final output value is [T]_ex; The arithmetic logic unit (107) transfers the execution result of the arithmetic logic operation to the execution / write-back pipeline register (111).

Images