Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: providing an upper wafer and a lower wafer; forming a groove in the edge region of the upper wafer; forming a first insulating dielectric layer covering the upper wafer, and the first insulating dielectric layer seals the groove so that the groove forms a hollow structure; bonding the side of the first insulating dielectric layer away from the upper wafer to the lower wafer; and thinning the side of the upper wafer away from the lower wafer. The technical solution of the present invention makes it possible to avoid the edge collapse problem during the thinning process from affecting the internal devices of the wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] To meet the needs of advanced IC packaging, the thickness of each layer of chips in the stack inevitably needs to be thinned while the overall thickness of the package remains unchanged or even decreases. In the traditional wafer thinning process, the wafer is firstly rough-ground to a certain thickness using a diamond grinding wheel, and then fine-ground by chemical mechanical grinding or wet etching.

[0003] However, during the wafer thinning process, the edges of the bonding interface often collapse, causing devices in the collapsed area of ​​the thinned wafer to be exposed, which in turn leads to problems such as bubbles in the photoresist, arc discharge during dry etching, and particle contamination of the exposed devices by wet etching in subsequent processes.

[0004] Therefore, how to prevent the edge collapse problem during the thinning process from affecting the internal devices of the wafer is an urgent problem that needs to be solved. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to avoid the edge collapse problem in the thinning process from affecting the internal devices of the wafer.

[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing an upper wafer and a lower wafer;

[0008] forming a groove at an edge region of the upper wafer;

[0009] Forming a first insulating medium layer to cover the upper wafer, and the first insulating medium layer seals the groove so that the groove forms a hollow structure;

[0010] Bonding a side of the first insulating dielectric layer away from the upper wafer to the lower wafer;

[0011] The upper wafer is thinned at a side away from the lower wafer.

[0012] Optionally, the first insulating medium layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure.

[0013] Optionally, before forming the first insulating dielectric layer to cover the upper wafer, the method for manufacturing the semiconductor device further includes:

[0014] A first trimming process is performed to remove a portion of the edge region of the upper wafer located outside the groove and / or a portion of the edge region of the lower wafer bonded to the upper wafer located outside the corresponding position of the groove.

[0015] Optionally, the groove is formed in the edge area of ​​the upper wafer by using a laser process or an etching process.

[0016] Optionally, before bonding the side of the first insulating dielectric layer away from the upper wafer to the lower wafer, the method for manufacturing the semiconductor device further includes:

[0017] Planarizing a side of the first insulating dielectric layer away from the upper wafer;

[0018] Alternatively, forming a metal layer in the first insulating dielectric layer;

[0019] The first insulating dielectric layer and the metal layer are planarized on a side away from the upper wafer.

[0020] Optionally, the upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer; the step of thinning a side of the upper wafer away from the lower wafer includes:

[0021] The side of the substrate away from the second insulating dielectric layer is thinned.

[0022] Optionally, the depth to which the groove extends into the substrate is greater than or equal to the thickness of the substrate remaining after thinning a side of the substrate away from the second insulating dielectric layer.

[0023] Optionally, after thinning the side of the upper wafer away from the lower wafer, the method for manufacturing the semiconductor device further comprises:

[0024] A second trimming process is performed to remove edge regions of the upper wafer and the lower wafer located at the periphery of the groove on one side close to the center of the upper wafer.

[0025] Optionally, the groove is a closed or discontinuous annular groove.

[0026] The present invention also provides a semiconductor device manufactured by adopting the manufacturing method of the semiconductor device.

[0027] The present invention also provides a semiconductor device, characterized in that it comprises:

[0028] upper wafer;

[0029] A groove is formed in an edge region of the upper wafer;

[0030] The first insulating medium layer covers the upper wafer, and the first insulating medium layer seals the groove to form a hollow structure of the groove.

[0031] Optionally, the first insulating medium layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure.

[0032] Optionally, the upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer.

[0033] Optionally, the groove is a closed or discontinuous annular groove.

[0034] Optionally, the semiconductor device further includes:

[0035] A lower wafer is bonded to a side of the first insulating medium layer away from the upper wafer.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] 1. The manufacturing method of the semiconductor device of the present invention provides an upper wafer and a lower wafer; forms a groove in the edge area of ​​the upper wafer; forms a first insulating dielectric layer covering the upper wafer, and the first insulating dielectric layer seals the groove so that the groove forms a hollow structure; bonds the side of the first insulating dielectric layer away from the upper wafer to the lower wafer; thins the side of the upper wafer away from the lower wafer, and the groove is arranged in a hollow structure so that the edge collapse problem during the thinning process can be avoided to affect the internal devices of the wafer.

[0038] 2. The semiconductor device of the present invention is manufactured by the semiconductor device manufacturing method, so that the edge collapse problem in the thinning process can be avoided to affect the internal devices of the wafer.

[0039] 3. The semiconductor device of the present invention comprises: an upper wafer; a groove formed in the edge area of ​​the upper wafer; a first insulating medium layer covering the upper wafer, and the first insulating medium layer seals the groove to form a hollow structure. The groove having a hollow structure can avoid the edge collapse problem during the thinning process from affecting the internal devices of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0041] Figure 2a to Figure 2i yes Figure 1 A schematic diagram of a device in a method for manufacturing a semiconductor device shown;

[0042] Figure 3 yes Figure 2d A schematic top view of a semiconductor device is shown.

[0043] Among them, Figure 1 to Figure 3 The reference numerals are described as follows:

[0044] 11-first substrate; 12-second insulating dielectric layer; 121-first metal interconnection structure; 13-groove; 14-first insulating dielectric layer; 15-first metal layer; 21-second substrate; 22-third insulating dielectric layer; 221-second metal interconnection structure; 231-fourth insulating dielectric layer; 232-second metal layer. DETAILED DESCRIPTION

[0045] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0046] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 ,from Figure 1 It can be seen that the method for manufacturing the semiconductor device includes:

[0047] Step S1, providing an upper wafer and a lower wafer;

[0048] Step S2, forming a groove in the edge area of ​​the upper wafer;

[0049] Step S3, forming a first insulating dielectric layer to cover the upper wafer, and the first insulating dielectric layer seals the groove to form a hollow structure of the groove;

[0050] Step S4, bonding a surface of the first insulating dielectric layer away from the upper wafer to the lower wafer;

[0051] Step S5, thinning a side of the upper wafer away from the lower wafer.

[0052] See below Figure 2a to Figure 2i and Figure 3 The method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 2a to Figure 2i It is also a longitudinal cross-sectional schematic diagram.

[0053] According to step S1, an upper wafer and a lower wafer are provided.

[0054] The upper wafer may be a device wafer or a carrier wafer, and the lower wafer may be a device wafer or a carrier wafer.

[0055] The device wafer can be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or a MOSFET wafer or an IGBT wafer containing a power device, or a passive device wafer, etc. The type of the device wafer depends on the function of the device to be ultimately manufactured.

[0056] The carrier wafer may not include a functional structure; or, the carrier wafer may include a functional structure, and the functional structure is located inside the carrier wafer rather than on the surface of the carrier wafer.

[0057] like Figure 2a As shown, the upper wafer includes a substrate (in order to distinguish it from the substrate in the lower wafer, the substrate in the upper wafer is defined as a first substrate 11, and the substrate in the lower wafer is defined as a second substrate 21) and a second insulating dielectric layer 12 formed on the first substrate 11, and a first metal interconnection structure 121 etc. may be formed in the second insulating dielectric layer 12; Figure 2b As shown, the lower wafer includes a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21 , and a second metal interconnection structure 221 and the like may be formed in the third insulating dielectric layer 22 .

[0058] According to step S2, Figure 2d As shown, a groove 13 is formed in the edge area of ​​the upper wafer.

[0059] The groove 13 may be formed in the edge region of the upper wafer by using a laser process or an etching process, and the depth and width of the groove 13 may be adjusted by adjusting parameters of the laser process or the etching process.

[0060] The groove 13 is recessed from the second insulating dielectric layer 12 and penetrates the second insulating dielectric layer 12 to further extend into the first substrate 11; preferably, the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after subsequently thinning the side of the first substrate 11 away from the second insulating dielectric layer 12.

[0061] For example, when the thickness of the first substrate 11 remaining after the first substrate 11 away from the second insulating dielectric layer 12 is subsequently thinned to 14 microns, the depth of the groove 13 extending into the first substrate 11 may be greater than or equal to 14 microns.

[0062] Preferably, Figure 3 As shown, the groove 13 is a closed annular groove, so that the groove 13 can completely block cracks and chipping edges outside the groove 13. In other embodiments, the groove 13 can also be an intermittent annular groove. It should be noted that Figure 3 yes Figure 2d The schematic top view of the semiconductor device shown in FIG. 1 is used to more clearly illustrate the position of the groove 13. Figure 3 The first substrate 11 at the bottom of the groove 13 is not shown.

[0063] Preferably, before subsequently forming a first insulating dielectric layer 14 to cover the upper wafer, the method for manufacturing the semiconductor device may further include: performing a first trimming process to remove a portion of the edge area of ​​the upper wafer located outside the groove 13 and / or a portion of the edge area of ​​the lower wafer located outside the corresponding position of the groove 13 after subsequent bonding with the upper wafer.

[0064] Since the edges of the surfaces to be bonded of the upper wafer and the lower wafer are uneven when the upper wafer and the lower wafer are manufactured, the uneven areas of the edges of the surfaces to be bonded of the upper wafer and / or the lower wafer can be removed by performing the first trimming process before bonding the upper wafer and / or the lower wafer, so that the surfaces to be bonded of the upper wafer and / or the lower wafer are flat after the first trimming process, thereby enhancing the bonding force between the upper wafer and the lower wafer after subsequent bonding.

[0065] Wherein, when performing the first trimming process, it is possible to trim from a partial edge area of ​​the second insulating dielectric layer 12 outside the groove 13 to a partial edge area of ​​the first substrate 11 of partial thickness or full thickness, and / or, trim from a partial edge area of ​​the third insulating dielectric layer 22 outside the corresponding position of the groove 13 to a partial edge area of ​​the second substrate 21 of partial thickness or full thickness. Figure 2c The embodiment shown is to trim the partial edge area of ​​the second insulating medium layer 12 from the periphery of the groove 13 to the partial edge area of ​​the first substrate 11 of partial thickness, that is, the partial edge area of ​​the first substrate 11 of partial thickness is retained and not removed.

[0066] Moreover, in one embodiment, after performing the first trimming process, an insulating dielectric layer may be formed on the bonding surface of the upper wafer and / or the lower wafer to make the bonding surface of the upper wafer and / or the lower wafer smoother.

[0067] In addition, the edge regions of the upper wafer and the lower wafer are non-chip regions located at the edges of the upper wafer and the lower wafer, respectively.

[0068] According to step S3, Figure 2e As shown, a first insulating dielectric layer 14 is formed to cover the upper wafer, and the first insulating dielectric layer 14 seals the groove 13 so that the groove 13 forms a hollow structure. The first insulating dielectric layer 14 covers the second insulating dielectric layer 12 .

[0069] The first insulating dielectric layer 14 may be formed by a chemical vapor deposition process.

[0070] Since the width of the groove 13 is very small, the groove 13 can be sealed in advance, and the first insulating medium layer 14 is only formed in a small amount on the inner wall of the groove 13, or the first insulating medium layer 14 is not formed in the groove 13 at all, that is, the first insulating medium layer 14 does not fill the groove 13, so that the groove 13 forms a hollow structure.

[0071] In addition, before subsequently bonding the side of the first insulating dielectric layer 14 away from the upper wafer to the lower wafer, the method for manufacturing the semiconductor device may further include: planarizing the side of the first insulating dielectric layer 14 away from the upper wafer. Alternatively, the method for manufacturing the semiconductor device may further include: Figure 2f As shown, a first metal layer 15 is formed in the first insulating dielectric layer 14, and the first metal layer 15 can be electrically connected to the first metal interconnect structure 121; and the first insulating dielectric layer 14 and the first metal layer 15 are planarized on a side away from the upper wafer.

[0072] Furthermore, before subsequently bonding the side of the first insulating dielectric layer 14 away from the upper wafer to the lower wafer, the method for manufacturing the semiconductor device may further include: forming a fourth insulating dielectric layer 231 on the lower wafer, and planarizing the side of the fourth insulating dielectric layer 231 away from the lower wafer. Alternatively, the method for manufacturing the semiconductor device may further include: Figure 2bAs shown, a fourth insulating dielectric layer 231 is formed on the lower wafer; a second metal layer 232 is formed in the fourth insulating dielectric layer 231, and the second metal layer 232 can be electrically connected to the second metal interconnect structure 221; and the fourth insulating dielectric layer 231 and the second metal layer 232 are planarized on a side away from the lower wafer.

[0073] According to step S4, Figure 2g As shown, the side of the first insulating dielectric layer 14 away from the upper wafer is bonded to the lower wafer.

[0074] Among them, if the first metal layer 15 is not formed in the first insulating dielectric layer 14, and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding of the upper wafer and the lower wafer is achieved by melt bonding between the side of the first insulating dielectric layer 14 away from the upper wafer and the side of the fourth insulating dielectric layer 231 away from the lower wafer; if the first metal layer 15 is formed in the first insulating dielectric layer 14, and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, as Figure 2g As shown, the bonding between the upper wafer and the lower wafer is achieved by hybrid bonding between a side of the first insulating dielectric layer 14 away from the upper wafer and a side of the fourth insulating dielectric layer 231 away from the lower wafer.

[0075] According to step S5, Figure 2h As shown, the side of the upper wafer away from the lower wafer is thinned.

[0076] The steps include: thinning the side of the first substrate 11 away from the second insulating dielectric layer 12. The first substrate 11 may be quickly and roughly ground to a certain thickness using a diamond grinding wheel, and then finely ground using chemical mechanical grinding or wet etching.

[0077] In the process of thinning the side of the upper wafer away from the lower wafer, cracks and edge collapse are likely to occur at the edge of the upper wafer starting from the bonding interface. However, the present invention forms the hollow groove 13 in the edge area of ​​the upper wafer, so that cracks and edge collapse only occur in the edge area outside the groove 13 (such as Figure 2hThe hollow portion in the groove 13 can prevent cracks and edge collapse from extending into the area surrounded by the groove 13, thereby preventing the devices in the area surrounded by the groove 13 from being exposed and affecting the devices inside the wafer. Furthermore, when the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after thinning the side of the first substrate 11 away from the second insulating dielectric layer 12, the side of the first substrate 11 away from the second insulating dielectric layer 12 after thinning can expose the groove 13, that is, the first substrate 11 within the thickness range where the groove 13 is not formed is thinned and removed, thereby further ensuring that no cracks and edge collapse are generated in the area surrounded by the groove 13 after thinning.

[0078] In addition, after thinning the side of the upper wafer away from the lower wafer, the method for manufacturing the semiconductor device may further include: Figure 2i As shown, a second trimming process is performed to remove the edge areas of the upper wafer and the lower wafer located on the periphery of the groove 13 close to the center of the upper wafer, so as to remove the edge areas of the upper wafer and the lower wafer with more defects.

[0079] When performing the second trimming process, the edge area of ​​the upper wafer at the periphery of the groove 13 close to the center of the upper wafer can be trimmed to the edge area of ​​the lower wafer of partial thickness or full thickness. Figure 2i The embodiment shown is that the edge area of ​​the upper wafer on the periphery of the groove 13 close to the center of the upper wafer is trimmed to the edge area of ​​the second substrate 21 of partial thickness of the lower wafer, that is, the edge area of ​​the second substrate 21 of partial thickness is retained and not removed.

[0080] In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing an upper wafer and a lower wafer; forming a groove in the edge area of ​​the upper wafer; forming a first insulating dielectric layer covering the upper wafer, and the first insulating dielectric layer seals the groove so that the groove forms a hollow structure; bonding the side of the first insulating dielectric layer away from the upper wafer to the lower wafer; and thinning the side of the upper wafer away from the lower wafer. In the method for manufacturing a semiconductor device of the present invention, the provision of the groove of the hollow structure can prevent the edge collapse problem during the thinning process from affecting the internal devices of the wafer.

[0081] An embodiment of the present invention provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method.

[0082] like Figure 2iAs shown, the semiconductor device includes an upper wafer and a lower wafer. The upper wafer is covered with a first insulating dielectric layer 14. The first insulating dielectric layer 14 is bonded to the lower wafer at a side away from the upper wafer.

[0083] The upper wafer includes a first substrate 11 and a second insulating dielectric layer 12 formed on the first substrate 11, and a first metal interconnection structure 121 and the like may be formed in the second insulating dielectric layer 12, and the first insulating dielectric layer 14 covers the second insulating dielectric layer 12; the lower wafer includes a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21, and a second metal interconnection structure 221 and the like may be formed in the third insulating dielectric layer 22.

[0084] like Figure 2i As shown, a first metal layer 15 may be formed in the first insulating dielectric layer 14, and the first metal layer 15 may be electrically connected to the first metal interconnect structure 121. In other embodiments, the first metal layer 15 may not be formed in the first insulating dielectric layer 14.

[0085] like Figure 2i As shown, the semiconductor device may further include: a fourth insulating dielectric layer 231 and a second metal layer 232, wherein the fourth insulating dielectric layer 231 is formed on the lower wafer, the fourth insulating dielectric layer 231 covers the third insulating dielectric layer 22, the second metal layer 232 is formed in the fourth insulating dielectric layer 231, and the second metal layer 232 may be electrically connected to the second metal interconnect structure 221. In other embodiments, the second metal layer 232 may not be formed in the fourth insulating dielectric layer 231.

[0086] Among them, if the first metal layer 15 is not formed in the first insulating dielectric layer 14, and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding of the upper wafer and the lower wafer is achieved by melt bonding between the side of the first insulating dielectric layer 14 away from the upper wafer and the side of the fourth insulating dielectric layer 231 away from the lower wafer; if the first metal layer 15 is formed in the first insulating dielectric layer 14, and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, as Figure 2i As shown, the bonding between the upper wafer and the lower wafer is achieved by hybrid bonding between a side of the first insulating dielectric layer 14 away from the upper wafer and a side of the fourth insulating dielectric layer 231 away from the lower wafer.

[0087] The upper wafer may be a device wafer or a carrier wafer, and the lower wafer may be a device wafer or a carrier wafer.

[0088] The device wafer can be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or a MOSFET wafer or an IGBT wafer containing a power device, or a passive device wafer, etc. The type of the device wafer depends on the function of the device to be ultimately manufactured.

[0089] The carrier wafer may not include a functional structure; or, the carrier wafer may include a functional structure, and the functional structure is located inside the carrier wafer rather than on the surface of the carrier wafer.

[0090] Since the semiconductor device is manufactured by the method for manufacturing the semiconductor device, it is possible to avoid the edge collapse problem in the thinning process affecting the internal devices of the wafer.

[0091] An embodiment of the present invention provides a semiconductor device, which includes: an upper wafer; a groove formed in an edge area of ​​the upper wafer; a first insulating medium layer covering the upper wafer, and the first insulating medium layer seals the groove to form a hollow structure.

[0092] See below Figure 2e to Figure 2g The semiconductor device provided in this embodiment is described in detail.

[0093] The upper wafer includes a substrate (in order to distinguish it from the substrate in the lower wafer, the substrate in the upper wafer is defined as a first substrate 11, and the substrate in the lower wafer is defined as a second substrate 21) and a second insulating dielectric layer 12 formed on the first substrate 11, and a first metal interconnection structure 121, etc. can be formed in the second insulating dielectric layer 12.

[0094] The groove 13 is formed at the edge region of the upper wafer.

[0095] The groove 13 is recessed from the second insulating dielectric layer 12 and penetrates the second insulating dielectric layer 12 to further extend into the first substrate 11. Preferably, the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after a subsequent process of thinning a side of the first substrate 11 away from the second insulating dielectric layer 12 is performed.

[0096] For example, when the thickness of the first substrate 11 remaining after the first substrate 11 away from the second insulating dielectric layer 12 is subsequently thinned to 14 microns, the depth of the groove 13 extending into the first substrate 11 may be greater than or equal to 14 microns.

[0097] Preferably, the groove 13 is a closed annular groove, so that the groove 13 can completely block cracks and chipping generated in the subsequent process of thinning the first substrate 11 at the periphery of the groove 13. In other embodiments, the groove 13 can also be a discontinuous annular groove.

[0098] The first insulating dielectric layer 14 covers the upper wafer, and the first insulating dielectric layer 14 seals the groove 13 so that the groove 13 forms a hollow structure. The first insulating dielectric layer 14 covers the second insulating dielectric layer 12 .

[0099] The first insulating medium layer 14 is only slightly formed on the inner wall of the groove 13 , or the first insulating medium layer 14 is not formed in the groove 13 at all, that is, the first insulating medium layer 14 does not fill the groove 13 , so that the groove 13 forms a hollow structure.

[0100] like Figure 2f As shown, the semiconductor device may further include: a first metal layer 15 formed in the first insulating dielectric layer 14, and the first metal layer 15 may be electrically connected to the first metal interconnection structure 121. Figure 2e In the illustrated embodiment, the first metal layer 15 may not be formed in the first insulating dielectric layer 14 .

[0101] like Figure 2g As shown, the semiconductor device may further include: a lower wafer, wherein the lower wafer is bonded to a side of the first insulating dielectric layer 14 away from the upper wafer.

[0102] The upper wafer may be a device wafer or a carrier wafer, and the lower wafer may be a device wafer or a carrier wafer.

[0103] The device wafer can be a pixel wafer containing a pixel array of an image sensor, or a MEMS wafer containing a MEMS microstructure of a MEMS device, or a MOSFET wafer or an IGBT wafer containing a power device, or a passive device wafer, etc. The type of the device wafer depends on the function of the device to be ultimately manufactured.

[0104] The carrier wafer may not include a functional structure; or, the carrier wafer may include a functional structure, and the functional structure is located inside the carrier wafer rather than on the surface of the carrier wafer.

[0105] The lower wafer includes a second substrate 21 and a third insulating dielectric layer 22 formed on the second substrate 21 . A second metal interconnection structure 221 and the like may be formed in the third insulating dielectric layer 22 .

[0106] like Figure 2g As shown, the semiconductor device may further include: a fourth insulating dielectric layer 231 and a second metal layer 232, wherein the fourth insulating dielectric layer 231 is formed on the lower wafer, the fourth insulating dielectric layer 231 covers the third insulating dielectric layer 22, the second metal layer 232 is formed in the fourth insulating dielectric layer 231, and the second metal layer 232 may be electrically connected to the second metal interconnect structure 221. In other embodiments, the second metal layer 232 may not be formed in the fourth insulating dielectric layer 231.

[0107] Among them, if the first metal layer 15 is not formed in the first insulating dielectric layer 14, and the second metal layer 232 is not formed in the fourth insulating dielectric layer 231, the bonding of the upper wafer and the lower wafer is achieved by melt bonding between the side of the first insulating dielectric layer 14 away from the upper wafer and the side of the fourth insulating dielectric layer 231 away from the lower wafer; if the first metal layer 15 is formed in the first insulating dielectric layer 14, and the second metal layer 232 is formed in the fourth insulating dielectric layer 231, as Figure 2g As shown, the bonding between the upper wafer and the lower wafer is achieved by hybrid bonding between a side of the first insulating dielectric layer 14 away from the upper wafer and a side of the fourth insulating dielectric layer 231 away from the lower wafer.

[0108] Preferably, part of the edge area of ​​the upper wafer located outside the groove 13 and / or part of the edge area of ​​the lower wafer located outside the corresponding position of the groove 13 can be trimmed and removed, so that the edge area of ​​the upper wafer located outside the groove 13 and / or the edge area of ​​the lower wafer located outside the corresponding position of the groove 13 are shrunk. Figure 2e to Figure 2g In the illustrated embodiment, the second insulating dielectric layer 12 and the edge region of the first substrate 11 located at the periphery of the groove 13 near the partial thickness of the second insulating dielectric layer 12 are retracted relative to the partial thickness of the first substrate 11 away from the second insulating dielectric layer 12 .

[0109] Since the edges of the surfaces to be bonded of the upper wafer and the lower wafer are uneven when the upper wafer and the lower wafer are manufactured, before bonding the upper wafer to the lower wafer, the uneven areas of the edges of the surfaces to be bonded of the upper wafer and / or the lower wafer are removed to make the surfaces to be bonded of the upper wafer and / or the lower wafer flat, thereby enhancing the bonding force between the upper wafer and the lower wafer after bonding.

[0110] The edge regions of the upper wafer and the lower wafer are non-chip regions located at the edges of the upper wafer and the lower wafer, respectively.

[0111] Since in the process of thinning the side of the upper wafer away from the lower wafer, cracks and edge collapse are likely to occur on the edge of the upper wafer starting from the bonding interface, in the present invention, since a hollow groove 13 is formed in the edge area of ​​the upper wafer, cracks and edge collapse generated during the thinning process will only occur in the edge area around the groove 13, and the hollow part in the groove 13 can prevent cracks and edge collapse from extending into the area surrounded by the groove 13, thereby preventing the devices in the area surrounded by the groove 13 from being exposed and affecting the internal devices of the wafer. Moreover, when the depth of the groove 13 extending into the first substrate 11 is greater than or equal to the thickness of the first substrate 11 remaining after thinning the side of the first substrate 11 away from the second insulating dielectric layer 12, the side of the first substrate 11 away from the second insulating dielectric layer 12 after thinning can expose the groove 13, that is, the first substrate 11 within the thickness range where the groove 13 is not formed is thinned and removed, thereby further ensuring that cracks and edge collapse are not generated in the area surrounded by the groove 13 after thinning.

[0112] In summary, the present invention provides a semiconductor device, comprising: an upper wafer; a groove formed in the edge region of the upper wafer; a first insulating dielectric layer covering the upper wafer, and the first insulating dielectric layer seals the groove so that the groove forms a hollow structure. In the semiconductor device of the present invention, the setting of the groove of the hollow structure can prevent the edge collapse problem during the thinning process from affecting the internal devices of the wafer.

[0113] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing an upper wafer and a lower wafer; Forming a groove in the edge area of ​​the upper wafer, and performing a first trimming process to remove a portion of the edge area of ​​the upper wafer located outside the groove; Forming a first insulating medium layer to cover the upper wafer, and the first insulating medium layer seals the groove so that the groove forms a hollow structure; Melt-bonding or hybrid-bonding a side of the first insulating dielectric layer away from the upper wafer to the lower wafer; The side of the upper wafer away from the lower wafer is thinned, and the groove is used to prevent cracks and chipping generated from the bonding interface between the first insulating medium layer and the lower wafer during the thinning process from extending into the area surrounded by the groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating medium layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the first insulating dielectric layer to cover the upper wafer, the method for manufacturing the semiconductor device further includes: A first trimming process is performed to remove a portion of the edge region of the lower wafer bonded to the upper wafer, which is located at the periphery of the position corresponding to the groove.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The groove is formed in the edge area of ​​the upper wafer by using a laser process or an etching process.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Before bonding the side of the first insulating dielectric layer away from the upper wafer to the lower wafer, the method for manufacturing the semiconductor device further includes: Planarizing a side of the first insulating dielectric layer away from the upper wafer; Alternatively, forming a metal layer in the first insulating dielectric layer; The first insulating dielectric layer and the metal layer are planarized on a side away from the upper wafer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer; The step of thinning a side of the upper wafer away from the lower wafer comprises: The side of the substrate away from the second insulating dielectric layer is thinned.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The depth to which the groove extends into the substrate is greater than or equal to the thickness of the substrate remaining after thinning a side of the substrate away from the second insulating dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: After thinning the side of the upper wafer away from the lower wafer, the method for manufacturing the semiconductor device further comprises: A second trimming process is performed to remove edge regions of the upper wafer and the lower wafer located at the periphery of the groove on one side close to the center of the upper wafer.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The groove is a closed or discontinuous annular groove.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

11. A semiconductor device, characterized in that: include: upper wafer; A groove is formed in an edge region of the upper wafer; A first insulating medium layer covers the upper wafer, and the first insulating medium layer seals the groove so that the groove forms a hollow structure; A lower wafer, wherein the lower wafer is melt-bonded or hybrid-bonded to a side of the first insulating dielectric layer away from the upper wafer, and a partial edge region of the upper wafer located at the periphery of the groove is retracted relative to another partial edge region, and the groove is used to prevent cracks and chipping generated at the bonding interface between the first insulating dielectric layer and the lower wafer during thinning of a side of the upper wafer away from the lower wafer from extending into the area surrounded by the groove.

12. The semiconductor device according to claim 11, wherein The first insulating medium layer is formed inside the groove and does not fill up the groove, so that the groove forms the hollow structure.

13. The semiconductor device according to claim 11, wherein The upper wafer includes a substrate and a second insulating dielectric layer formed on the substrate, the groove is recessed from the second insulating dielectric layer and penetrates the second insulating dielectric layer to further extend into the substrate, and the first insulating dielectric layer covers the second insulating dielectric layer.

14. The semiconductor device according to claim 11, wherein: The groove is a closed or discontinuous annular groove.

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