Semiconductor chip leveling and alignment system, method and device

Abstract

The present invention discloses a semiconductor chip leveling and alignment system, method and equipment. The system includes bolts, an adsorption clamping module, a four-degree-of-freedom leveling and correction platform, a laser rangefinder, a visual inspection mechanism, two groups of first gantry guide rails, a second gantry guide rail, a carrying platform, a gantry platform and a host computer; the carrying platform is provided with screw holes, and the four-degree-of-freedom leveling and correction platform is fixedly mounted on the upper surface of the carrying platform through the bolts and the screw holes; the two groups of first gantry guide rails are respectively arranged at two ends of the carrying platform, and the two ends of the gantry platform are movably connected to the first gantry guide rails; the adsorption clamping module and the laser rangefinder are both adjacently arranged on the side of the gantry platform; the visual inspection mechanism is movably mounted on the gantry platform; the system solves the technical problem that the existing chip leveling and alignment system cannot achieve multi-degree-of-freedom leveling and correction in space, resulting in the inability to meet the high-precision alignment requirements of semiconductor chips.

Description

Technical Field

[0001] The present invention relates to the field of pan-semiconductor detection technology, and in particular to a semiconductor chip leveling and alignment system, method, and equipment. Background Art

[0002] As semiconductor chips continue to develop towards miniaturization, high density, and high integration, before semiconductor testing equipment such as lithography, quantum dots, OLED, and Micro / MiniLED new displays are packaged, chips and other processed objects must be subjected to high-precision defect and posture detection and multi-degree-of-freedom precise alignment to ensure final product quality, thereby improving semiconductor product yield and production efficiency.

[0003] During chip inspection operations, it is required to identify the defect characteristics of different chips and mark defective chips, which puts forward requirements such as fast dynamic detection and variable distance detection for the visual inspection system; in addition, during the packaging alignment process, in order to ensure the chip transfer and packaging quality, high requirements are placed on the chip alignment accuracy.

[0004] The linear motor gantry motion system used in the existing chip leveling and alignment system has a low degree of integration, which makes its application function relatively simple. It can only perform motion alignment in the XYZ directions and cannot achieve spatial θx, θy, and θz multi-degree-of-freedom leveling and correction, resulting in an inability to meet the high-precision alignment requirements of semiconductor chips. Summary of the Invention

[0005] The present invention provides a semiconductor chip leveling and alignment system, method and equipment, which solves the technical problem that the existing chip leveling and alignment system can only perform motion alignment in the XYZ directions and cannot achieve spatial θx, θy, θz multi-degree-of-freedom leveling and correction, resulting in the inability to meet the high-precision alignment requirements of semiconductor chips.

[0006] A first aspect of the present invention provides a semiconductor chip leveling and alignment system, the system comprising bolts, an adsorption clamping module, a four-degree-of-freedom leveling and correction platform, a laser rangefinder, a visual inspection mechanism, two sets of first gantry guide rails, a second gantry guide rail, a carrying platform, a gantry platform, and a host computer;

[0007] The upper surface of the four-degree-of-freedom leveling and deviation-correcting platform is provided with a chip substrate, and the lower surface of the adsorption clamping module is provided with a chip carrier, and the chip to be tested is placed on the carrier;

[0008] The bearing platform is provided with screw holes, and the four-degree-of-freedom leveling and deviation-correcting platform is fixedly mounted on the upper surface of the bearing platform through the bolts and the screw holes;

[0009] Two sets of the first gantry guide rails are respectively arranged at two ends of the carrying platform, and the two ends of the gantry platform are movably connected to the first gantry guide rails;

[0010] The adsorption clamping module and the laser rangefinder are both adjacently arranged on a side surface of the gantry platform through the second gantry guide rail, and the side surface is adjacent to the four-degree-of-freedom leveling and correction platform;

[0011] The visual detection mechanism is movably mounted on the gantry platform via the second gantry guide rail and is located above the adsorption clamping module and the laser rangefinder;

[0012] The visual inspection mechanism is communicatively connected to the four-degree-of-freedom leveling and correcting platform, and the laser rangefinder, the visual inspection mechanism and the four-degree-of-freedom leveling and correcting platform are all communicatively connected to the host computer;

[0013] The host computer is configured to, upon receiving the substrate coordinate data and the plurality of carrier plane coordinates sent by the laser rangefinder, determine a plurality of plane position differences and send them to the four-degree-of-freedom leveling and correction platform; and determine a position offset difference based on the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction and send it to the four-degree-of-freedom leveling and correction platform;

[0014] The four-degree-of-freedom leveling and correction platform is used to perform a leveling operation on the chip substrate based on the received plane position difference values, generate the first instruction and send it to the visual inspection mechanism, and perform a positioning operation on the chip substrate based on the received position offset difference values.

[0015] Optionally, the host computer is specifically used to:

[0016] When receiving the substrate coordinate data and the multiple carrier plane coordinates sent by the laser rangefinder, the substrate coordinate data and the multiple carrier plane coordinates are substituted into a preset first formula to determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform;

[0017] When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, matching the chip image with a preset chip template image based on a template matching algorithm;

[0018] If the chip image and the preset chip template image match, the position data is substituted into a preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform;

[0019] The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

[0020] Optionally, the plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; and the preset first formula is specifically:

[0021]

[0022] Where Z Di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X′ i is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y′ i is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z si is the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane;

[0023] The preset second formula is specifically:

[0024]

[0025] Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

[0026] Optionally, the carrying platform includes a marble vibration isolation platform and a linear motor platform;

[0027] The linear motor platform and the marble vibration isolation platform are both provided with screw holes, and the linear motor platform is fixedly installed at the central position of the marble vibration isolation platform through the bolts and the screw holes;

[0028] The four-degree-of-freedom leveling and deviation-correcting platform is fixedly mounted on the upper surface of the linear motor platform through the bolts and the screw holes;

[0029] Two groups of the first gantry guide rails are respectively arranged at two ends of the marble vibration isolation platform, and the two ends of the gantry platform are movably connected to the first gantry guide rails.

[0030] Optionally, the four-degree-of-freedom leveling and deviation-correcting platform is further used for:

[0031] After performing an alignment operation on the chip substrate based on the received position offset difference, a second instruction is generated and sent to the visual inspection mechanism.

[0032] Optionally, the system further comprises a laser galvanometer mechanism;

[0033] The laser galvanometer mechanism is movably mounted on the gantry platform via the second gantry guide rail and is adjacent to the visual detection mechanism;

[0034] The laser galvanometer mechanism is communicatively connected to the host computer;

[0035] The laser galvanometer mechanism is used to respond to a third instruction and perform an array repair operation on the chip to be inspected.

[0036] Optionally, the hyperposition is further used for:

[0037] determining a target offset difference based on the target position data of the chip to be inspected sent by the visual inspection mechanism in response to the second instruction;

[0038] If the target offset difference satisfies a preset deviation condition, the third instruction is generated and sent to the laser galvanometer mechanism.

[0039] A second aspect of the present invention provides a semiconductor chip leveling and alignment method, comprising:

[0040] When receiving the substrate coordinate data and the multiple carrier plane coordinates sent by the laser rangefinder, the substrate coordinate data and the multiple carrier plane coordinates are substituted into a preset first formula to determine the multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform;

[0041] Performing a leveling operation on the chip substrate based on the received plane position difference values ​​by the four-degree-of-freedom leveling and correction platform, and generating a first instruction to be sent to the visual inspection mechanism;

[0042] When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, matching the chip image with a preset chip template image based on a template matching algorithm;

[0043] If the chip image and the preset chip template image match, the position data is substituted into a preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform;

[0044] Performing an alignment operation on the chip substrate based on the received position offset difference by the four-degree-of-freedom leveling and correction platform;

[0045] The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

[0046] Optionally, the plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; and the preset first formula is specifically:

[0047]

[0048] Where Z Di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X i ' is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y i ′ is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z siis the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane;

[0049] The preset second formula is specifically:

[0050]

[0051] Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

[0052] A third aspect of the present invention provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the semiconductor chip leveling and alignment method as described in any one of the above items.

[0053] It can be seen from the above technical solutions that the present invention has the following advantages:

[0054] The first aspect of the above technical solution of the present invention provides a semiconductor chip leveling and alignment system, which includes bolts, an adsorption clamping module, a four-degree-of-freedom leveling and correction platform, a laser rangefinder, a visual inspection mechanism, two sets of first gantry guide rails, a second gantry guide rail, a carrying platform, a gantry platform and a host computer; wherein, the upper surface of the four-degree-of-freedom leveling and correction platform is provided with a chip substrate, the lower surface of the adsorption clamping module is provided with a chip carrier, and the chip to be detected is placed on the carrier; the carrying platform is provided with screw holes, and the four-degree-of-freedom leveling and correction platform is fixedly installed on the upper surface of the carrying platform by bolts and screw holes; the two sets of first gantry guide rails The door guide rails are respectively arranged at both ends of the carrying platform, and the two ends of the gantry platform are movably connected to the first gantry guide rail; the adsorption clamping module and the laser rangefinder are both adjacently arranged on the side of the gantry platform through the second gantry guide rail, and the side is adjacent to the four-degree-of-freedom leveling and correction platform; the visual inspection mechanism is movably installed on the gantry platform through the second gantry guide rail, and is located at the upper end of the adsorption clamping module and the laser rangefinder; the visual inspection mechanism is communicatively connected to the four-degree-of-freedom leveling and correction platform, and the laser rangefinder, the visual inspection mechanism and the four-degree-of-freedom leveling and correction platform are all communicatively connected to the host computer; the host computer receives the information sent by the laser rangefinder When the substrate coordinate data and multiple carrier plane coordinates are received, multiple plane position differences are determined and sent to the four-degree-of-freedom leveling and correction platform. After the four-degree-of-freedom leveling and correction platform performs a leveling operation on the chip substrate based on the received plane position differences, it generates a first instruction and sends it to the visual inspection mechanism. The host computer determines the position offset difference based on the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction and sends it to the four-degree-of-freedom leveling and correction platform. The four-degree-of-freedom leveling and correction platform performs an alignment operation on the chip substrate based on the received position offset difference. The above scheme first passes through the host computer. The computer transmits the calculated position differences of each plane to the four-degree-of-freedom leveling and correction platform. After the four-degree-of-freedom leveling and correction platform performs leveling operations on the chip substrate based on the position differences of each plane, it triggers the visual inspection mechanism to obtain the chip image and position data of the chip to be inspected. Then, the host computer determines the position offset difference based on the chip image and position data and sends it to the four-degree-of-freedom leveling and correction platform. The four-degree-of-freedom leveling and correction platform performs alignment operations on the chip substrate based on the received position offset difference, realizing spatial multi-degree-of-freedom leveling and correction of θx, θy, and θz, which can meet the high-precision alignment requirements of semiconductor chips.

[0055] The second aspect of the above technical solution of the present invention provides a semiconductor chip leveling and alignment method, which, when receiving substrate coordinate data and multiple carrier plane coordinates sent by a laser rangefinder, substitutes the substrate coordinate data and each carrier plane coordinate into a preset first formula, determines multiple plane position differences and sends them to a four-degree-of-freedom leveling and correction platform; the four-degree-of-freedom leveling and correction platform performs a leveling operation on the chip substrate based on the received plane position differences, and generates a first instruction and sends it to a visual inspection mechanism; when receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, the chip image and the preset chip template image are matched based on a template matching algorithm. Matching; if the chip image and the preset chip template image are compatible, the position data is substituted into the preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform; the chip substrate is aligned based on the received position offset difference through the four-degree-of-freedom leveling and correction platform; in the above scheme, the chip substrate is first leveled based on multiple plane position differences through the four-degree-of-freedom leveling and correction platform, and then the chip substrate is aligned based on the position offset difference. Compared with the existing chip alignment system that can only perform motion alignment in the XYZ directions, it realizes spatial θx, θy, and θz multi-degree-of-freedom leveling and correction, which can meet the high-precision alignment requirements of semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A schematic structural diagram of a semiconductor chip leveling and alignment system provided in Embodiment 1 of the present invention;

[0058] Figure 2 A schematic diagram of obtaining substrate coordinate data and multiple carrier plane coordinates provided in the first embodiment of the present invention;

[0059] Figure 3 A schematic diagram of performing an alignment operation on a chip substrate according to the first embodiment of the present invention;

[0060] Figure 4 This is a flowchart of the steps of a semiconductor chip leveling and alignment method provided in the second embodiment of the present invention.

[0061] The meanings of the symbols in the accompanying drawings are as follows:

[0062] 1. Marble vibration isolation platform; 2. Linear motor platform; 3. Gantry platform; 4. Visual inspection mechanism; 5. Four-degree-of-freedom leveling and correction platform; 6. Adsorption clamping module; 7. Laser rangefinder; 8. Laser galvanometer mechanism; 9. First gantry guide rail; 10. Second gantry guide rail. DETAILED DESCRIPTION

[0063] Embodiments of the present invention provide a semiconductor chip leveling and alignment system, method, and device, which are used to solve the technical problem that the existing chip leveling and alignment system can only perform motion alignment in the XYZ directions and cannot achieve spatial θx, θy, θz multi-degree-of-freedom leveling and correction, resulting in the inability to meet the high-precision alignment requirements of semiconductor chips.

[0064] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0065] See also Figure 1 , Figure 1 This is a structural diagram of a semiconductor chip leveling and alignment system provided in Example 1 of the present invention.

[0066] The present invention provides a semiconductor chip leveling and alignment system, which includes bolts, an adsorption clamping module 6, a four-degree-of-freedom leveling and correction platform 5, a laser rangefinder 7, a visual inspection mechanism 4, two groups of first gantry guide rails 9, a second gantry guide rail 10, a carrying platform, a gantry platform 3 and a host computer; the upper surface of the four-degree-of-freedom leveling and correction platform 5 is provided with a chip substrate, the lower surface of the adsorption clamping module is provided with a chip carrier, and the chip to be detected is placed on the carrier; the carrying platform is provided with screw holes, and the four-degree-of-freedom leveling and correction platform 5 is fixedly installed on the upper surface of the carrying platform through bolts and screw holes; the two groups of first gantry guide rails 9 are respectively provided at both ends of the carrying platform, and the two ends of the gantry platform 3 are movably connected to the first gantry guide rails 9; the adsorption clamping module 6 and the laser rangefinder 7 are both adjacent to the side of the gantry platform 3 through the second gantry guide rail 10, and the side is adjacent to the four-degree-of-freedom leveling and correction platform 5; the visual inspection mechanism 4 is provided through The second gantry guide rail 10 is movably mounted on the gantry platform 3 and is located at the upper end of the adsorption clamping module 6 and the laser rangefinder 7; the visual inspection mechanism 4 and the four-degree-of-freedom leveling and correcting platform 5 are communicatively connected, and the laser rangefinder 7, the visual inspection mechanism 4 and the four-degree-of-freedom leveling and correcting platform 5 are all communicatively connected with the host computer; the host computer is used to determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correcting platform 5 when receiving the substrate coordinate data and multiple carrier plane coordinates sent by the laser rangefinder 7, and determine the position offset difference and send it to the four-degree-of-freedom leveling and correcting platform 5 based on the chip image and position data of the chip to be inspected sent by the visual inspection mechanism 4 in response to the first instruction; the four-degree-of-freedom leveling and correcting platform 5 is used to perform a leveling operation on the chip substrate based on the received plane position differences, generate a first instruction and send it to the visual inspection mechanism 4, and perform a positioning operation on the chip substrate based on the received position offset difference.

[0067] It should be noted that, first, the substrate coordinate data corresponding to the substrate and the multiple carrier plane coordinates corresponding to the carrier are obtained by the laser rangefinder 7 and sent to the host computer. The host computer determines the multiple plane position differences based on the received substrate coordinate data and the multiple carrier plane coordinates and sends them to the four-degree-of-freedom leveling and correction platform 5. After the four-degree-of-freedom leveling and correction platform 5 performs a leveling operation on the chip substrate based on the received plane position differences, it generates a first instruction and sends it to the visual inspection mechanism 4. Then, the visual inspection mechanism 4 responds to the first instruction to obtain the chip image and position data of the chip to be inspected and sends it to the host computer. The host computer determines the position offset difference based on the received chip image and position data and sends it to the four-degree-of-freedom leveling and correction platform 5. Finally, the four-degree-of-freedom leveling and correction platform 5 performs a positioning operation on the chip substrate based on the received position offset difference.

[0068] Furthermore, the laser rangefinder 7 can be used to measure the distance between the upper surface of the four-degree-of-freedom leveling and correction platform 5 and the adsorption clamping module 6, and can also be used for system accuracy calibration; the four-degree-of-freedom leveling and correction platform 5 is specifically a ZTTθ four-degree-of-freedom leveling and correction platform, which includes a high-precision, large-load leveling and correction device with four degrees of freedom of Z, θx, θy, and θz, and is used for leveling and correction operations of the workpiece carrier; the visual inspection mechanism 4 is used to obtain the position data and chip image of the chip or workpiece to be inspected, and form feedback with the ZTTθ four-degree-of-freedom leveling and correction platform and the host computer; the gantry platform 3 can carry various equipment and complete the high-precision movement required for inspection and alignment.

[0069] As a further improvement, the host computer is specifically used to:

[0070] When receiving the substrate coordinate data and multiple carrier plane coordinates sent by the laser rangefinder 7, the substrate coordinate data and each carrier plane coordinate are substituted into the preset first formula to determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform 5;

[0071] When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism 4 in response to the first instruction, matching the chip image with the preset chip template image based on the template matching algorithm;

[0072] If the chip image matches the preset chip template image, the position data is substituted into the preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform 5;

[0073] The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

[0074] Furthermore, the plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; and the preset first formula is specifically:

[0075]

[0076] Where Z Di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X i' is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y i ′ is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z si is the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane;

[0077] The preset second formula is specifically:

[0078]

[0079] Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

[0080] The coordinates of the substrate measurement points are the horizontal coordinates and the vertical coordinates of three measurement points calibrated in advance on the upper surface (chip substrate) of the four-degree-of-freedom leveling and deflection-correcting platform 5 .

[0081] The preset calibration coordinates are the spatial positions of the chip that have been calibrated in advance.

[0082] For example, see Figure 2, obtain the XY coordinates (X1', Y1'), (X2', Y2'), (X3', Y3') of the measuring point on the chip substrate plane through the laser rangefinder 7, that is, the coordinates of the first substrate measurement point, the second substrate measurement point and the third substrate measurement point, the coordinates of any three points on the chip carrier plane (X1, Y1, Z1), (X2, Y2, Z2), (X3, Y3, Z3), that is, the coordinates of the first carrier plane, the second carrier plane and the third carrier plane, and the chip substrate on the four-degree-of-freedom leveling and correction platform 5. The coordinates of any three points on the plane are (X1, Y1, Z1'), (X2, Y2, Z2'), and (X3, Y3, Z3'), namely the first substrate plane coordinates, the second substrate plane coordinates, and the third substrate plane coordinates; the above coordinates are substituted into the preset first formula by the host computer to calculate the distance between the carrier plane at the measuring point (vertical distance between the carrier measuring point) and the distance between the substrate plane at the measuring point (vertical distance between the substrate measuring point) and make the difference, output the displacement of the measuring point (plane position difference) and send it to the four-degree-of-freedom leveling and correction platform 5.

[0083] Further, see Figure 3 , the visual inspection mechanism 4 mainly performs position and defect detection through edge contour recognition and template matching algorithm; first, the chip edge line of the chip to be inspected is identified and the chip image of the chip to be inspected is obtained, and the two endpoint coordinates of the edge line are extracted to obtain the position coordinates and angle values. Then, the host computer uses the template matching algorithm to match the chip image with the complete preset chip template to identify the shape difference between the two, that is, the defect. If the chip image does not match the preset chip template (preset chip template image), the system stops operating and reminds that the chip is defective; if the chip image is compatible with the preset chip template, the position data is substituted into the second preset formula, the position offset difference is output and sent to the four-degree-of-freedom leveling and correction platform 5, and the four-degree-of-freedom leveling and correction platform 5 aligns the chip substrate and the chip carrier according to the position offset difference.

[0084] As a further improvement, the four-degree-of-freedom leveling and correction platform 5 is also used to: after performing an alignment operation on the chip substrate based on the received position offset difference, generate a second instruction and send it to the visual inspection mechanism 4.

[0085] Optionally, the system also includes a laser galvanometer mechanism 8; the laser galvanometer mechanism 8 is movably installed on the gantry platform 3 through a second gantry guide rail and is adjacent to the visual inspection mechanism 4; the laser galvanometer mechanism 8 is communicatively connected to the host computer; the laser galvanometer mechanism 8 is used to respond to a third instruction and perform an arrayed repair operation on the chip to be inspected.

[0086] Optionally, the upper level is also used to: determine the target offset difference based on the target position data of the chip to be inspected sent by the visual inspection mechanism 4 in response to the second instruction; if the target offset difference meets the preset deviation condition, generate a third instruction and send it to the laser galvanometer mechanism 8.

[0087] It should be noted that after the four-degree-of-freedom leveling and correction platform 5 completes the alignment operation on the chip substrate, it generates a second instruction and sends it to the visual inspection mechanism 4. The visual inspection mechanism 4 responds to the second instruction and obtains the position data of the chip to be inspected (target position data) again and sends it to the host computer. The host computer substitutes the position data into the preset second formula to determine the target offset difference. If the target offset difference meets the preset deviation condition, the laser galvanometer mechanism 8 is driven to generate a laser beam, and the laser beam is used to perform array transfer or repair operations on the chip to be inspected; if the target offset difference does not meet the preset deviation condition, the four-degree-of-freedom leveling and correction platform 5 is driven to perform the alignment operation on the chip substrate again according to the target position data; wherein, the preset deviation condition refers to the position offset difference (target offset difference) being less than 1 micron, which is met.

[0088] As a further improvement, the bearing platform includes a marble vibration isolation platform 1 and a linear motor platform 2;

[0089] The linear motor platform 2 and the marble vibration isolation platform 1 are both provided with screw holes, and the linear motor platform 2 is fixedly installed at the central position of the marble vibration isolation platform 1 through bolts and screw holes;

[0090] The four-degree-of-freedom leveling and deviation-correcting platform 5 is fixedly mounted on the upper surface of the linear motor platform 2 through bolts and screw holes;

[0091] Two sets of first gantry guide rails 9 are respectively arranged at two ends of the marble vibration isolation platform 1 , and two ends of the gantry platform 3 are movably connected to the first gantry guide rails 9 .

[0092] It should be noted that the linear motor platform 2 is specifically an XY linear motor platform. In conjunction with the gantry platform 3 and the inspection requirements, it is equipped with a ZTTθ four-degree-of-freedom leveling and correction platform to perform defect detection and leveling and alignment on the chip to be inspected. The marble vibration isolation platform 1 can reduce the impact of external vibration on the accuracy of the entire system. In addition to obtaining the position and image of the chip, the visual inspection mechanism 4 can also be used for Z-axis distance measurement, that is, measuring the distance between the chip substrate and the carrier. The measured distance is then fed back to the ZTTθ four-degree-of-freedom leveling and correction platform to adjust the parallelism deviation (θx, θy) between the substrate and the carrier.

[0093] Furthermore, before the system works, the laser rangefinder 7 is used to perform precision calibration on each motion module. Then, the gantry platform 3 drives the adsorption and clamping module 6 to move along the y-axis to the loading position to perform chip carrier or workpiece adsorption and loading operations. At the same time, the XY linear motor platform drives the ZTTθ four-degree-of-freedom leveling and correction platform to move to the substrate loading position. After loading is completed, they all move back to the processing position; the visual inspection mechanism 4 is driven to move along the x-axis to above the workpiece and perform position leveling and defect detection on the chip or workpiece to be inspected after loading. The gantry platform 3 includes a large gantry platform provided with adjacent laser galvanometer mechanisms 8 and visual inspection mechanisms 4, and a small gantry platform provided with adjacent adsorption and clamping modules 6 and laser rangefinders 7, and the forward and backward movements of the large gantry platform and the small gantry platform do not interfere with each other.

[0094] In an embodiment of the present invention, the present application provides a semiconductor chip leveling and alignment system, which includes bolts, an adsorption clamping module, a four-degree-of-freedom leveling and correction platform, a laser rangefinder, a visual inspection mechanism, two sets of first gantry guide rails, a second gantry guide rail, a carrying platform, a gantry platform and a host computer; wherein, the upper surface of the four-degree-of-freedom leveling and correction platform is provided with a chip substrate, the lower surface of the adsorption clamping module is provided with a chip carrier, and the chip to be detected is placed on the carrier; the carrying platform is provided with screw holes, and the four-degree-of-freedom leveling and correction platform is fixedly installed on the upper surface of the carrying platform by bolts and screw holes; the two sets of first gantries are provided with a chip substrate, and the chip carrier is provided with a chip carrier under the adsorption clamping module. The chip to be detected is placed on the carrier; the carrying platform is provided with screw holes, and the four-degree-of-freedom leveling and correction platform is fixedly installed on the upper surface of the carrying platform by bolts and screw holes; The guide rails are respectively arranged at both ends of the carrying platform, and both ends of the gantry platform are movably connected to the first gantry guide rail; the adsorption clamping module and the laser rangefinder are both adjacently arranged on the side of the gantry platform through the second gantry guide rail, and the side is adjacent to the four-degree-of-freedom leveling and correction platform; the visual inspection mechanism is movably installed on the gantry platform through the second gantry guide rail, and is located at the upper end of the adsorption clamping module and the laser rangefinder; the visual inspection mechanism is communicatively connected to the four-degree-of-freedom leveling and correction platform, and the laser rangefinder, the visual inspection mechanism and the four-degree-of-freedom leveling and correction platform are all communicatively connected to the host computer; the host computer receives the information sent by the laser rangefinder through the host computer. When the coordinate data of the substrate and the coordinates of the planes of the multiple carriers are received, the multiple plane position differences are determined and sent to the four-degree-of-freedom leveling and correction platform. After the four-degree-of-freedom leveling and correction platform performs a leveling operation on the chip substrate based on the received plane position differences, a first instruction is generated and sent to the visual inspection mechanism. The host computer determines the position offset difference based on the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction and sends it to the four-degree-of-freedom leveling and correction platform. The four-degree-of-freedom leveling and correction platform performs an alignment operation on the chip substrate based on the received position offset difference. The above scheme is first performed by the host computer. The computer transmits the calculated position differences of each plane to the four-degree-of-freedom leveling and correction platform. After the four-degree-of-freedom leveling and correction platform performs leveling operations on the chip substrate based on the position differences of each plane, it triggers the visual inspection mechanism to obtain the chip image and position data of the chip to be inspected. Then, the host computer determines the position offset difference based on the chip image and position data and sends it to the four-degree-of-freedom leveling and correction platform. The four-degree-of-freedom leveling and correction platform performs alignment operations on the chip substrate based on the received position offset difference, realizing spatial multi-degree-of-freedom leveling and correction of θx, θy, and θz, which can meet the high-precision alignment requirements of semiconductor chips.

[0095] See also Figure 4 , Figure 4 This is a flowchart of the steps of a semiconductor chip leveling and alignment method provided in the second embodiment of the present invention.

[0096] The present invention provides a semiconductor chip leveling and alignment method, comprising:

[0097] Step 401: When receiving substrate coordinate data and multiple carrier plane coordinates sent by the laser rangefinder, substitute the substrate coordinate data and each carrier plane coordinate into a preset first formula, determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform.

[0098] In this embodiment, when the substrate coordinate data and multiple carrier plane coordinates sent by the laser rangefinder are received, the substrate coordinate data and each carrier plane coordinate are substituted into the preset first formula to determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform.

[0099] Step 402: Perform a leveling operation on the chip substrate based on the received plane position differences using a four-degree-of-freedom leveling and correction platform, and generate a first instruction that is sent to a visual inspection mechanism.

[0100] In this embodiment, a four-degree-of-freedom leveling and correction platform is used to perform a leveling operation on the chip substrate based on the received plane position differences, and a first instruction is generated and sent to the visual inspection mechanism.

[0101] Step 403 : When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, matching the chip image with a preset chip template image based on a template matching algorithm.

[0102] In this embodiment, when the chip image and position data of the chip to be inspected are received from the visual inspection mechanism in response to the first instruction, the chip image is matched with a preset chip template image based on a template matching algorithm.

[0103] Step 404: If the chip image matches the preset chip template image, the position data is substituted into the preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform.

[0104] In this embodiment, if the chip image matches the preset chip template image, the position data is substituted into the preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform.

[0105] Step 405: Perform an alignment operation on the chip substrate based on the received position offset difference using a four-degree-of-freedom leveling and correction platform.

[0106] In this embodiment, the chip substrate is aligned using a four-degree-of-freedom leveling and correction platform based on the received position offset difference.

[0107] The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

[0108] Optionally, the plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; and the preset first formula is specifically:

[0109]

[0110] Where Z Di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X i ' is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y i ′ is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z si is the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane;

[0111] The preset second formula is specifically:

[0112]

[0113] Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

[0114] In an embodiment of the present invention, the present application provides a semiconductor chip leveling and alignment method, when receiving substrate coordinate data and multiple carrier plane coordinates sent by a laser rangefinder, the substrate coordinate data and each carrier plane coordinate are substituted into a preset first formula, multiple plane position differences are determined and sent to a four-degree-of-freedom leveling and correction platform; the four-degree-of-freedom leveling and correction platform performs a leveling operation on the chip substrate based on the received plane position differences, and generates a first instruction and sends it to a visual inspection mechanism; when the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction are received, the chip image and the preset chip template image are matched based on the template matching algorithm. Match; if the chip image and the preset chip template image are compatible, the position data is substituted into the preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform; the chip substrate is aligned based on the received position offset difference through the four-degree-of-freedom leveling and correction platform; in the above scheme, the chip substrate is first leveled based on multiple plane position differences through the four-degree-of-freedom leveling and correction platform, and then the chip substrate is aligned based on the position offset difference. Compared with the existing chip alignment system that can only perform motion alignment in the XYZ directions, it realizes spatial θx, θy, and θz multi-degree-of-freedom leveling and correction, which can meet the high-precision alignment requirements of semiconductor chips.

[0115] An embodiment of the present invention further provides an electronic device, comprising: a memory and a processor, wherein a computer program is stored in the memory; when the computer program is executed by the processor, the processor executes the semiconductor chip leveling and alignment method as described in the second embodiment above.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0118] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0119] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor chip leveling and alignment system, characterized in that: The system includes bolts, an adsorption clamping module, a four-degree-of-freedom leveling and correction platform, a laser rangefinder, a visual inspection mechanism, two sets of first gantry guide rails, a second gantry guide rail, a carrying platform, a gantry platform and a host computer; The upper surface of the four-degree-of-freedom leveling and correction platform is provided with a chip substrate, and the lower surface of the adsorption clamping module is provided with a chip carrier, and the chip to be tested is placed on the carrier; The bearing platform is provided with screw holes, and the four-degree-of-freedom leveling and deviation-correcting platform is fixedly mounted on the upper surface of the bearing platform through the bolts and the screw holes; Two sets of the first gantry guide rails are respectively arranged at two ends of the carrying platform, and the two ends of the gantry platform are movably connected to the first gantry guide rails; The adsorption clamping module and the laser rangefinder are both adjacently arranged on a side surface of the gantry platform through the second gantry guide rail, and the side surface is adjacent to the four-degree-of-freedom leveling and correction platform; The visual detection mechanism is movably mounted on the gantry platform via the second gantry guide rail and is located above the adsorption clamping module and the laser rangefinder; The visual inspection mechanism is communicatively connected to the four-degree-of-freedom leveling and correcting platform, and the laser rangefinder, the visual inspection mechanism and the four-degree-of-freedom leveling and correcting platform are all communicatively connected to the host computer; The host computer is configured to, upon receiving the substrate coordinate data and the plurality of carrier plane coordinates sent by the laser rangefinder, determine a plurality of plane position differences and send them to the four-degree-of-freedom leveling and correction platform; and determine a position offset difference based on the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction and send it to the four-degree-of-freedom leveling and correction platform; The four-degree-of-freedom leveling and correction platform is used to perform a leveling operation on the chip substrate based on the received plane position difference values, generate the first instruction and send it to the visual inspection mechanism, and perform a positioning operation on the chip substrate based on the received position offset difference values.

2. The semiconductor chip leveling and alignment system according to claim 1, wherein: The host computer is specifically used for: When receiving the substrate coordinate data and the multiple carrier plane coordinates sent by the laser rangefinder, the substrate coordinate data and the multiple carrier plane coordinates are substituted into a preset first formula to determine multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform; When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, matching the chip image with a preset chip template image based on a template matching algorithm; If the chip image and the preset chip template image match, the position data is substituted into a preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform; The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

3. The semiconductor chip leveling and alignment system according to claim 2, wherein: The plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; the preset first formula is specifically: Where Z Di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X i ′ is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y i ′ is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z si is the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane; The preset second formula is specifically: Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

4. The semiconductor chip leveling and alignment system according to claim 1, wherein: The bearing platform includes a marble vibration isolation platform and a linear motor platform; The linear motor platform and the marble vibration isolation platform are both provided with screw holes, and the linear motor platform is fixedly installed at the central position of the marble vibration isolation platform through the bolts and the screw holes; The four-degree-of-freedom leveling and deviation-correcting platform is fixedly mounted on the upper surface of the linear motor platform through the bolts and the screw holes; Two groups of the first gantry guide rails are respectively arranged at two ends of the marble vibration isolation platform, and the two ends of the gantry platform are movably connected to the first gantry guide rails.

5. The semiconductor chip leveling and alignment system according to claim 1, wherein: The four-degree-of-freedom leveling and deviation-correcting platform is also used for: After performing an alignment operation on the chip substrate based on the received position offset difference, a second instruction is generated and sent to the visual inspection mechanism.

6. The semiconductor chip leveling and alignment system according to claim 5, wherein: The system also includes a laser galvanometer mechanism; The laser galvanometer mechanism is movably mounted on the gantry platform via the second gantry guide rail and is adjacent to the visual detection mechanism; The laser galvanometer mechanism is communicatively connected to the host computer; The laser galvanometer mechanism is used to respond to a third instruction and perform an array repair operation on the chip to be inspected.

7. The semiconductor chip leveling and alignment system according to claim 6, wherein: The above mentioned positions are also used for: determining a target offset difference based on the target position data of the chip to be inspected sent by the visual inspection mechanism in response to the second instruction; If the target offset difference satisfies a preset deviation condition, the third instruction is generated and sent to the laser galvanometer mechanism.

8. A semiconductor chip leveling and alignment method, characterized in that: include: When receiving the substrate coordinate data and the multiple carrier plane coordinates sent by the laser rangefinder, the substrate coordinate data and the multiple carrier plane coordinates are substituted into a preset first formula to determine the multiple plane position differences and send them to the four-degree-of-freedom leveling and correction platform; Performing a leveling operation on the chip substrate based on the received plane position difference values ​​by the four-degree-of-freedom leveling and correction platform, and generating a first instruction to be sent to the visual inspection mechanism; When receiving the chip image and position data of the chip to be inspected sent by the visual inspection mechanism in response to the first instruction, matching the chip image with a preset chip template image based on a template matching algorithm; If the chip image and the preset chip template image match, the position data is substituted into a preset second formula to determine the position offset difference and send it to the four-degree-of-freedom leveling and correction platform; Performing an alignment operation on the chip substrate based on the received position offset difference by the four-degree-of-freedom leveling and correction platform; The substrate coordinate data includes a plurality of substrate plane coordinates and a plurality of substrate measurement point coordinates, and the position data includes chip position coordinates and angle values.

9. The semiconductor chip leveling and alignment method according to claim 8, wherein: The plurality of substrate plane coordinates include first substrate plane coordinates, second substrate plane coordinates, and third substrate plane coordinates; the plurality of substrate measurement point coordinates include first substrate measurement point coordinates, second substrate measurement point coordinates, and third substrate measurement point coordinates; the plurality of carrier plane coordinates include first carrier plane coordinates, second carrier plane coordinates, and third carrier plane coordinates; the preset first formula is specifically: Where Z di is the vertical distance of the i-th carrier measurement point, i∈[1,3]; Z3 is the vertical coordinate in the third carrier plane coordinate; Y1 is the longitudinal coordinate in the first carrier plane coordinate; Y2 is the longitudinal coordinate in the second carrier plane coordinate; Z1 is the vertical coordinate in the first carrier plane coordinate; Z2 is the vertical coordinate in the second carrier plane coordinate; X′ i is the horizontal coordinate of the i-th substrate measurement point in the coordinates; X3 is the horizontal coordinate in the third carrier plane coordinates; X1 is the horizontal coordinate in the first carrier plane coordinates; X2 is the horizontal coordinate in the second carrier plane coordinates; Y i ′ is the vertical coordinate of the measurement point on the i-th substrate; Y3 is the vertical coordinate on the third carrier plane; Z si is the vertical distance of the i-th substrate measurement point; C3 is the vertical coordinate in the third substrate plane coordinate; B1 is the longitudinal coordinate in the first substrate plane coordinate; B2 is the longitudinal coordinate in the second substrate plane coordinate; C1 is the vertical coordinate in the first substrate plane coordinate; C2 is the vertical coordinate in the second substrate plane coordinate; A3 is the horizontal coordinate in the third substrate plane coordinate; A1 is the horizontal coordinate in the first substrate plane coordinate; A2 is the horizontal coordinate in the second substrate plane coordinate; C3 is the vertical coordinate in the third substrate plane coordinate; ΔZ i is the position difference of the i-th plane; The preset second formula is specifically: Where x o is the horizontal coordinate of the preset calibration coordinate; o is the longitudinal coordinate of the preset calibration coordinate; θ o is the preset calibration angle value; x' is the horizontal coordinate of the chip position coordinate; y' is the vertical coordinate of the chip position coordinate; θ' is the angle value; Δx is the horizontal coordinate difference in the position offset difference; Δy is the vertical coordinate difference in the position offset difference; Δθ is the angle difference in the position offset difference.

10. An electronic device, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the semiconductor chip leveling and alignment method according to any one of claims 8 to 9.

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