A noise model circuit based on time-interleaved pipeline ADC system

Abstract

The invention discloses a noise model circuit based on a time-interleaved pipeline ADC system, which relates to the technical field of integrated circuits and comprises an isolation amplifier noise model, a reference circuit noise model and a time-interleaved pipeline ADC model; the isolation amplifier noise model is composed of an operational amplifier and an external feedback structure, and processes the thermal noise of the operational amplifier and its feedback network; the reference circuit noise model processes the thermal noise and quantization noise generated by the reference circuit; the time-interleaved pipeline ADC model comprises a time-interleaved circuit and a pipeline ADC, and processes the noise generated by the sampling structure and the operational amplifier; the invention not only includes a traditional ADC structure in structure, but also innovatively considers the influence of the isolation amplifier and the power supply, which has a better guiding role in building a highly integrated ADC system.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a noise model circuit based on a time-interleaved pipeline ADC system. Background Art

[0002] Noise is the most important factor affecting high-speed and high-precision ADCs. Since the birth of integrated circuits, people have begun to study the power consumption and noise required by circuits. As the feature size of devices enters deep submicron, the impact of noise in CMOS circuits, especially mixed analog circuits, on circuit performance has become more and more significant, and the noise problem has begun to rise to another bottleneck problem. The research on low noise issues in mixed analog circuits involves three parts: noise source, coupling medium, and receiving part (circuit sensitive to noise, etc.). Therefore, the way to reduce noise is to try to remove, reduce or convert any one or more of the above three items. The noise source is composed of the inherent noise and interference noise of the device. The inherent noise of CMOS devices mainly includes thermal noise and 1 / f noise, and there are many sources of interference noise in the circuit. Signal crosstalk noise, substrate coupling noise, power supply voltage drop, ground bounce noise, and charge distribution effect, i.e. charge sharing noise, will all affect the performance of mixed analog circuits.

[0003] Noise-sensitive circuits mainly refer to analog circuits in mixed-signal circuits. With the rapid development of CMOS ultra-large-scale integrated circuit manufacturing technology, modern communications have continuously increased the requirements for signal frequency and accuracy. ADCs using clock alternation and SAR structures no longer meet design requirements in terms of accuracy and performance. This makes the need for the superposition of pipeline structure and clock alternation technology urgent. Designers combine pipeline + clock alternation structure, or other composite structures + clock alternation and other new structures, making the choice of high-speed and high-precision ADC design more diverse. The current research direction of high-speed and high-precision ADCs is a resolution greater than 10 bits and a sampling rate of the order of GHz. High-speed and high-precision ADCs have a wide range of applications, especially high-performance ADC design technology. High-precision design technology is required to deal with pulse signals. To deal with agile signals, ADCs need to develop high-speed sampling technology. Therefore, the most critical issue in the development of high-speed ADCs is to establish an accurate noise model so that it can effectively serve the design of ADCs and can make a more accurate evaluation of the dynamic performance of ADCs at the beginning of the project.

[0004] There are many structures of high-speed ADC in the prior art. The noise is random and its amplitude cannot be predicted. We can only predict its average power to represent the noise size, and use auxiliary theorems to simplify noise analysis and mathematically model the corresponding noise. In a complex ADC system, it is difficult to abstract the noise model, and there are many sources of noise. Summary of the invention

[0005] The purpose of the present invention is to provide a noise model circuit based on a time-interleaved pipeline ADC system, which aims to effectively serve the performance evaluation of the ADC and reduce the error caused by noise when studying high-speed ADC.

[0006] In order to solve the above technical problems, the present invention provides a noise model circuit based on a time-interleaved pipeline ADC system, including an isolation amplifier noise model, a reference circuit noise model and a time-interleaved pipeline ADC model;

[0007] The isolation amplifier noise model is composed of an operational amplifier and an external feedback structure, and processes the thermal noise of the operational amplifier and its feedback network; the feedback structure includes a capacitor C2 and a resistor R2 connected in parallel between the negative input terminal and the output terminal of the operational amplifier, a resistor R1 connected to the negative input terminal of the operational amplifier, and the other end of the resistor R1 is grounded; the output terminal of the operational amplifier is also connected in series with a resistor R3, a capacitor C1 and a resistor R4, the other end of the resistor R4 is grounded, and the positive input terminal of the operational amplifier is grounded through a voltage source Vamp;

[0008] The reference circuit noise model processes the quantization noise generated by the reference circuit;

[0009] The time-interleaved pipeline ADC model includes a time-interleaved circuit and a pipeline ADC, and processes the noise generated by the sampling structure and the operational amplifier;

[0010] The time interleaving circuit comprises an analog-to-digital converter ADC1, an analog-to-digital converter ADC2, an analog-to-digital converter ADC3, an analog-to-digital converter ADC4 and a reference ADC, the input end of each analog-to-digital converter is connected to a four-frequency division circuit and a three-frequency division circuit, the output clock of the four-frequency division circuit and the three-frequency division circuit cross-controls the sampling of the analog-to-digital converter and the reference ADC, the output end of each analog-to-digital converter is connected to a four-to-one selection circuit, and the output end of the reference ADC is connected to a digital background calibration through a delay circuit;

[0011] The pipeline ADC includes a clock generation circuit, a sampling and holding circuit SHA, a multi-stage pipeline conversion structure, a delay alignment register circuit and a redundant bit digital correction circuit. The output end of the pipeline conversion structure of the last stage is provided with a flash memory type ADC. The clock generation circuit is connected to the pipeline conversion structures of each stage to control the working sequence of the pipeline conversion structure. The sampling and holding circuit SHA is connected to the input end of the pipeline conversion structure, and serves as the front-end sampling channel of each stage of the pipeline conversion structure channel to provide the pipeline conversion structure with the sampled input voltage. The structure of each stage of the pipeline conversion structure is the same, and the output of the previous stage is used as the input of the next stage to complete the working mode of the pipeline. The delay alignment register circuit and the redundant bit digital correction circuit are connected to the output of the four-select-one selection circuit to store and calibrate the digital code output by the pipeline conversion structure. By performing noise analysis on the first stage of the pipeline structure, the total noise model of the structure is equivalently calculated.

[0012] Preferably, the clock generating circuit is used to generate two sets of clock control signals with non-overlapping phases, control the multi-stage pipelines of the pipeline conversion structure and use different timings to make the circuits work alternately;

[0013] The pipeline conversion structure is used to divide the conversion operation into multiple stages, and each stage conversion obtains a certain digital output bit, forming a pipeline working mode, mainly processing the thermal noise and flicker noise generated by the sampling and holding circuit and operational amplifier of each stage;

[0014] The delay alignment register circuit synchronizes the output data of each stage of pipeline conversion structure;

[0015] The redundant bit digital correction circuit uses the redundant bits to perform error correction on the conversion result.

[0016] Preferably, each stage of the pipeline conversion structure includes an MDAC and a sub-ADC; the MDAC includes a sample-and-hold circuit and a sub-DAC for realizing digital-to-analog conversion, subtraction, amplification and sample-and-hold functions.

[0017] The MDAC includes a sampling and holding circuit, an operational amplifier G2 and a sub-DAC. The input ends of the sampling and holding circuit and the sub-ADC are connected to the input signal, the output end of the sub-ADC is connected to the input end of the sub-DAC, and the output ends of the sampling and holding circuit and the sub-DAC are connected to the input end of the operational amplifier G2. The operational amplifier G2 completes signal amplification, and the amplified signal is connected to the next pipeline conversion structure.

[0018] Preferably, the sampling and holding circuit is used to collect the analog signal input by the ADC circuit, and hold the sampled value until the next clock cycle arrives, and then supply it to the subsequent circuit for quantization processing;

[0019] The sub-DAC is used to convert the digital output code in each stage of the pipeline conversion structure into an analog signal.

[0020] The sample-and-hold circuit includes a switch S1, a switch S2, a switch S3, a sampling capacitor Cs1, and a feedback capacitor Cf1. The two ends of the switch S1 are respectively connected to the input voltage Vi and the sampling capacitor Cs1. The switch S2 is connected to the input end of the operational amplifier OTA and the ground. The switch S3 is connected to the output end of the operational amplifier OTA and the common-mode voltage. The sampling capacitor Cs1 is respectively connected to the switch S1 and the input end of the operational amplifier. One end of the feedback capacitor Cf1 is connected to the input end of the operational amplifier OTA, and the other end is connected to the output end of the operational amplifier OTA.

[0021] Preferably, the sampling and holding circuit is equivalent to a switched capacitor circuit, the switched capacitor circuit includes a sampling capacitor Cs1, a feedback capacitor Cf1, and an operational amplifier OTA, and the equivalent noise of the sampling and holding circuit is:

[0022]

[0023] Where k is the Boltzmann constant, T is the absolute temperature, C s1 is the capacitance value of the sampling capacitor Cs1, C f1 is the capacitance value of the feedback capacitor Cf1;

[0024] The equivalent noise voltage of the operational amplifier OTA is:

[0025]

[0026] Where n f is the noise factor, which is determined by the structure of the operational amplifier, C c1 is the Miller compensation capacitance value of the operational amplifier, k is the Boltzmann constant and T is the absolute temperature.

[0027] Preferably, the pipeline ADC includes a plurality of pipeline stage circuits, and the equivalent noise of the first stage circuit is calculated by the following formula:

[0028]

[0029] Where n f represents the noise factor, which is determined by the structure of the operational amplifier, γ is the noise coefficient of the transistor, C c1 is the Miller compensation capacitance value of the operational amplifier, C s1 is the capacitance value of the sampling capacitor Cs1, C f1 is the capacitance value of the feedback capacitor Cf1, k is the Boltzmann constant, T is the absolute temperature, is the equivalent noise voltage of the operational amplifier.

[0030] Preferably, the output noise of the isolation amplifier noise model is:

[0031]

[0032] In the formula, Gain is the gain of the amplifier, R1 and R2 are the resistance values ​​of resistors R1 and R2 respectively, and BW is n is the noise bandwidth, k is the Boltzmann constant, R eq is the equivalent resistance of resistors R1 and R2, T k is the Kelvin temperature.

[0033] Compared with the related art, the present invention has the following beneficial effects:

[0034] The high-speed ADC proposed in the present invention adopts a pipeline + time interleaved sampling structure, which is more in line with the needs of high-speed ADC. Among the noise sources of high-speed ADC, the proportion of clock jitter becomes larger, and as the clock frequency continues to rise, its proportion gradually increases, which is closely related to thermal noise and power supply noise. Therefore, the present invention not only includes the traditional ADC structure in structure, but also innovatively considers the influence of isolation amplifier and power supply, which has a better guiding role in building a highly integrated ADC system. For the analysis of noise, focus on analyzing the noise mechanism and equivalent noise model, establish the noise model of the main noise in the integrated ADC system, specifically analyze the influence of noise on ADC, and better evaluate the performance of high-speed and high-precision ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is the total noise equivalent model diagram of the integrated ADC of the present invention;

[0036] Figure 2 It is a structural block diagram of the time-interleaved pipeline ADC of the present invention;

[0037] Figure 3 It is a structural block diagram of a single-channel pipeline ADC of the present invention;

[0038] Figure 4 This is a noise equivalent model diagram of a single-channel pipeline ADC of the present invention;

[0039] Figure 5 This is the noise simulation result of the single-channel pipeline ADC of the present invention;

[0040] Figure 6 This is a noise equivalent model diagram of the isolation amplifier circuit of the present invention;

[0041] Figure 7 This is the noise simulation result of the isolation amplifier circuit of the present invention;

[0042] Figure 8 This is a noise equivalent model diagram of the reference circuit of the present invention;

[0043] Fig. 9 This is the noise simulation result of the reference circuit of the present invention. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0045] like Figure 1 - Fig. 9 As shown, a noise model circuit based on a time-interleaved pipeline ADC system includes a time-interleaved pipeline ADC model, an isolation amplifier noise model and a reference circuit noise model.

[0046] The time-interleaved pipeline ADC model is mainly composed of a time-interleaved circuit and a pipeline ADC; the isolation amplifier noise model is mainly composed of an operational amplifier and an external feedback structure; and the reference circuit noise model is generated during the reference voltage quantization process from the internal structure.

[0047] like Figure 2 As shown, the time-interleaved pipeline ADC model (TIADC) adopts four single-channel pipeline ADCs (ADC1~ADC4) with a sampling rate of fs / 4 for alternate sampling. The back end uses a four-to-one channel selection circuit to MUX the output results of the four sub-channel ADCs to the output under the control of the clock, so that the sampling rate of the entire time-interleaved pipeline ADC model reaches fs, thereby realizing an increase in the sampling rate of the entire system.

[0048] Figure 2 The reference channel ADC5 in the TIADC is a reference channel ADC with a sampling rate of fs / 3. The output result of the reference channel ADC5 is provided to the digital background calibration circuit. The digital background calibration circuit performs digital signal processing on the outputs of the four sub-channels ADC1~ADC4 and the reference channel ADC5 to achieve mismatch calibration of the four channels ADC1~ADC4. The calibrated output is used as the output of the entire system. CK is the clock of the entire TIADC system. CK1~CK4 is a four-phase clock after CK is divided by four. CK5 is a clock after CK is divided by three. V ip and V in They are the positive input and negative input of the entire TIADC system, V refp and V refnThey are the positive reference voltage and the negative reference voltage respectively.

[0049] The pipeline ADC is as Figure 3 As shown, the pre-sampling and holding circuit SHA is relatively stable in sampling clock relative to the input analog signal V in Sampling is performed, and the discretized signal is output to the first stage circuit Stage1 when the clock phase is held. At the same time, the Stage1 circuit in the sampling clock phase samples the output result of the pre-sampling and holding circuit SHA which holds the clock phase. The sub-ADC of this stage converts the input signal to obtain the D1-bit coarse quantization result of the first stage circuit Stage1 circuit. D1 is used as the digital input of the sub-DAC of this stage when the clock phase is held, and the subtraction circuit realizes the subtraction between the input signal of this stage and the output of the sub-DAC. The difference is passed through the gain amplifier stage circuit Stage2-Stagek with the same working principle.

[0050] like Figure 4 As shown, the pipeline conversion structure of each stage includes a sub-MDAC and a sub-ADC. The present invention takes into account the noise from the sampling circuit and the operational amplifier. In the sampling circuit, it can be equivalent to a switch capacitor circuit, including a sampling capacitor Cs1, a feedback capacitor Cf1, and an operational amplifier OTA. Due to the influence of the switch on-resistance, there will be thermal noise voltage on the sampling capacitor and the feedback capacitor. According to the transistor noise model working in the linear region and the principle of non-correlated noise superposition, the equivalent noise source voltage accumulated on the sampling capacitor is:

[0051]

[0052] The first-order approximate transfer function is: v

[0053]

[0054] Where k is the Boltzmann constant, T is the absolute temperature, C s1 is the capacitance value of the sampling capacitor Cs1, gds1 is the small signal admittance of the switch S1 in the figure, and gds2 is the small signal admittance of the switch S2 in the figure.

[0055] Therefore, the integrated noise voltage on the sampling capacitor is:

[0056]

[0057] In the formula, C s1 is the capacitance value of the sampling capacitor Cs1.

[0058] Similarly, the integrated noise on the feedback capacitor is:

[0059] According to the principle of non-correlated noise superposition, the equivalent noise of the sample-and-hold circuit is:

[0060]

[0061] This formula shows that the integrated noise voltage on the sampling capacitor and the feedback capacitor has nothing to do with the switch on-resistance and only depends on the capacitance value. This part of the noise voltage affects the sampling accuracy of the subsequent stages of the pipeline ADC through charge transfer.

[0062] The equivalent noise voltage of the operational amplifier OTA is calculated as follows:

[0063]

[0064] is the noise power spectral density of the operational amplifier, G n is the noise gain, BW n is the equivalent bandwidth of the noise. If the operational amplifier OTA is approximated as a single-pole operational amplifier, the power spectrum density of the operational amplifier is as follows:

[0065]

[0066] In the formula, g m is the transconductance of the field effect tube;

[0067] The noise gain can be expressed as:

[0068]

[0069] For a single-pole op amp, the equivalent bandwidth of its noise is the frequency of the pole. The equivalent noise bandwidth is:

[0070]

[0071] In the formula, C c1 is the Miller compensation capacitor of the operational amplifier, The noise at the output and input of the amplified phase operational amplifier is:

[0072]

[0073]

[0074] n f is the noise factor, which is determined by the structure of the operational amplifier, γ is the noise coefficient of the transistor, and g m1 is the transconductance of the amplifier input tube. The noise of the operational amplifier is related to the Miller capacitance value C c1 Inversely proportional, the larger the Miller capacitance value, the smaller the equivalent thermal noise, but at the same time it will cause the gain-bandwidth product of the operational amplifier to decrease, so the value of the Miller capacitance needs to be compromised.

[0075] Since the actual circuit has differential input, according to the principle of non-correlated noise superposition, the total thermal noise of the first-stage circuit is twice the single-ended thermal noise, so the thermal noise of the first-stage circuit can be obtained from the following formula:

[0076]

[0077] According to the derivation of thermal noise and corresponding parameters, the equivalent noise voltage of the first stage circuit can be obtained as follows:

[0078]

[0079] Its RMS value is 95.9uV.rms, and the overall noise of the ADC is 287.7uV.rms according to theoretical derivation. Figure 5 The simulation results shown are single-ended equivalent noises. Therefore, the equivalent noise of the first stage circuit of the fully differential structure is 84.42uV.rms, and the actual noise of the ADC is 253.26uV.rms.

[0080] The isolation amplifier noise model is as follows Figure 6 As shown, including resistors R1, R2, R3, R4 and operational amplifier, the bandwidth calculation result is as follows. The feedback network bandwidth is 1.33MHZ, the RC filter bandwidth is 5.81MHZ, and the amplifier gain bandwidth product is limited to 1.82MHZ. These three parts together constitute a filter.

[0081]

[0082]

[0083]

[0084]

[0085] In the formula, f c_feedback is the feedback network bandwidth, f c_ChargeBucket is the bandwidth of the RC filter, Gain is the gain of the amplifier, f c_AMP is the gain bandwidth of the amplifier, GBW is the gain bandwidth product of the amplifier, C1 is, C2 is the capacitance value of the feedback capacitor and the filter capacitor, R1, R2, R3 are the resistance values ​​of resistors R1, R2, and R3 respectively. Since the cutoff points of the operational amplifier and the feedback network are very close, the filter is approximated as a second-order filter with a cutoff frequency of 1.33MHZ to simplify the calculation, and considering the position of each node will give a more accurate result, and the noise bandwidth BW is calculated. n It is 1.62MHZ.

[0086]

[0087]

[0088] In the formula, f c_system is the cutoff frequency of the filter, K n are the coefficients of the second-order filter.

[0089] In the calculation of feedback network noise, two resistors (R1, R2) are connected in parallel to form an equivalent feedback resistor network, and then the thermal noise is calculated using the resistors, Boltzmann constant, and Kelvin temperature.

[0090]

[0091]

[0092] Where k is the Boltzmann constant, R eq is the equivalent resistance, E nReq is the noise spectrum density of the equivalent resistance, T k is the Kelvin temperature;

[0093] Combining the feedback network noise and the operational amplifier noise, multiplying the total noise by the square root of the bandwidth converts the spectral density to an input noise of 17.88uV.rms. Finally, multiplying this noise by the noise gain gives the isolation amplifier noise of 196.7uV.rms.

[0094]

[0095]

[0096] E n_Total =Gain·E n_in_Total =(11)·(17.88uV.rms)=196.7uV.rms (24);

[0097] In the formula, E n is the noise spectrum of the isolation amplifier, E n_in_Total is the noise spectrum of the isolation amplifier within the bandwidth, E n_Total is the total noise voltage of the isolation amplifier, E nAMP is the noise spectrum of the operational amplifier.

[0098] The simulation results of the isolation amplifier noise model are as follows: Figure 7As shown. Noise simulation requires the amplifier to be in the linear operating range to ensure correct results. After simulation, the simulated noise spectral density and integrated noise curves can be seen on the right. The total noise curve tends to be flat at the end, and the final value of convergence is 174.83uV.rms. The calculated result of the total noise of the isolation amplifier is 196.7uV.rms. The difference between these two numbers is because the simulation more accurately considers all nodes in the circuit.

[0099] The reference circuit noise model is as follows Figure 8 As shown in Figure 2, this model provides a voltage reference standard for the analog-to-digital converter quantization process. The N-bit ADC divides the reference voltage into 2 N The voltage of the measured signal is quantified.

[0100] The reference voltage noise is a cumulative growth process for the noise generated by the quantization process. For the input, when the voltage value of the input signal is higher, the overall noise is proportional to the ADC DC input voltage, and the reference voltage has a greater impact on the quantization process. in / V REF The ratio increases accordingly, so when the ADC uses full-scale input, its noise dominates the overall system noise. When the input voltage reaches the full measurement scale, the reference voltage source noise has the greatest impact on the quantization process, but as long as it is still much smaller than 1 / 2LSB, the noise calculation can be ignored. The simulation results are as follows: Fig. 9 shown.

[0101] The equivalent noise of the present invention is:

[0102]

[0103] To calculate the SNR of the present invention, the full-scale root mean square noise input voltage range is required. The full-scale range of the present invention is 1.2V, and the full-scale range corresponds to the peak input, which needs to be converted into an effective value for calculation, as shown in the following formula:

[0104] V FSR_rms =0.5 V FSR_ppk ·0.707=0.5·1.2V·0.707=0.424V (26);

[0105] Therefore, the signal-to-noise ratio of the present invention is:

[0106]

[0107] Where V nADC is the total rms noise of the ADC, V nREF is the total rms noise of the reference circuit, E nAMP is the total rms noise of the isolation amplifier, V FSR_ppk is the peak value of the full-scale input voltage, VFSR_rms is the effective value of the full-scale input voltage, V ntotal is the equivalent noise of the system;

[0108] Table 1 Data results of theoretical model and actual model of the present invention

[0109] <![CDATA[V nREF ]]> <![CDATA[V nADC ]]> <![CDATA[V nAMP ]]> <![CDATA[V ntotal ]]> SNDR Theoretical Model 23.67 287.7 196.7 349.31 61.6 Actual Model 23.67 253.26 174.83 308.65 62.7

[0110] As shown in Table 1, the present invention not only includes a pipeline ADC, but also introduces a noise model of a reference circuit and an isolation amplifier. The full-scale signal-to-noise ratio of the pipeline ADC used in the present invention is 54.6 dB, and the signal-to-noise ratio of the system model is 61.6 dB. This is because the addition of an isolation amplifier reduces the noise in the signal path from the ground loop, thereby reducing the overall noise of the ADC system.

[0111] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A noise model circuit based on a time-interleaved pipeline ADC system, characterized in that: Includes isolation amplifier noise model, reference circuit noise model and time-interleaved pipeline ADC model; The isolation amplifier noise model is composed of an operational amplifier and an external feedback structure, and processes the thermal noise of the operational amplifier and its feedback network; the feedback structure includes a capacitor C2 and a resistor R2 connected in parallel between the negative input terminal and the output terminal of the operational amplifier, a resistor R1 connected to the negative input terminal of the operational amplifier, and the other end of the resistor R1 is grounded; the output terminal of the operational amplifier is also connected in series with a resistor R3, a capacitor C1 and a resistor R4, the other end of the resistor R4 is grounded, and the positive input terminal of the operational amplifier is grounded through a voltage source Vamp; The reference circuit noise model processes the quantization noise generated by the reference circuit; The time-interleaved pipeline ADC model includes a time-interleaved circuit and a pipeline ADC, and processes the noise generated by the sampling structure and the operational amplifier; The time interleaving circuit comprises an analog-to-digital converter ADC1, an analog-to-digital converter ADC2, an analog-to-digital converter ADC3, an analog-to-digital converter ADC4 and a reference ADC, the input end of each analog-to-digital converter is connected to a four-frequency division circuit and a three-frequency division circuit, the output clock of the four-frequency division circuit and the three-frequency division circuit cross-controls the sampling of the analog-to-digital converter and the reference ADC, the output end of each analog-to-digital converter is connected to a four-to-one selection circuit, and the output end of the reference ADC is connected to a digital background calibration through a delay circuit; The pipeline ADC includes a clock generating circuit, a sampling and holding circuit SHA, a multi-stage pipeline conversion structure, a delay alignment register circuit and a redundant bit digital correction circuit. The output end of the pipeline conversion structure of the last stage is provided with a flash memory type ADC. The clock generating circuit is connected to the pipeline conversion structures of each stage to control the working timing of the pipeline conversion structure. The sampling and holding circuit SHA is connected to the input end of the pipeline conversion structure and serves as a front-end sampling channel of each stage of the pipeline conversion structure channel to provide the pipeline conversion structure with a sampled input voltage. The structure of each stage of the pipeline conversion structure is the same, and the output of the previous stage is used as the input of the next stage to complete the working mode of the pipeline. The delay alignment register circuit and the redundant bit digital correction circuit are connected to the output of the four-to-one selection circuit to store and calibrate the digital code output by the pipeline conversion structure.

2. The noise model circuit based on the time-interleaved pipeline ADC system according to claim 1, characterized in that: The clock generating circuit is used to generate two sets of clock control signals with non-overlapping phases, control the multi-stage pipelines of the pipeline conversion structure and use different timings to make the circuits work alternately; The pipeline conversion structure is used to divide the conversion operation into multiple stages, and each stage conversion obtains a certain digital output bit, forming a pipeline working mode, mainly processing the thermal noise generated by the sampling and holding circuit and operational amplifier of each stage; The delay alignment register circuit synchronizes the output data of each stage of pipeline conversion structure; The redundant bit digital correction circuit uses the redundant bits to perform error correction on the conversion result.

3. The noise model circuit based on the time-interleaved pipeline ADC system according to claim 1, characterized in that: The pipeline conversion structure is composed of the MDAC and sub-ADC circuits inside the analog-to-digital converter, which are used to realize digital-to-analog conversion, subtraction, amplification and sampling and holding functions; The MDAC includes a sampling and holding circuit, an operational amplifier G2 and a sub-DAC. The input ends of the sampling and holding circuit and the sub-ADC are connected to the input signal, the output end of the sub-ADC is connected to the input end of the sub-DAC, and the output ends of the sampling and holding circuit and the sub-DAC are connected to the input end of the operational amplifier G2. The operational amplifier G2 completes signal amplification, and the amplified signal is connected to the next pipeline conversion structure.

4. The noise model circuit based on the time-interleaved pipeline ADC system according to claim 3, characterized in that: The sampling and holding circuit is used to collect the analog signal input by the ADC circuit, and hold the sampled value until the next clock cycle arrives, and then supply it to the subsequent circuit for quantization processing; the sub-DAC is used to convert the digital output code in each stage of the pipeline conversion structure into an analog signal; The sample-and-hold circuit includes a switch S1, a switch S2, a switch S3, a sampling capacitor Cs1, and a feedback capacitor Cf1. The two ends of the switch S1 are respectively connected to the input voltage Vi and the sampling capacitor Cs1. The switch S2 is connected to the input end of the operational amplifier OTA and the ground. The switch S3 is connected to the output end of the operational amplifier OTA and the common-mode voltage. The sampling capacitor Cs1 is respectively connected to the switch S1 and the input end of the operational amplifier. One end of the feedback capacitor Cf1 is connected to the input end of the operational amplifier OTA, and the other end is connected to the output end of the operational amplifier OTA.

5. The noise model circuit based on time-interleaved pipeline ADC system according to claim 3, characterized in that: The sample-and-hold circuit is equivalent to a switched capacitor circuit, which includes a sampling capacitor Cs1, a feedback capacitor Cf1, and an operational amplifier OTA. The equivalent noise voltage of the sample-and-hold circuit is: Where k is the Boltzmann constant, T is the absolute temperature, C s1 is the capacitance value of the sampling capacitor Cs1, C f1 is the capacitance value of the feedback capacitor Cf1; The equivalent noise voltage of the operational amplifier OTA is: Where n f is the noise factor, which is determined by the structure of the operational amplifier, C c1 is the Miller compensation capacitance value of the operational amplifier, k is the Boltzmann constant and T is the absolute temperature.

6. The noise model circuit based on the time-interleaved pipeline ADC system according to claim 5, characterized in that: The pipeline ADC includes a plurality of pipeline stage circuits, and the equivalent noise of the first stage circuit is calculated by the following formula: Where n f is the noise factor, which is determined by the structure of the operational amplifier, γ is the noise coefficient of the transistor, C c1 is the Miller compensation capacitance value of the operational amplifier, C s1 is the capacitance value of the sampling capacitor Cs1, C f1 is the capacitance value of the feedback capacitor Cf1, k is the Boltzmann constant, T is the absolute temperature, is the equivalent noise voltage of the operational amplifier.

7. The noise model circuit based on time-interleaved pipeline ADC system according to claim 1, characterized in that: The equivalent output noise of the isolation amplifier noise model is: In the formula, Gain is the gain of the amplifier, R1 and R2 are the resistance values ​​of resistors R1 and R2 respectively, and BW is n is the noise bandwidth, k is the Boltzmann constant, R eq is the equivalent resistance of resistors R1 and R2, T k is the Kelvin temperature, E n_in_Total is the noise voltage of the isolation circuit within the bandwidth, E n_Total is the total noise voltage of the isolation circuit, E nReq is the noise voltage of the equivalent resistance, E nAMP To isolate the noise of the operational amplifier.

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