Method and electronic device for designing a network of logic gates

Abstract

The present disclosure relates to a method, device and equipment for designing a logic gate network. The method comprises initializing a logic gate network, updating a candidate logic gate network set based on the initialized logic gate network by modifying input connections of the candidate logic gate network set using an evolutionary algorithm, and evaluating an encoding success rate of the candidate logic gate network set after each update until a candidate logic gate network with an encoding success rate exceeding a threshold is obtained, and determining the candidate logic gate network as a target logic gate network. Since the input connections of each logic gate of the target logic gate network are updated iteratively by the evolutionary algorithm, the input connections of each logic gate are optimized, and the encoding success rate for the target logic gate network is also improved accordingly.

Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more particularly to methods and electronic devices for designing test circuits. Background Technology

[0002] During the chip manufacturing and packaging process, defects are inevitably introduced due to various reasons (such as process technology and materials), causing the chip to malfunction. The main task of chip testing is to identify defective chips. Because the costs incurred by defective chips entering the market far outweigh the costs of chip testing itself, chip testing is a crucial part of the chip manufacturing process.

[0003] Specifically, design for testability (DFT) structures, such as scan chains, can be added to the chip during the chip design phase, and chips with DFT structures can be manufactured. Automatic test pattern generation (ATPG) tools can be used to generate chip test patterns, and automatic test equipment (ATE) can be used to input these test patterns into the chip under test. By comparing the response of the chip under test with the expected response, quality inspection can be performed immediately after production.

[0004] As chip integration and complexity continue to increase, the required test vector sets are also growing rapidly. This leads to a several-fold increase in chip testing time, which in turn significantly increases testing costs. To alleviate this problem, test compression techniques have been developed. However, conventional test compression techniques suffer from problems such as a large number of encoded bits. Summary of the Invention

[0005] In view of the above problems, embodiments of this disclosure aim to provide a method, apparatus, and device for designing logic gate networks, as well as a circuit for testing a circuit under test. The logic gate network is used to test a circuit under test within the same chip.

[0006] According to a first aspect of this disclosure, a method for designing a logic gate network is provided. The method includes constructing a candidate logic gate network set comprising multiple candidate logic gate networks by modifying at least one input connection of at least one logic gate in at least one initial logic gate network. Each of the at least one initial logic gate network comprises multiple logic gates, each logic gate being associated with multiple scan chains in a circuit under test (TBD). The method further includes determining a target logic gate network for testing the TBD based on characteristics of the TBD and the candidate logic gate network set, the characteristics of the TBD including at least one of a scan chain distribution of the TBD's scan chains during a test cycle or an unknown state distribution of the unknown states during a test cycle. By modifying the logic gate input connections of the logic gate networks and selecting a suitable target logic gate network from the modified logic gate network set using the scan chain distribution or the unknown state distribution, a logic gate network with optimized input connection number and / or connection method can be obtained. Since the input connections of the logic gate network are optimized for the TBD, the number of input connections of the logic gate network can be reduced compared to a conventional balanced XOR gate network, thereby reducing the number and / or complexity of the encoded bits associated with the input connections. Furthermore, the combination of encoded bits received by each logic gate in the logic gate network is also optimized. Consequently, the encoding success rate can be improved. In addition, the overhead of computational resources can be reduced.

[0007] In one possible implementation, determining the target logic gate network includes iteratively updating the candidate logic gate network set at least once by: determining multiple network evaluation results of multiple candidate logic gate networks in the candidate logic gate network set using features of the circuit under test; updating the candidate logic gate network set by changing at least one input connection of at least one gate of the multiple candidate logic gate networks if all multiple network evaluation results are below a first threshold using an evolutionary algorithm; and selecting the target logic gate network from the updated candidate logic gate network set based on the multiple network evaluation results of the multiple candidate logic gate networks in the updated candidate logic gate network set. By updating and evaluating the candidate logic gate network set, the candidate logic gate network set can be continuously optimized, thereby further improving the encoding success rate.

[0008] In one possible implementation, updating the candidate logic gate network set includes determining a first group and a second group of candidate logic gate networks from the set, wherein at least one network corresponding to the first group of candidate logic gate networks has a lower evaluation result than at least one network corresponding to the second group of candidate logic gate networks; generating a third group of candidate logic gate networks by modifying at least one input connection of at least one logic gate in the second group of candidate logic gate networks using an evolutionary algorithm; removing the first group of candidate logic gate networks from the candidate logic gate network set; and adding the third group of candidate logic gate networks to the candidate logic gate network set. By using an evolutionary algorithm to modify the candidate logic gate networks, a more optimized candidate logic gate network for the circuit under test can be obtained. This candidate logic gate network can reduce the number of encoding bits used and improve the encoding success rate. Furthermore, by using an evolutionary algorithm, a better candidate logic gate network can be obtained more quickly, reducing design time.

[0009] In one possible implementation, generating a third set of candidate logic gate networks from a second set of candidate logic gate networks in the candidate logic gate network set involves hybridizing or mutating at least a portion of the logic gate networks in the second set to generate the third set of candidate logic gate networks. By using hybridization or mutation, a logic gate network with optimized connections can be obtained more quickly than by sequentially changing the input connections, reducing computational load and resource consumption.

[0010] In one possible implementation, hybridizing at least a portion of the logic gate networks in the second group of candidate logic gate networks to generate a third group of candidate logic gate networks includes: selecting a first logic gate network and a second logic gate network from the second group of candidate logic gate networks; and combining the first group of logic gates in the first group of logic gate networks and the second group of logic gates in the second group of logic gate networks to form a third group of candidate logic gate networks. The first group of logic gates corresponds to the first scan chain among multiple scan chains, and the second group of logic gates corresponds to the second scan chain among multiple scan chains. The first scan chain is different from the second scan chain. By using candidate logic gates with high encoding efficiency for hybridization, the encoding success rate of the hybridized candidate logic gates can be maintained to a large extent or with a high probability.

[0011] In one possible implementation, mutating at least a portion of the logic gate networks in the second group of candidate logic gate networks to generate the third group of candidate logic gate networks involves altering the input connections of at least a portion of the logic gates in the second group of candidate logic gate networks using a mutation rate. By using candidate logic gates with higher coding efficiency for mutation, the coding success rate of the candidate logic gates generated by the hybridization can be maintained to a large extent or with a high probability. Furthermore, it is possible to expand beyond the range of encoded bits in the original population of candidate logic gate networks to obtain new candidate logic gate networks with significantly different encoded bits compared to the parent candidate logic gate networks. This increases the possibility of obtaining better candidate logic gate networks.

[0012] In one possible implementation, updating the candidate logic gate network set includes selecting at least one logic gate from the candidate logic gate network set based on the logic gate encoding performance evaluation results for the logic gates in the candidate logic gate network set; and adding input connections to at least one logic gate to update the candidate logic gate network set. By adding encoding bits to the candidate logic gate network, the encoding space of the candidate logic gate network can be significantly increased, thereby increasing encoding flexibility and correspondingly increasing the encoding success rate.

[0013] In one possible implementation, updating the candidate logic gate network set involves adding input connections to at least one logic gate to include usage correlations with other logic gates in the same candidate logic gate network based on at least one logic gate. Input connections not present in the logic gates associated with at least one logic gate are added to the at least one logic gate to update the candidate logic gate network set. Correlation is used to represent the probability that two logic gates are used simultaneously during a test cycle. By using correlation, the encoding space of the candidate logic gate network can be increased more efficiently, thereby increasing encoding flexibility and correspondingly increasing the encoding success rate.

[0014] In one possible implementation, the circuit under test (DUT) is further characterized by the total number of scan chains in the DUT, and the method further includes using the total number of scan chains to determine at least one initial logic gate network. By using the total number of scan chains, the logic gate network can be initialized randomly relatively easily. This can reduce the design time of the logic gate network.

[0015] In one possible implementation, each of the initial logic gate networks in at least one initial logic gate network includes multiple XOR gates, the multiple XOR gates having the same number of input connections, the inputs of the multiple XOR gates being configured to receive different combinations of encoded bits, and the outputs of the multiple XOR gates being configured to output different decoded bits.

[0016] In one possible implementation, the target logic gate network is configured to be coupled to the circuit under test (DUT) in the chip or to the same circuit as the DUT.

[0017] According to a second aspect of this disclosure, a computer-readable storage medium is provided that stores a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method according to the first aspect.

[0018] According to a third aspect of this disclosure, a computer program product is provided, comprising a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method according to the first aspect.

[0019] According to a fourth aspect of this disclosure, an electronic device is provided, including one or more processors; and a memory including computer instructions, which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method according to the first aspect of this disclosure.

[0020] According to a fifth aspect of this disclosure, an electronic device is provided, including a construction unit and a determination unit. The construction unit is configured to construct a candidate logic gate network set comprising multiple candidate logic gate networks by changing at least one input connection of at least one logic gate in at least one initial logic gate network. Each initial logic gate network comprises multiple logic gates, each logic gate being associated with multiple scan chains in a circuit under test (DUT). The determination unit is configured to determine a target logic gate network for testing the DUT based on features of the DUT and the candidate logic gate network set. The features of the DUT include at least one of a scan chain distribution of the DUT's scan chains during a test cycle or an unknown state distribution of the unknown states during a test cycle. By changing the logic gate input connections of the logic gate networks and selecting a suitable target logic gate network from the changed logic gate network set using the scan chain distribution or the unknown state distribution, a logic gate network with optimized input connection number and / or connection method can be obtained. Since the input connections of the logic gate network are optimized for the DUT, the number of input connections of the logic gate network can be reduced compared to a conventional balanced XOR gate network, thereby reducing the number and / or complexity of the encoded bits associated with the input connections. Furthermore, the combination of encoded bits received by each logic gate in the logic gate network is also optimized. Consequently, the encoding success rate can be improved. In addition, the overhead of computational resources can be reduced.

[0021] In one possible implementation, the determining unit is further configured to update the candidate logic gate network set by iteratively performing the following operations at least once: determining multiple network evaluation results of multiple candidate logic gate networks in the candidate logic gate network set using features of the circuit under test; updating the candidate logic gate network set by changing at least one input connection of at least one logic gate of the multiple candidate logic gate networks if all multiple network evaluation results are below a first threshold using an evolutionary algorithm; and selecting a target logic gate network from the updated candidate logic gate network set based on the multiple network evaluation results of the multiple candidate logic gate networks in the updated candidate logic gate network set. By updating and evaluating the candidate logic gate network set, the candidate logic gate network set can be continuously optimized, thereby further improving the encoding success rate.

[0022] In one possible implementation, the determining unit is further configured to: determine a first group of candidate logic gate networks and a second group of candidate logic gate networks from the candidate logic gate network set, wherein at least one network corresponding to the first group of candidate logic gate networks has a lower evaluation result than at least one network corresponding to the second group of candidate logic gate networks; generate a third group of candidate logic gate networks by modifying at least one input connection of at least one logic gate in the second group of candidate logic gate networks using an evolutionary algorithm; remove the first group of candidate logic gate networks from the candidate logic gate network set; and add the third group of candidate logic gate networks to the candidate logic gate network set. By using an evolutionary algorithm to modify the candidate logic gate networks, a more optimized candidate logic gate network for the circuit under test can be obtained. This candidate logic gate network can reduce the number of encoding bits used and improve the encoding success rate. Furthermore, by using an evolutionary algorithm, a better candidate logic gate network can be obtained more quickly, reducing design time.

[0023] In one possible implementation, the determining unit is further configured to: hybridize or mutate at least a portion of the logic gate networks in the second set of candidate logic gate networks to generate a third set of candidate logic gate networks. By using hybridization or mutation, a logic gate network with optimized connections can be obtained more quickly than by sequentially changing the input connections, reducing computational load and resource consumption.

[0024] In one possible implementation, the determining unit is further configured to: select a first logic gate network and a second logic gate network from the second group of candidate logic gate networks; and combine the first group of logic gates in the first group of logic gate networks and the second group of logic gates in the second group of logic gate networks into a third group of candidate logic gate networks, wherein the first group of logic gates corresponds to the first scan chain among multiple scan chains, and the second group of logic gates corresponds to the second scan chain among multiple scan chains, and the first scan chain is different from the second scan chain. By using candidate logic gates with high coding efficiency for hybridization, the coding success rate of the candidate logic gates generated by hybridization can be maintained to a large extent or with a high probability.

[0025] In one possible implementation, the determining unit is further configured to modify the input connections of at least a portion of the logic gates in at least a portion of the second set of candidate logic gate networks using a mutation rate to generate a third set of candidate logic gate networks. By using candidate logic gates with higher coding efficiency for mutation, the coding success rate of the candidate logic gates generated by hybridization can be maintained to a large extent or with a high probability. Furthermore, it is possible to move beyond the range of encoded bits in the original population of candidate logic gate networks to obtain new candidate logic gate networks with significantly different encoded bits from those of the parent candidate logic gate networks. This increases the possibility of obtaining better candidate logic gate networks.

[0026] In one possible implementation, the determining unit is further configured to select at least one logic gate from the candidate logic gate network set based on the logic gate encoding performance evaluation results for the logic gates in the candidate logic gate network set; and to add input connections to the at least one logic gate to update the candidate logic gate network set. By adding encoding bits to the candidate logic gate network, the encoding space of the candidate logic gate network can be significantly increased, thereby increasing encoding flexibility and correspondingly increasing the encoding success rate.

[0027] In one possible implementation, the determining unit is further used to add input connections that the at least one logic gate does not have to the at least one logic gate, based on the usage correlation of at least one logic gate with other logic gates in the same candidate logic gate network, to update the candidate logic gate network set. The correlation representation is used to indicate the probability that two logic gates are used simultaneously during a test cycle. By using correlation, the encoding space of the candidate logic gate network can be increased more efficiently, thereby increasing encoding flexibility and correspondingly increasing the encoding success rate.

[0028] In one possible implementation, each of the initial logic gate networks in at least one initial logic gate network includes multiple XOR gates, the multiple XOR gates having the same number of input connections, the inputs of the multiple XOR gates being configured to receive different combinations of encoded bits, and the outputs of the multiple XOR gates being configured to output different decoded bits.

[0029] In one possible implementation, the target logic gate network is configured to be coupled to the circuit under test (DUT) in the chip or to the same circuit as the DUT.

[0030] According to a sixth aspect of this disclosure, a circuit for testing a circuit under test is provided. The circuit includes a first logic gate network coupled to the circuit under test and includes: a first logic gate including a first plurality of input connections and configured to decode a first plurality of encoded bits received at the first plurality of input connections into a first decoded bit; and a second logic gate including a second plurality of input connections and configured to decode a second plurality of encoded bits received at the second plurality of input connections into a second decoded bit, the number of the second plurality of input connections being different from the number of the first plurality of input connections. By using an unbalanced logic gate network with logic gates having different numbers of input connections, a logic gate network with optimized input connection numbers and / or connection methods can be obtained. Since the input connections of the logic gate network are optimized for the circuit under test, the number of input connections of the logic gate network can be reduced compared to a conventional balanced XOR gate network, thereby reducing the number and / or complexity of encoded bits associated with the input connections. Furthermore, the combination of encoded bits received by each logic gate of the logic gate network is also optimized. Accordingly, the encoding success rate can be improved. In addition, the overhead of computational resources can be reduced.

[0031] In one possible implementation, the circuit further includes: a second logic gate network and a third logic gate network. The second logic gate network is coupled to the circuit under test (DUT) and includes a third logic gate, including a third plurality of input connections, and configured to decode a third plurality of encoded bits received at the third plurality of input connections into a third decoded bit; and a fourth logic gate, including a fourth plurality of input connections, and configured to decode a fourth plurality of encoded bits received at the fourth plurality of input connections into a fourth decoded bit, the number of the fourth plurality of input connections being different from the number of the third plurality of input connections. The third logic gate network is coupled to the DUT and includes a fifth logic gate, including a fifth plurality of input connections, and configured to decode a fifth plurality of encoded bits received at the fifth plurality of input connections into a fifth decoded bit; and a sixth logic gate, including a sixth plurality of input connections, and configured to decode a sixth plurality of encoded bits received at the sixth plurality of input connections into a sixth decoded bit, the number of the sixth plurality of input connections being different from the number of the sixth plurality of input connections. By setting the second and third logic gate networks for the decoder in the test circuit as unbalanced logic gate networks—that is, optimizing the multiple input connections of the logic gates in each logic gate network to have different numbers of input connections—the number of input connections of the logic gate network can be further reduced, thereby reducing the number and / or complexity of the encoded bits associated with the input connections. Furthermore, the combination of encoded bits received by each logic gate of the logic gate network is also optimized. Accordingly, the encoding success rate can be improved. Additionally, the overhead of computational resources can be reduced. In one possible implementation, the circuit further includes a first plurality of AND gates coupled to the first and second logic gate networks, and configured to: perform a logical AND operation on the first decoded bit output of the first logic gate and the third decoded bit output of the second logic gate to generate a first logic value for input to the first scan chain of the circuit under test; and perform a logical AND operation on the second decoded bit output of the first logic gate and the fourth decoded bit output of the second logic gate to generate a second logic value for input to the second scan chain of the circuit under test. By using multiple AND gates, the scanning chain can be opened or closed, thereby keeping the power consumption of the circuit under test below a threshold.

[0032] In one possible implementation, the circuit further includes a second plurality of AND gates coupled to a plurality of scan chains and a third logic gate network in the circuit under test, and is configured to: perform a logical AND operation on the fifth decoded bit output of the fifth logic gate and the bit output of the first scan chain in the plurality of scan chains to generate a first test logic value, and perform a logical AND operation on the sixth decoded bit output of the sixth logic gate and the bit output of the second scan chain in the plurality of scan chains to generate a second test logic value. By using the plurality of AND gates, the opening or closing of the scan chains can be controlled, thereby masking the unknown state output of the circuit under test to correctly observe the simulation output. It should be understood that the content described in the summary section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0033] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic circuit diagram of a conventional logic gate network is shown.

[0034] Figure 2 A schematic block diagram of a chip for applying a compression technique according to some embodiments of the present disclosure is shown.

[0035] Figure 3 A circuit diagram of an exemplary logic gate network according to some embodiments of the present disclosure is shown.

[0036] Figure 4 A flowchart illustrating a method for designing logic gate networks according to some embodiments of the present disclosure is shown.

[0037] Figure 5 A flowchart illustrating a method for determining a target logic gate network according to some embodiments of the present disclosure is shown.

[0038] Figure 6 A schematic diagram is shown illustrating the use of an evolutionary algorithm to update a set of candidate logic gate networks according to some embodiments of this disclosure.

[0039] Figure 7 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0040] Figure 8 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0041] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0042] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. The term "and / or" indicates at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0043] It should be understood that the technical solutions provided in the embodiments of this application may not be repeated in the following description of specific embodiments, but it should be regarded as that there are mutual references between these specific embodiments and they can be combined with each other.

[0044] In the electronic design automation (EDA) process for chips, users input configurations into EDA software, which generates logic circuits. The chips are then fabricated and manufactured. During chip testing, the chip can be mounted in an ATE (Automatic Design Equipment) system, and the ATE inputs test stimuli to the IC chip's input pins. By comparing the responses of the chip's output pins with the expected responses, the chip's qualification can be determined. As mentioned above, with the continuous increase in chip integration and complexity, the required test vector set also grows rapidly. This leads to an increase in chip testing costs. To control testing costs, test compression techniques have been proposed to ensure test coverage while compressing test vectors. Test compression techniques are based on scan chains. Scan chain technology essentially connects flip-flops in sequential circuits into multiple "shift registers," where the input and output values ​​of each shift register can be observed individually.

[0045] The feasibility of the compression test is based on the fact that a single raw test vector generated by ATPG contains the input values ​​of all shift registers on the scan chain, but only a small portion of the input values ​​on these shift registers are valid. Therefore, the raw test vector can be compressed and decompressed by the excitation decompressor to recover the valid values. Additionally, the output values ​​on the scan chain can also be compressed by the response compressor. The compressed output value is sent to the ATE via an output pin, and the ATE compares the compressed output value with the expected value to locate the shift register position in the scan chain where the error occurred.

[0046] In test compression techniques, the compression ratio of the input and output values ​​of the scan chain shift register can often reach hundreds or thousands, thus greatly reducing the storage size of the test vector. However, this also introduces two of the most critical issues in the field of test compression. The first issue concerns power consumption. The original input values ​​of the shift register have very few valid values ​​(exhibiting sparsity), so the shift power consumption on the scan chain during the input phase is also very low. However, the input compressed values ​​often lose their sparsity after decompression. In the process of directly shifting the decompressed values ​​to the corresponding shift register, unacceptable shift power consumption will be generated. This will cause a decrease in chip test yield, a reduction in test stability, and may even lead to the chip overheating and burning out during testing. The second issue concerns the masking of unknown states (X states) generated during the test. Due to the unknown functions of some circuit modules, some unpredictable unknown values ​​will be output, which are called X states. Some circuits that generate X states are distributed on the scan chain output values. When the compression module performs compression, these X states can mask the valid values ​​of other circuits that are compressing simultaneously, resulting in unobservable locations in the circuit. This can lead to decreased fault coverage and an increase in the number of test vectors.

[0047] The conventional approach addresses these two issues by introducing a low-power control module and a mask control module, respectively. Functionally similar, both are decoders. The low-power control module's decoder output controls the input value of the scan chain. When the decoder output is 0, a fixed value is input to the shift register of the controlled scan chain; otherwise, the output value of the decompression module is input to the shift register of the controlled scan chain. The mask control module's decoder output controls the input value of the corresponding scan chain to the response compression module. When the decoder output is 0, the input value of the controlled scan chain to the response compression module is clamped to a fixed value; otherwise, the output value of the controlled scan chain is input to the response compression module. The decoder outputs of these two control modules are connected to each scan chain, and setting the decoder output value to 1 or 0 enables the corresponding scan chain to be turned on or off. The low-power control module enables scan chains containing valid input values ​​to allow the excitation decompression module to input shift values ​​into the scan chains of the circuit under test (DUT), while the mask control module disables scan chains containing X-state outputs to prevent X-state outputs from the scan chains in the DUT. For example, in some conventional schemes, an XOR gate network can be used to form the decoder.

[0048] Figure 1 Some logic gate networks 100 used to construct a conventional decoder are shown. Logic gate network 100 is a balanced logic gate network, and the logic gates used are XOR gates. The number of input connections for each logic gate in the balanced logic gate network is the same, for example, in... Figure 1 In this configuration, each XOR operation has three input connections. Figure 1In this structure, the logic gate network 100 includes 6 encoded bits X1, X2...X6 and 12 decoded bits Y1, Y2...Y12. Each XOR has three input connections that receive three encoded bits from the 6 encoded bits X1, X2...X6 respectively. Each XOR performs an XOR operation based on the logical values ​​of the three encoded bits to generate one of the 12 decoded bits Y1, Y2...Y12. In some embodiments, the logic gate network can also be based on XOR and AND gates. Generally, this structure uses the value of the XOR operation on the three encoded bits to represent the control state of the corresponding scan chain. For low-power control modules, when the user-set input shift power threshold is low, this structure uses more encoded bits and further performs AND operations on multiple output values ​​of the XOR network structure to control a scan chain. However, this balanced XOR gate network structure provides equal control for each scan chain, but the actual frequency of use for each scan chain during automatic test vector generation is different. Therefore, using this type of balanced logic gate network can lead to a waste or inadequacy of encoding capacity. Furthermore, to ensure encoding success rate, this structure uses a large number of encoding bits, resulting in significant consumption of computational resources, including hardware and software overhead.

[0049] In some embodiments of this disclosure, it can be based on, for example Figure 1 The initial logic gate network, such as the logic gate network 100 shown, is designed as the control circuit of the decoder, featuring unbalanced input connections. The target logic gate network can be determined by changing the number and / or connection objects of the input connections of each logic gate in the initial logic gate network, based on the characteristics of the circuit under test. The target logic gate network can be an unbalanced logic gate network, and the number of input connections for each logic gate in the unbalanced logic gate network can vary. For example, some logic gates in the logic gate network may have one or two input connections, while others may have three or more connections. The specific number of input connections for each logic gate is not limited here. Since the number and / or connection objects of each logic gate are optimized based on the characteristics of the circuit under test, fewer encoding bits are required for unbalanced logic gates compared to a conventional balanced XOR gate network, thus improving the encoding success rate.

[0050] Figure 2 A schematic block diagram of a chip 200 for applying a compression technique according to some embodiments of the present disclosure is shown. Figure 2As shown, chip 200 includes a circuit under test (DUT) 11, a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, a low-power controller 14, a mask controller 15, and multiple AND gates 7-1, 7-2…..7-N and multiple AND gates 9-1, 9-2…9-N, where N represents an integer greater than 1. In chip 200, the low-power shift register 16, mask register 18, decompression module 12, compression module 13, low-power controller 14, mask controller 15, and multiple AND gates 7-1, 7-2…..7-N and multiple AND gates 9-1, 9-2…9-N are used to test the DUT 11. Therefore, in one embodiment, the test circuit of chip 200 may include at least one of the low-power controller 14 or the mask controller 15. In another embodiment, the test circuit of chip 200 may further include a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, and multiple AND gates 7-1, 7-2…7-N and multiple AND gates 9-1, 9-2…9-N. During actual testing of chip 200, the ATE inputs the ATPG test vector to the low-power shift register 16 of chip 200 through a small number of input pins. The ATPG test vector contains the input compressed value of the decompression module 12, i.e., the compressed seed, the encoded value of the low-power controller 14, and the encoded value of the mask controller 15, etc. The input compressed value is injected into the decompression module 12 via the low-power shift register 16 and the mask register 18. The encoded value of the low-power controller 14 is injected into the low-power controller 14 via the low-power shift register 16, and the encoded value of the mask controller 15 is injected into the mask controller 15 via the low-power shift register 16 and the mask register 18. During the input phase, the low-power controller 14 decodes the encoded value to open the appropriate scan chain. The decompression module 12 decompresses the input compressed value of the low-power shift register 16 and, under the control of the low-power controller 14, fills the decompressed value into the corresponding shift register through shifting.

[0051] During the output stage, the mask controller 15 decodes the encoded value, masks the X-state in the scan chain output value by using the decoded bit value, and sends the processed output value to the response compression module 13 for compression. In one embodiment, the circuit under test 11 includes multiple scan chains 11-1, 11-2...11-N (hereinafter individually or collectively referred to as 11), the number of scan chains corresponding to multiple AND gates 7-1, 7-2...7-N (hereinafter individually or collectively referred to as 7) and multiple AND gates 9-1, 9-2...9-N (hereinafter individually or collectively referred to as 9). Each scan chain may include one or more sequential logic circuits in the circuit under test, such as registers. The sequential logic XOR gate network generates a shift output in response to a shift output. The low-power controller 14 includes a low-power register 141 and a decoder 142, which generates control signals through decoding to control the on or off of one or more AND gates among AND gates 7-1, 7-2...7-N. For example, over multiple cycles, decoder 142 can continuously generate logic values ​​"1" for AND gate 7-1, causing the decompressed value to be successively shifted and input to scan chain 11-1. Simultaneously, decoder 142 can output "0" to turn off AND gates 7-2…7-N, allowing scan chains 11-2…11-N to continuously receive "0". Since scan chains 11-2…11-N do not change logic values, the sequential logic gates in the chip do not operate. Because the sequential logic gates do not operate, power consumption during testing can be reduced. Mask controller 15 includes mask register 151 and mask decoder 152. Mask decoder 152 generates control signals through decoding to control the on / off state of one or more AND gates 9-1, 9-2…9-N. Similarly, mask decoder 152 can generate control signals through decoding to turn off the AND gates 9-1, 9-2…9-N corresponding to the scan chain with state X.

[0052] It should be understood that the embodiments of this application do not limit the structure of the decompression module 12. The decompression module 12 can be any circuit capable of expanding a small number of test stimuli into a large number of scan chain test vectors and outputting the test vectors. The decompression module 12 can be based on a random signal generator, for example. In some embodiments of this disclosure, the decompression module 12 may include a pseudo-random sequence generator 121 and a phase shifter 122 based on a logic gate network. The pseudo-random sequence generator 121 can decompress the injected input compressed value for the first time to generate a pseudo-random sequence with a larger bit width. The phase shifter 122 decodes the pseudo-random sequence to obtain the shift values ​​of each scan chain corresponding to each period. For a given pseudo-random sequence bit width, the pseudo-random sequence state space generated by the pseudo-random sequence generator 121 is preferred, and the maximum number of pseudo-random sequences is fixed. This also determines the upper limit of the solution space that the decompression structure can utilize. Therefore, designing a better phase shifter 122 under the premise of a finite and fixed solution space of the decompression structure is also a core issue of the decompression module. In some embodiments of this disclosure, a phase shift code generator 122 based on an unbalanced logic gate network is provided, wherein at least some of the logic gates in the unbalanced logic gate network may have different numbers of input connections.

[0053] Similarly, this application embodiment does not limit the structure of the response compression module 13. The response compression module 13 can be any circuit capable of receiving test responses and performing logical operations on the received test responses to output them from a small number of output channels. The response compression module 13 can be, for example, a compression module based on a multiple-input signature register (MISR) or a logic gate network such as an XOR gate network.

[0054] Figure 3 A circuit diagram of an exemplary logic gate network 300 according to some embodiments of the present disclosure is shown. Figure 3 The logic gate network 300 in the diagram is an unbalanced logic gate network, and the logic gates used are XOR. Although in Figure 3 The configuration of the logic gate network is illustrated using XOR, but this disclosure is not limited thereto. For example, in other embodiments, an XNOR gate or other logic gates or combinations thereof may be used. It is understood that XOR or XNOR may be represented as a combination of AND gates, OR gates, and NOT gates. Such as Figure 3 The logic gate network shown can be applied to... Figure 2Any one of the phase shifter 122, low-power decoder 142, or mask decoder 152 shown. For ease of description, in the following text, the inputs of the phase shifter 122, low-power decoder 142, and mask decoder 152 connected to each other are referred to as, or collectively referred to as, the coded bits, and the outputs of the phase shifter 122, low-power decoder 142, and mask decoder 152 are referred to as, or collectively referred to as, the decoded bits.

[0055] In an unbalanced logic gate network, at least some of the logic gates have a different number of input connections, for example in... Figure 3 In some XOR converters, there are two input connections, while others have three input connections. Figure 3 In this circuit, the logic gate network 300 includes 6 coded bits X1, X2...X6 and 12 decoded bits Y1, Y2...Y12. Each XOR has 2 or 3 input connections that receive 2 or 3 of the 6 coded bits X1, X2...X6 respectively. Each XOR generates one of the 12 decoded bits Y1, Y2...Y12 by performing an XOR operation based on the logic values ​​of the 2 or 3 coded bits. For example, for the low-power decoder 142 or the mask decoder 152, each decoded bit can be used to control the on or off state of its corresponding AND gate 7 or 9. For the phase shifter 122, each decoded bit can shift the input decoded bit.

[0056] In other embodiments, a combination of multiple logic gates can be used to control the on or off of the scan chain. For example, in Figure 3 In the case where the logic gate network 300 is applied to the low-power decoder 142, decoded bits Y1 and Y2 can be further ANDed to control AND gate 7-1 and its corresponding scan chain 11-1, decoded bits Y3 and Y4 can be further ANDed to control AND gate 7-2 and its corresponding scan chain 11-2, and so on. Although two logic gates are used herein to represent a combination, it is understood that this is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, a combination of three or more logic gates can be used to perform an AND operation to control an AND gate 7 and its corresponding scan chain 11. The number of decoded bits controlling each scan chain (i.e., the number of decoded bits performing an AND operation) is related to a user-defined power threshold. The lower the power threshold, the more decoded bits can be set to control each scan chain. This allows for better satisfaction of the test power limitations required for chip testing.

[0057] Although Figure 3The diagram illustrates 12 XORs with 2 or 3 input connections, but the scope of this disclosure is not limited thereto. The logic gate network can have more or fewer logic gates, and each logic gate can have one or more input connections. Furthermore, the encoded bits received by the input connections of each logic gate in the logic gate network can differ from... Figure 3 The example shown. Used for designing such as Figure 3 The methods for using logic gate networks, such as the exemplary logic gate networks in the example, are described in detail below.

[0058] Figure 4 A flowchart illustrating a method 400 for designing logic gate networks according to some embodiments of the present disclosure is shown. The above pertains to... Figures 2-3 The various aspects described may be selectively applied to method 400. The methods for designing logic gate networks described in the embodiments of this disclosure can be performed by a computing-capable electronic device such as a computer, and this disclosure does not limit this. After obtaining an optimized target logic gate network, the optimized target logic gate network can be incorporated into a chip design including the circuit under test 11 for actual chip manufacturing.

[0059] In step 402, the electronic device constructs a candidate logic gate network set comprising multiple candidate logic gate networks by altering at least one input connection of at least one logic gate in at least one initial logic gate network. Each of the at least one initial logic gate network comprises multiple logic gates, which are respectively associated with multiple scan chains in the circuit under test. In one embodiment, the initial logic gate network may be, for example, similar to... Figure 1 The diagram illustrates a balanced logic gate network. For example, each logic gate in the initial logic gate network may have one or two input connections for receiving one or two bit inputs. In one embodiment, the logic gate may be, for example, an XOR. In another embodiment, the logic gate may be, for example, an XNOR. Other logic gates or combinations of logic gates may also be applied here as needed or as required by the design or the characteristics of the circuit under test, and this disclosure does not limit this application.

[0060] Each logic gate in the initial logic gate network may have one or more input connections designed to receive different encoded bits. Each initial logic gate network includes multiple logic gates, each associated with a multiple scan chain in the circuit under test 11. In one embodiment, the total number of scan chains in the circuit under test 11 may be determined, for example, based on a netlist file, and the number of logic gates in the initial logic gate network may be determined accordingly. For example, when the total number of scan chains is 12, the number of initial logic gates may be determined to be 12. In another embodiment, the number of logic gates in the initial logic gate network may also be determined in other ways, such as by user specification.

[0061] After determining the number of logic gates in the initial logic gate network, the input connections of each logic gate in the initial logic gate network can be initialized, that is, one or more coded bits of each logic gate. In one embodiment, the electronic device can randomly generate one or more input connections of each logic gate in the initial logic gate network. In another embodiment, the number of logic gates connected to each coded bit can be limited, and multiple coded bits can be sequentially assigned to multiple logic gates accordingly. For example, coded bit X1 can be assigned to the first logic gate and the second logic gate, and coded bit X2 can be assigned to the second logic gate and the third logic gate, and so on. This disclosure does not limit the allocation method of the input connections of each logic gate in the initial logic gate network.

[0062] Although the initial logic gate network is shown herein in the form of a balanced logic gate network, this disclosure is not limiting. In some embodiments, an unbalanced logic gate network may also be used to form the initial logic gate network. For example, a first set of initial logic gates in the initial logic gate network has one input connection to receive one encoded bit, and a second set of initial logic gates in the initial logic gate network has two input connections to receive two encoded bits.

[0063] In some embodiments, the electronic device also generates multiple initial logic gate networks to form an initial logic gate network set. For example, the electronic device may initialize multiple times based on the number of scan chains to generate multiple random initial logic gate networks. In other embodiments, the initial logic gate network set may also be generated in other ways, such as by user specification.

[0064] In one embodiment, the electronic device can evaluate an initial set of logic gate networks, including multiple initial logic gate networks. For example, the multiple initial logic gate networks can be evaluated separately using features of the circuit under test 11. For the low-power decoder 142 and the phase shifter 122, the multiple initial logic gate networks used to form the low-power decoder 142 and the phase shifter 122 can be evaluated separately using the scan chain distribution of the scan chain of the circuit under test 11 during the test cycle. For the mask decoder 152, the multiple initial logic gate networks used to form the mask decoder 152 can be evaluated separately using the unknown state distribution of the unknown states during the test cycle.

[0065] As described above, the circuit under test 11 receives test vectors comprising multiple test packet data during testing. Each decoded data in the test vector is shifted and input into the scan chain periodically. The data input is decoded by a phase shifter 122, and the opening or closing of each scan chain is controlled by a low-power decoder 142 based on a power consumption threshold; that is, the low-power decoder 142 controls which decoded inputs are shifted into the scan chain 11. For example, one scan chain of the circuit under test 11 receives the first decoded bit of the first test packet data or the default logic value when the scan chain is closed, such as logic "0", in the first cycle, and the second decoded bit of the first test packet or the default logic value in the second cycle, and so on. It can be understood that during one cycle, multiple scan chains actually receive multiple shifted decoded bits or default logic values. For simplicity, this document describes only one scan chain. After the first test packet data is received by this scan chain, the data included in the second test data is received sequentially, and so on, until all test vectors are input.

[0066] Not all scan chains of the circuit under test 11 are always used throughout the entire test cycle. For example, during the first cycle, only the first scan chain of the circuit under test 11 is used, while during the second cycle, only the second and third scan chains of the circuit under test 11 are used. Therefore, by using the distribution of scan chains, multiple initial logic gate networks can be verified. For example, if a scan chain is incorrectly opened or closed during the testing of a test packet, the test packet is considered to have failed. For the phase shifter 122, since the phase shifter 122 has extremely high requirements for encoding success rate, the number of failed test packets can be used for evaluation. For the low-power decoder 142, the low-power decoder 142 needs to have the highest possible encoding success rate under a given power threshold, so a weighted average of the number of failed test packets and the average power consumption of successful test packets can be used for comprehensive evaluation. For the mask decoder 152, it needs to minimize the impact of decoding on scan chains that do not require masking, provided that encoding is successful. Therefore, it can be evaluated by combining the number of failed test packets and the average number of scan chains that are additionally shut down due to masking. The specific weighting of the evaluation can vary depending on the specific design of the circuit under test 11.

[0067] The electronic device can then construct a candidate logic gate network set, comprising multiple candidate logic gate networks, based on the evaluation results by modifying at least one input connection of at least one logic gate in at least one initial logic gate network. In one embodiment, the electronic device can optimize the encoded bits received by at least one input of at least one logic gate in at least one initial logic gate network, for example, by modifying an input connection of a first logic gate from receiving a first encoded bit to receiving a second encoded bit to improve the encoding success rate. When that input connection of the first logic gate receives the first encoded bit, the first logic gate may generate an unwanted logic value during decoding. For example, when the first encoded bit is used to make the second logic gate output a correct logic value, the first encoded bit may generate an incorrect decoding output logic value with other inputs of the first logic gate. When that input of the first logic gate is modified to receive the second encoded bit, this error can be avoided, thereby improving the encoding success rate.

[0068] In another embodiment, the electronic device can improve encoding success rate by increasing the number of input connections of at least one logic gate in at least one initial logic gate network. For example, changing the first logic gate from two input connections to three input connections improves the encoding success rate. When one input connection of the first logic gate receives the first encoded bit, the first logic gate may generate an undesirable logic value similar to the one described above during decoding. By adding one input connection to the first logic gate, the encoded bit received by the additional third input connection can be used to correct the logic value output by the first logic gate in this case, thereby improving the encoding success rate.

[0069] In this disclosure, various methods can be used to optimize the modification of at least one input connection of at least one logic gate in at least one initial logic gate network to construct a candidate logic gate network set including multiple candidate logic gate networks by using evaluation results. Alternatively, a candidate logic gate network set including multiple candidate logic gate networks can also be directly constructed based on experience by modifying at least one input connection of at least one logic gate in at least one initial logic gate network without prior evaluation. In other embodiments, the initial logic gate network can be directly constructed as or used as a candidate logic gate network set. This disclosure does not limit this.

[0070] In 404, an electronic device determines a target logic gate network for testing the circuit under test based on the characteristics of the circuit under test and a set of candidate logic gate networks. The characteristics of the circuit under test include at least one of the scan chain distribution of the circuit under test during the test cycle or the unknown state distribution of the unknown state during the test cycle.

[0071] After obtaining the candidate logic gate network set, the electronic device can evaluate multiple candidate logic gate networks in the set using the characteristics of the circuit under test, as described above, and iteratively update the set based on the evaluation results. If a candidate logic gate network that meets the target exists in the iteratively updated candidate logic gate network set, that candidate logic gate network can be determined as the target logic gate network for testing the circuit under test 11. If no candidate logic gate network that meets the target still exists in the iteratively updated candidate logic gate network set, the candidate logic gate network set can continue to be iteratively updated until the target logic gate network is determined.

[0072] In one embodiment, an evolutionary algorithm can be used to determine the target logic gate network for testing the circuit under test based on the features of the circuit under test and a set of candidate logic gate networks, as described in detail below. Alternatively, other machine learning methods, such as reinforcement learning or neural network algorithms, can also be used to determine the target logic gate network for testing the circuit under test based on the features of the circuit under test and a set of candidate logic gate networks.

[0073] Figure 5 A flowchart illustrating a method 500 for determining a target logic gate network according to some embodiments of the present disclosure is shown. Method 500 may be... Figure 4 This is a specific implementation of the 404 error, and method 500 can be executed by an electronic device such as a computer. Therefore, the above addresses... Figures 2-4 The aspects described are optionally applicable to method 500. It is understood that the electronic device can execute method 500 at least once to determine the target logic gate network.

[0074] In step 502, the electronic device uses features of the circuit under test 11 to determine multiple network evaluation results for multiple candidate logic gate networks in a candidate logic gate network set. As described above, the features of the circuit under test include at least one of scan chain distribution or unknown state distribution. Fault sampling can be performed using netlist data representing the circuit under test 11, and test vectors comprising multiple test packages can be obtained through automatic test vector generation, where each test package targets a fault. By using the test vectors, the usage of multiple scan chains in the circuit under test 11 during the test cycle, i.e., the scan chain distribution, can be obtained. Furthermore, the distribution of unknown states during the test cycle, i.e., the unknown state distribution, can be obtained using netlist data.

[0075] Since the electronic device can obtain or determine the scan chain distribution and unknown state distribution, and the input and output connections of the logic gates of each of the multiple candidate logic gate networks, i.e., the encoded bits and decoded bits, are determined, the characteristics of the circuit under test 11 can be used to evaluate each logic gate network. As mentioned above, for the phase shifter 122, since the phase shifter 122 has extremely high requirements for encoding success rate, the number of failed test packets can be used for evaluation. For the low-power decoder 142, the low-power decoder 142 needs to have the highest possible encoding success rate under a given power threshold, so the weighted average of the number of failed test packets and the average power consumption of successful test packets can be used for comprehensive evaluation. For the mask decoder 152, the mask decoder 152 needs to minimize the impact on scan chains that do not require masking after decoding, under the premise of successful encoding, so the weighted average of the number of failed test packets and the average number of scan chains that are additionally shut down due to masking can be used for comprehensive evaluation. The specific weight allocation for evaluation can vary depending on the specific design of the circuit under test 11.

[0076] In step 504, the electronic device determines whether all evaluation results are below a first threshold. It is understood that different thresholds can be used for different application scenarios of the logic gate network. For example, when the logic gate network is applied to the phase shifter 122, the first threshold can be used, while when the logic gate network is applied to the low-power decoder 142, a second threshold different from the first threshold can be used. In the following text, the first threshold is used to represent different thresholds in different scenarios for simplification.

[0077] In step 506, if multiple network evaluation results are all below a first threshold, the electronic device updates the candidate logic gate network set by changing at least one input connection of at least one logic gate in multiple candidate logic gate networks using an evolutionary algorithm. Evolutionary algorithms are also called evolutionary computation, evolutionary strategies, or evolutionary models. The use of evolutionary algorithms to change at least one input connection of at least one logic gate in multiple candidate logic gate networks is explained below. Figure 6 Detailed description: When multiple network evaluation results are all below a first threshold, it indicates that multiple candidate logic gate networks in the candidate logic gate network set do not meet the circuit design requirements, and the candidate logic gate network set needs to be updated. Specifically, at least one input connection of at least one logic gate can be changed / added to improve the encoding success rate.

[0078] In step 508, the electronic device selects a target neural network model from an updated set of candidate logic gate networks based on multiple network evaluation results of multiple candidate logic gate networks in an updated set of candidate logic gate networks. In one embodiment, if at least one of the multiple evaluation results is not lower than a first threshold, the highest evaluation result can be selected from the at least one evaluation result, and the candidate logic gate network corresponding to the highest evaluation result can be determined as the target logic gate network. In other embodiments, the target logic gate can also be selected based on other factors. For example, if at least one of the multiple evaluation results is not lower than a first threshold, the logic gate network with the fewest encoded bits can be selected from the at least one logic gate network corresponding to the at least one evaluation result as the target logic gate network. This disclosure does not limit this.

[0079] Figure 6 A schematic diagram illustrating the use of an evolutionary algorithm to update a set of candidate logic gate networks according to some embodiments of this disclosure is shown. Figure 6 In the candidate logic gate network set 610-1, there are a first candidate logic gate network 601, a second candidate logic gate network 602, a third candidate logic gate network 603, a fourth candidate logic gate network 604, a fifth candidate logic gate network 605, and a sixth candidate logic gate network 606. The candidate logic gate network set 610-1 is, for example,... Figure 5 A concrete example of the candidate logic gate network set at position 502. Although in Figure 6 The candidate logic gate network set 610-1 is shown as including only 6 candidate logic gate networks, but this is only illustrative and not intended to limit the scope of this disclosure. The candidate logic gate network set may include other numbers of candidate logic gate networks.

[0080] The evaluation results of each candidate logic gate network in the candidate logic gate network set 610-1 are, for example, all below a first threshold. The electronic device then uses an evolutionary algorithm to connect at least one input of at least one gate of the plurality of candidate logic gate networks to update the candidate logic gate network set. In one embodiment, the electronic device can determine a first group of candidate logic gate networks and a second group of candidate logic gate networks from the candidate logic gate network set, wherein at least one network corresponding to the first group of candidate logic gate networks has an evaluation result lower than at least one network corresponding to the second group of candidate logic gate networks. For example, the first group of candidate logic gate networks includes, for example, a fourth candidate logic gate network 604, a fifth candidate logic gate network 605, and a sixth candidate logic gate network 606, while the second group of candidate logic gate networks includes a first candidate logic gate network 601, a second candidate logic gate network 602, and a third candidate logic gate network 603.

[0081] An electronic device generates a third set of candidate logic gate networks by altering at least one input connection of at least one gate in a second set of candidate logic gate networks using an evolutionary algorithm. For example, the third set of candidate logic gate networks includes a seventh candidate logic gate network 607 and an eighth candidate logic gate network 608. Figure 6 As shown, an electronic device can generate a third set of logic gate networks, for example, by hybridizing and / or mutating the second set of logic gate networks. In one embodiment, generating a third set of candidate logic gate networks using the second set of candidate logic gate networks in the candidate logic gate network set includes hybridizing or mutating at least a portion of the logic gate networks in the second set of candidate logic gate networks to generate the third set of candidate logic gate networks. For example, the electronic device can hybridize the first candidate logic gate network 601 and the second candidate logic gate network 602 to generate a seventh candidate logic gate network 607. Furthermore, the electronic device can mutate the third candidate logic gate network 603 to generate an eighth candidate logic gate network 608. It is understood that hybridizing or mutating the candidate logic gate networks in the second set of candidate logic gate networks can be independent of each other, or mutation can be performed after hybridization, or mutation can be performed before hybridization. This disclosure does not impose any limitations in this regard.

[0082] In one embodiment, the first candidate logic gate network 601 includes, for example, 12 logic gates, and the second candidate logic gate network 602 similarly has 12 logic gates. During hybridization, the 12 logic gates can be randomly divided into a first group and a second group, and the first group of logic gates from the first candidate logic gate network 601 and the second group of logic gates from the second candidate logic gate network 602 can be combined to form a seventh candidate logic gate network 607. Thus, the first group of logic gates and their input connections in the seventh candidate logic gate network 607 originate from the first candidate logic gate network 601, while the second group of logic gates and their input connections in the seventh candidate logic gate network 607 originate from the second candidate logic gate network 602. It is understood that the above grouping and combination methods are merely illustrative and not intended to limit the scope of this disclosure. Other hybridization methods can also be used. For example, the logic gates and their input connections in the seventh candidate logic gate network 607 can originate from the first candidate logic gate network 601, the second candidate logic gate network 602, and the third candidate logic gate network 603. Furthermore, the number of parent logic gates used for hybridization or their proportion in the logic gate network can be set as needed, and this disclosure does not impose any restrictions on this.

[0083] In one embodiment, the electronic device can mutate candidate logic gate networks in a candidate logic gate network set according to a mutation rate. The electronic device can use the mutation rate to change the input connections of at least a portion of the logic gates in at least a portion of the second set of candidate logic gate networks to generate a third set of candidate logic gate networks. For example, in the third candidate logic gate network 603... Figure 3 In the case of the logic gate network 300 shown, the electronic device can use a mutation rate to mutate the input connections of a portion of the logic gates in the logic gate network 300, such as the input connection of the logic gate corresponding to the decoded bit Y1. For example, the input connection of the logic gate corresponding to the decoded bit Y1 can be mutated to receive encoded bits X1, X2, and X4. To avoid an increase in the uncertainty of the encoding success rate due to an excessively large mutation rate, the mutation rate can be set according to actual needs, for example, below 5%.

[0084] While some examples of evolutionary algorithms have been described above with examples of mutation and hybridization, this disclosure is not limited thereto. In some embodiments, the input connections of at least a portion of the logic gates in a candidate logic gate network may be increased so that the logic gate can receive more encoded bits. In some cases, such as when each logic gate has a small number of encoded bits, there may not be a combination of encoded bits that can achieve the desired encoding success rate, so additional encoded bits are needed to improve the encoding success rate. In one embodiment, an electronic device may select at least one logic gate from a candidate logic gate network set based on a logic gate encoding performance evaluation result for the logic gates in the candidate logic gate network set; and increase the input connections of at least one logic gate to update the candidate logic gate network set.

[0085] Electronic devices can determine the logic gate encoding performance evaluation results in, for example, two ways. The first way is to identify the scan chain that is most frequently opened in the test packet data that failed to encode. The logic gate corresponding to this scan chain is the logic gate with the poor encoding performance evaluation result. This method can be used, for example, for the encoding performance evaluation of low-power decoder 142 and phase shifter 122. The second way is to identify the scan chain number that is additionally opened most frequently after decoding in the successfully encoded test packet data. This method can be used, for example, for the encoding performance evaluation of mask decoder 152.

[0086] Accordingly, electronic devices can add additional input connections to logic gates to receive additional coded bits in two ways. The first method is to add additional input connections based on the relevance of the scan chains. Scan chain relevance represents the probability that each scan chain is used simultaneously with other scan chains. For example, the first and second scan chains have the highest relevance, and the logic gate corresponding to the first scan chain has the worst encoding performance evaluation result in the logic gate network. The electronic device can select coded bits that the logic gate corresponding to the first scan chain does not have from the coded bits received by the logic gate corresponding to the second scan chain, and add an additional input connection to the logic gate corresponding to the first scan chain to receive that coded bit. The second method is to add an additional input connection to the logic gate and randomly couple that input connection to any coded bit that the logic gate did not receive before the additional input connection was added.

[0087] For example, see Figure 3 In logic gate network 300, the logic gate corresponding to the decoded bit Y1 receives three encoded bits, which may be due to the increased input connections of this logic gate. In contrast, the logic gate corresponding to the decoded bit Y2 receives only two encoded bits, which may be randomly assigned by the initial logic gate network. By adding additional encoded bits, the logic gate can have a larger encoding space, thereby improving the encoding success rate of the candidate logic gate network. As described above, through evolutionary methods such as mutation, crossover, adding encoded bits, and their combinations, the candidate logic gate network set can be used to obtain new candidate logic gate networks, i.e., the third set of candidate logic gate networks, based on candidate logic gate networks with higher encoding success rates.

[0088] The electronic device then removes the first group of candidate logic gate networks from the candidate logic gate network set 610-1 and adds a third group of candidate logic gate networks to the candidate logic gate network set to form an updated candidate logic gate network set 610-2. The updated candidate logic gate network set 610-2 includes the first candidate logic gate network 601, the second candidate logic gate network 602, and the third candidate logic gate network 603 inherited from the previous candidate logic gate network set 610-1, as well as a new third group of candidate logic gate networks generated using the second group of candidate logic gate networks. It also removes the poorly evaluated first group of candidate logic gate networks, namely, the fourth candidate logic gate network 604, the fifth candidate logic gate network 605, and the sixth candidate logic gate network 606.

[0089] Electronic devices then such as Figure 5 The updated candidate logic gate network set 610-2 is re-evaluated and compared with the first threshold, as shown. If the target logic gate network still cannot be determined, the electronic device can proceed as follows: Figure 6The evolutionary algorithm is then used again to update the candidate logic gate network set, and so on, until the target logic gate network is determined.

[0090] In embodiments of this disclosure, the target logic gate network obtained through methods such as evolutionary algorithms can be an unbalanced logic gate network, meaning that the number of input connections for each logic gate in the network can vary. Furthermore, the encoded bits of each logic gate are also different from each other, and the number of logic gates or decoding bits corresponding to each encoded bit can be different. Through evolutionary learning, maximum utilization of the encoding state space can be achieved, and a higher encoding success rate can be achieved using fewer encoded bits. On the other hand, according to embodiments of this disclosure, the number of encoded bits in the logic gate network can be dynamically expanded based on the encoding success rate requirements, thereby further improving the encoding success rate.

[0091] In some embodiments of this disclosure, by Figures 4-6 The target logic gate network obtained by the method shown can be applied to, for example, [the following]. Figure 2 The circuit includes at least one of phase shifter 122, low-power decoder 142, and mask decoder 152. In one embodiment, the circuitry in the chip used to test the circuit under test 11 may include a first logic gate network serving as phase shifter 122, a second logic gate network serving as low-power decoder 142, and a third logic gate network serving as mask decoder 152.

[0092] A first logic gate network is coupled to the circuit under test 11 and includes a first logic gate and a second logic gate. The first logic gate includes a first plurality of input connections and is configured to decode a first plurality of encoded bits received at the first plurality of input connections into a first decoded bit. The second logic gate includes a second plurality of input connections and is configured to decode a second plurality of encoded bits received at the second plurality of input connections into a second decoded bit, the number of the second plurality of input connections being different from the number of the first plurality of input connections. Although the first logic gate network is described herein with two logic gates, it is to be understood that this is merely illustrative and not a limitation of the present disclosure. The first logic gate network may include more logic gates.

[0093] The second logic gate network is coupled to the circuit under test 11 and includes a third logic gate and a fourth logic gate. The third logic gate includes a third plurality of input connections and is configured to decode a third plurality of encoded bits received at the third plurality of input connections into a third decoded bit. The fourth logic gate includes a fourth plurality of input connections and is configured to decode a fourth plurality of encoded bits received at the fourth plurality of input connections into a fourth decoded bit, the number of the fourth plurality of input connections being different from the number of the third plurality of input connections. Although the second logic gate network is described herein with two logic gates, it is to be understood that this is merely illustrative and not a limitation of this disclosure. The second logic gate network may include more logic gates.

[0094] A third logic gate network is coupled to the circuit under test 11 and includes a fifth logic gate and a sixth logic gate. The fifth logic gate includes a fifth plurality of input connections and is configured to decode a fifth plurality of encoded bits received at the fifth plurality of input connections into a fifth decoded bit. The sixth logic gate includes a sixth plurality of input connections and is configured to decode a sixth plurality of encoded bits received at the sixth plurality of input connections into a sixth decoded bit, the number of which differs from the number of sixth plurality of input connections. Although the third logic gate network is described herein as consisting of two logic gates, this is to be understood as illustrative only and not as a limitation of the present disclosure. The third logic gate network may include more logic gates.

[0095] The circuit for testing the circuit under test 11 also includes a first plurality of AND gates 7. The first plurality of AND gates 7 are coupled to a first logic gate network and a second logic gate network, and are configured to perform a logical AND operation on a first decoded bit output by the first logic gate and a third decoded bit output by the second logic gate to generate a first logic value for input to a first scan chain of the circuit under test, and to perform a logical AND operation on a second decoded bit output by the first logic gate and a fourth decoded bit output by the second logic gate to generate a second logic value for input to a second scan chain of the circuit under test.

[0096] The circuitry used to test the circuit under test 11 also includes a second plurality of AND gates 9. The second plurality of AND gates 9 are coupled to a plurality of scan chains and a third logic gate network in the circuit under test 11, and are configured to perform a logical AND operation on the fifth decoded bit output by the fifth logic gate and a bit output by the first scan chain of the plurality of scan chains to generate a first test logic value, and to perform a logical AND operation on the sixth decoded bit output by the sixth logic gate and a bit output by the second scan chain of the plurality of scan chains to generate a second test logic value.

[0097] By using a logic gate network optimized for the circuit under test 11 to obtain the phase shifter 122, low-power decoder 142, and mask decoder 152, in addition to improving decoding success rate, computational resource consumption and hardware cost can be reduced. This is because fewer encoded bits are used, and therefore less resource consumption and hardware cost are required for decoding.

[0098] Figure 7 A schematic block diagram of an electronic device 700 according to some embodiments of the present disclosure is shown. The electronic device 700 may include multiple modules for performing, for example... Figures 4-6 The corresponding steps in the methods discussed herein. For example... Figure 7 As shown, in one embodiment, the electronic device 700 includes a construction unit 702 and a determination unit 704. The construction unit 702 is used to construct a candidate logic gate network set comprising multiple candidate logic gate networks by changing at least one input connection of at least one logic gate in at least one initial logic gate network. Each initial logic gate network comprises multiple logic gates, which are respectively associated with multiple scan chains in the circuit under test. The determination unit 704 is used to determine a target logic gate network for testing the circuit under test based on the characteristics of the circuit under test and the candidate logic gate network set. The characteristics of the circuit under test include at least one of the scan chain distribution of the circuit under test during the test cycle or the distribution of unknown states during the test cycle.

[0099] In one embodiment, the determining unit 704 is further configured to update the candidate logic gate network set by iteratively performing the following operations at least once: determining multiple network evaluation results of multiple candidate logic gate networks in the candidate logic gate network set using features of the circuit under test; and updating the candidate logic gate network set by changing at least one input connection of at least one logic gate of the multiple candidate logic gate networks if the multiple network evaluation results are all below a first threshold using an evolutionary algorithm; and selecting a target logic gate network from the updated candidate logic gate network set based on the multiple network evaluation results of the multiple candidate logic gate networks in the updated candidate logic gate network set.

[0100] In one embodiment, the determining unit 704 is further configured to determine a first group of candidate logic gate networks and a second group of candidate logic gate networks from the candidate logic gate network set, wherein the evaluation result of at least one network corresponding to the first group of candidate logic gate networks is lower than the evaluation result of at least one network corresponding to the second group of candidate logic gate networks; generate a third group of candidate logic gate networks by changing at least one input connection of at least one logic gate of the second group of candidate logic gate networks using an evolutionary algorithm; remove the first group of candidate logic gate networks from the candidate logic gate network set; and add the third group of candidate logic gate networks to the candidate logic gate network set.

[0101] In one embodiment, the determining unit 704 is further configured to hybridize or mutate at least a portion of the logic gate networks in the second group of candidate logic gate networks to generate a third group of candidate logic gate networks.

[0102] In one embodiment, the determining unit 704 is further configured to select a first logic gate network and a second logic gate network from a second group of candidate logic gate networks; and to combine the first group of logic gates in the first group of logic gate networks and the second group of logic gates in the second group of logic gate networks into a third group of candidate logic gate networks, wherein the first group of logic gates corresponds to a first group of scan chains in a plurality of scan chains, and the second group of logic gates corresponds to a second group of scan chains in a plurality of scan chains, wherein the first group of scan chains is different from the second group of scan chains.

[0103] In one embodiment, the determining unit 704 is further configured to use a variation rate to change the input connections of at least a portion of the logic gates in at least a portion of the second set of candidate logic gate networks to generate a third set of candidate logic gate networks.

[0104] In one embodiment, the determining unit 704 is further configured to select at least one logic gate from the candidate logic gate network set based on the logic gate encoding performance evaluation results for the logic gates in the candidate logic gate network set; and to add input connections to at least one logic gate to update the candidate logic gate network set.

[0105] In one embodiment, the determining unit 704 is further configured to add input connections that are not present in the logic gates associated with the at least one logic gate to the at least one logic gate based on the usage correlation of the at least one logic gate with other logic gates in the same candidate logic gate network, so as to update the candidate logic gate network set, and use the correlation representation to represent the probability that two logic gates are used simultaneously in the test cycle.

[0106] In one embodiment, each of the at least one initial logic gate network includes multiple XOR gates having the same number of input connections, the inputs of the multiple XOR gates being configured to receive different combinations of encoded bits, and the outputs of the multiple XOR gates being configured to output different decoded bits.

[0107] In one embodiment, the target logic gate network is configured to be coupled to the circuit under test (DUT) in the chip or to the same circuit as the DUT.

[0108] Figure 8A schematic block diagram of an example device 800 that can be used to implement embodiments of the present disclosure is shown. Device 800 can be used to implement electronic device 700. As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to computer program instructions stored in random access memory (RAM) and / or read-only memory (ROM) 802 or computer program instructions loaded into RAM and / or ROM 802 from storage unit 807. Various programs and data required for the operation of device 800 may also be stored in RAM and / or ROM 802. The computing unit 801 and RAM and / or ROM 802 are interconnected via bus 803. Input / output (I / O) interface 804 is also connected to bus 803.

[0109] Multiple components in device 800 are connected to I / O interface 804, including: input unit 805, such as keyboard, mouse, etc.; output unit 806, such as various types of monitors, speakers, etc.; storage unit 807, such as disk, optical disk, etc.; and communication unit 808, such as network card, modem, wireless transceiver, etc. Communication unit 808 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0110] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as method 400 and / or method 500. For example, in some embodiments, method 400 and / or method 500 may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 807. In some embodiments, part or all of the computer program may be loaded and / or installed on device 800 via RAM and / or ROM and / or communication unit 808. When the computer program is loaded into RAM and / or ROM and executed by the computing unit 801, one or more steps of method 400 and / or method 500 described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform method 400 and / or method 500 by any other suitable means (e.g., by means of firmware).

[0111] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0112] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0113] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0114] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for designing logic gate networks, comprising: By changing at least one input connection of at least one logic gate in at least one initial logic gate network, a candidate logic gate network set is constructed, which includes multiple candidate logic gate networks. Each of the at least one initial logic gate network includes multiple logic gates, which are respectively associated with multiple scan chains in the circuit under test. as well as Based on the characteristics of the circuit under test and the candidate logic gate network set, a target logic gate network for testing the circuit under test is determined. The characteristics of the circuit under test include at least one of the scan chain distribution of the circuit under test in the test cycle or the distribution of unknown states in the test cycle.

2. The method according to claim 1, wherein determining the target logic gate network comprises: The candidate logic gate network set is updated by iteratively performing the following operations at least once: The characteristics of the circuit under test are used to determine multiple network evaluation results of the multiple candidate logic gate networks in the candidate logic gate network set; as well as If the evaluation results of the multiple networks are all below the first threshold, the candidate logic gate network set is updated by changing at least one input connection of at least one logic gate of the multiple candidate logic gate networks using an evolutionary algorithm. as well as The target logic gate network is selected from the updated candidate logic gate network set based on the network evaluation results of multiple candidate logic gate networks in the updated candidate logic gate network set.

3. The method of claim 2, wherein updating the candidate logic gate network set comprises: A first group of candidate logic gate networks and a second group of candidate logic gate networks are determined from the candidate logic gate network set. The evaluation result of at least one network corresponding to the first group of candidate logic gate networks is lower than the evaluation result of at least one network corresponding to the second group of candidate logic gate networks. A third set of candidate logic gate networks is generated by changing at least one input connection of at least one logic gate in the second set of candidate logic gate networks using an evolutionary algorithm. Remove the first group of candidate logic gate networks from the candidate logic gate network set; as well as Add the third set of candidate logic gate networks to the candidate logic gate network set.

4. The method according to claim 3, wherein generating the third set of candidate logic gate networks using the second set of candidate logic gate networks in the candidate logic gate network set comprises: At least a portion of the logic gate networks in the second group of candidate logic gate networks are hybridized or mutated to generate the third group of candidate logic gate networks.

5. The method of claim 4, wherein hybridizing at least a portion of the logic gate networks in the second group of candidate logic gate networks to generate the third group of candidate logic gate networks comprises: Select the first logic gate network and the second logic gate network from the second group of candidate logic gate networks; as well as The first group of logic gates in the first group of logic gate networks and the second group of logic gate networks in the second group of logic gate networks are combined to form the third group of candidate logic gate networks. The first group of logic gates corresponds to the first group of scan chains in the plurality of scan chains, and the second group of logic gates corresponds to the second group of scan chains in the plurality of scan chains. The first group of scan chains is different from the second group of scan chains.

6. The method of claim 4, wherein mutating at least a portion of the logic gate networks in the second group of candidate logic gate networks to generate the third group of candidate logic gate networks comprises: The input connections of at least a portion of the logic gates in at least a portion of the second set of candidate logic gate networks are modified using a mutation rate to generate the third set of candidate logic gate networks.

7. The method according to any one of claims 2-6, wherein updating the candidate logic gate network set comprises: Based on the logic gate encoding performance evaluation results for the logic gates in the candidate logic gate network set, at least one logic gate is selected from the candidate logic gate network set; as well as Add input connections to the at least one logic gate to update the candidate logic gate network set.

8. The method of claim 7, wherein adding the input connections of the at least one logic gate to update the candidate logic gate network set comprises: Based on the usage correlation of the at least one logic gate with other logic gates in the same candidate logic gate network, input connections that the at least one logic gate does not have are added to the at least one logic gate from the logic gates associated with the at least one logic gate to update the candidate logic gate network set. The usage correlation represents the probability that two logic gates are used simultaneously in the test period.

9. The method according to any one of claims 1-6, wherein the circuit under test further comprises the total number of scan chains in the circuit under test, and wherein the method further comprises: The total number of scan chains is used to determine the at least one initial logic gate network.

10. The method according to any one of claims 1-6, wherein each of the at least one initial logic gate network comprises a plurality of XOR gates having the same number of input connections, the inputs of the plurality of XOR gates being configured to receive different combinations of encoded bits, and the outputs of the plurality of XOR gates being configured to output different decoded bits.

11. The method according to any one of claims 1-6, wherein the target logic gate network is configured to be coupled to the circuit under test in the chip or coupled to the same circuit as the circuit under test.

12. A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method of any one of claims 1-11.

13. A computer program product comprising a plurality of programs configured to be executed by one or more processors, the plurality of programs comprising instructions for performing the method of any one of claims 1-11.

14. An electronic device comprising: One or more processors; The electronic device includes a memory containing computer instructions that, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 1-11.

15. An electronic device comprising: A construction unit is configured to construct a candidate logic gate network set comprising multiple candidate logic gate networks by changing at least one input connection of at least one logic gate in at least one initial logic gate network, wherein each initial logic gate network comprises multiple logic gates, and the multiple logic gates are respectively associated with multiple scan chains in the circuit under test. as well as The determining unit is configured to determine a target logic gate network for testing the circuit under test based on the characteristics of the circuit under test and the candidate logic gate network set. The characteristics of the circuit under test include at least one of the scan chain distribution of the circuit under test in the test cycle or the distribution of unknown states in the test cycle.

16. The electronic device of claim 15, wherein the determining unit is further configured to update the candidate logic gate network set by iteratively performing the following operations at least once: The characteristics of the circuit under test are used to determine multiple network evaluation results of the multiple candidate logic gate networks in the candidate logic gate network set; as well as If the evaluation results of the multiple networks are all below the first threshold, the candidate logic gate network set is updated by changing at least one input connection of at least one logic gate of the multiple candidate logic gate networks using an evolutionary algorithm. as well as The target logic gate network is selected from the updated candidate logic gate network set based on the network evaluation results of multiple candidate logic gate networks in the updated candidate logic gate network set.

17. The electronic device of claim 16, wherein the determining unit is further configured to: A first group of candidate logic gate networks and a second group of candidate logic gate networks are determined from the candidate logic gate network set. The evaluation result of at least one network corresponding to the first group of candidate logic gate networks is lower than the evaluation result of at least one network corresponding to the second group of candidate logic gate networks. A third set of candidate logic gate networks is generated by changing at least one input connection of at least one logic gate in the second set of candidate logic gate networks using an evolutionary algorithm. Remove the first group of candidate logic gate networks from the candidate logic gate network set; as well as Add the third set of candidate logic gate networks to the candidate logic gate network set.

18. The electronic device of claim 17, wherein the determining unit is further configured to: At least a portion of the logic gate networks in the second group of candidate logic gate networks are hybridized or mutated to generate the third group of candidate logic gate networks.

19. The electronic device of claim 18, wherein the determining unit is further configured to: Select a first logic gate network and a second logic gate network from the second group of candidate logic gate networks; and The first group of logic gates in the first group of logic gate networks and the second group of logic gate networks in the second group of logic gate networks are combined to form the third group of candidate logic gate networks. The first group of logic gates corresponds to the first group of scan chains in the plurality of scan chains, and the second group of logic gates corresponds to the second group of scan chains in the plurality of scan chains. The first group of scan chains is different from the second group of scan chains.

20. The electronic device of claim 18, wherein the determining unit is further configured to: The input connections of at least a portion of the logic gates in at least a portion of the second set of candidate logic gate networks are modified using a mutation rate to generate the third set of candidate logic gate networks.

21. The electronic device according to any one of claims 16-20, wherein the determining unit is further configured to: Based on the logic gate encoding performance evaluation results for the logic gates in the candidate logic gate network set, at least one logic gate is selected from the candidate logic gate network set; and Add input connections to the at least one logic gate to update the candidate logic gate network set.

22. The electronic device of claim 21, wherein the determining unit is further configured to: Based on the usage correlation of the at least one logic gate with other logic gates in the same candidate logic gate network, input connections that the at least one logic gate does not have are added to the at least one logic gate from the logic gates associated with the at least one logic gate to update the candidate logic gate network set. The usage correlation represents the probability that two logic gates are used simultaneously in the test period.

23. The electronic device according to any one of claims 15-20, wherein each of the at least one initial logic gate network comprises a plurality of XOR gates having the same number of input connections, the inputs of the plurality of XOR gates being configured to receive different combinations of encoded bits, and the outputs of the plurality of XOR gates being configured to output different decoded bits.

24. The electronic device according to any one of claims 15-20, wherein the target logic gate network is configured to be coupled in a chip to the circuit under test or to the same circuit as the circuit under test.

25. A circuit for testing a circuit under test, comprising: A first logic gate network, coupled to the circuit under test, wherein the first logic gate network is the target logic gate network determined by the method according to any one of claims 1 to 11, and comprises: A first logic gate includes a plurality of first input connections and is configured to decode a plurality of first encoded bits received at the plurality of first input connections into first decoded bits; and A second logic gate includes a plurality of second input connections and is configured to decode a plurality of second encoded bits received at the plurality of second input connections into second decoded bits, wherein the number of the plurality of second input connections is different from the number of the plurality of first input connections.

26. The circuit of claim 25, further comprising: A second logic gate network, coupled to the circuit under test, and including... A third logic gate includes multiple third input connections and is configured to decode multiple third encoded bits received at the multiple third input connections into third decoded bits; as well as A fourth logic gate includes a plurality of fourth input connections and is configured to decode a plurality of fourth encoded bits received at the plurality of fourth input connections into fourth decoded bits, wherein the number of the plurality of fourth input connections is different from the number of the plurality of third input connections; A third logic gate network is coupled to the circuit under test and includes... A fifth logic gate includes a plurality of fifth input connections and is configured to decode a plurality of fifth encoded bits received at the plurality of fifth input connections into fifth decoded bits; as well as A sixth logic gate includes a plurality of sixth input connections and is configured to decode a plurality of sixth encoded bits received at the plurality of sixth input connections into a sixth decoded bit, wherein the number of the plurality of sixth input connections is different from the number of the plurality of sixth input connections.

27. The circuit of claim 26, further comprising a plurality of first AND gates coupled to the first logic gate network and the second logic gate network, and configured to: The first decoded bit output from the first logic gate and the third decoded bit output from the second logic gate are logically ANDed to generate a first logic value for input to the first scan chain of the circuit under test. The second decoded bit output by the first logic gate and the fourth decoded bit output by the second logic gate are logically ANDed to generate a second logic value for input to the second scan chain of the circuit under test.

28. The circuit of claim 26, further comprising a plurality of second AND gates coupled to a plurality of scan chains in the circuit under test and the third logic gate network, and configured to: The fifth decoded bit output from the fifth logic gate is logically ANDed with the bit output from the first scan chain in the plurality of scan chains to generate a first test logic value. The sixth decoded bit output from the sixth logic gate is logically ANDed with the bit output from the second scan chain in the plurality of scan chains to generate a second test logic value.

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