Electroencephalogram signal acquisition and processing device and method

Abstract

The present invention provides an electroencephalogram (EEG) signal acquisition and processing device and method. The device includes: an analog front-end processing circuit, including an analog front-end chip, which is used to use a clock signal with a first clock frequency of an external clock as a clock input to acquire EEG signals, obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to a control unit; a frequency division circuit, which is connected to the external clock with the first clock frequency and is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of a target clock frequency, where N is an even multiple of 2 and N = f1 / f g , f1 represents the first clock frequency, and f g represents the target clock frequency; and the control unit, which is used to use the clock signal with the target clock frequency obtained after frequency division by the frequency division circuit as a clock input to perform data processing on the EEG digital signals from the analog front-end chip.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and more particularly to an electroencephalogram (EEG) signal acquisition and processing device and method. Background Art

[0002] The most important neuroelectrophysiological signals include EEG (Electroencephalography) signals, EMG (Electromyography) signals collected on the scalp surface, local field potentials collected in the brain, and spike signals directly corresponding to neural activities. These signals have different characteristics, such as different amplitudes and frequency bands, and the electrodes for collecting them also have many different properties, such as different impedances, and different electrode polarization voltages will form different biases, etc.

[0003] Currently, the development of high-precision analog-to-digital converters (ADCs) enables the acquisition of these neurophysiological signals to be generally implemented by analog front-end chips. The recommended clock of the external clock of many high-precision analog front-ends (or called analog integrated front-ends) is 2.048 MHz, and the corresponding sampling rate is 250 Hz at this time.

[0004] In the process of implementing the present invention, the inventors found that in some applications, it is necessary to synchronously collect (such as multi-channel synchronous collection) and process multiple physiological signals. For example, not only electroencephalogram (EEG) signals need to be collected, but also physiological signals such as electrodermal activity (EDA) signals, photoplethysmography (PPG) signals, eye movement, heart rate, and / or functional near-infrared spectroscopy (fNIRS) signals need to be collected. The sampling rates commonly used for collecting these physiological signals are 8 Hz, 16 Hz, 64 Hz, 128 Hz, or 256 Hz, etc. Therefore, a data processing unit (main control chip) with a sampling rate of 256 Hz or an integer multiple of 256 Hz is required for processing these signals. However, a main control chip with a sampling rate of 256 Hz or an integer multiple of 256 Hz cannot be used in cooperation with an analog front-end chip with a sampling rate of 250 Hz. This is because the sampling rate required by the main control chip MCU is 256 Hz or an integer multiple of 256 Hz. When using an analog front-end chip with a sampling rate of 250 Hz to cooperate with the selected main control chip for collection, only the sampling rate of EEG signals that is 250 Hz and an integer multiple of 250 Hz can be achieved, making it difficult for the main control chip to perform data processing. If forced to collect at a sampling rate of 256 Hz, there will be a phenomenon of mismatch between the clock of the analog front-end chip and the main control unit, resulting in abnormal collection of physiological signal data. Therefore, the EEG signals cannot be processed synchronously with other physiological signals by the same main control chip clock.

[0005] Therefore, how to solve the problem of asynchronous clocks in data collection and data processing and collaborative processing is an urgent problem to be solved. Summary of the Invention

[0006] In view of this, the present invention provides an EEG signal acquisition and processing device and a frequency division circuit to achieve cooperative acquisition and time synchronization between an analog front-end chip and a main control chip with a sampling rate of 256 Hz.

[0007] One aspect of the present invention provides an EEG signal acquisition and processing device, which includes:

[0008] An analog front-end processing circuit, including an analog front-end chip, which uses a clock signal with a first clock frequency of an external clock as a clock input, acquires EEG signals at a first sampling rate matching the first clock frequency, obtains EEG analog signals, converts the EEG analog signals into EEG digital signals, and transmits the EEG digital signals to a control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate;

[0009] A frequency division circuit, which is connected to an external clock of the first clock frequency and is used to divide the clock crystal oscillator of the external clock by N times to obtain a clock signal with a clock frequency of the target clock frequency, where N is an even multiple of 2 and N = f1 / f g , where f1 represents the first clock frequency and f g represents the target clock frequency; and

[0010] The control unit is used to use the clock signal with the target clock frequency obtained after frequency division by the frequency division circuit as a clock input to process the electroencephalogram digital signal from the analog front-end chip.

[0011] In some embodiments of the present invention, the device further includes: a power supply circuit for supplying power to the analog front-end chip and the main control chip. The power supply circuit includes a main power supply module and a sub-power supply module. The main power supply module includes an analog circuit power supply circuit and a digital circuit power supply circuit; the analog circuit power supply circuit includes a low-dropout regulator for supplying a first voltage to the analog circuit of the electroencephalogram signal acquisition device; the digital circuit power supply circuit includes a buck circuit for supplying a first voltage to the digital circuit of the electroencephalogram signal acquisition device; the sub-power supply module divides a second voltage from the voltage provided by the analog circuit power supply circuit to supply power to the analog front-end chip.

[0012] In some embodiments of the present invention, the range of the first clock frequency is 1.5M to 2.25MHz, and the first sampling rate is F, satisfying: F = f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048 or 4096.

[0013] In some embodiments of the present invention, the first clock frequency is 2.097MHz, N is 64, the first sampling rate is 256Hz or a multiple of 256Hz, and the target clock frequency is 32.768KHz.

[0014] In some embodiments of the present invention, the frequency division circuit includes: a first frequency division sub-circuit connected to an external clock of the first clock frequency and used to divide the clock crystal oscillator of the external clock by M times, where M is an even multiple of 2; and a second frequency division sub-circuit used to further divide the signal after being divided by M times by the first frequency division sub-circuit by L times to obtain a clock signal with the target clock frequency, where L is an even multiple of 2 and L = N / M.

[0015] In some embodiments of the present invention, the frequency division circuit includes: a first frequency division sub-circuit, connected to an external clock of the first clock frequency, for performing a 4-fold frequency division on the clock crystal of the external clock; a second frequency division sub-circuit, for further performing a 4-fold frequency division on the signal after the 4-fold frequency division by the first frequency division sub-circuit; and a third frequency division sub-circuit, for further performing a 4-fold frequency division on the signal after the 4-fold frequency division by the second frequency division sub-circuit to obtain a clock signal of 32.768 KHz.

[0016] In some embodiments of the present invention, the analog front-end processing circuit further includes: an electrostatic protection circuit, which is disposed at the electroencephalogram signal input end for electrostatic protection.

[0017] In some embodiments of the present invention, the analog front-end processing circuit further includes: a low-pass filter circuit, which is disposed at the electroencephalogram signal input end for filtering out high-frequency electromagnetic waves and high-frequency crosstalk.

[0018] In some embodiments of the present invention, the analog front-end chip includes a multi-channel electroencephalogram signal MUX switching module for polling and collecting electroencephalogram signals.

[0019] In some embodiments of the present invention, the range of the first voltage is 1.8 - 3.6 V, preferably 3.0 V; the second voltage is represented as AVDD: AVDD = AVDD + -AVDD - where AVDD + and AVDD - respectively represent the high voltage and the low voltage of the analog front-end chip, and the range of AVDD is 4.75 - 5.25 V.

[0020] On the other hand, the present invention also provides a method for collecting and processing electroencephalogram signals, the method comprising the following steps:

[0021] The analog front-end chip uses a clock signal of the first clock frequency of the external clock as the clock input, collects electroencephalogram signals at a first sampling rate matching the first clock frequency to obtain electroencephalogram analog signals, converts the electroencephalogram analog signals into electroencephalogram digital signals, and transmits the electroencephalogram digital signals to the control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate;

[0022] Connect an external clock of the first clock frequency through a frequency division circuit for performing an N-fold frequency division on the clock crystal of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, where N is an even multiple of 2, and N = f1 / f g where f1 represents the first clock frequency and f g represents the target clock frequency; and

[0023] Using the clock signal with the target clock frequency obtained by frequency division of the control unit through the frequency division circuit as the clock input, data processing is performed on the EEG digital signal from the analog front-end chip.

[0024] In some embodiments of the present invention, connecting the external clock with the first clock frequency through the frequency division circuit, which is used to perform N-fold frequency division on the clock oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, includes: connecting the external clock with the first clock frequency, performing M-fold frequency division on the clock oscillator of the external clock, where M is an even multiple of 2; and further performing L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit to obtain the clock signal with the target clock frequency, where L is an even multiple of 2 and L = N / M.

[0025] In some embodiments of the present invention, connecting the external clock with the first clock frequency through the frequency division circuit, which is used to perform N-fold frequency division on the clock oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, includes: connecting the external clock with the first clock frequency, which is used to perform the first 4-fold frequency division on the clock oscillator of the external clock; further performing the second 4-fold frequency division on the signal after the first 4-fold frequency division; and further performing the third 4-fold frequency division on the signal after the second 4-fold frequency division to obtain the clock signal with the target clock frequency.

[0026] The EEG signal acquisition and processing device and method of the present invention can realize the cooperative acquisition of the analog front-end chip and the main control chip, so that the same main control chip with a selected sampling rate (such as 256Hz) can realize the synchronous processing of various physiological signals including EEG signals, greatly expanding the application scenarios of physiological signals.

[0027] The additional advantages, objects, and features of the present invention will be partially described below, and will become partially apparent to those of ordinary skill in the art after studying the following text, or can be learned from the practice of the present invention. The objects and other advantages of the present invention can be achieved and obtained through the structures specifically pointed out in the specification and the drawings.

[0028] Those skilled in the art will understand that the objects and advantages that can be achieved by the present invention are not limited to the above specifically described, and the above and other objects that the present invention can achieve will be more clearly understood according to the following detailed description. Brief Description of the Drawings

[0029] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and do not constitute a limitation to the present invention.

[0030] Figure 1Schematic diagram of an electroencephalogram (EEG) signal acquisition and processing device in an embodiment of the present invention.

[0031] Figure 2 Schematic diagram of an electroencephalogram (EEG) signal acquisition and processing device in another embodiment of the present invention.

[0032] Figure 3 Schematic diagram of an external clock circuit.

[0033] Figure 4 Schematic diagram of a frequency division circuit in an embodiment of the present invention.

[0034] Figure 5 Schematic flowchart of an electroencephalogram (EEG) signal acquisition and processing method in an embodiment of the present invention.

[0035] Figure 6 Schematic diagram of the structure of an analog front-end processing circuit in an embodiment of the present invention. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the implementation manners and the accompanying drawings. Herein, the illustrative implementation manners of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0037] Herein, it should also be noted that in order to avoid obscuring the present invention due to unnecessary details, only the structures and / or processing steps closely related to the solution according to the present invention are shown in the drawings, while other details less related to the present invention are omitted.

[0038] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0039] As described above, when an analog front-end chip with a sampling rate of 250 Hz is used in cooperation with a main control chip (MCU) with a sampling rate of 256 Hz for acquisition, only the sampling rate of EEG signals that is 250 Hz and integer multiples of 250 Hz can be achieved, making it difficult for the main control chip to perform data processing. If the analog front-end chip is forced to use a sampling rate of 256 Hz for acquisition, there will be a phenomenon of mismatch between the clock of the analog front-end chip and the main control unit, resulting in abnormal acquisition of physiological signal data. Therefore, EEG signals cannot be processed synchronously with other physiological signals by the same main control chip clock.

[0040] In addition, for an analog front-end chip with a default or fixed sampling rate that is neither 250 Hz or its multiple, nor 256 Hz or its multiple, there are also the same problems when converting to a sampling rate of 256 Hz for sampling.

[0041] To address this technical problem, the present invention proposes an improved electroencephalogram (EEG) signal acquisition and processing device. By changing the external input clock, the device can convert the fixed 250 Hz sampling rate (or other sampling rates different from 256 Hz and its multiples) of the analog integrated front-end into a customized 256 Hz sampling rate. This enables the coordinated acquisition between the analog front-end chip and the main control chip, allowing the main control chip with a 256 Hz sampling rate to synchronously process various physiological signals, including EEG signals. As a result, multiple physiological signals can be used for the collaborative discrimination of the subject's physiological state, greatly expanding the application scenarios of physiological signals.

[0042] The analog front-end chip allows for the input of an external clock. Taking an analog front-end chip with a 250 Hz sampling rate as an example, the allowable input range of the external clock is 1.5 MHz to 2.25 MHz, and the recommended external clock input is 2.048 MHz (the 250 Hz sampling rate is obtained based on (2.048 MHz / 2 / 4096)). Within this allowable range, instead of using the recommended external clock input of 2.048 MHz, the present invention selects to use a 2.097 MHz clock. The 2.097 MHz clock is an integer multiple of 32.768 KHz, which is exactly the clock of the main control chip. Therefore, by modifying the external input clock of the analog front-end chip to 2.097 MHz, the analog integrated front-end with a fixed sampling rate of 250 Hz can be transformed into a sampling rate of 256 Hz. However, when achieving the sampling of the analog integrated front-end at a 256 Hz sampling rate by changing the external input clock to 2.097 MHz, a defect occurs, that is, there will be a problem of clock asynchronization between the analog front-end and the main control chip due to frequency deviation, namely, there will also be a clock deviation between the analog front-end and the main control chip due to clock asynchronization. To address this, the present invention further designs a frequency division circuit in addition to using 2.097 MHz as the clock input of the analog front-end. The 2.097 MHz is divided by 64 to obtain 32.768 KHz as the clock input of the main control chip, replacing the original 32.768 KHz clock of the main control chip, thereby achieving the unification of the clock source and further realizing clock synchronization. In this way, while enabling the analog front-end to collect EEG signals at a 256 Hz sampling rate, the purpose of clock synchronization between the analog front-end and the main control chip can be achieved.

[0043] For other analog front-end chips with a default or fixed sampling rate that is neither 250 Hz or a multiple thereof, nor 256 Hz or a multiple thereof, the present invention also needs to be converted to sample at a custom sampling rate (such as 256 Hz), and also select to change the clock frequency of the external clock of the analog front-end chip from the fixed or default clock frequency to a clock frequency that matches the target sampling rate, so that the electroencephalogram (EEG) signal can be collected at a first sampling rate that matches the external input clock frequency, and an EEG analog signal can be obtained. Correspondingly, in order to achieve clock synchronization between the analog integrated front-end and the main control chip, a frequency division circuit is used to divide the external input clock frequency to obtain a target clock frequency that is consistent with the main control chip and input it to the main control chip.

[0044] Figure 1 The following shows a schematic structural diagram of an EEG signal acquisition and processing device in an embodiment of the present invention, as Figure 1 shown, the EEG signal acquisition and processing device includes: an analog front-end processing circuit, a frequency division circuit, and a main control chip (MCU).

[0045] The analog front-end processing circuit includes an analog front-end chip, which is used to use the clock signal with the first clock frequency of the external clock as the clock input, collect EEG signals at a first sampling rate that matches the first clock frequency, obtain an EEG analog signal, convert the EEG analog signal into an EEG digital signal, and transmit the EEG digital signal to the control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate.

[0046] In the embodiment of the present invention, the range of the first clock frequency f1 is 1.5 M to 2.25 MHz, and the first sampling rate F that matches the first clock frequency is: F = f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048, and 4096. As an example, the first clock frequency is 2.097 MHz, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the second sampling rate is 250 Hz or a multiple of 250 Hz. At this time, the analog front-end chip is used to use the clock signal of 2.097 MHz of the external clock as the clock input, collect EEG signals, obtain an EEG analog signal, convert the EEG analog signal into an EEG digital signal, and transmit the EEG digital signal to the control unit (i.e., the main control chip MCU).

[0047] The frequency division circuit is connected to the external clock with the first clock frequency, and is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, where N is an even multiple of 2, and N = f1 / f g , f1 represents the first clock frequency, f g represents the target clock frequency.

[0048] When the first clock frequency is 2.097 MHz and the first sampling rate is 256 Hz or a multiple of 256 Hz, the target clock frequency is 32.768 KHz and N is 64. At this time, the frequency division circuit is connected to a 2.097 MHz external clock, which is used to divide the 2.097 MHz clock oscillator by 64 times to obtain a 32.768 KHz clock signal.

[0049] The main control chip MCU is used to take the clock signal with the target clock frequency obtained after frequency division by the frequency division circuit as the clock input, and perform data processing on the EEG digital signal from the analog front-end chip.

[0050] In some other embodiments of the present invention, the EEG signal acquisition and processing device further includes a power supply circuit for supplying power to the analog front-end chip and the main control chip.

[0051] The power supply circuit can provide power supply for the digital circuit with the first voltage, and power supply for the analog circuit with the first voltage and the second voltage, which are used to respectively provide the required voltages for the digital circuit and the analog circuit in the devices including the analog front-end chip and the main control chip in the EEG signal acquisition and processing device. Among them, the range of the first voltage is 1.8 - 3.6 V, preferably 3.0 V; the second voltage can be expressed as AVDD: AVDD = AVDD+ - AVDD-, where AVDD + and AVDD - respectively represent the high voltage and the low voltage of the analog front-end chip. The range of AVDD is 4.75 - 5.25 V, preferably 5 V. As an example, the power supply circuit can include a main power supply module and a sub-power supply module. The main power supply module includes a power management chip, and the power management chip includes an analog circuit power supply circuit and a digital circuit power supply circuit. Among them, the analog circuit power supply circuit includes a low dropout regulator (LDO) for providing a 3.0 V power supply voltage for the analog circuit of the EEG signal acquisition device; the digital circuit power supply circuit includes a buck circuit for providing a 3.0 V power supply voltage for the digital circuit of the EEG signal acquisition device.

[0052] The sub-power supply module can divide out ±2.5 V from the voltage provided by the analog circuit power supply circuit to provide a ±2.5 V power supply voltage for the analog front-end chip, that is, AVDD + is +2.5 V and AVDD- is -2.5 V. For example, the provided 3.0 V analog circuit power supply voltage is first boosted to output 5 V, and 5 V is output through a buck chip to obtain a 2.5 V power supply voltage; -2.5 V power supply voltage is obtained by converting 5 V to -5 V and then converting -5 V to -2.5 V.

[0053] Since the power supply circuit can be implemented by an existing circuit that can supply power to digital circuits at 3.0V, analog circuits at 3.0V and ±2.5V, it will not be elaborated here.

[0054] In some embodiments of the present invention, as Figure 6 shown, in addition to the analog front-end chip, the analog front-end processing circuit may further include an ESD (Electrostatic Protection) circuit, which is arranged at the electroencephalogram signal input end for electrostatic protection of each acquisition channel. When the device receives a lightning surge and ESD electrostatic discharge or other instantaneous voltages, it can provide a protection effect to the circuit to protect the device from transient lightning surges and ESD static electricity damage.

[0055] In some embodiments of the present invention, as Figure 6 shown, the analog front-end processing circuit may further include a low-pass filter circuit, which is arranged at the electroencephalogram signal input end for:

[0056] (1) Filtering high-frequency electromagnetic waves for each acquisition channel. When there is a conduction current on the wire, the higher the frequency of the current, the easier it is to form radiation, thus generating relatively strong radiation interference. Therefore, filtering these high-frequency noises will effectively reduce cable radiation.

[0057] (2) Filtering high-frequency crosstalk for each acquisition channel. Between wires or cables, due to the existence of distributed capacitance and mutual inductance, mutual crosstalk will be generated, and these interferences are mainly high-frequency. Therefore, low-pass filtering can remove these interferences.

[0058] In some embodiments of the present invention, the analog front-end chip internally includes:

[0059] A multi-channel electroencephalogram signal MUX switching module (such as 8 channels or 16 channels, etc., the present invention is not limited thereto), a programmable gain module, an analog-to-digital signal conversion module, and a right leg drive module (right leg drive circuit), etc.

[0060] The EEG signals measured by the analog front-end chip can be 8-channel EEG signals or 16-channel EEG signals. After the 8-channel EEG signals or 16-channel EEG signals enter the analog front-end chip, data acquisition is not performed simultaneously, but data is cyclically acquired through the MUX switching module. The programmable gain module can amplify the EEG signals by 1 times, 2 times, 4 times, 6 times, 8 times, 12 times, 24 times, etc. The amplified analog signal is converted into a digital signal through the analog-to-digital signal conversion module, and then communicates with the main control chip MCU through the SPI protocol to transmit the digital signal to the MCU. In addition, the right leg drive module is used to reduce common-mode interference. After the EEG signal is amplified, the common-mode component is extracted by the programmable gain module and then sent to the right leg drive module and then flows back to the human body to reduce interference. Since the multi-channel EEG signal MUX switching module, programmable gain module, analog-to-digital signal conversion module, and right leg drive module are modules inside the existing analog front-end chip, they will not be elaborated here.

[0061] In some embodiments of the present invention, the frequency division circuit may include 2, 3 or more frequency division sub-circuits. For example, the frequency division circuit may include:

[0062] A first frequency division sub-circuit, connected to an external clock of a first clock frequency, for performing M-fold frequency division on the clock crystal of the external clock, where M is an even multiple of 2; and

[0063] A second frequency division sub-circuit, which is used to further perform L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit to obtain a clock signal with a target clock frequency, where L is an even multiple of 2 and L = N / M.

[0064] In the case of N = 64, in the case where the 64-fold frequency division circuit includes 2 frequency division sub-circuits, the 64-fold frequency division circuit may include:

[0065] A first frequency division sub-circuit, connected to the 2.097 MHz external clock, for performing M-fold frequency division on the 2.097 MHz clock crystal, where M is an even multiple of 2, preferably M is 4, 8 or 16.

[0066] A second frequency division sub-circuit, which is used to further perform L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit to obtain a 32.768 KHz clock signal, where L = 64 / M.

[0067] That is, the 2.097 MHz crystal oscillator can be frequency-divided by 16 first, and then the signal that has been frequency-divided by 16 can be further frequency-divided by 4, achieving a total of 64 times of frequency division. Finally, 32.768 KHz is output as the input clock of the MCU, and this input clock is the input clock with the same source as the analog integrated front end. It is also possible to first frequency-divide the 2.097 MHz crystal oscillator by 8, and then further frequency-divide the signal that has been frequency-divided by 8 by 8, achieving a total of 64 times of frequency division. Finally, 32.768 KHz is output as the input clock with the same source as the analog integrated front end. It is also possible to first frequency-divide the 2.097 MHz crystal oscillator by 4, and then further frequency-divide the signal that has been frequency-divided by 4 by 16, achieving a total of 64 times of frequency division. Finally, 32.768 KHz is output as the input clock with the same source as the analog integrated front end.

[0068] When the 64-times frequency division circuit includes 3 frequency division sub-circuits, the 64-frequency division circuit may include:

[0069] The first frequency division sub-circuit, connected to the 2.097 MHz external clock, is used to frequency-divide the 2.097 MHz clock crystal oscillator by 4;

[0070] The second frequency division sub-circuit is used to further frequency-divide the signal frequency-divided by 4 by the first frequency division sub-circuit; and

[0071] The third frequency division sub-circuit is used to further frequency-divide the signal frequency-divided by 4 by the second frequency division sub-circuit to obtain a 32.768 KHz clock signal.

[0072] That is, the first frequency division sub-circuit, the second frequency division sub-circuit, and the third frequency division sub-circuit are the same 4-times frequency division circuits.

[0073] In some other embodiments of the present invention, more frequency division sub-circuits may also be included, and the frequency division multiple is 2 to 16 frequency divisions, which will not be listed one by one here.

[0074] Figure 3 The figure shows a schematic diagram of the external clock circuit in an embodiment of the present invention. Figure 4 It is a schematic diagram of the frequency division circuit in an embodiment of the invention. As Figure 3As shown, the pin 3 of the clock circuit X1 outputs a clock of 2.097 MHz. One direction is output to the analog front-end chip as the clock source of the analog front-end chip, and the other direction is output to the pin 2 of the first frequency division sub-circuit (chip U6, which is a 16-fold frequency division circuit) as the main input of the frequency division circuit. Then, after being 16-fold frequency divided by chip U6, the 16-fold frequency divided clock is output from pin 11. Then, it is input from the pin 3 of the second frequency division sub-circuit (chip U8, which is a 4-fold frequency division circuit), and after being 4-fold frequency divided by chip U8, the desired 32.768 KHz clock is output from pin 11. This clock is given to the main control chip MCU as the clock signal of the MUC. Thus, not only can the analog front-end chip collect EEG signals at 256 Hz, but also the clock synchronization between the analog front-end chip and the main control chip can be achieved.

[0075] In some embodiments of the present invention, the main control chip MCU selected is a chip integrating Bluetooth and wired. After the ADC of the analog front-end chip transmits the data (digital signal) to the MCU through the SPI protocol, the MCU processes the data and further transmits the processed data to the host computer through the Bluetooth protocol or wired transmission method.

[0076] The main control chip MCU mainly includes:

[0077] The indicator light circuit control module can be used to control the charging indicator light, Bluetooth indicator light, etc.;

[0078] The analog integrated front-end EEG signal data receiving and processing module is used to receive and process the EEG digital signals from the analog integrated front-end;

[0079] The power supply circuit control module is used for power monitoring and charging detection and performs corresponding charging control;

[0080] The Lead off switching control (disconnection detection control) module is used for cyclic detection of the connection degree of multi-channel impedance;

[0081] The EEG signal switching control module is used for cyclic detection of multi-channel EEG signals;

[0082] The two-channel BIO signal receiving and processing module is used for physiological signal detection.

[0083] The main control chip MCU can be implemented by using an existing MCU chip or a self-developed chip that can achieve similar functions.

[0084] As described above, in the present invention, by using hardware, an analog integrated front end with a fixed sampling rate of 250 Hz can be converted into a sampling rate of 256 Hz, and a frequency division circuit is used to solve the problem of clock asynchronization caused by changing the sampling rate. Thus, a single master control chip with a sampling rate of 256 Hz can be used to synchronously process various physiological signals including electroencephalogram (EEG) signals, greatly expanding the application scenarios of physiological signals.

[0085] Correspondingly, the present invention also provides a method for collecting and processing EEG signals, as Figure 5 shown, the method includes the following steps:

[0086] Step S110: An analog front-end chip uses a clock signal with a first clock frequency of an external clock as a clock input, collects EEG signals at a first sampling rate matching the first clock frequency to obtain EEG analog signals, converts the EEG analog signals into EEG digital signals, and transmits the EEG digital signals to a control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate.

[0087] In the previous example, the first clock frequency is 2.097 MHz, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the second sampling rate is 250 Hz.

[0088] Step S120: Connect the external clock with the first clock frequency through a frequency division circuit, which is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of a target clock frequency, where N is an even multiple of 2, and N = f1 / f g , f1 represents the first clock frequency, f g represents the target clock frequency.

[0089] In the previous example, the target clock frequency is 32.768 KHz, and N is 64.

[0090] Step S130: The control unit uses the clock signal with the target clock frequency obtained after frequency division by the frequency division circuit as a clock input to perform data processing on the EEG digital signals from the analog front-end chip.

[0091] As an example, the step of connecting the external clock with the first clock frequency through a frequency division circuit, which is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of a target clock frequency, includes: connecting the external clock with the first clock frequency, performing M-fold frequency division on the clock crystal oscillator of the external clock, where M is an even multiple of 2; and further performing L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit to obtain a clock signal of 32.768 KHz, where L is an even multiple of 2 and L = N / M.

[0092] As another example, when the first clock frequency is 2.097 MHz, N is 64, the first sampling rate is 256 Hz or a multiple of 256 Hz, and the target clock frequency is 32.768 KHz, the external clock connecting the first clock frequency through the frequency division circuit, which is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, includes: connecting a 2.097 MHz external clock, which is used to perform the first 4-fold frequency division on the 2.097 MHz clock crystal oscillator; further performing the second 4-fold frequency division on the signal after the first 4-fold frequency division; and further performing the third 4-fold frequency division on the signal after the second 4-fold frequency division to obtain a 32.768 KHz clock signal.

[0093] Those of ordinary skill in the art should understand that the various exemplary components, systems, and methods described in connection with the embodiments disclosed herein can be implemented in hardware, software, or a combination of both. Specifically, whether to implement in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave on a transmission medium or a communication link.

[0094] It should be clear that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, the detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of the present invention.

[0095] In the present invention, the features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, and / or combined with the features of other embodiments or replace the features of other embodiments.

[0096] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An electroencephalogram signal acquisition and processing device, characterized in that, The device includes: An analog front-end processing circuit, including an analog front-end chip, which is used to take the clock signal with the first clock frequency of an external clock as the clock input, collect electroencephalogram (EEG) signals at the first sampling rate matching the first clock frequency to obtain EEG analog signals, convert the EEG analog signals into EEG digital signals, and transmit the EEG digital signals to the control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate; Frequency division circuit, which is connected to an external clock of the first clock frequency and is used to perform N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, where N is an even multiple of 2 and N = f1 / f g , f1 represents the first clock frequency, f g represents the target clock frequency; and The control unit is used to take the clock signal with the target clock frequency obtained after frequency division by the frequency division circuit as the clock input, and perform data processing on the EEG digital signals from the analog front-end chip.

2. The device according to claim 1, characterized in that, The device further includes: A power supply circuit, which is used to supply power to the analog front-end chip and the main control chip. The power supply circuit includes a main power supply module and a sub-power supply module. The main power supply module includes an analog circuit power supply circuit and a digital circuit power supply circuit; the analog circuit power supply circuit includes a low dropout regulator, which is used to supply the first voltage to the analog circuit of the EEG signal acquisition device; the digital circuit power supply circuit includes a buck circuit, which is used to supply the first voltage to the digital circuit of the EEG signal acquisition device; The sub-power supply module divides the second voltage from the first voltage provided by the analog circuit power supply circuit to supply power to the analog front-end chip.

3. The device according to claim 1, characterized in that, The range of the first clock frequency is 1.5M~2.25MHz, and the first sampling rate is F, satisfying: F = f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048 or 4096.

4. The device according to any one of claims 1 to 3, characterized in that, The frequency division circuit includes: A first frequency division sub-circuit, connected to the external clock with the first clock frequency, which is used to perform M-fold frequency division on the clock crystal oscillator of the external clock, where M is an even multiple of 2; and A second frequency division sub-circuit, which is used to further perform L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit to obtain a clock signal with the target clock frequency, where L is an even multiple of 2 and L = N / M.

5. The device according to claim 3, characterized in that, When N is 64, the frequency division circuit includes: A first frequency division sub-circuit, connected to the external clock with the first clock frequency, which is used to perform 4-fold frequency division on the clock crystal oscillator of the external clock; A second frequency division sub-circuit, which is used to further perform 4-fold frequency division on the signal after 4-fold frequency division by the first frequency division sub-circuit; and A third frequency division sub-circuit, which is used to further perform 4-fold frequency division on the signal after 4-fold frequency division by the second frequency division sub-circuit to obtain a clock signal with the target clock frequency.

6. The device according to claim 1, characterized in that, The analog front-end processing circuit further includes: An electrostatic protection circuit, which is arranged at the EEG signal input end for electrostatic protection; and A low-pass filter circuit, which is arranged at the EEG signal input end for filtering high-frequency electromagnetic waves and high-frequency crosstalk.

7. The device according to claim 2, characterized in that, The analog front-end chip includes a multi-channel EEG signal MUX switching module, which is used to perform polling acquisition on EEG signals; The range of the first voltage is 1.8~3.6V; The second voltage is denoted as AVDD: AVDD = AVDD + -AVDD - , where AVDD + and AVDD - respectively represent the high voltage and low voltage of the analog front-end chip, and the range of AVDD is 4.75~5.25V.

8. A method for collecting and processing electroencephalogram signals, characterized in that, The method includes the following steps: The analog front-end chip uses the clock signal with the first clock frequency of the external clock as the clock input, collects the electroencephalogram (EEG) signal at the first sampling rate matching the first clock frequency to obtain an analog EEG signal, converts the analog EEG signal into a digital EEG signal, and transmits the digital EEG signal to the control unit; wherein, the default sampling rate of the analog front-end chip is a second sampling rate different from the first sampling rate. Connect an external clock with the first clock frequency through a frequency division circuit, which is used to perform N-fold frequency division on the clock oscillator of the external clock to obtain a clock signal with a clock frequency of the target clock frequency, where N is an even multiple of 2 and N = f1 / f g , f1 represents the first clock frequency, f g represents the target clock frequency; and The control unit uses the clock signal with the target clock frequency obtained by frequency division of the frequency division circuit as the clock input to process the digital EEG signal from the analog front-end chip.

9. The method according to claim 8, wherein The frequency division circuit is connected to the external clock with the first clock frequency and is used for performing N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with the clock frequency of the target clock frequency, including: Connecting the external clock with the first clock frequency through the first frequency division sub-circuit of the frequency division circuit to perform M-fold frequency division on the clock crystal oscillator of the external clock, where M is an even multiple of 2; and Further performing L-fold frequency division on the signal after M-fold frequency division by the first frequency division sub-circuit through the second frequency division sub-circuit of the frequency division circuit to obtain the clock signal with the target clock frequency, where L is an even multiple of 2 and L = N / M.

10. The method according to claim 8, wherein The range of the first clock frequency is 1.5M to 2.25MHz, N is 64, and the first sampling rate is F, satisfying: F = f1 / 2 / k, where k is selected from 64, 128, 256, 512, 1024, 2048, or 4096. The frequency division circuit is connected to the external clock with the first clock frequency and is used for performing N-fold frequency division on the clock crystal oscillator of the external clock to obtain a clock signal with the clock frequency of the target clock frequency, including: Connecting the external clock with the first clock frequency for performing the first 4-fold frequency division on the clock crystal oscillator of the external clock. Further performing the second 4-fold frequency division on the signal after the first 4-fold frequency division. Further performing the third 4-fold frequency division on the signal after the second 4-fold frequency division to obtain the clock signal with the target clock frequency.

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