Structure and manufacturing method for improving short-circuit robustness of sic power devices

Abstract

A structure and manufacturing method for improving short-circuit robustness of SIC power devices. It relates to the technical field of power semiconductors. It comprises the following steps: step 001, providing an N-type heavily doped substrate, i.e. an N+ type SiC semiconductor substrate, with a doping concentration of 360~400um and a doping concentration of 1e19 cm ‑2 ; the N+ type substrate has two surfaces, which are divided into a front surface and a back surface, a layer of N type buffer layer is formed on the front surface, the thickness is 0.8~1um, and the doping concentration is 1e18 cm ‑2 ; the N type buffer layer covers an N type lightly doped drift layer, i.e. an N type drift layer, with a thickness of 5~15um and a doping concentration of 5e15~1e16 cm ‑2 , and a metal electrode layer is formed on the back surface; step 002, P type doping is performed on the surface of the drift layer through a photoetching mask to form a P-Well well region; the manufacturing process of the application is simple, the effect is remarkable, and it can be applied to the manufacturing of new type silicon carbide MOSFET power devices.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a structure and manufacturing method for improving the short-circuit robustness of SiC power devices. Background Technology

[0002] Power devices, as core components in the field of power electronics, are widely used in transportation, industry, medical, and home electronics, playing a significant role in human life and the socio-economic landscape. In today's world, with scarce resources and a rapidly changing climate, the semiconductor industry is also striving to maximize resource utilization. Silicon carbide, as a representative of third-generation wide-bandgap semiconductors, exhibits excellent performance in high-temperature environments, high-power applications, and heat dissipation, leading to extensive research into silicon carbide power devices worldwide.

[0003] SiC MOSFETs offer advantages such as low on-resistance, high withstand voltage, low switching losses, and high frequency, and are expected to gradually replace silicon-based IGBTs. SiC MOSFETs often operate in harsh environments, making short-circuit testing a crucial test for characterizing device reliability. Due to human error or equipment failure, power devices are at risk of short circuits. Once a short circuit is detected, the protection circuit triggers its mechanism to disconnect the circuit. However, the triggering protection circuit has a certain reaction time, requiring the power device to withstand short-term short circuits. This is the feedback mechanism for the device's short-circuit robustness. Even if the short circuit time is only on the order of microseconds, a large density of current will flow through the device instantaneously, generating a significant amount of heat, ultimately leading to thermal failure.

[0004] Most researchers, both domestically and internationally, explore ways to improve the short-circuit robustness of devices by examining short-circuit failure phenomena and external protection circuits. However, improving the inherent short-circuit robustness of the device itself is of great significance. SiC has a high breakdown field strength and a wide bandgap, allowing for higher doping concentrations in the epitaxial layer compared to silicon-based devices. This results in SiC chips having stronger current-carrying capacity and smaller size. Experimental tests show that the short-circuit time of conventional Si IGBTs can reach over 10µs, while that of SiC MOSFETs is only 3-5µs. This is because the high short-circuit current density of SiC MOSFETs leads to excessively high temperatures, and the small chip size results in slower heat dissipation, thus making the short-circuit robustness of SiC MOSFETs lower than that of SiIGBTs.

[0005] Therefore, improving the short-circuit robustness of SiC MOSFETs to adapt to applications in harsh operating circuit environments is an urgent task to be solved. Summary of the Invention

[0006] To address the above problems, this invention provides a structure and manufacturing method for improving the short-circuit robustness of trench gate SiC MOSFET structures, thereby enhancing the short-circuit robustness of SiC power devices.

[0007] The technical solution of this invention is: a method for manufacturing a structure to improve the short-circuit robustness of SiC power devices, comprising the following steps: Step 001: Provide an N-type heavily doped substrate, specifically an N+ type SiC semiconductor substrate, with a doping concentration of 360~400µm and a doping concentration of 1e19 cm⁻¹. -2 The N+ type substrate has two surfaces, a front side and a back side. An N-type buffer layer with a thickness of 0.8~1µm and a doping concentration of 1e18 cm⁻¹ is formed on the front side. -2 A lightly doped N-type drift layer is formed by covering an N-type buffer layer with a thickness of 5-15 μm and a doping concentration of 5e15-1e16 cm⁻¹. -2 A metal electrode layer is formed on the back side; Step 002: P-type doping is performed on the surface of the drift layer using a photolithographic mask to form a P-Well region; Step 003: After determining the P-Well region, perform two light doping operations using a secondary mask to form a buried layer doping layer under the P-Well region, forming carrier extension layer CSL-1 and carrier extension layer CSL-2. Step 004: N-type heavy doping is performed on the surface of the P-Well region using a photolithographic mask to form the source region; Step 005: P-type heavy doping is performed on the surface of the P-Well region using a photolithographic mask to form an ohmic contact region; Step 006: Using a photolithography mask, a trench structure is formed in the center of the P-Well region by dry etching. P-type ions are implanted at the bottom of the trench by ion implantation to perform P-type heavy doping; thus forming a shielding layer. Step 007: A gate oxide layer is formed on the surface of the trench through a dry oxygen thermal oxidation process. The interface between the gate oxide layer and the P-Well region forms a channel. Polysilicon is deposited on the surface of the gate oxide layer to form a gate electrode structure. Step 008: Isolate the gate electrode structure from the ohmic contact region by depositing a passivation layer; Step 009: An ohmic contact window is created by etching the passivation layer, and a good source ohmic contact layer is formed by depositing metal and alloying it with high-temperature annealing. Step 010: Source metal is formed on the front side by depositing electrode metal; Step 011: The substrate is thinned sequentially through a thinning process on the back side; metal is deposited to form the back drain ohmic contact layer; electrode metal is deposited on the back side to form the drain contact electrode.

[0008] Specifically, in step 001, the N-type heavily doped substrate is a 4H-SiC substrate with a doping concentration of 1e19cm⁻¹. -2 .

[0009] Specifically, in step 002, the P-Well region is p-type doped, and a 20-50 nm SiO2 thin film pad is formed on the surface of the drift layer before implantation to prevent high-energy ion implantation from damaging the surface of the SiC drift layer.

[0010] Specifically, in step 003, the carrier extension layer CSL-1 is p-type doped, which compensates for the p-type doping concentration of the drift layer, thereby reducing the p-type doping concentration of the drift layer. The carrier extension layer CSL-2 is p-type doped, thereby increasing the p-type doping concentration of the carrier extension layer CSL-2. Before implantation, a 20-50 nm SiO2 thin film pad is formed on the surface of the drift layer to prevent high-energy ion implantation from damaging the surface of the SiC drift layer.

[0011] Specifically, in step 004, the source region is doped with N-type.

[0012] Specifically, in step 005, the ohmic contact region is p-type doped.

[0013] Specifically, in step 6, the shielding layer is p-type doped; after all ion implantation is completed, activation annealing is required. In this case, a high-temperature vacuum annealing furnace is used, with an annealing temperature of 1650~1750℃ and an annealing time of 10~30min.

[0014] Specifically, in step 7, the gate oxide growth temperature is 1250~1350℃, the growth thickness is 50~60nm, and the grown gate oxide structure is subjected to NO annealing treatment to reduce the interface states of the gate oxide growth and improve the conduction mobility. The annealing temperature and time are 1250℃ and 1H, respectively.

[0015] A structure for improving the short-circuit robustness of SiC power devices is characterized by comprising, from bottom to top, a drain contact electrode, a drain ohmic contact layer, a substrate, an N-type buffer layer, a drift layer, and a P-Well region. The P-Well region is provided with carrier extension layers CSL-1 and CSL-2, which are connected to the drift layer; The end of the P-Well region is provided with an ohmic contact region connected to the carrier extension layer CSL-2; The top of the P-Well trap region is provided with a source region connected to the ohmic contact region; The top surface of the source region is provided with a channel extending downward into the drift layer; The channel is provided with a shielding layer and a gate oxide layer; the gate oxide layer is provided with a gate electrode (5) that is encapsulated within it. The top surface of the gate oxide layer (10) is provided with an upwardly extending gate passivation layer (15). The top surfaces of the ohmic contact region (6), the source region (14), and the gate passivation layer (15) are covered by the source metal (8).

[0016] Specifically, the carrier extension layer CSL-1 (11) is located in the middle of the carrier extension layer CSL-2 (12).

[0017] Specifically, the N-type doping concentration of the carrier extension layer CSL-2 (12) is 5e16~8e16 cm⁻¹. -2 ; The concentration of the carrier extension layer CSL-1 (11) is 1e15~5e15 cm⁻¹ -2 .

[0018] This invention provides two different doping concentrations in the carrier extension layer, namely CSL-1 and CSL-2. The doping concentration in the CSL-2 region, closer to the channel, is higher than that in CSL-1. When a lower voltage is applied to the drain electrode, the device operates in the linear region, and the P-Well region and the shielding layer at the bottom of the trench hardly generate a depletion layer, resulting in a wider current path. Figure 11 As shown, when the device encounters a short circuit, the voltage applied to the drain is higher, and the depletion layer formed by the P-Well region and the shielding layer at the bottom of the trench is wider, causing the current path to deviate. Figure 12 As shown. When normally conducting, the overall on-resistance is reduced due to the addition of the highly doped CSL-2 region. When short-circuited, the current flows through the high-resistance region CSL-1, and the current density is reduced, effectively reducing short-circuit power consumption and thus enhancing short-circuit robustness.

[0019] This method has a simple manufacturing process and significant effects, and can be applied to the manufacture of new silicon carbide MOSFET power devices. Attached Figure Description

[0020] Figure 1 A schematic diagram of the substrate for a SiC MOSFET is provided. Figure 2 A schematic diagram of SiC MOSFET epitaxy is provided; Figure 3 Provides a schematic diagram of the formation of a P-Well region in a SiC MOSFET; Figure 4 A schematic diagram is provided showing the formation of carrier extension layers CSL-1 and CSL-2 in a SiC MOSFET. Figure 5Provides a schematic diagram of the ohmic contact region and source region of a SiC MOSFET; Figure 6 Provides a schematic diagram of the trench and shielding area formation for a SiC MOSFET; Figure 7 Provides a schematic diagram of the gate structure formed by SiC MOSFET; Figure 8 Provides a schematic diagram of gate passivation formation in a SiC MOSFET; Figure 9 A schematic diagram showing the formation of the source contact in a SiC MOSFET is provided. Figure 10 A schematic diagram showing the formation of the drain contact in a SiC MOSFET is provided. Figure 11 Provides the current path when the SiC MOSFET is normally turned on; Figure 12 Provides the current path for SiC MOSFETs under short-circuit conditions; In the figure, 1 is the drain contact electrode, 2 is the drain ohmic contact layer, 3 is the substrate, 4 is the drift layer, 5 is the gate electrode, 6 is the ohmic contact region, 7 is the source ohmic contact layer, 8 is the source metal, 9 is the shielding layer, 10 is the gate oxide layer, 11 is the carrier extension layer CSL-1, 12 is the carrier extension layer CSL-2, 13 is the P-Well region, 14 is the source region, 15 is the gate passivation layer, 16 is the channel, and 17 is the N-type buffer layer. Detailed Implementation

[0021] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0022] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0023] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The embodiments of the present invention are described below with reference to Figures 1-12; A method for manufacturing a structure to improve the short-circuit robustness of SiC power devices includes the following steps: Step 001, provide an N-type heavily doped substrate 3, referring to... Figure 1 As shown, this is an N+ type SiC semiconductor substrate. An N+ type substrate has two surfaces: a front surface and a back surface. (Refer to...) Figure 2 As shown, an N-type buffer layer 17 is formed on the front side, and an N-type lightly doped drift layer 4 is covered on the N-type buffer layer 17, while a metal electrode layer is formed on the back side. Step 002, refer to Figure 3 As shown, a second type of doping is performed on the surface of the epitaxial layer 4 using a photolithographic mask to form a P-Well region 13; Step 003: After determining the well region, perform two light doping operations using a secondary mask to form a buried layer doping layer under the P-Well well region 13, forming carrier extension layers CSL-1 11 and CSL-2 12. Step 004: N-type heavy doping is performed on the surface of the well region using a photolithographic mask to form the source region 14; (Refer to...) Figure 4 As shown; Step 005: P-type heavy doping is performed on the surface of the well region using a photolithographic mask to form an ohmic contact region 6; (Refer to...) Figure 5 As shown; Step 006: Using a photolithography mask, a channel 16 is formed in the center of the well region by dry etching. Then, second-type doped ions are implanted at the bottom of the channel via ion implantation to perform p-type heavy doping, forming a shielding layer 9. (Refer to...) Figure 6 As shown; Step 007: A gate oxide layer 10 is formed on the surface of the channel 16, and polysilicon is deposited on the surface of the gate oxide layer 10 to form the gate electrode 5 structure, as shown in the figure. Figure 7 As shown; Step 008: Isolate the gate electrode 5 structure from the ohmic contact region 6 by depositing a passivation layer, referring to... Figure 8 As shown; Step 009: An ohmic contact window is created by etching the passivation layer, and a good ohmic contact layer 7 is formed by depositing metal and alloying it with high-temperature annealing. (Refer to...) Figure 9 As shown; Step 010: Source metal 8 is formed on the front side by depositing electrode metal, as shown in the reference. Figure 9 As shown; Step 011: The substrate is thinned on the back side using a thinning process to reduce the on-resistance; metal is deposited, and laser annealing is performed to form the drain ohmic contact layer 2; electrode metal is deposited to form the drain contact electrode 1, as shown in the reference. Figure 10 As shown.

[0025] Further specifying, in step 001, the N-type heavily doped substrate 3 is a 4H-SiC substrate with a doping concentration of 1e19cm⁻¹. -2 The thickness is 360um, the thickness of the buffer layer is 1um, and the doping concentration is 1e18cm. -2 The thickness and doping concentration of the drift layer were determined to be 10 μm and 8e15 cm. -2 .

[0026] Further specifying, in step 002, the P-Well region 13 is p-type doped, and a 20-50 nm SiO2 thin film pad is formed on the surface of the drift layer before implantation to prevent high-energy ion implantation from damaging the surface of the SiC drift layer. The energy of each implantation in the P-Well region is 100-600 keV, and the implantation dose is 1e12-1e14 cm⁻¹. -2 The number of injections is 3-5 times. In this case, the P-Well well region was injected 4 times, with the injection energy and dose being 560 KeV and 1e14 cm⁻¹, respectively. -2 390Kev 1e13cm -2 280Kev 5e12cm -2 ,120Kev1e12cm -2 .

[0027] Further specifying, in step 003, the carrier extension layer CSL-1 11 is p-type doped, which compensates for the n-type doping concentration of the drift layer 4, thus reducing the n-type doping concentration of the drift layer 4. The carrier extension layer CSL-2 12 is n-type doped, thus increasing the n-type doping concentration of the carrier extension layer CSL-2 12. Before implantation, a 20-50 nm SiO2 thin film pad is formed on the surface of the drift layer 4 to prevent high-energy ion implantation from damaging the surface of the SiC drift layer. In this case, CSL-1 is implanted twice, with implantation energies and doses of 700 KeV and 4e11 cm⁻¹, respectively. -2 600Kev 3e11cm -2The implanted P-type ions and the N-type doping in the drift layer compensate for each other, resulting in an N-type doping concentration of 1e¹⁵ to 3e¹⁵ cm⁻¹ in the CSL-1 region. -2 The CSL-2 injection was performed three times, with the injected energy and dose being 700 KeV and 8e11 cm⁻¹, respectively. -2 600Kev 7e11cm -2 500Kev 6e11cm -2 This increases the N-type doping concentration in the CSL-2 region to 7e16~8e16 cm⁻¹ -2 .

[0028] Further specifying, in step 004, source region 14 uses N-type doping. In this case, the implantation is performed three times, with implantation energies and doses of 280 KeV and 1e15cm, respectively. -2 160Kev 9e14cm -2 80Kev 8e14cm -2 .

[0029] Further specifying, in step 005, the ohmic contact region 6 is p-type doped. In this case, the implantation is performed three times, with implantation energies and doses of 350 KeV and 1e15cm, respectively. -2 220Kev 9e14cm -2 100Kev 8e14cm -2 .

[0030] Further specifying, in step 6, the shielding layer 9 uses P-type doping. In this case, the implantation is performed three times, with implantation energies and doses of 260 KeV and 1e15cm, respectively. -2 160Kev 9e14cm -2 80Kev 8e14cm -2 After all ion implantation is completed, activation annealing is required. In this case, a high-temperature vacuum annealing furnace is used, with an annealing temperature of 1700℃ and an annealing time of 30min.

[0031] Further specified, the gate oxide growth temperature in step 7 is 1350℃, the growth thickness is 60nm, and the grown gate oxide structure is subjected to NO annealing treatment to reduce the interface states of the gate oxide growth and improve the conduction mobility. The annealing temperature and time are 1250℃ and 1H, respectively.

[0032] Further specifying, in this case, the passivation layer is formed using LPCVD, with a growth thickness of 0.6 μm. The deposited ohmic contact metal is Ni, and the alloying conditions are 960 °C for 5 min; the electrode metal deposited on the front side is Al, with a thickness of 4-5 μm; the substrate is thinned to 180-200 μm; the ohmic contact metal deposited on the back side is Ni, and alloying is performed using laser local annealing.

[0033] Further specifying, the back contact electrode metal in this case is Ti / Ni / Ag with a thickness of 1.5um, formed by sputtering process.

[0034] In summary, this invention provides a method for manufacturing a silicon carbide MOS power device with high short-circuit robustness. The advantage of this method lies in providing two carrier extension layers, namely CSL-1 and CSL-2. The doping concentration of the CSL-2 region near the channel is higher than that of CSL-1, which significantly improves short-circuit robustness while enhancing current carrying capacity and reducing on-resistance. This invention demonstrates significant effectiveness, has a simple manufacturing process, and shows broad prospects for the manufacturing and application of novel silicon carbide MOS devices.

[0035] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for manufacturing a structure to improve the short-circuit robustness of SiC power devices, characterized in that, Includes the following steps: Step 001: Provide an N-type heavily doped substrate (3), form an N-type buffer layer (17) on the front side; form a metal electrode layer on the back side of the N-type buffer layer (17) covering an N-type lightly doped drift layer (4); Step 002: P-type doping is performed on the surface of the drift layer (4) to form a P-Well region (13) using a photolithographic mask. Step 003: After determining the P-Well region (13), perform two light doping operations through a secondary mask to form a buried layer doping under the P-Well region (13), forming a carrier extension layer CSL-1 (11) and a carrier extension layer CSL-2 (12). Step 004: N-type heavy doping is performed on the surface of the P-Well region (13) using a photolithographic mask to form the source region (14). Step 005: P-type heavy doping is performed on the surface of the P-Well region (13) using a photolithographic mask to form an ohmic contact region (6); Step 006: Using a photolithography mask, a trench structure is formed in the center of the P-Well region (13) by dry etching. P-type ions are implanted at the bottom of the trench by ion implantation to perform P-type heavy doping; thus forming a shielding layer (9). Step 007: A gate oxide layer (10) is formed on the surface of the trench by a dry oxygen thermal oxidation process. The interface between the gate oxide layer (10) and the P-Well region (13) forms a channel. Ploy silicon is deposited on the surface of the gate oxide layer (10) to form a gate electrode (5) structure. Step 008: The gate electrode (5) structure is isolated from the ohmic contact region (6) by depositing a passivation layer; Step 009: An ohmic contact window is created by etching the passivation layer, and a good source ohmic contact layer is formed by depositing metal and alloying it with high-temperature annealing (7). Step 010: Source metal is formed on the front side by depositing electrode metal (8). Step 011: The substrate is thinned by a thinning process on the back side; metal is deposited to form the back drain ohmic contact layer (2); electrode metal is deposited on the back side to form the drain contact electrode (1).

2. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 001, the N-type heavily doped substrate (3) is a 4H-SiC substrate with a doping concentration of 1e19cm⁻¹. -2 .

3. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 003, the carrier extension layer CSL-1 (11) is p-type doped. By compensating for the n-type doping concentration of the drift layer (4), the n-type doping concentration of the drift layer (4) is reduced. The carrier extension layer CSL-2 (12) is n-type doped, which increases the n-type doping concentration of the carrier extension layer CSL-2 (12). Before implantation, a 20~50nm SiO2 thin film pad is formed on the surface of the drift layer (4) to prevent high-energy ion implantation from damaging the surface of the SiC drift layer.

4. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 004, the source region (14) is doped with N-type.

5. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 005, the ohmic contact region (6) is p-type doped.

6. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 6, the shielding layer (9) is p-type doped; after all ion implantation is completed, activation annealing is required. In this case, a high-temperature vacuum annealing furnace is used, with an annealing temperature of 1650~1750℃ and an annealing time of 10~30min.

7. The method for manufacturing a structure to improve the short-circuit robustness of SiC power devices according to claim 1, characterized in that, In step 7, the gate oxide growth temperature is 1250~1350℃, and the growth thickness is 50~60nm. The grown gate oxide structure is subjected to NO annealing treatment to reduce the interface states of the gate oxide growth and improve the conduction mobility. The annealing temperature and time are 1250℃ and 1H, respectively.

8. A structure for improving the short-circuit robustness of a SiC power device, prepared by the structural manufacturing method for improving the short-circuit robustness of a SiC power device according to claim 1, is characterized in that, From bottom to top, it includes a drain contact electrode (1), a drain ohmic contact layer (2), a substrate (3), an N-type buffer layer (17), a drift layer (4), and a P-Well region (13). The P-Well trap region (13) is provided with a carrier extension layer CSL-1 (11) and a carrier extension layer CSL-2 (12) connected to the drift layer (4). The end of the P-Well trap region (13) is provided with an ohmic contact region (6) connected to the carrier extension layer CSL-2 (12); The top of the P-Well trap region (13) is provided with a source region (14) connected to the ohmic contact region (6). The top surface of the source region (14) is provided with a channel (16) extending downward into the drift layer (4). The channel (16) is provided with a shielding layer (9) and a gate oxide layer (10); the gate oxide layer (10) is provided with a gate electrode (5) encapsulated therein. The top surface of the gate oxide layer (10) is provided with an upwardly extending gate passivation layer (15). The top surfaces of the ohmic contact region (6), the source region (14), and the gate passivation layer (15) are covered by the source metal (8).

9. A structure for improving the short-circuit robustness of SiC power devices according to claim 8, characterized in that, The carrier extension layer CSL-1 (11) is located in the middle of the carrier extension layer CSL-2 (12).

10. A structure for improving the short-circuit robustness of SiC power devices according to claim 8, characterized in that, The N-type doping concentration of the carrier extension layer CSL-2 (12) is 5e16~8e16 cm⁻¹. -2 ; The concentration of the carrier extension layer CSL-1 (11) is 1e15~5e15 cm⁻¹ -2 .

Images