A decoding method, chip and related device

Abstract

This application provides a decoding method, chip, and related apparatus. By introducing a threshold judgment mechanism, the controller chip can simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput. Simultaneously, the algorithm for calculating the number of bits that do not satisfy the parity check equation for each bit is optimized, reducing the probability of correct bits being incorrectly flipped, thereby reducing the error plane in the decoding.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a decoding method, chip, and related apparatus. Background Technology

[0002] A solid-state drive (SSD) is a hard drive made of an array of solid-state electronic storage chips. An SSD includes a control unit and storage units. The storage medium used in SSDs is flash memory chips (such as NAND flash memory). The advantages of SSDs are fast boot times, fast read speeds, no need for addressing, and direct data access without affecting read / write speeds.

[0003] When evaluating the performance of SSD storage devices, factors such as read speed on NAND flash memory and device lifespan are typically considered. Read speed depends on the decoding speed (or throughput) of the error correction algorithm, while device lifespan depends on the maximum decoding performance of the error correction algorithm. Improving both SSD read speed and lifespan is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This application provides a decoding method, chip, and related apparatus, which reduces the probability of correct bits being incorrectly flipped, while also reducing the decoding latency of the controller chip and improving the decoding throughput.

[0005] In a first aspect, this application provides a decoding method, the method comprising: reading a first bit sequence and obtaining a verification matrix H of the first bit sequence, wherein the first bit sequence contains n bits of data; in a first iteration, obtaining a first corrector S1 based on the first bit sequence and the verification matrix H; if the first corrector S1 is not all zeros, the chip determines, based on the first bit sequence and the first corrector S1, the first number of bits in the first bit sequence that do not satisfy the verification equation in the verification matrix H; if the first number of bits in the first bit sequence that do not satisfy the verification equation in the verification matrix H is greater than or equal to a first threshold T1, flipping the first bit data to obtain a second bit sequence; in a second iteration... After obtaining the second bit sequence, a second corrector S2 is obtained based on the second bit sequence and the test matrix H. If the second corrector S2 is not all zeros, a second number of bits in the second bit sequence that do not satisfy the check equation in the test matrix H is obtained based on the second bit sequence, the second corrector S2, and the first regularization term, where the first regularization term is less than or equal to 0. If the second number of bits in the second bit sequence that do not satisfy the check equation in the test matrix H is greater than or equal to the first threshold T2, the second bit sequence is flipped to obtain the third bit sequence. After obtaining the third bit sequence, a third corrector S3 is obtained based on the third bit sequence and the test matrix H. If the third corrector S3 is all zeros, the third bit sequence is output.

[0006] This process continues until the corrector is all zeros, or the maximum number of iterations is reached.

[0007] The first approach optimizes the algorithm for calculating the number of bits that do not satisfy the parity check equation, reducing the probability of correct bits being incorrectly flipped and thus lowering the decoding error level. Secondly, a threshold judgment mechanism is introduced, allowing the controller chip to simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing decoding latency and improving decoding throughput. Thirdly, a random sequence generator is proposed, assigning a certain probability constraint to bits that meet the flipping condition, reducing the occurrence of the same bit getting stuck in an infinite loop due to repeated flipping. This further reduces decoding latency and improves decoding throughput.

[0008] In conjunction with the first aspect, in one possible implementation, the method further includes: during the third iteration, if the third corrector S3 is not all zeros, based on the third bit sequence, the second corrector S2, and the second regularization term, obtaining the third number of times each bit in the third bit sequence does not satisfy the check equation in the check matrix H, where the second regularization term is less than or equal to 0; if the third number of times the third bit in the third bit sequence does not satisfy the check equation in the check matrix H is greater than or equal to the third threshold T3, flipping the third bit sequence to obtain the fourth bit sequence; after obtaining the fourth bit sequence, obtaining the fourth corrector S4 based on the fourth bit sequence and the check matrix H; if the fourth corrector S4 is all zeros, outputting the third bit sequence. This process continues until the corrector is all zeros or the maximum number of iterations is reached.

[0009] In conjunction with the first aspect, in one possible implementation, the first regularization term is less than 0 when the first bit data has the same position in the first bit sequence and the second bit data has the same position in the second bit sequence. This optimizes the algorithm for the controller chip to calculate the number of bits that do not satisfy the check equation, reducing the probability of correct bits being incorrectly flipped, and thus reducing the error level in decoding.

[0010] Optionally, if the position of the first bit data in the first bit sequence is different from the position of the second bit data in the second bit sequence, the first regularization term is equal to 0.

[0011] In conjunction with the first aspect, in one possible implementation, if the positions of the first bit data in the first bit sequence, the second bit data in the second bit sequence, and the third bit data in the third bit sequence are the same, then the second regularization term is equal to the first regularization term, and the second regularization term is less than 0. Thus, if the same bit data is repeatedly flipped, when calculating the number of times the bit data does not satisfy the check equation, a regularization term less than 0 is added to reduce the probability of repeated flips.

[0012] In conjunction with the first aspect, in one possible implementation, the value of the second regularization term is 0 when the position of the second bit data in the second bit sequence is different from the position of the third bit data in the third bit sequence.

[0013] In conjunction with the first aspect, in one possible implementation, while flipping the first bit data, the method further includes: if the fourth bit data in the first bit sequence does not satisfy the first number of check equations in the check matrix H that is greater than or equal to the first threshold T1, then the fourth bit data is flipped to obtain the second bit sequence. This introduces a threshold judgment mechanism, allowing the controller chip to simultaneously calculate the number of bits that do not satisfy the check equations and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput.

[0014] In conjunction with the first aspect, in one possible implementation, the first threshold T1 is determined based on the test matrix H.

[0015] In conjunction with the first aspect, in one possible implementation, after obtaining the second bit sequence and before flipping the second bit data, the method further includes: obtaining a fourth number of bits that do not satisfy the check equations in the check matrix H based on a first number of bits that do not satisfy the check equations in the check matrix H and a preset maximum number of bits that do not satisfy the check equations in the check matrix H; the chip determines the maximum value between the first number of bits that do not satisfy the check equations in the check matrix H and the fourth number of bits that do not satisfy the check equations in the check matrix H as a second threshold T2. Thus, the threshold T needs to be updated after each flip.

[0016] In conjunction with the first aspect, in one possible implementation, based on E j 1 =d vj +1-E j Determine the fourth number of times each bit of data does not satisfy the check equation in the check matrix H; where E j 1 This indicates that each bit of data does not satisfy the fourth number of the parity check equations in the parity check matrix H, d vj This indicates the maximum number of bits of data that do not satisfy the check equations in the check matrix H, E j This indicates the number of times each bit of data does not satisfy the first check equation in the check matrix H.

[0017] In conjunction with the first aspect, in one possible implementation, flipping the first bit data specifically includes: obtaining a first digital sequence based on a first probability value and a first random sequence generator; wherein the number of elements in the first digital sequence is the same as the number of bits in the first bit sequence that are flipped, the elements in the first digital sequence are either 0 or 1, and the proportion of elements in the first digital sequence that are 1 is the first probability value; a random sequence generator is used to determine the position of the first bit data in the first bit sequence, and a certain probability constraint is assigned to flip bits that meet the flipping condition. This reduces the occurrence of the same bit getting stuck in an infinite loop due to repeated flipping. It also reduces the decoding latency of the controller chip and improves the decoding throughput. When the element corresponding to the position in the first digital sequence is 1, the first bit data is flipped.

[0018] In conjunction with the first aspect, in one possible implementation, the first bit sequence is output when the first corrector S1 is all 0.

[0019] In conjunction with the first aspect, in one possible implementation, the second bit sequence is output when the second corrector S2 is all 0.

[0020] Secondly, this application provides a chip, which includes a processing circuit and an interface circuit. The interface circuit is used to receive code instructions and transmit them to the processing circuit. The processing circuit is used to run the code instructions to execute a decoding method provided in any possible implementation of any of the above aspects.

[0021] Thirdly, this application provides a decoding apparatus, which includes a chip and a memory; the memory is used to store a first bit sequence, and the chip is used to read the first bit sequence from the memory and execute a decoding method provided in any possible implementation of any of the above aspects.

[0022] Fourthly, this application provides a computer-readable storage medium storing instructions that, when executed on a chip, cause the chip to perform a decoding method provided in any possible implementation of any of the above aspects.

[0023] Fifthly, this application provides a computer program product that, when executed by a chip, causes the chip to execute a decoding method provided in any possible implementation of any of the above aspects. Attached Figure Description

[0024] Figure 1 A schematic diagram of a multi-level decoding algorithm provided in this application embodiment;

[0025] Figure 2 A schematic diagram illustrating the principle of a GDBF algorithm provided in an embodiment of this application;

[0026] Figure 3 A schematic diagram of a Tanner diagram provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram provided for an embodiment of this application;

[0028] Figure 5 An SSD storage system using NAND media is provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram illustrating the error correction process of an SSD controller chip provided in an embodiment of this application;

[0030] Figure 7 A schematic diagram of an LDPC code decoding method provided in an embodiment of this application;

[0031] Figure 8A schematic diagram of a 0-1 number sequence generated by a random sequence generator provided in an embodiment of this application;

[0032] Figure 9 A schematic diagram illustrating another multi-level decoding algorithm provided in this application embodiment;

[0033] Figure 10 This is a schematic diagram of a decoding method provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0036] To ensure throughput and lifespan, current controller chips typically employ multi-level decoding algorithms.

[0037] Figure 1 An exemplary schematic diagram of a multi-level decoding algorithm is shown.

[0038] For example, a multi-level decoding algorithm could be a first-level decoding algorithm that is a bit-flipping (BF) decoding algorithm, a second-level decoding algorithm that is a hard-decision normalized min sum (NMS) decoding algorithm, and a third-level decoding algorithm that is a soft-decision NMS decoding algorithm.

[0039] S101, the controller chip reads stored data from the NAND flash memory.

[0040] S102, the controller chip performs decoding based on a bit-flipping decoding algorithm.

[0041] The controller chip performs decoding based on a bit-flipping decoding algorithm. Once the decoding is successful, the controller chip will output the correct stored data, and the decoding process will end.

[0042] If the controller chip fails to decode using the bit-flipping decoding algorithm, it will execute the next level of decoding algorithm.

[0043] S103, the controller chip performs decoding based on the hard-decision NMS decoding algorithm.

[0044] The controller chip performs decoding based on the hard-decision NMS decoding algorithm. After successful decoding, the controller chip will output the correct stored data, and the decoding will end.

[0045] If the controller chip fails to decode using the hard-decision NMS decoding algorithm, it will execute the next level of decoding algorithm.

[0046] S104, the controller chip performs decoding based on the soft-decision NMS decoding algorithm.

[0047] The controller chip performs decoding based on the soft-decision NMS decoding algorithm. After successful decoding, the controller chip will output the correct stored data, and the decoding will end.

[0048] If the controller chip fails to decode using the soft-decision NMS decoding algorithm, the decoding process ends, and the controller chip cannot recover the correct stored data.

[0049] The aforementioned multi-level decoding algorithm addresses the low error probability of NAND media in its initial stages of use. To improve throughput, the controller chip prioritizes bit-flip decoding, which offers extremely fast decoding speed but limited error correction capabilities. As the number of erase / write cycles increases and charge leakage occurs in cells during data storage, the error probability of the NAND media grows. At this point, the likelihood of bit-flip decoding failure also increases, making it impossible to recover the correct stored data. To extend the lifespan of the SSD, the controller chip will activate a hard-decision NMS decoding algorithm with stronger error correction capabilities but longer decoding latency, eventually transitioning to a soft-decision NMS decoding algorithm.

[0050] Therefore, the read speed of an SSD mainly depends on the bit-flip decoding algorithm, i.e., improving the decoding speed of the bit-flip decoding algorithm. The lifespan of an SSD mainly depends on extending the time between the bit-flip decoding algorithm and the hard-decision NMS decoding algorithm and the soft-decision NMS decoding algorithm, i.e., improving the error correction capability of the bit-flip decoding algorithm. The stronger the error correction capability of the bit-flip decoding algorithm, the less time is spent using the hard-decision NMS decoding algorithm and the soft-decision NMS decoding algorithm, and the longer the lifespan of the SSD.

[0051] Bit-flipping decoding algorithms can be based on gradient descent bit-flipping (GDBF) algorithms.

[0052] The implementation principle of the GDBF algorithm will be introduced next.

[0053] Figure 2 An exemplary schematic diagram of the GDBF algorithm is shown.

[0054] The GDBF algorithm includes the following steps:

[0055] S201, The controller chip reads the stored data r from the NAND flash memory.

[0056] First, the controller chip reads the stored data r. The stored data r can be a bit sequence of length n, and can be represented as (r0, r1, r2, r3, r4, r5, ..., rn-1).

[0057] S202, the controller chip calculates the corrector Si based on the stored data r and the parity matrix H.

[0058] S203, is the corrector Si all zeros?

[0059] If yes, execute S204. The decoding was correct this time, and the stored data r is output. If no, execute S205.

[0060] S205, has the maximum number of iterations been reached?

[0061] If yes, then execute S206; the decoding failed and the decoding process ends. If no, then execute S207.

[0062] The following section explains how the controller chip calculates the corrector Si.

[0063] The controller chip obtains the parity check matrix H of the stored data. The parity check matrix is ​​an m x n matrix, and its elements are either 0 or 1. The length of the parity check matrix H is the same as the length of the stored data r. The parity check matrix H is a sparse matrix, meaning the number of non-zero elements is much smaller than the number of zero elements. The correct stored data c satisfies H*cT = 0. However, after transmission through the channel, the correct bit sequence c is susceptible to noise and other interference, easily resulting in bit errors. Therefore, the received information is r. Thus, H*rT = 0 no longer holds. Decoding is needed to find and correct the errors in r until H*rT = 0 is satisfied or the maximum set number of iterations is reached. The value of H*rT can be understood as the corrector.

[0064] The set of positions containing element 1 in the i-th row of the parity-check matrix can be represented as C(i), and the degree of C(i) can be represented as d. ci d ci This represents the number of elements that are 1 in the i-th row. The set of positions containing elements 1 in the j-th column of the parity-check matrix can be represented as V(j), and the degree of V(j) can be represented as d. vj dvj This represents the number of elements that are 1 in the j-th column.

[0065] In one possible implementation, the controller chip can calculate the corrector of the stored data r and determine whether all values ​​of the corrector are 0. If all values ​​of the corrector are 0, the decoding is correct, and the controller chip outputs the correct decoding information. If the values ​​of the corrector are not all 0, the decoding is incorrect. If a decoding error occurs, the controller chip needs to identify the bit with the decoding error and flip it. Specifically, the flipping method is as follows: if the value of the bit is 0, then change 0 to 1; if the value of the bit is 1, then change 1 to 0.

[0066] The controller chip can calculate the corrector for each bit in the stored data r based on the test matrix H and the stored data r.

[0067] The formula for calculating the calibrator is shown in formula (1).

[0068]

[0069] As shown in formula (1), Si represents the value of the corrector of the i-th bit in the stored data r, and Si can be either 0 or 1. Based on formula (1), the controller chip can calculate the corrector of each bit in the stored data r, and the corrector of the stored data r can be represented as S(S0, S1, S2, S3, S4...Sm-1). In the first calculation process, equals r j .

[0070] If S is all 0s, the decoding is correct, and the controller chip outputs the decoding information. If S is not all 0s, the decoding is incorrect, and the controller chip needs to determine the location of the decoding error.

[0071] S207. The controller chip calculates the number of bits that do not satisfy the check equation and determines the bit with the most non-satisfactions.

[0072] S208, the controller chip will flip the bit with the most non-compliant check equations.

[0073] In the event of a decoding error, the controller chip needs to determine the location of the error. The location of the decoding error is the bit with the most non-compliant check equations.

[0074] The controller chip can determine the location of decoding errors based on the stored data r and the corrector. The controller chip can calculate the energy of each bit j, and can determine the energy value of each bit based on formula (1). The energy value of each bit can also be referred to as the number of times each bit does not satisfy the check equation.

[0075]

[0076] As shown in formula (2), E j The energy of bit j is represented by the symbol. This represents the XOR operation. The energy of bit j can be understood as the number of times bit j fails to satisfy the parity check equation. The more times a bit fails to satisfy the parity check equation, the higher its unreliability; the fewer times bit j fails to satisfy the parity check equation, the lower its unreliability.

[0077] After determining the number of bits j that do not satisfy the parity check equation, the controller chip identifies the bit j with the most non-satisfactions. Then, the controller chip flips this bit based on formula (3).

[0078]

[0079] As shown in formula (3), after determining the bit j that does not satisfy the check equation the most, the controller chip flips the bit. That is, if the value of the bit is 1, the value of the bit is flipped from 1 to 0. If the value of the bit is 0, the value of the bit is flipped from 1 to 1.

[0080] Based on S202-S208 above, the location of the decoding error is determined. The decoding process continues until the maximum number of iterations is reached, at which point it exits, indicating a decoding failure. Alternatively, if the value of the corrector is all 0, it indicates that the decoding is correct, the decoding is successful, and the process ends, with the controller chip outputting the correct decoding result.

[0081] Next, we will use specific examples to explain in detail the principles of how to calculate the corrector and how to calculate the number of bits that do not satisfy the check equation, as described in the above embodiments, so as to make it easier to understand the subsequent embodiments.

[0082] First, the controller chip reads the stored data r, which can be a bit sequence of length n. Then, the low-density parity check (LDPC) decoder can use the bit sequence as information from the 0th variable node to the check node, or the LDPC decoder can determine the information from the 0th variable node to the check node based on the bit sequence.

[0083] During the iteration process, based on the Tanner diagram, the LDPC decoder can first update each check node. Updating a check node can be done by iterating through it, which involves obtaining information passed from the iterating check node to the variable node. Then, based on the iteration results of the check nodes, each variable node is updated. Updating a variable node can also be done by iterating through it, which involves obtaining information passed from the iterating variable node to the check node. The check node is then updated based on the updated variable node results, and the updated check node results are used to update the variable nodes again. This process is repeated multiple times until the iteration termination condition is met.

[0084] After each update of the check node and / or variable node, the LDPC decoder can use the updated variable node and / or updated check node to determine the iteration termination condition. If the updated variable node and / or updated check node determine that the iteration termination condition is met (e.g., the corrector is all zeros), the decoding process ends, and the decoding result is determined from the variable node and check node of the last iteration. If the updated variable node and / or updated check node do not meet the iteration termination condition, the next iteration process begins, until the maximum number of iterations is reached.

[0085] Tanner proposed the concept of using a graph model to describe codewords, thus mapping the parity-check matrix of LDPC codes to a bipartite graph called the Tanner graph. LDPC codes constructed using the Tanner graph can significantly reduce decoding complexity through parallel decoding.

[0086] Tanner graphs are bidirectional graphs used to represent LDPC codes. A Tanner graph contains two types of vertices: n codeword bit nodes (also called bit nodes), corresponding to the columns of the parity-check matrix; and m parity-check equation vertices (also called parity nodes), corresponding to the rows of the parity-check matrix. A Tanner graph can represent the parity-check matrix of an LDPC code, where each row represents a parity-check equation and each column represents a codeword bit. Elements of 1 in the parity-check matrix indicate the existence of an edge connecting a bit node and a parity node in the Tanner graph. This edge is called an adjacent edge between the two nodes, and the nodes at both ends of an adjacent edge are called adjacent nodes. The number of adjacent edges for each node is called its degree.

[0087] For example, storing data (Also known as a bit sequence) The sequence can be represented as (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9). Assume the bit sequence... Specifically, (1,0,0,0,0,0,0,0,0,0), and the parity check matrix H of the LDPC code is shown in formula (4):

[0088]

[0089] The bit sequence r must satisfy the linear equation system H*rT=0. After transmission through the channel, the bit sequence r=(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9) received by the LDPC decoder may contain errors. Therefore, H*rT=0 no longer holds, and it is necessary to find and correct the locations of the errors using the decoding method. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of a Tanner diagram provided in an embodiment of this application. From Figure 3 As can be seen, X0, X1, ..., X9 are called variable nodes, representing 10 bits, which are the unknown variables to be solved by the decoder. f0, f1, f2, f3, and f4 in the diagram are called check nodes, representing each check equation in the thread equation set. Elements of "1" in the check matrix H represent the connections between variable nodes and check nodes in the Tanner diagram.

[0090] The decoding iteration process involves transmitting information between variable nodes and check nodes. In the Tanner graph, information can be transmitted between variable nodes and check nodes when there is a connection between them. The LDPC decoder can use the bit sequence Y as the information from the 0th variable node to the check node, or the LDPC can determine the information from the 0th variable node to the check node based on the bit sequence Y. That is, for check node f0, it can receive information transmitted from variable nodes X0, X1, X2, X5, X6, and X9. Similarly, for check node f1, it can receive information from variable nodes X0, X2, X4, X5, X7, and X8; for check node f2, it can receive information from variable nodes X2, X3, X4, X6, X8, and X9; for check node f3, it can receive information from variable nodes X1, X3, X4, X5, X7, and X9; and for check node f4, it can receive information from variable nodes X0, X1, X3, X6, X7, and X8. Each check node processes the received information and then passes the processed information to its neighboring variable nodes. That is, variable node X0 can receive information from verification nodes f0, f1, and f4; variable node X1 can receive information from verification nodes f0, f3, and f4; variable node X2 can receive information from verification nodes f0, f1, and f2; variable node X3 can receive information from verification nodes f2, f3, and f4; variable node X4 can receive information from verification nodes f1, f2, and f3; variable node X5 can receive information from verification nodes f0, f1, and f3; variable node X6 can receive information from verification nodes f0, f2, and f4; variable node X7 can receive information from verification nodes f1, f3, and f4; variable node X8 can receive information from verification nodes f1, f2, and f4; and variable node X9 can receive information from verification nodes f0, f2, and f3. Each variable node then processes the received information. Finally, the processed information is decoded. If the corrector of the bit sequence is all 0, the decoding ends. Otherwise, the decoding is repeated multiple times until the maximum number of iterations is reached.

[0091] Next, combining the verification equation shown in formula (4) and the bit sequence r, we will introduce how the controller chip calculates the number of bits that do not satisfy the verification equation and the corrector.

[0092] As shown in the verification equation (4), based on the verification equation (4), the set of positions of element 1 in the 0th row of the verification matrix H can be represented as C(0)={0,1,2,5,6,9}.

[0093] The set of positions of element 1 in the first row of the parity check matrix H can be represented as C(1) = {0, 2, 4, 5, 7, 8}.

[0094] The set of positions of element 1 in the second row of the parity matrix H can be represented as C(2) = {2,3,4,6,8,9}.

[0095] The set of positions of element 1 in the 3rd row of the parity check matrix H can be represented as C(3) = {1, 3, 4, 5, 7, 9}.

[0096] The set of positions of element 1 in the 4th row of the parity check matrix H can be represented as C(4) = {0, 1, 3, 6, 7, 8}.

[0097] In C(0), C(1), C(2), C(3), and C(4), each number represents the position of element 1 in each row of the parity check matrix H.

[0098] Based on C(0), C(1), C(2), C(3) and C(4), the number of 1s in each row of the parity check matrix H can be obtained, which is the degree of C(i). The degree of C(i) can be represented as d ci.

[0099] Where, d c(0) =d c(1) =d c(2) =d c(3) =d c(4) =6.

[0100] As shown in the verification equation (4), based on the verification equation (4), the set of positions of element 1 in column 0 of the verification matrix H can be represented as V(0)={0,1,4}.

[0101] The set of positions of element 1 in the first column of the parity matrix H can be represented as V(1)={0,3,4}.

[0102] The set of positions of element 1 in the second column of the parity matrix H can be represented as V(2)={0,1,2}.

[0103] The set of positions of element 1 in the 3rd column of the verification matrix H can be represented as V(3)={2,3,4}.

[0104] The set of positions of element 1 in the 4th column of the parity matrix H can be represented as V(4)={1,2,3}.

[0105] The set of positions of element 1 in the 5th column of the parity matrix H can be represented as V(5) = {0, 1, 3}.

[0106] The set of positions of element 1 in the 6th column of the parity matrix H can be represented as V(6)={0,2,4}.

[0107] The set of positions of element 1 in the 7th column of the parity matrix H can be represented as V(7)={0,3,4}.

[0108] The set of positions of element 1 in the 8th column of the parity matrix H can be represented as V(8)={1,2,4}.

[0109] The set of positions of element 1 in the 9th column of the parity matrix H can be represented as V(9)={0,2,3}.

[0110] In V(0), V(1), V(2), V(3), V(4), V(5), V(6), V(7), V(8), V(9), each number represents the position of element 1 in each column of the check matrix H.

[0111] Based on V(0), V(1), V(2), V(3), V(4), V(5), V(6), V(7), V(8), and V(9), the number of 1s in each column of the parity check matrix H can be obtained, which is the degree of V(j). The degree of V(j) can be expressed as d. vj Among them, d vj It can also represent the maximum number of bits that do not satisfy the check equation.

[0112] Where, d v(0) =d v(1) =d v(2) =d v(3) =d v(4) =d v(5) =d v(6) =d v(7) =d v(8) =d v(9) =3. Therefore, the bit sequence... The maximum number of bits that do not satisfy the parity check equation is 3.

[0113] Assuming a bit sequence Based on the check equation H and bit sequence shown in formula (4) Through formula The corrector S can be obtained either by formula (1).

[0114] Next, we will explain how the controller chip obtains the corrector S using formula (1).

[0115]

[0116]

[0117]

[0118]

[0119]

[0120] It is possible to obtain the parity check matrix H and the bit sequence. The corrector S is obtained as (11001). Since the corrector S is not all zeros, the bit sequence is... If there are erroneous bits, the controller chip needs to find the bit sequence. The position of the erroneous bit is determined, and the erroneous bit is flipped.

[0121] The method for confirming the location of erroneous bits is as follows: The controller chip calculates the number of bits that do not meet the check equation for each bit. The bit with the most bits that do not meet the check equation is the erroneous bit. Based on the check equation H shown in formula (4), the number of elements 1 in each column can be determined as the maximum number of bits that do not meet the check equation for each bit. It can be seen that the maximum number of bits that do not meet the check equation for each bit is 3 or 4. However, in actual calculations, the number of bits that do not meet the check equation for each bit is less than or equal to 3 or less than or equal to 4.

[0122] The controller chip can calculate the number of bits that do not meet the test equation based on the aforementioned formula (2).

[0123] The number of bits that do not satisfy the test equation is:

[0124] The number of bits that do not satisfy the test equation is:

[0125] The number of bits that do not satisfy the test equation is:

[0126] The number of bits that do not satisfy the test equation is:

[0127] The number of bits that do not satisfy the test equation is:

[0128] The number of bits that do not satisfy the test equation is:

[0129] The number of bits that do not satisfy the test equation is:

[0130] The number of bits that do not satisfy the test equation is:

[0131] The number of bits that do not satisfy the test equation is:

[0132] The number of bits that do not satisfy the test equation is:

[0133] From E0 to E9, it can be seen that the maximum value is E0, meaning that the 0th bit has the most errors. The controller chip can determine that the 0th bit is the bit where the error occurred. The controller chip can flip the 0th bit according to formula (3) to obtain the flipped bit sequence, that is, change the 0th bit from "1" to "0". The flipped bit sequence can be represented as follows:

[0134] Based on the parity-check matrix S shown in formula (4) and the flipped bit sequence Calculate the corrector again. If the corrector is all zeros, the decoding is correct, and the flipped bit sequence is output. If the bit sequence is not all zeros, then the flipped bit sequence can be calculated using the steps described above. In this process, if each bit does not meet the required number of check squares, the erroneous bit is identified. Based on this method, if the corrector is all 0s in a certain iteration, the decoding is correct, and the flipped bit sequence is output. If, in subsequent iterations, the corrector is not all 0s and the maximum number of iterations has been reached, the decoding ends, and the decoding fails.

[0135] Based on the foregoing analysis, we can obtain Figure 2 The GDBF algorithm shown has the following drawbacks:

[0136] Defect 1: such as Figure 4As shown, the GDBF algorithm may fall into an infinite loop until it reaches the maximum number of iterations, leading to decoding failure. Specifically, the controller chip might flip two correct bits and two incorrect bits during a single bit flip. In the next bit flip, the controller chip might flip the two correct bits again and the two incorrect bits again. This process continues indefinitely, potentially causing the controller chip to repeatedly flip the two correct bits and the two incorrect bits, ultimately resulting in decoding failure.

[0137] Defect 2: When an infinite loop as shown in Defect 1 occurs again, the GDBF algorithm has a high error level, and as the raw bit error rate (RBER) decreases, the uncorrectable bit error rate (UBER) cannot be significantly improved.

[0138] Defect 3: Figure 2 The illustrated GDBF algorithm requires calculating the number of bits that do not satisfy the parity check equation before identifying the potentially erroneous bits based on the bit with the highest number of non-parity check equations, and then flipping the potentially erroneous bits. In other words, calculating the number of bits that satisfy the parity check equation and the bit flipping process cannot be performed simultaneously, resulting in high decoding latency and reduced throughput.

[0139] Based on the above analysis, the embodiments of this application mainly target the first-level decoding, namely the bit-flipping decoding algorithm. By optimizing the bit-flipping decoding algorithm, a high-performance, high-throughput bit-flipping decoding algorithm is provided to improve the lifespan of SSD devices.

[0140] The optimized bit-flipping decoding algorithm mainly includes the following improvements:

[0141] Improvement 1: The algorithm for the controller chip to calculate the number of bits that do not satisfy the parity check equation has been optimized, reducing the probability of correct bits being incorrectly flipped, thereby reducing the error level of the decoding.

[0142] Improvement 2: Introducing a threshold judgment mechanism allows the controller chip to simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput.

[0143] Improvement 3: A random sequence generator is proposed, which assigns a certain probability constraint to bits that meet the flip condition for flipping. This reduces the occurrence of the same bit getting stuck in an infinite loop due to repeated flipping. It also reduces the decoding latency of the controller chip and improves the decoding throughput.

[0144] The specific details of Improvement 1, Improvement 2 and Improvement 3 will be described in detail in the subsequent embodiments, and will not be repeated here in the embodiments of this application.

[0145] This invention is applied to various NAND-based SSD storage systems. The solution provided by this invention serves the data error correction module on the SSD controller chip, ensuring the reliability of the stored information reading process and extending the lifespan of the storage device. This solution is applicable to SSD products that use low-density parity check (LDPC) codes as error correction codes. These products include, but are not limited to, computer equipment, mobile terminals, high-performance servers, and data centers. High-performance server products may include those used in OceanStor Dorado storage, OceanStor 5000F storage, and other server products.

[0146] Figure 5 An SSD storage system using NAND media is illustrated by way of example according to an embodiment of this application.

[0147] This system includes, but is not limited to, the host, host interface, SSD controller, SSD NAND interface, and multiple NAND chips.

[0148] NAND flash memory is a type of storage medium, specifically a non-volatile memory.

[0149] The SSD NAND interface is used to read or write data from NAND flash memory chips.

[0150] The SSD controller, also known as the master controller chip or master controller, is mainly used to read or write data from NAND flash memory chips by controlling the SSD NAND interface.

[0151] The user (host) is used to read or write data through the SSD controller.

[0152] like Figure 5 As shown, users can exchange commands and transfer data with the SSD controller via the Host interface, while the SSD controller handles read and write operations on the NAND flash memory chips via the SSD NAND interface. In other words, users can read data from the NAND flash memory chips through the Host interface, SSD controller, and SSD NAND interface. Users can also write data to the NAND flash memory chips through the same three interfaces.

[0153] Figure 6 An exemplary diagram illustrating the error correction process of an SSD controller chip is shown.

[0154] The SSD controller chip reads data from the NAND flash memory chip via the SSD NAND interface. This read data may be erroneous. Therefore, to output correct data to the user, the SSD controller chip needs to decode the data using a NAND error correcting code (NAND ECC) module to recover the correct data. How the SSD controller chip performs error correction and recovers the correct data will be described in detail in subsequent embodiments; this application's embodiments will not elaborate on it here.

[0155] In the following embodiments of this application, the SSD controller chip may also be referred to simply as the controller chip.

[0156] The following describes the LDPC code decoding method provided in the embodiments of this application.

[0157] Figure 7 This is a schematic diagram of an LDPC code decoding method provided in an embodiment of this application.

[0158] S701, the controller chip reads the stored data r from the NAND flash memory chip, and...

[0159] First, the controller chip reads stored data r from the NAND flash memory. Stored data r can be a bit sequence of length n, also referred to as bit sequence r, which can be represented as (r0, r1, r2, r3, r4, r5, ..., rn-1). The controller chip obtains the parity check matrix H of the stored data. The parity check matrix is ​​an m x n matrix, and its elements are either 0 or 1. The parity check matrix H is a sparse matrix, meaning the number of non-zero elements is much smaller than the number of zero elements. Correct data c satisfies H*cT = 0. After transmission through the channel, the bit sequence r is susceptible to noise and other interference, making it prone to bit errors. Therefore, the received information is... So, This will no longer hold true. Decoding is needed to identify the errors present in r.

[0160] Before the first iteration, let the bit sequence

[0161] S702, controller chip based on stored data The corrector Si is calculated using the check matrix H, and the threshold T is determined based on the check matrix.

[0162] Based on the parity-check matrix H, the controller chip can determine the maximum number of bits that do not satisfy the parity-check equation. In other words, the number of 1s in each column of the parity-check matrix H represents the maximum number of bits that do not satisfy the parity-check equation. This can also be referred to as the maximum degree of each bit. Each bit can also be called a variable node, therefore, the maximum number of variable nodes that do not satisfy the parity-check equation, or the maximum degree of a variable node, can also be referred to.

[0163]

[0164] As shown in formula (5), T represents the maximum number of bits that do not satisfy the parity check equation. vj The degree of the j-th bit represents the maximum number of bits that do not satisfy the parity check equation, or the number of 1s in the j-th column of the parity check matrix H. After obtaining the degree of each bit, the controller chip selects the maximum degree as the threshold T. The threshold T is used by the controller chip to compare the actual number of bits that do not satisfy the parity check equation with the threshold T. If the actual number of bits that do not satisfy the parity check equation is greater than or equal to the threshold T, then the bit is an erroneous bit. If the actual number of bits that do not satisfy the parity check equation is less than the threshold T, then the bit is a correct bit.

[0165] Secondly, the controller chip also needs to be based on stored data The checksum matrix H is used to calculate the corrector Si. This relates to how the controller chip uses stored data... The corrector Si is calculated from the parity check matrix H. Please refer to the relevant descriptions in the foregoing embodiments. The embodiments of this application will not be repeated here.

[0166] S703, is the corrector Si all zeros?

[0167] If yes, then execute S704. If the decoding is correct, output the stored data. No, then execute S705.

[0168] S705, has the maximum number of iterations been reached?

[0169] If yes, then execute S706; the decoding failed, and the decoding process ends. If no, then execute S707.

[0170] The S707 controller chip calculates the number of bits that do not satisfy the parity check equation and performs bit flipping. And update Ej 1 =d vj +1-E j .

[0171] After the controller chip determines that the corrector Si is not all zeros, it needs to calculate the number of bits that do not meet the check equation. It then compares this number with a threshold T. If the number of bits that do not meet the check equation is less than the threshold T, the bit is considered correct. If the number of bits that do not meet the check equation is greater than or equal to the threshold T, the bit is considered incorrect and needs to be flipped.

[0172] During the first iteration, the controller chip can calculate the number of bits that do not meet the test equation based on formula (6).

[0173]

[0174] As shown in formula (6), the difference between formula (6) and formula (2) is that formula (6) increases the number of bits that do not satisfy the test equation by adding R(lj), where R(lj) is less than or equal to 0, and the intermediate variable l j The cumulative number of iterations used to record the impact of bit flips is L, which is a preset value. In some embodiments, R(lj) can also be called a regularization term. If bit j flips, then l is updated in the next calculation of the number of times that bit does not satisfy the test equation. j =L, that is, in calculating the bit E j When R(L) is added, R(L) < 0, reducing the number of bits that do not satisfy the test equation; if bit j is not flipped, then when calculating the number of bits that do not satisfy the test equation in the next iteration, l is updated. j =max(l j -1,0). Where, 0=R(0)>R(1)>=R(2)>=R(3)…>=R(L).

[0175] In some embodiments, the method for calculating the number of optimized bits that do not satisfy the parity equation and the parallel operation implementation of the bit error correction algorithm provided in this application can be called the Regular Term Bit Flipping (RTBF) algorithm.

[0176] For example, L = 2.

[0177] For example, in the first calculation, the number of bits j that do not satisfy the test equation (i.e., obtaining E) j1 After that, if E is determined j1 If the value is greater than or equal to the threshold T1, then bit j needs to be flipped. After bit j is flipped once, when calculating the number of bits that do not satisfy the test equation for the second time, E j2 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j1If the value is less than the threshold T1, then bit j does not need to be flipped. Therefore, when calculating the number of bits that do not satisfy the test equation for the second time, E... j2 In the equation, R(lj) = R(0), R(0) = 0.

[0178] In the second calculation, the number of bits j that do not satisfy the test equation is obtained (i.e., E is obtained). j2 After that, if bit j has already been flipped once, and E is determined... j2 If the value is greater than or equal to the threshold T2, then bit j needs to be flipped. After bit j has been flipped twice, when calculating the number of bits that do not satisfy the test equation for the third time, E j3 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j3 If the value is less than the threshold T2, then bit j does not need to be flipped. Therefore, when calculating the number of bits that do not satisfy the test equation for the third time, E... j3 Among them, R(lj)=R(L-1)=R(1), 0>R(1)>=R(2).

[0179] If E is determined without bit j being flipped. j2 If the value is greater than or equal to the threshold T2, then bit j needs to be flipped. After bit j is flipped once, when calculating the number of bits that do not satisfy the test equation for the third time, E j3 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j2 If the value is less than the threshold T2, then bit j does not need to be flipped. Therefore, when calculating the number of bits that do not satisfy the test equation for the third time, E... j3 In the middle, R(lj) = R(0) = 0.

[0180] In the third calculation, the number of bits j that do not satisfy the test equation is obtained (i.e., E is obtained). j3 After that, if bit j has been flipped twice, and E is determined... j3 If the value is greater than or equal to the threshold T3, then bit j needs to be flipped. After bit j has been flipped three times, when calculating the number of bits that do not satisfy the test equation for the fourth time, E j4 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j3 If the value is less than the threshold T3, then bit j does not need to be flipped. Therefore, in the fourth calculation of the number of bits that do not satisfy the test equation, E... j4 Among them, R(lj)=R(L-1)=R(1), 0>R(1)>=R(2).

[0181] After bit j has been flipped once and not flipped once, if E is determined... j3If the value is greater than or equal to the threshold T3, then bit j needs to be flipped. After bit j is flipped again, when calculating the number of bits that do not satisfy the test equation for the fourth time, E j4 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j3 If the value is less than the threshold T3, then bit j does not need to be flipped. If bit j is not flipped twice consecutively, then when calculating the number of times the bit does not satisfy the test equation for the fourth time, E... j4 Among them, R(lj)=R(1-1)=R(0)=0.

[0182] In the third calculation, the number of bits j that do not satisfy the test equation is obtained (i.e., E is obtained). j3 After that, after bit j has not been flipped once and after it has been flipped once, if E is determined... j3 If the value is greater than or equal to the threshold T3, then bit j needs to be flipped. After bit j has been flipped twice consecutively, when calculating the number of bits that do not satisfy the test equation for the fourth time, E j4 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j3 If the value is less than the threshold T3, then bit j does not need to be flipped. Therefore, in the fourth calculation of the number of bits that do not satisfy the test equation, E... j4 Among them, R(lj)=R(L-1)=R(1), 0>R(1)>=R(2).

[0183] If E is determined without bit j being flipped. j3 If the value is greater than or equal to the threshold T3, then bit j needs to be flipped. After bit j is flipped once, when calculating the number of bits that do not satisfy the test equation for the fourth time, E j4 In the equation R(lj) = R(L) = R(2), R(2) < 0. If E is determined... j3 If the value is less than the threshold T3, then bit j does not need to be flipped. Therefore, in the fourth calculation of the number of bits that do not satisfy the test equation, E... j4 In the middle, R(lj) = R(0) = 0.

[0184] It should be noted that the threshold T is updated in each of the above iterations. For details, please refer to the relevant descriptions in the subsequent embodiments.

[0185] If the bits are flipped, update l. j If bit j is flipped, then in the next L iterations, a non-positive number is added to the calculation of the number of flipped bits that do not satisfy the test equation. This may reduce the number of bits j that do not satisfy the test equation, thus decreasing the probability that bit j is repeatedly flipped. If the bit is not flipped, then update l. j =max(lj If R(lj) = [0 = R(0) > R(1) ≥ … ≥ R(L)], then the number of bits that do not satisfy the check equation will gradually increase, which can prevent the situation where the erroneous bits are not flipped.

[0186] Similarly, if the current bit is flipped, then in the next L iterations, the number of times this bit does not satisfy the parity check equation will be incremented by a value less than 0. Therefore, the corresponding E for this bit will be... j This means the number of bits that do not satisfy the check equation decreases. After the bit stops flipping, the number of bits that do not satisfy the check equation is incremented by a value less than 0, and this value gradually increases until the incremented value (or regularization term) is 0.

[0187] As can be seen from the above process, when the current bit is flipped, in the next L iterations, the number of times this bit does not satisfy the parity check equation will be increased by a value less than 0. Therefore, the corresponding E for this bit... j This means the number of bits that do not satisfy the test equation is reduced.

[0188] In this way, when calculating the number of bits that do not satisfy the test equation, if bit j is flipped, then in the next L iterations, a non-positive number is added to the calculation of the number of flipped bits that do not satisfy the test equation. The number of bits that do not satisfy the test equation may decrease, and the probability of bit j being flipped repeatedly is also reduced. In this way, the probability of bits being flipped repeatedly can be reduced, achieving the effect of fine-grained control over bit flipping.

[0189] Furthermore, as can be seen from S702 and S707, the threshold T is calculated before the controller chip calculates the number of bits that do not meet the check equation. Therefore, the controller chip can simultaneously calculate the number of bits that do not meet the check equation and determine whether to flip multiple bits based on the relationship between the number of bits that do not meet the check equation and the threshold T. That is, for multiple different bits, the calculation process of the number of bits that do not meet the check equation and the bit flipping process can be performed synchronously. Compared with the previous embodiment, the controller chip does not need to calculate the number of bits that do not meet the check equation separately and then determine which bits to flip based on the number of bits that do not meet the check equation, which improves the error correction efficiency of the controller chip, reduces decoding latency, and improves decoding efficiency.

[0190] In the first iteration, the controller chip obtains the number of bits that do not satisfy the test equation based on formula (6). If the number of bits that do not satisfy the test equation is greater than or equal to the threshold T1, the controller chip then calculates the number of bits that do not satisfy the test equation based on formula (6). Flip the bit to obtain the flipped bit sequence.

[0191] After obtaining the flipped bit sequence, the number of bits that do not satisfy the test equation also changes. Therefore, the controller chip needs to update the number of bits that do not satisfy the test equation after the flip so that the threshold T can be updated subsequently.

[0192] After the first iteration, the controller chip can update the number of bits that do not meet the check equation based on formula (7), that is, update the number of bits that do not meet the check equation after the flip.

[0193] E j 1 =d vj +1-E j Formula (7)

[0194] As shown in formula (4), E j 1 This indicates the number of bits that do not satisfy the test equation after the flip. E j This represents the number of bits that do not satisfy the test equation before the flip. The controller chip can obtain the number of bits that do not satisfy the test equation after the flip based on the number of bits that do not satisfy the test equation before the flip and the maximum degree of each bit. It should be noted that formula (7) is the number of bits that do not satisfy the test equation after the flip estimated by the controller chip so that the controller chip can update the threshold T.

[0195] S708, Controller chip update threshold T, where T2 = max{maxE j maxE j 1}

[0196] After a bit flip, the number of times the j-th bit fails to satisfy the test equation may be greater than or equal to the number of times the j-th bit fails to satisfy the test equation before the bit flip. Therefore, the controller chip needs to find the maximum value between the number of times each bit fails to satisfy the test equation before and after the bit flip, and use this maximum value as the updated value of the threshold T, i.e., threshold T2, where threshold T2 = max{maxE} j maxE j 1}

[0197] After the controller chip updates the threshold T to obtain the threshold T2, it continues to execute S702. In the second iteration, the controller chip only needs to calculate the corrector Si based on the flipped bit data and the test matrix H. It no longer needs to determine the threshold T2 based on the test matrix H, as the threshold T2 has already been calculated after the bit flip.

[0198] The subsequent error correction process can be referred to the descriptions in S703-S707 above, until the corrector is all 0, then the correct decoding result is output. Alternatively, if the maximum number of iterations is reached, the decoding fails.

[0199] Optionally, in some embodiments, the controller chip may also execute S709, which includes the following.

[0200] The controller chip is based on a random sequence generator. For bits that meet the flip condition, the controller chip restricts the flipping of the bit with a certain probability. Its main function is to further mitigate the occurrence of repeated flipping of the same bit, thereby effectively reducing the error level.

[0201] Specifically, the controller chip is based on a random sequence generator and a preset probability value p, where p is the probability of a 0 appearing in the 0-1 sequence. When the random sequence generator outputs 0, the bits that satisfy the flip condition are not flipped. When the random sequence generator outputs 1, the bits that satisfy the flip condition are flipped. The number of elements 0 and 1 in the 0-1 sequence is the same as the number of bits that satisfy the flip condition.

[0202] For example, in a bit series with 10 bits, the controller chip determines that bits 0, 3, 4, 5, 7, and 9 out of the 10 bits satisfy the flip condition, meaning a total of 6 bits satisfy the flip condition. Based on a random sequence generator and a preset probability value (e.g., 50%), the controller chip determines that only 3 of these 6 bits need to be flipped. The random sequence generator generates 6 sequences of numbers containing 0-1, where each sequence contains 3 zeros and 3 ones. When the random sequence generator outputs a 0, the controller chip prevents the bits that currently satisfy the flip condition from flipping. When the random sequence generator outputs a 1, the controller chip flips the bits that currently satisfy the flip condition.

[0203] like Figure 8 As shown, Figure 8 An exemplary diagram is shown of a sequence of 0-1 numbers generated by a random sequence generator.

[0204] Figure 8As shown, when the random sequence generator outputs its first 0, the controller chip prevents the 0th bit, which satisfies the flip condition, from flipping. When the random sequence generator outputs its first 1, the controller chip flips the 3rd bit, which satisfies the flip condition. When the random sequence generator outputs its second 0, the controller chip prevents the 4th bit, which satisfies the flip condition, from flipping. When the random sequence generator outputs its third 0, the controller chip prevents the 5th bit, which satisfies the flip condition, from flipping. When the random sequence generator outputs its second 1, the controller chip flips the 7th bit, which satisfies the flip condition. When the random sequence generator outputs its third 1, the controller chip flips the 9th bit, which satisfies the flip condition.

[0205] In this way, the controller chip can control the number of bit flips that meet the flip condition, use a random sequence generator to reduce the influence of the trap set, and implement a hardware-friendly generator using a 0-1 proportional sequence.

[0206] In some embodiments, the probabilistic bit flipping algorithm provided by this application based on the RTBF algorithm can be referred to as the Regular Term Probabilistic Bit Flipping (RTPBF) algorithm.

[0207] The embodiments of this application focus on the first-level decoding scheme of the SSD controller chip. By combining the optimization of the calculation method for the number of bits that do not satisfy the parity equation, parallel operation, and random flipping mechanism, the error correction capability of bit flipping decoding and the throughput of the overall scheme are effectively improved, and the service life of the SSD storage device is extended.

[0208] Table 1 compares the error correction capabilities of the GDBF, RTPF, and RTPBF algorithms under different RBER values.

[0209] Table 1

[0210] RBER 0.005 0.0045 0.004 0.0035 0.003 0.0025 0.002 GDBF 5.39E-06 9.37E-07 1.08E-07 1.05E-08 4.81E-09 1.60E-09 5.62E-10 RTBF 5.90E-06 1.15E-06 7.20E-08 1.88E-09 2.74E-11 3.49E-12 1.32E-12 RTPBF 5.90E-06 1.11E-06 6.71E-08 2.04E-09 1.50E-11 9.60E-13 1.80E-13

[0211] As shown in Table 1, the existing GDBF algorithm exhibits a significant error floor phenomenon as RBER decreases. The RTBF and RTPBF algorithms proposed in this application reduce the error floor by two orders of magnitude (100 times) and three orders of magnitude (1000 times) respectively when RBER = 0.002, thereby reducing the proportion of the controller chip entering the second / third stage of decoding with longer delays.

[0212] Table 2 compares the average number of iterations for error correction of the GDBF, RTPF, and RTPBF algorithms under different RBERs.

[0213] Table 2

[0214] RBER 0.005 0.0045 0.004 0.0035 0.003 0.0025 0.002 GDBF 23.64 15.73 11.57 8.97 7.17 5.806 4.689 RTBF 23.33 15.295 11.054 8.781 7.285 6.128 5.023 RTPBF 23.38 15.302 11.053 8.782 7.284 6.128 5.015

[0215] Table 2 compares the average number of error correction iterations for the GDBF, RTPF, and RTPBF algorithms under different RBERs. This application parallelizes the calculation of the number of bits that do not satisfy the parity check equation and the bit flipping process, thus doubling the overall throughput.

[0216] Consumer-grade SSD devices typically use LDPC codes with a quasi-cyclic block size of 256, a code length of 18944, an information dimension of 17152, and a code rate of 0.905. To meet the requirements of product throughput and lifespan, this embodiment of the invention employs a three-level decoding structure, such as... Figure 9 As shown. In the early stages of NAND flash memory usage, the read error rate (RBER) is low, and the controller chip will initiate RTBF decoding in this invention to provide high-speed data reading to the user. As the number of read / write operations on the NAND flash memory increases and the usage time lengthens, the read error rate will increase, and the proportion of RTBF decoding failures will also increase. At this point, the controller chip will initiate the second-level decoding—hard-decision NMS decoding. Since the second-level decoding does not require reading soft information, it provides a trade-off between error correction capability and decoding latency. If the second-level decoding fails, the controller chip needs to read soft information from the NAND flash memory and perform the first two levels of decoding again. If these two levels of decoding fail again, then soft-decision NMS decoding will be initiated, using a more precise and complex algorithm to correct errors and restore data to the user. However, the corresponding decoding latency will also increase. The final level of decoding is mainly to ensure the lifespan of the SSD device.

[0217] Figure 9 A schematic diagram of another multi-level decoding algorithm provided in an embodiment of this application.

[0218] For example, a multi-level decoding algorithm could be a first-level decoding algorithm using the RTBF algorithm, a second-level decoding algorithm using the hard-decision NMS algorithm, and a third-level decoding algorithm using the soft-decision NMS decoding algorithm.

[0219] S901, the controller chip reads stored data from NAND flash memory.

[0220] The S902 controller chip decodes based on a regular term bit-flipping algorithm or a regular term probabilistic bit-flipping algorithm.

[0221] The controller chip performs decoding based on either the RTBF or RTPBF algorithm. Upon successful decoding, the controller chip outputs the correct stored data, which is then transmitted to the host via the host interface. Decoding is complete.

[0222] If the controller chip fails to decode using the RTBF or RTPBF algorithm, it will execute the next level of decoding algorithm.

[0223] The S903 controller chip uses the hard-decision NMS algorithm for decoding.

[0224] Hard-decision NMS and RTBF (RTPBF) algorithms use the same data for decoding. Hard-decision NMS and RTBF / RTPBF algorithms, however, use different data for decoding than soft-decision NMS.

[0225] The controller chip performs decoding based on the hard-decision NMS algorithm. After successful decoding, the controller chip will output the correct stored data, that is, transmit the decoded stored data to the host through the host interface, and the decoding ends.

[0226] If the controller chip fails to decode using the hard-decision NMS algorithm, it will execute the next level of decoding algorithm. Simultaneously, the hard-decision NMS algorithm sends a read soft information command to the NAND flash memory chip.

[0227] After obtaining soft information from the NAND flash memory, the S904 controller chip decodes the information based on the soft-decision NMS algorithm.

[0228] The controller chip performs decoding based on the soft-decision NMS algorithm. After successful decoding, the decoded storage data is transmitted to the host through the host interface. The controller chip will then output the correct storage data, and the decoding process will end.

[0229] If the controller chip fails to decode using the soft-decision NMS algorithm, the decoding process ends, and the controller chip cannot recover the correct stored data.

[0230] Figure 10 This is a schematic diagram of a decoding method provided in an embodiment of this application.

[0231] S1001. Read the first bit sequence and obtain the verification matrix H of the first bit sequence, where the first bit sequence contains n bits of data.

[0232] S1002. Based on the first bit sequence and the test matrix H, the first corrector S1 is obtained. If the first corrector S1 is not all zeros, based on the first bit sequence and the first corrector S1, the first number of bits in the first bit sequence that do not satisfy the check equation in the test matrix H is determined. If the first number of bits in the first bit sequence that do not satisfy the check equation in the test matrix H is greater than or equal to the first threshold T1, the first bit sequence is flipped to obtain the second bit sequence.

[0233] In one possible implementation, while flipping the first bit data, the method further includes: if the fourth bit data in the first bit sequence does not satisfy the first number of check equations in the check matrix H that is greater than or equal to a first threshold T1, then the fourth bit data is flipped to obtain the second bit sequence. This threshold judgment mechanism allows the controller chip to simultaneously calculate the number of bits that do not satisfy the check equations and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput.

[0234] In one possible implementation, the first threshold T1 is determined based on the test matrix H.

[0235] In one possible implementation, flipping the first bit data specifically includes: obtaining a first digital sequence based on a first probability value and a first random sequence generator; wherein the number of elements in the first digital sequence is the same as the number of bits in the first bit sequence that are flipped, the elements in the first digital sequence are either 0 or 1, and the proportion of elements in the first digital sequence that are 1 is the first probability value; a random sequence generator is used to determine the position of the first bit data in the first bit sequence, and a certain probability constraint is assigned to flip bits that meet the flipping condition. This reduces the occurrence of the same bit getting stuck in an infinite loop due to repeated flipping. It also reduces the decoding latency of the controller chip and improves the decoding throughput. The first bit data is flipped when the element corresponding to the position in the first digital sequence is 1.

[0236] In one possible implementation, the first bit sequence is output when the first corrector S1 is all 0.

[0237] S1003. After obtaining the second bit sequence, based on the second bit sequence and the test matrix H, the second corrector S2 is obtained; if the second corrector S2 is not all zeros, based on the second bit sequence, the second corrector S2, and the first regularization term, the second number of bits in the second bit sequence that do not satisfy the check equation in the test matrix H is obtained, where the first regularization term is less than or equal to 0.

[0238] In one possible implementation, the first regularization term is less than 0 when the first bit of data is in the same position in the first bit sequence and the second bit of data is in the same position in the second bit sequence. This optimizes the algorithm for the controller chip to calculate the number of bits that do not satisfy the parity check equation, reducing the probability of correct bits being incorrectly flipped, and thus reducing the error level in the decoding.

[0239] Optionally, if the position of the first bit data in the first bit sequence is different from the position of the second bit data in the second bit sequence, the first regularization term is equal to 0.

[0240] In one possible implementation, the second bit sequence is output when the second corrector S2 is all 0.

[0241] S1004. If the second bit data in the second bit sequence does not satisfy the second quantity of the verification equation in the verification matrix H that is greater than or equal to the second threshold T2, the second bit data is flipped to obtain the third bit sequence. After obtaining the third bit sequence, the third corrector S3 is obtained based on the third bit sequence and the verification matrix H. If the third corrector S3 is all 0, the third bit sequence is output.

[0242] In one possible implementation, after obtaining the second bit sequence and before flipping the second bit data, the method further includes: obtaining a fourth number of bits that do not satisfy the check equations in the check matrix H based on a first number of bits that do not satisfy the check equations in the check matrix H and a preset maximum number of bits that do not satisfy the check equations in the check matrix H; the chip determines the maximum value between the first number of bits that do not satisfy the check equations in the check matrix H and the fourth number of bits that do not satisfy the check equations in the check matrix H as a second threshold T2. Thus, the threshold T needs to be updated after each flip.

[0243] In one possible implementation, based on E j 1 =d vj +1-E j Determine the fourth number of times each bit of data does not satisfy the check equation in the check matrix H; where E j 1 This indicates that each bit of data does not satisfy the fourth number of the parity check equations in the parity check matrix H, d vj This indicates the maximum number of bits of data that do not satisfy the check equations in the check matrix H, E j This indicates the number of times each bit of data does not satisfy the first check equation in the check matrix H.

[0244] In one possible implementation, the method further includes: if the third corrector S3 is not all zeros, based on the third bit sequence, the second corrector S2, and the second regularization term, obtaining the third number of times each bit in the third bit sequence does not satisfy the check equation in the check matrix H, where the second regularization term is less than or equal to 0; if the third number of times the third bit in the third bit sequence does not satisfy the check equation in the check matrix H is greater than or equal to the third threshold T3, flipping the third bit sequence to obtain the fourth bit sequence; after obtaining the fourth bit sequence, obtaining the fourth corrector S4 based on the fourth bit sequence and the check matrix H; if the third corrector S4 is all zeros, outputting the third bit sequence. This process is repeated until the corrector is all zeros or the maximum number of iterations is reached.

[0245] In one possible implementation, if the positions of the first bit data in the first bit sequence, the second bit data in the second bit sequence, and the third bit data in the third bit sequence are the same, then the second regularization term is equal to the first regularization term, and the second regularization term is less than 0. Thus, if the same bit data is repeatedly flipped, when calculating the number of times the bit data does not satisfy the check equation, a regularization term less than 0 is added to reduce the probability of repeated flips.

[0246] In one possible implementation, the value of the second regularization term is 0 if the position of the second bit data in the second bit sequence is different from the position of the third bit data in the third bit sequence.

[0247] This process continues until the corrector is all zeros, or the maximum number of iterations is reached.

[0248] The first approach optimizes the algorithm for calculating the number of bits that do not satisfy the parity check equation, reducing the probability of correct bits being incorrectly flipped and thus lowering the decoding error level. Secondly, a threshold judgment mechanism is introduced, allowing the controller chip to simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing decoding latency and improving decoding throughput. Thirdly, a random sequence generator is proposed, assigning a certain probability constraint to bits that meet the flipping condition, reducing the occurrence of the same bit getting stuck in an infinite loop due to repeated flipping. This further reduces decoding latency and improves decoding throughput.

[0249] This application also provides a chip, which includes a processing circuit and an interface circuit. The interface circuit is used to receive code instructions and transmit them to the processing circuit, and the processing circuit is used to execute the code instructions to perform... Figure 10 An example of a decoding method is provided.

[0250] This application also provides a decoding device, which includes a chip and a memory; the memory stores a first bit sequence, and the chip reads the first bit sequence from the memory and executes... Figure 10 An example of a decoding method is provided.

[0251] This application also provides a computer-readable storage medium storing instructions that, when executed on a chip, cause the chip to perform... Figure 10 An example of a decoding method is provided.

[0252] This application also provides a computer program product that, when executed by a chip, causes the chip to perform... Figure 10 An example of a decoding method is provided.

[0253] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0254] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0255] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0256] In summary, the above description is merely an embodiment of the technical solution of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made according to the disclosure of the present invention should be included within the scope of protection of the present invention.

Claims

1. A decoding method, characterized in that, The method includes: Read the first bit sequence and obtain the test matrix H of the first bit sequence, wherein the first bit sequence contains n bits of data; Based on the first bit sequence and the test matrix H, the first corrector S1 is obtained; If the first calibrator S1 is not all zeros, based on the first bit sequence and the first calibrator S1, determine the first number of bits in the first bit sequence that do not satisfy the check equation in the check matrix H. If the first bit data in the first bit sequence does not satisfy the first number of verification equations in the verification matrix H that is greater than or equal to the first threshold T1. The first bit data is flipped to obtain the second bit sequence; After obtaining the second bit sequence, the second corrector S2 is obtained based on the second bit sequence and the test matrix H; When the second corrector S2 is not all zeros, based on the second bit sequence, the second corrector S2, and the first regularization term, the second number of bits in the second bit sequence that do not satisfy the check equation in the check matrix H is obtained, wherein the first regularization term is less than or equal to 0. If the second bit data in the second bit sequence does not satisfy the second number of the verification equation in the verification matrix H being greater than or equal to the second threshold T2. The second bit data is flipped to obtain the third bit sequence; After obtaining the third bit sequence, the third corrector S3 is obtained based on the third bit sequence and the test matrix H; When the third corrector S3 is all 0, the third bit sequence is output.

2. The method according to claim 1, characterized in that, The method further includes: When the third corrector S3 is not all zeros, based on the third bit sequence, the third corrector S3, and the second regularization term, the third number of bits in the third bit sequence that do not satisfy the check equation in the check matrix H is obtained, wherein the second regularization term is less than or equal to 0. If the third bit data in the third bit sequence does not satisfy the condition that the third number in the check equation of the check matrix H is greater than or equal to the third threshold T3, then... The third bit of data is flipped to obtain the fourth bit sequence; After obtaining the fourth bit sequence, the fourth corrector S4 is obtained based on the fourth bit sequence and the test matrix H; If the fourth corrector S4 is all 0, output the fourth bit sequence.

3. The method according to claim 1 or 2, characterized in that, When the position of the first bit data in the first bit sequence is the same as the position of the second bit data in the second bit sequence, the first regularization term is less than 0.

4. The method according to claim 2, characterized in that, If the positions of the first bit data in the first bit sequence, the second bit data in the second bit sequence, and the third bit data in the third bit sequence are the same, then the second regularization term is equal to the first regularization term, and the second regularization term is less than 0.

5. The method according to claim 2 or 4, characterized in that, If the position of the second bit data in the second bit sequence is different from the position of the third bit data in the third bit sequence, the value of the second regularization term is 0.

6. The method according to any one of claim 1, claim 2, or claim 4, characterized in that, In the While the first bit of data is being flipped, the method further includes: If the fourth bit in the first bit sequence does not satisfy the first number of the verification equation in the verification matrix H being greater than or equal to the first threshold T1, the fourth bit is flipped to obtain the second bit sequence.

7. The method according to any one of claim 1, claim 2, or claim 4, characterized in that, The first threshold T1 is determined based on the test matrix H.

8. The method according to any one of claim 1, claim 2, or claim 4, characterized in that, After obtaining the second bit sequence, Before the second bit of data is flipped, the method further includes: Based on the first number of times each bit data does not satisfy the check equation in the check matrix H and the preset maximum number of times each bit data does not satisfy the check equation in the check matrix H, a fourth number of times each bit data does not satisfy the check equation in the check matrix H is obtained. The maximum value of the first number of times each bit of data does not satisfy the check equation in the check matrix H and the fourth number of times each bit of data does not satisfy the check equation in the check matrix H is determined as the second threshold T2.

9. The method according to claim 8, characterized in that, Based on E j 1 =d vj +1-E j Determine the fourth number of times each bit of data does not satisfy the check equation in the check matrix H; wherein, the E j 1 This indicates that each bit of data does not satisfy the fourth number of the check equations in the check matrix H, d vj This indicates the maximum number of times each bit of data in the preset data does not satisfy the check equations in the check matrix H, E j This indicates the first number of times that each bit of data does not satisfy the check equation in the check matrix H.

10. The method according to any one of claim 1, claim 2, claim 4, or claim 9, characterized in that, Flipping the first bit of data specifically includes: A first digital sequence is obtained based on a first probability value and a first random sequence generator; wherein the number of elements in the first digital sequence is the same as the number of flipped bits in the first bit sequence, the value of an element in the first digital sequence is 0 or 1, and the proportion of elements in the first digital sequence that are 1 is the first probability value. When the value of the element corresponding to the position of the first bit data in the first bit sequence is 1, the first bit data is flipped.

11. The method according to any one of claim 1, claim 2, claim 4, or claim 9, characterized in that, When the first corrector S1 is all 0, the first bit sequence is output.

12. The method according to any one of claim 1, claim 2, claim 4, or claim 9, characterized in that, When the second corrector S2 is all 0, the second bit sequence is output.

13. A chip, characterized in that, The chip includes a processing circuit and an interface circuit. The interface circuit is used to receive code instructions and transmit them to the processing circuit. The processing circuit is used to execute the code instructions to perform the method as described in any one of claims 1-12.

14. A decoding device, characterized in that... The decoding device includes a chip and a memory; the memory is used to store a first bit sequence, and the chip is used to read the first bit sequence from the memory and execute the method according to any one of claims 1-12.

15. A computer-readable storage medium, characterized in that... The computer-readable storage medium stores instructions that, when executed on the chip, cause the chip to perform the method as described in any one of claims 1-12.

16. A computer program product, characterized in that, When the computer program product is executed by the chip, the chip performs the method as described in any one of claims 1-12.

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