A method, device and storage medium for locating errors in logic system design

Abstract

An embodiment of the present application provides a method for locating an error in a logic system design, comprising: simulating a first logic system design and a second logic system design to obtain a first waveform file and a second waveform file respectively, wherein the first logic system design includes a first design to be tested, the second logic system design includes a second design to be tested, and the second waveform file includes a second input stimulus for the second design to be tested; applying the second input stimulus to the first design to be tested to obtain a reference waveform file of multiple signals of the first design to be tested under the second input stimulus; and comparing the reference waveform file and the second waveform file to locate an error in the second logic system design.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer software technology, and in particular, to a method, device, and storage medium for locating errors in logic system design. Background Art

[0002] With the development of electronic technology, logic system design (e.g., chip design) has been widely used. The debugging of logic system design usually involves the debugging of simulation waveforms. For example, for a logic system design, a simulation waveform diagram of multiple signals within a certain period of time can be obtained through a simulation tool. The simulation waveform is stored as a waveform database, and the waveform database can be read by a debugging tool to reproduce the simulation waveform, and the debugging work of the logic system design is carried out accordingly.

[0003] In the daily development of chip design, the source code of the logic system design will be constantly modified and iterated, which will inevitably introduce errors. The traditional positioning method is to manually find the abnormal point by viewing the simulation waveform, and then manually trace the signal step by step until the source of the error is found. This method mainly relies on manual experience and is time-consuming and labor-intensive. In addition, the source of the error can be located by tracing back the source code and re-simulating the logic system design. However, these methods cannot solve the problem of changes in the verification simulation environment. Manually tracing the signal cannot accurately locate the source of the error. Therefore, how to quickly locate the source of the error is the key to improving verification efficiency. Summary of the invention

[0004] A first aspect of the present application provides a method for locating an error in a logic system design, comprising: simulating a first logic system design and a second logic system design to obtain a first waveform file and a second waveform file respectively, wherein the first logic system design includes a first design to be tested, the second logic system design includes a second design to be tested, and the second waveform file includes a second input stimulus for the second design to be tested; applying the second input stimulus to the first design to be tested to obtain a reference waveform file of multiple signals of the first design to be tested under the second input stimulus; and comparing the reference waveform file and the second waveform file to locate an error in the second logic system design.

[0005] The second aspect of the present application provides an electronic device, which includes a memory for storing a group of instructions and at least one processor configured to execute the group of instructions so that the electronic device executes the method according to the first aspect.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and the set of instructions is used to cause the computer to perform the method as described in the first aspect when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0008] Figure 1 A schematic diagram of a host according to an embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a simulation tool and a debugging tool according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a method for simulating logic system design is shown.

[0011] Figure 4 A method for generating a reference waveform according to an embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a method for generating a reference waveform file according to an embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of a method for locating errors in logic system design according to an embodiment of the present application is shown.

[0014] Figure 7 A flow chart of a method for quickly locating errors in logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0017] Simulation testing is to apply various stimuli to the logic system design on the host running the simulation test system to detect whether the logic system design can achieve the predetermined functions.

[0018] Figure 1 FIG. 1 is a schematic diagram of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the host through the bus 110.

[0019] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0020] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating errors in the logic system design of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0021] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC) etc.), a cellular network, the Internet or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0022] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0023] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (e.g., a USB port, a PCI-E bus), etc.

[0024] It should be noted that, although the above host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the host architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above host architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0025] Figure 2 The schematic diagram of the simulation tool 202 and the debugging tool 200 according to the embodiment of the present application is shown. The simulation tool 202 and the debugging tool 200 may be computer programs running on the host 100.

[0026] In the field of chip design, a design can usually be simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd. Figure 2 The exemplary simulation tool 202 shown may include a compiler 120 and a simulator 220. The compiler 120 may compile a design (e.g., a verification system 210) into a target code 204, and the simulator 220 may perform simulation according to the target code 204 and output a simulation result 206. For example, the simulation tool 202 may output the simulation result (e.g., a simulation waveform) via Figure 1 The verification system 210 may include a logic system design 210a and a verification environment 210b. The verification environment 210b may also be referred to as a testbench. For example, the verification environment 210b may be a UVM environment.

[0027] The simulation result 206 may also be stored in the form of a waveform database. The waveform database storing the waveform data may also be referred to as a waveform file.

[0028] The debugging tool 200 can also read the simulation result 206. The debugging tool 200 can be, for example, the Fusion Debug debugging tool produced by Xinhuazhang Technology Co., Ltd. For example, the debugging tool 200 can read the simulation result 206 stored in a waveform file, and generate a corresponding simulation waveform for debugging. The debugging tool 200 can also read the description of the verification system 210 (usually SystemVerilog and Verilog code) and display it to the user. The debugging tool 200 can also generate various graphical interfaces (for example: debugging window) to facilitate the user's debugging work. The user can issue a debugging command to the debugging tool 200 (for example, run the verification system 210 to a certain moment), and the debugging tool 200 applies the debugging command to the simulation tool 202 to execute accordingly. The debugging tool 200 can also read a log file. The log file can include various information of the simulation process, including information of the simulation error, the line number of the error, the time when the simulation error occurred, etc.

[0029] It is understandable that, in addition to being connected to the simulation tool 202 , the debugging tool 200 may also be connected to a hardware emulator.

[0030] Before the logic system design is put into actual operation, the compiled logic system design needs to be run and debugged using the aforementioned debugging tool 200. The debugging tool 200 can receive user instructions 212 from the user and make corresponding debugging actions. In some embodiments, the user can issue user instructions 212 by clicking the mouse in the graphical interface; in some embodiments, the user can enter a command line in the command line interface to issue a user instruction 212. If an abnormality is found in the logic system design during the debugging process, it is necessary to further diagnose the abnormality found, find out the cause and the specific source location of the abnormality, and make corrections to ensure the robustness of the logic system design.

[0031] In the field of integrated circuits, simulation can refer to compiling a logical system design and then running it with a simulation tool to simulate and test various functions of the design. It is used for the design of application-specific integrated circuits (ASIC) or system-on-chips (SOC). Therefore, the design tested or verified in the simulation can also be called the design under test (DUT).

[0032] In the daily development of chip design, the source code of the design to be tested will be constantly modified and iterated, which will inevitably introduce errors. The traditional positioning method is to check the simulation waveform, find the abnormal point manually, and then manually track the signal step by step until the source of the error is found. This method mainly relies on manual experience and is time-consuming and labor-intensive. In addition, the source of the error can be located by tracing back the source code and re-simulating the logic system design.

[0033] However, in the actual verification environment, random excitation is mainly used to test the test bench. Since the excitation is random, if a problem is found in the iterative design under test, it is impossible to directly compare it with the simulation results of the old design under test. If a new excitation is directly applied to the old design under test, it may cause the subsequent simulation of the old design under test to end prematurely. In addition, errors in the design under test tend to spread step by step, and manually tracing signals step by step often cannot effectively locate the source of the error in a timely manner.

[0034] Therefore, how to quickly and accurately locate errors in logic system design when the verification environment changes is an urgent problem that needs to be solved.

[0035] Figure 3 A schematic diagram of a method for simulating logic system design is shown.

[0036] like Figure 3 As shown, the logic system design 302 may include a DUT 3022 and a TB 3024. The DUT 3022 may be a complete chip design or a portion of a complete chip design. The TB 3024 may be used to provide test stimulus to the DUT 3022, determine test results, and generate test feedback (e.g., test logs, error reports, etc.).

[0037] The simulation tool 202 may read and compile the description (eg, source code) of the logical system design 302 and generate an executable file for simulation.

[0038] TB 3024 can apply multiple stimulus signals to DUT 3022. Multiple stimulus signals are generally applied to each port of DUT. DUT 3022 running in simulator 220 will process multiple stimulus signals in sequence. After DUT processes multiple stimulus signals, the output end of DUT will apply the output signal to TB to verify the output signal to confirm whether it meets the requirements of logic system design. Figure 3 As shown, the Checker module in TB 3024 will check the output signal of DUT 3022. It can be understood that the output signal generated by DUT 3022 processing multiple stimulus signals applied by TB 3024 can pass the verification of TB 3024. It is easy to understand that if DUT 3022 processes multiple stimulus signals other than those applied by TB 3024, the output signal of DUT 3022 may not pass the verification of TB 3024. If the verification fails, the subsequent simulation process cannot be continued.

[0039] When the simulation is finished, the DUT 3022 will store the simulation data in the memory 104. Subsequently, the simulator 220 can generate a waveform file based on the simulation data in the memory 104. The waveform file can include a test log, an output waveform of each port of the DUT, and multiple stimulus signals received by the DUT.

[0040] Figure 4 A method for generating a reference waveform according to an embodiment of the present application is shown.

[0041] like Figure 4 As shown, the initial logic system design 302 may include a DUT 3022 and a TB 3024, and the revised logic system design 304 may include a DUT 3042 and a TB 3044. The revised logic system design 304 is obtained after updating the initial logic system design 302. The revised logic system design 304 may be obtained after modifying the TB 3024 and the DUT 3022 in the initial logic system design 302.

[0042] It can be understood that the initial logic system design 302 is usually considered correct, and the errors of the revised logic system design 304 are often introduced after the initial logic system design 302 is modified. For example, after the DUT 3022 of the initial logic system design 302 is modified to obtain the DUT 3042, some errors are introduced.

[0043] It is understandable that the DUT 3042 and the DUT 3022 may be identical in terms of frame structure. In other words, the output and input ports and the internal module structure of the DUT 3042 and the DUT 3022 may correspond to each other.

[0044] The simulation tool 202 can simulate the initial logic system design 302 to obtain the initial waveform file 3026 , and simulate the revised logic system design 304 to obtain the revised waveform file 3046 . The initial waveform file 3026 and the revised waveform file 3046 are stored in the memory 104 .

[0045] like Figure 4 As shown, during the simulation of the initial logic system design 302, TB 3024 can apply a set of stimulus signals (e.g., stimulus signals a and b) to DUT 3022. During the simulation of the revised logic system design 304, TB 3044 can apply a set of stimulus signals (e.g., stimulus signals c and d) to DUT 3042.

[0046] The revised waveform file 3046 may include another set of stimulus signals (eg, stimulus signals c and d). The stimulus signals c and d are extracted from the revised waveform file 3046 and applied to the DUT 3022 for simulating the DUT 3022. The DUT 3022 may generate the reference waveform file 400 based on the stimulus signals c and d.

[0047] It can be seen that, compared with the initial waveform file 3026, the biggest difference of the reference waveform file 400 is that the design to be tested is changed back to DUT 3022 from DUT 3042. Therefore, the difference between the initial waveform file 3026 and the reference waveform file 400 is only caused by the modification of the design to be tested, while other variables (including the test bench and the input stimulus) are the same. Accordingly, the difference between the initial waveform file 3026 and the reference waveform file 400 can reflect the modification of the design to be tested, for example, reflect the error caused by the modification. Therefore, by comparing the initial waveform file 3026 and the reference waveform file 400, the error in DUT 3042 can be located.

[0048] Figure 5 A schematic diagram of a method for generating a reference waveform file according to an embodiment of the present application is shown.

[0049] like Figure 5 As shown, the stimulus signals c and d in the waveform file 3046 are extracted and applied to the input terminal of the DUT 3022. Since the output and input ports and the internal module structures of the DUT 3022 and the DUT 3024 can correspond to each other, the stimulus signal c can be applied to the input terminal a of the DUT 3022, and the stimulus signal d can be applied to the input terminal b of the DUT 3022.

[0050] After the simulation of DUT 3022 is completed, waveforms will be output at the output terminals, i.e., reference waveform file 400. Reference waveform file 400 is stored in memory 104. After the simulation of DUT 3022 is completed, TB 3024 will read and verify the output waveforms of output terminals e and f. Since the input stimulus signal has changed, the output of DUT 3022 may trigger the error reporting mechanism (e.g., Checker module) in TB 3024, and the simulation ends.

[0051] Therefore, in order to trick TB 3024 into believing that the result is correct and to keep the simulation running continuously, the correct output from the initial waveform file 3026 is applied to the output of DUT 3022 (i.e., the input of TB 3024), so that TB 3024 believes that the output of DUT 3022 is correct and keeps the simulation running continuously until a complete reference waveform file 400 is generated.

[0052] Figure 6 A schematic diagram of a method for locating errors in logic system design according to an embodiment of the present application is shown.

[0053] The debugging tool 200 may read the reference waveform file 400 and the revised waveform file 3046 from the memory 104 .

[0054] In some embodiments, for example, Figure 6 The output terminal b of DUT 3022 may correspond to the output terminal B of DUT 3042. DUT 3022 may receive a stimulus signal d from an input terminal, process the stimulus signal d, and output a waveform signal from output port b, which is stored in the reference waveform file 400. Similarly, DUT 3024 may receive a stimulus signal d from an input terminal, process the stimulus signal d, and output a waveform signal from output port B, which is stored in the revised waveform file 3046. Figure 6 As shown, module 502 in DUT 3022 may correspond to module 602 in DUT 3042 , module 504 in DUT 3022 may correspond to module 604 in DUT 3042 , and module 506 in DUT 3022 may correspond to module 606 in DUT 3042 .

[0055] There are usually independent logic modules inside the DUT. The connection relationship between the logic module units can usually be tree-like. Figure 6 As shown, there are multiple independent logic module units inside DUT 3022. Among them, the input of module 504 is the output of module 506, and the output of module 504 is the input of module 502. Similarly, there are logic module units corresponding to DUT 3022 and the connection relationship between the logic module units inside DUT 3024.

[0056] The DUT input terminal receives multiple stimulus signals respectively. From the input terminal to the output terminal, the simulation is performed one by one on the logic module. Figure 6 As shown, the simulation result of module 506 is transmitted to module 504 , and the simulation result of module 504 is then transmitted to module 502 .

[0057] The output waveform of the output port of the DUT can be the output waveform of the logic module closest to the port. Figure 5 As shown, the output waveform of port b of DUT 3022 may be the output waveform of module 502 , and the output waveform of port B of DUT 3042 may be the output waveform of module 602 .

[0058] The debugging tool 200 compares the signal waveforms of each output port of the DUT 3022 and the DUT 3042 in time based on the reference waveform file 400 and the revised waveform file 3046. Figure 6 As shown, the debugging tool 200 compares the output waveform of the b port of the DUT 3022 with the output waveform of the B port of the DUT 3042 in terms of time. The output waveform of the DUT is closely related to the logic module structure inside the DUT. Each logic module corresponds to a section of the output signal waveform of the output port.

[0059] The debugging tool 200 finds the difference point between the reference waveform file 400 and the revised waveform file 3046 in time. The difference point can be the first difference that appears on the waveform, for example, including the difference point of the output waveform of port b and port B. Compare the reference waveform output by port b and the waveform output by port B, and find the first difference point in time, which is the difference point of the output waveform of port b and port B. The debugging tool 200 finds the logic module inside the DUT corresponding to the difference point based on the difference point of the output waveform of port b and port B. It can be understood that the simulation waveform of each logic module inside the DUT will be reflected in the output waveform file.

[0060] like Figure 6 As shown, according to the output waveform difference point between port b and port B, the debugging tool 200 finds the logic module unit 502 corresponding to the difference point inside the DUT 3022. Since the internal structures of the DUT 3022 and the DUT 3042 can be consistent, the debugging tool can find the logic unit module 602 inside the DUT 3042, which corresponds to the logic module unit 502 of the DUT 3022.

[0061] The debugging tool 200 compares the input signal and output signal of the logic unit module step by step from the logic module where the waveform difference point appears to the input end. Figure 5As shown, the output signals of module 502 and module 602 are different, and the debugging tool 200 compares the input signals of module 502 and module 602. If the input signals of module 502 and module 602 are also different, compare whether the input signals of module 504 and module 604 are the same. Among them, the output signal of module 504 is the input signal of module 502, and the output signal of module 604 is the input signal of module 602. If the input signal of module 504 and the input signal of module 604 are also different, compare the input signals of module 506 and module 606. If the input signals of module 506 and module 606 are the same, module 606 in DUT 3042 is the root cause of the error. If the input signals of module 506 and module 606 are different, continue to trace back to the input end until a logic module with the same input signal and different output is found. This module is the root cause of the error in the design under test 3042.

[0062] The embodiment of the present application overcomes the factor of constantly changing verification environment in the chip design process by comparing the reference waveform file and the revised waveform file. By comparing the input and output of the internal logic module of the corresponding waveform, the source of the error is found, which solves the problem of manual error tracking being time-consuming and labor-intensive and relying on manpower, and also solves the problem of error propagation being difficult to locate manually.

[0063] The embodiment of the present application also provides a method for quickly locating errors in logic system design.

[0064] Figure 7 FIG. 7 is a flowchart of a method 700 for quickly locating errors in a logic system design according to an embodiment of the present application. The method 700 may be Figure 1 The method 700 may include the following steps.

[0065] In step 702, a first logic system design (eg, Figure 4 302) and a second logical system design (eg, Figure 4 304) to obtain the first waveform file (for example, Figure 4 The initial waveform file 3026 in the example and the second waveform file (eg, Figure 4 Revised waveform file 3046 in ).

[0066] In some embodiments, the first logic system design includes a first design to be tested (eg, Figure 4 The second logic system design includes a second design under test (eg, Figure 4 3042 in the DUT), the second waveform file includes a second input stimulus of the second design under test (e.g., Figure 4 The excitation signals in c and d).

[0067] In some embodiments, the second logic system design is obtained by modifying the first logic system design, especially by changing the design to be tested in the first logic system design to obtain the second logic system design.

[0068] In some embodiments, Figure 4 As shown, the test bench 3024 and the design under test 3022 in the logic system design 302 , especially the design under test 3022 , are changed to obtain the logic system design 304 .

[0069] In some embodiments, the first waveform file and the second waveform file may include a test log, an output waveform of each port of the design under test, and a plurality of stimulus signals received by the design under test.

[0070] At step 704, the second input stimulus (eg, Figure 4 The stimulus signals c and d in the figure are applied to the first design under test (e.g., Figure 4 The DUT 3022 in the device is used to obtain a reference waveform file (e.g., Figure 4 Reference waveform file 400 in ).

[0071] In some embodiments, the second waveform file may include a second input stimulus. Figure 4 As shown, the revised waveform file 3046 may include the stimulus signal b applied by the test bench 3044 to the design under test 3042. Therefore, the stimulus signal b may be extracted from the revised waveform file 3046 and applied to the design under test 3022 to generate the reference waveform file 400.

[0072] In some embodiments, Figure 5 As shown, after the reference waveform file 400 is generated, the initial waveform file 3026 in the memory 104 is called. The initial waveform file 3026 is reapplied to the output end of the design under test 3022 to ensure that the subsequent simulation of the logic system design 302 continues to run.

[0073] In step 706, the reference waveform file (eg, Figure 4 or Figure 6 400) and the second waveform file (eg, Figure 4 or Figure 6 3046) to locate the second logic system design (e.g., Figure 4 Error in logical system design 304).

[0074] In some embodiments, the debugging tool 200 compares the reference waveform file and the second waveform file in terms of time. Figure 6As shown, the debugging tool 200 finds the difference between the output waveform of the port c of the design under test 3022 and the output waveform of the port d of the design under test 3042 in terms of time, and further finds the internal logic module corresponding to the difference.

[0075] In some embodiments, the debugging tool 200 traces back to the input end and compares the input signal and output signal of the module corresponding to the difference point until a module with the same input signal but different output signal is found, which is the root error module. Figure 6 As shown, the input signals of module 502 and module 402 are compared. If they are different, the input signals of module 404 and module 504 are compared until a logic module with the same input signal and different output is found. This module is the source of the error in the design under test.

[0076] The embodiment of the present application overcomes the factor of constantly changing verification environment in the chip design process by comparing the reference waveform file and the revised waveform file. By comparing the input and output of the internal logic module of the corresponding waveform, the source of the error is found, which solves the problem of manual error tracking being time-consuming and labor-intensive and relying on manpower, and also solves the problem of error propagation being difficult to locate manually.

[0077] The present application also provides an electronic device. The electronic device may be Figure 1 The electronic device may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method 700.

[0078] The embodiment of the present application further provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of computer instructions, and the set of instructions is used to make the computer perform method 700 when executed.

[0079] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0080] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0081] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0082] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for locating an error in a logic system design, comprising: Simulating a first logic system design and a second logic system design to obtain a first waveform file and a second waveform file respectively, wherein the second logic system design is modified from the first logic system design, the first logic system design includes a first design to be tested, the second logic system design includes a second design to be tested, and the second waveform file includes a second input stimulus for the second design to be tested; Applying the second input stimulus to the first design under test to obtain a reference waveform file of a plurality of signals of the first design under test under the second input stimulus; Comparing the reference waveform file with the second waveform file to find the difference between the reference waveform file and the second waveform file in terms of time; Finding, based on the difference point, a logic module in the first design to be tested and the second design to be tested that corresponds to the difference point; The input signals and output signals of the logic modules are compared step by step toward the input end until a logic module with the same input signal and different output signal is found, so as to locate the design error of the second logic system.

2. The method according to claim 1, wherein: The first design to be tested includes a first module, the first module includes a first input signal and a first output signal, and comparing the reference waveform file with the second waveform file to locate the error of the second logic system design further includes: Reading a first reference output waveform and a first output waveform corresponding to the first output signal from the reference waveform file and the second waveform file respectively; determining whether the first reference output waveform and the first output waveform are the same; In response to determining that the first reference output waveform and the first output waveform are not identical, determining whether a first input signal of the first module is identical in the reference waveform file and the second waveform file.

3. The method according to claim 2, wherein: The first design under test further includes a second module, the second module includes a second input signal and a second output signal, the second output signal is connected to the first input signal, and comparing the reference waveform file with the second waveform file to locate the error of the second logic system design further includes: In response to the first input signal of the first module being different in the reference waveform file and the second waveform file, it is determined whether the second input signal of the second module is the same in the reference waveform file and the second waveform file.

4. The method according to claim 3, wherein: Comparing the reference waveform file with the second waveform file to locate errors in the second logic system design further includes: In response to determining that the second input signal of the second module is the same in the reference waveform file and the second waveform file, determining that the module corresponding to the second module in the second design under test is an error module.

5. The method according to claim 1, wherein: Applying the second input stimulus to the first design under test to obtain a reference waveform file of a plurality of signals of the first design under test under the second input stimulus further comprises: Applying the output waveform of the first design under test in the first waveform file to the output terminal of the first design under test.

6. An electronic device comprising: a memory for storing a set of computer instructions; as well as A processor, configured to execute the computer instructions so that the electronic device executes the method as claimed in any one of claims 1 to 5. 7 . A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method according to claim 1 .

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