A pixel circuit suitable for high resolution display screens

Abstract

The application discloses a pixel circuit suitable for a high-resolution display screen, which comprises a TFT, a capacitor, a scanning unit and a light-emitting device; wherein the first to fourth TFTs and the eighth TFT in the TFT are sequentially connected; the fifth TFT is connected with the third, fourth and ninth TFTs respectively; the sixth TFT is connected with the second, third and eighth TFTs respectively; the seventh TFT is connected with the first and ninth TFTs respectively; the eighth TFT is connected with the first and ninth TFTs respectively; the first end of the first capacitor in the capacitor is electrically connected between the first and eighth TFTs, and the second end is electrically connected to the intersection of the second, third, sixth and eighth TFTs; the first end of the second capacitor is electrically connected between the third and fourth TFTs, and the second end is electrically connected between the fifth and ninth TFTs; the first scanning unit in the scanning unit is connected with the second TFT; the second scanning unit is connected with the fifth TFT; and the third scanning unit is connected with the third TFT. The application is suitable for high-resolution display screens.

Description

Technical Field

[0001] This invention belongs to the field of pixel circuits, and particularly relates to a pixel circuit suitable for high-resolution displays. Background Technology

[0002] With the continuous development of the information society, people's demand for high-resolution displays is constantly increasing. Higher resolution at the same size means a more delicate display. However, the pixel circuits currently used in the industry are not very suitable for high-resolution displays. This is because higher resolution means less data voltage charging and discharging time for each row of pixel circuits in the display. Currently, the data voltage VDATA charging time of the pixel circuits generally needs to be more than 3µs to fully compensate for the Vth of the pixel circuit TFT. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a pixel circuit that allows the data voltage VDATA to be input to the pixel circuit for Vth compensation in a very short time, supporting higher resolution; at the same time, the luminous current is independent of ELVDD, eliminating the IR drop of ELVDD.

[0004] To achieve the above objectives, the present invention provides the following solution: a pixel circuit suitable for a high-resolution display screen, comprising:

[0005] TFT, capacitor, scanning unit, light-emitting device;

[0006] The TFT is connected to the light-emitting device accordingly;

[0007] The TFT includes a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, and a ninth TFT;

[0008] The capacitor includes a first capacitor and a second capacitor;

[0009] The scanning unit includes a first scanning unit, a second scanning unit, and a third scanning unit;

[0010] The first TFT, the second TFT, the third TFT, the fourth TFT, and the eighth TFT are connected in sequence;

[0011] The fifth TFT is connected to the third TFT, the fourth TFT, and the ninth TFT respectively;

[0012] The sixth TFT is connected to the second TFT, the third TFT, and the eighth TFT respectively;

[0013] The seventh TFT is connected to the first TFT and the ninth TFT respectively;

[0014] The eighth TFT is connected to the first TFT and the ninth TFT respectively;

[0015] The first terminal of the first capacitor is electrically connected between the first TFT and the eighth TFT, and the second terminal is electrically connected to the intersection of the second TFT, the third TFT, the sixth TFT, and the eighth TFT.

[0016] The first terminal of the second capacitor is electrically connected between the third TFT and the fourth TFT, and the second terminal is electrically connected between the fifth TFT and the ninth TFT;

[0017] The first scanning unit is connected to the second TFT and is used to generate a first scanning signal;

[0018] The second scanning unit is connected to the fifth TFT and is used to generate a second scanning signal;

[0019] The third scanning unit is connected to the third TFT and is used to generate a third scanning signal.

[0020] Preferably, the ninth TFT in the TFT is an N-type TFT, and the rest are P-type TFTs.

[0021] Preferably, the light-emitting device includes OLED and micro LED.

[0022] Preferably, the fourth TFT is used to receive the first EM control signal EM1;

[0023] The sixth TFT is used to receive the second EM control signal EM2.

[0024] Preferably, the operation of the pixel circuit includes,

[0025] P1 stage: The first scan signal, the third scan signal, and the second EM control signal EM2 are at low level, and the first TFT, the second TFT, the third TFT, the sixth TFT, and the seventh TFT are turned on; then the light-emitting device is reverse biased, and the ninth TFT is turned off;

[0026] P2 stage: When the second and third scan signals are low, the third and fifth TFTs are turned on;

[0027] P3 stage: The first EM control signal EM1 is low, and the fourth TFT is turned on;

[0028] P4 stage: The first EM control signal EM1 and the second EM control signal EM2 are at low level, the fourth TFT continues to conduct, and the sixth TFT also conducts.

[0029] Preferably, in the P1 stage, the first scan signal, the third scan signal, and the second EM control signal EM2 are at low levels, and the first TFT, the second TFT, the third TFT, the sixth TFT, and the seventh TFT are turned on. At this time, Vdp = Vb = Vanode = Vgn = VINIT; the light-emitting device is reverse biased, the ninth TFT is turned off, and there is no current in the two driver TFTs. At this time, Vgp = VDATA, and the voltage difference across the first capacitor is VDATA - VINIT.

[0030] Preferably, in the P2 stage, the second scan signal and the third scan signal are at a low level, and the third TFT and the fifth TFT are turned on.

[0031] Vgn = ELVDD, Vs, Vdp, and Vgp are charged and discharged, Vs = Vgn - Vthn = ELVDD - Vthn.

[0032] Vgp=Vs+Vthp=ELVDD-Vthn+Vthp;

[0033] The voltage difference across the first capacitor remains constant.

[0034] Vb=Vdp=Vgp+VINIT-VDATA=ELVDD-Vthn+Vthp+VINIT-VDATA;

[0035] The voltage difference across the second capacitor is:

[0036] Vgn-Vb=ELVDD-(ELVDD-Vthn+Vthp+VINIT-VDATA)=VDATA-VININ+Vth n-Vthp.

[0037] Preferably, in the P3 stage, the first EM control signal EM1 is at a low level, the fourth TFT is turned on, and Vgp = Vb. Compared with the P2 stage, the voltages across the first capacitor and the second capacitor remain unchanged.

[0038] Preferably, in the P4 stage, the first EM control signal EM1 and the second EM control signal EM2 are at low levels, the fourth TFT continues to conduct, the sixth TFT also conducts, Vdp is pulled down to Vanode, the Vanode is related to the voltage difference between ELVSS and OLED, Vgp = Vb, the Vgn voltage changes, the voltage difference between the first capacitor and the second capacitor is the same as in the P3 stage, and the luminous current is related to the voltage difference between Vgn and Vgp.

[0039] Compared with the prior art, the present invention has the following advantages and technical effects:

[0040] The pixel circuit provided by this invention, suitable for high-resolution displays, directly charges the data voltage VDATA onto the capacitor. The time that each row of pixel circuits uses VDATA is very short (far less than 3µs in the prior art, such as 0.5µs), making it suitable for high-resolution displays. Finally, it can also compensate for the Vth of the two driving TFTs, and the luminous current is independent of ELVDD, that is, there is no IR drop of ELVDD. Attached Figure Description

[0041] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0042] Figure 1 This is a circuit diagram of the pixel circuit according to an embodiment of the present invention;

[0043] Figure 2 This is a timing diagram of the pixel circuit according to an embodiment of the present invention;

[0044] Figure 3 This is a diagram of the NTFT+PTFT series structure according to an embodiment of the present invention. Detailed Implementation

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0047] like Figure 1 As shown, the pixel circuit suitable for high-resolution displays provided by the present invention includes a TFT, a capacitor, a scanning unit, and a light-emitting device.

[0048] The TFT is connected to the light-emitting device accordingly;

[0049] TFTs include the first TFT, the second TFT, the third TFT, the fourth TFT, the fifth TFT, the sixth TFT, the seventh TFT, the eighth TFT, and the ninth TFT;

[0050] The capacitor includes a first capacitor and a second capacitor;

[0051] The scanning unit includes a first scanning unit, a second scanning unit, and a third scanning unit;

[0052] The scheme is further optimized so that the first TFT, second TFT, third TFT, fourth TFT, and eighth TFT are connected in sequence;

[0053] The fifth TFT is connected to the third TFT, the fourth TFT, and the ninth TFT, respectively;

[0054] The sixth TFT is connected to the second TFT, the third TFT, and the eighth TFT, respectively;

[0055] The seventh TFT is connected to both the first TFT and the ninth TFT.

[0056] The eighth TFT is connected to both the first TFT and the ninth TFT.

[0057] In a further optimized scheme, the first end of the first capacitor is electrically connected between the first TFT and the eighth TFT, and the second end is electrically connected to the intersection of the second TFT, the third TFT, the sixth TFT, and the eighth TFT.

[0058] The first terminal of the second capacitor is electrically connected between the third TFT and the fourth TFT, and the second terminal is electrically connected between the fifth TFT and the ninth TFT;

[0059] In a further optimized scheme, the first scanning unit is connected to the second TFT to generate the first scanning signal;

[0060] The second scanning unit is connected to the fifth TFT and is used to generate the first scanning signal;

[0061] The third scanning unit is connected to the third TFT and is used to generate the third scanning signal.

[0062] Further optimization of the scheme: the ninth TFT in the TFT is an N-type TFT, and the rest are P-type TFTs.

[0063] Further optimization of the solution involves light-emitting devices including OLED and micro LED.

[0064] In a further optimized scheme, the fourth TFT is used to receive the first EM control signal EM1;

[0065] The sixth TFT is used to receive the second EM control signal EM2.

[0066] Further optimization of the scheme, the working process of the pixel circuit includes,

[0067] In P1 stage: the first scan signal, the third scan signal, and the second EM control signal EM2 are at low level, and the first TFT, the second TFT, the third TFT, the sixth TFT, and the seventh TFT are turned on. At this time, Vdp = Vb = Vanode = Vgn = VINIT; the light-emitting device is reverse biased, the ninth TFT is turned off, and there is no current in the two driver TFTs. At this time, Vgp = VDATA, and the voltage difference across the first capacitor is VDATA - VINIT.

[0068] P2 phase: The second and third scan signals are low, and the third and fifth TFTs are turned on.

[0069] Vgn = ELVDD, Vs, Vdp, and Vgp are charged and discharged, Vs = Vgn - Vthn = ELVDD - Vthn.

[0070] Vgp=Vs+Vthp=ELVDD-Vthn+Vthp;

[0071] The voltage difference across the first capacitor remains constant.

[0072] Vb=Vdp=Vgp+VINIT-VDATA=ELVDD-Vthn+Vthp+VINIT-VDATA;

[0073] The voltage difference across the second capacitor is:

[0074] Vgn-Vb=ELVDD-(ELVDD-Vthn+Vthp+VINIT-VDATA)=VDATA-VININ+Vth n-Vthp.

[0075] In stage P3: the first EM control signal EM1 is low, the fourth TFT is turned on, and Vgp = Vb. Compared with stage P2, the voltages across the first and second capacitors remain unchanged.

[0076] In stage P4: the first EM control signal EM1 and the second EM control signal EM2 are at low levels, the fourth TFT continues to conduct, the sixth TFT also conducts, Vdp is pulled down to Vanode, the Vanode is related to the voltage difference between ELVSS and OLED, Vgp = Vb, Vgn voltage changes, the voltage difference between the first capacitor and the second capacitor is the same as in stage P3, and the luminous current is related to the voltage difference between Vgn and Vgp.

[0077] Example 1

[0078] like Figure 1As shown, the pixel circuit suitable for high-resolution displays provided by the present invention includes 9 TFTs (where MDN is an N-type TFT and the rest are P-type TFTs), 2 capacitors and 1 light-emitting device (which can be an OLED or micro LED, etc.).

[0079] like Figure 2 As shown, the working process of the pixel circuit includes,

[0080] Phase 1:

[0081] SCAN1, SCAN3, and EM2 are low, M1, M2, M3, M6, and M7 are on, Vdp = Vb = Vanode = Vgn = VINIT, the OLED is reverse biased, MDN is off, and there is no current in the two driver TFTs; Vgp = VDATA, and the voltage difference across C1 = VDATA - VINIT. Note that at this time, VDATA is directly charging capacitor C1, which can theoretically be completed instantly. However, current pixel circuits charge the capacitor by connecting DTFTs in a diode structure, and the charging current is very small, resulting in a long charging time.

[0082] Phase 2:

[0083] When SCAN2 and SCAN3 are low, M3 and M5 are enabled.

[0084] Vgn = ELVDD, Vs, Vdp, and Vgp will be charged and discharged, and finally Vs = Vgn - Vthn = ELVDD - Vthn.

[0085] Vgp = Vs + Vthp = ELVDD - Vthn + Vthp; while the pressure difference across C1 remains constant.

[0086] Vb=Vdp=Vgp+VINIT-VDATA=ELVDD-Vthn+Vthp+VINIT-VDATA;

[0087] Pressure difference across C2

[0088] =Vgn-Vb=ELVDD-(ELVDD-Vthn+Vthp+VINIT-VDATA)=VDATA-VININ+Vthn-Vthp;

[0089] P3 phase:

[0090] When EM1 is low, M4 is on, Vgp = Vb. Compared with stage P2, the voltages across C1 and C2 remain unchanged.

[0091] Phase 4:

[0092] EM1 and EM2 are at low levels, M4 continues to conduct, and M6 also conducts. Vdp is pulled down to equal Vanode. Although Vanode is related to the voltage difference between ELVSS and the OLED at this time, and Vgp = Vb and Vgn voltages will change, the voltage difference between C1 and C2 is still the same as in stage P3. The luminous current is related to the voltage difference between Vgn and Vgp (i.e., the voltage difference across C2). The proof will be given below:

[0093] like Figure 3 The NTFT+PTFT cascaded structure shown allows both the NTFT MDN and PTFT MDP to operate in the saturation region:

[0094] Idn = Kn(Vgn - Vx - Vthn) 2

[0095] Idp = Kp(Vgp - Vx - Vthp) 2

[0096] Since Idn = Idp, therefore

[0097] Kn(Vgn-Vx-Vthn) 2 =Kp(Vgp-Vx-Vthp) 2

[0098] Where Mgn-Vx-Vthn>0, Mgp-Vx-Vthp<0.

[0099] Solving for the problem,

[0100] Then V X Substitute I dn expression:

[0101]

[0102] During the luminescence stage, Vgn-Mgp = VDATA-VINIT + Vthn-Vthp.

[0103] Substitute the above I dn Expression: (The rest of the text appears to be a series of symbols and characters, possibly indicating a corrupted or incomplete expression.)

[0104]

[0105] and

[0106] Where μn is the electron mobility of the MDN channel, Coxn is the channel capacitance per unit area of ​​the driving MDN, Wn is the channel width of the driving MDN, Ln is the channel length of the driving MDN, and Vthn is the threshold voltage of the MDN.

[0107] and

[0108] Where μp is the electron mobility of the MDN channel, Coxp is the channel capacitance per unit area of ​​the driving MDP, Wp is the channel width of the driving MDP, Lp is the channel length of the driving MDP, and Vthp is the threshold voltage of the MDP.

[0109] In the last I d (i.e. I dn From the expression, we can see that I d This circuit is independent of both Vthn and Vthp; and I d It is unrelated to ELMDD and ELVSS, and is not affected by the voltage drop IR Dro caused by the resistance on this power supply trace. p The impact.

[0110] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit suitable for high-resolution displays, characterized in that, include: TFT, capacitor, scanning unit, light-emitting device; The TFT is connected to the light-emitting device accordingly; The TFT includes a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, and a ninth TFT; The capacitor includes a first capacitor and a second capacitor; The scanning unit includes a first scanning unit, a second scanning unit, and a third scanning unit; The first TFT, the second TFT, the third TFT, the fourth TFT, and the eighth TFT are connected in sequence; The fifth TFT is connected to the third TFT, the fourth TFT, and the ninth TFT respectively; The sixth TFT is connected to the second TFT, the third TFT, and the eighth TFT respectively; The seventh TFT is connected to the first TFT and the ninth TFT respectively; The eighth TFT is connected to the first TFT and the ninth TFT respectively; The first terminal of the first capacitor is electrically connected between the first TFT and the eighth TFT, and the second terminal is electrically connected to the intersection of the second TFT, the third TFT, the sixth TFT, and the eighth TFT. The first terminal of the second capacitor is electrically connected between the third TFT and the fourth TFT, and the second terminal is electrically connected between the fifth TFT and the ninth TFT; The first scanning unit is connected to the second TFT and is used to generate a first scanning signal; The second scanning unit is connected to the fifth TFT and is used to generate a second scanning signal; The third scanning unit is connected to the third TFT and is used to generate a third scanning signal; The gates of the first TFT, the second TFT, and the seventh TFT are all connected to the first scanning unit; The source of the first TFT is connected to the second node, and the drain of the first TFT is connected to the data signal terminal, which is used to provide the data signal VDATA. The source of the second TFT is connected to the fifth node, and the drain of the second TFT is connected to the initialization signal terminal, which is used to provide the initialization voltage VINIT. The source of the seventh TFT is connected to the first node, and the drain of the seventh TFT is connected to the initialization signal terminal; The gate of the third TFT is connected to the third scanning unit, the drain of the third TFT is connected to the fourth node, and the source of the third TFT is connected to the fifth node. The gate of the fourth TFT is connected to the first light-emitting control signal terminal, which is used to provide the first EM control signal EM1. The drain of the fourth TFT is connected to the second node, and the source of the fourth TFT is connected to the fourth node. The gate of the fifth TFT is connected to the second scanning unit, the drain of the fifth TFT is connected to the first power supply terminal, and the source of the fifth TFT is connected to the first node. The first power supply terminal is used to provide the power signal ELVDD. The gate of the sixth TFT is connected to the second light-emitting control signal terminal, which is used to provide the second EM control signal EM2. The drain of the sixth TFT is connected to the fifth node. The source of the sixth TFT is connected to the anode of the light-emitting device. The cathode of the light-emitting device is connected to the second power supply terminal, which is used to provide the power supply signal ELVSS. The gate of the eighth TFT is connected to the second node, the source of the eighth TFT is connected to the third node, and the drain of the eighth TFT is connected to the fifth node. The gate of the ninth TFT is connected to the first node, the drain of the ninth TFT is connected to the first power supply terminal, and the source of the ninth TFT is connected to the third node. The ninth TFT is an N-type TFT, and the first TFT to the eighth TFT are all P-type TFTs; The first capacitor is connected between the second node and the fifth node, and the second capacitor is connected between the first node and the fourth node; The eighth TFT and the ninth TFT are driving TFTs, the first TFT is a data writing TFT, the second TFT and the seventh TFT are initialization TFTs, the fifth TFT is connected to the first power supply terminal, and the sixth TFT is connected to the light-emitting device; The fourth TFT is used to receive the first EM control signal EM1; The sixth TFT is used to receive the second EM control signal EM2.

2. The pixel circuit suitable for a high-resolution display screen according to claim 1, characterized in that, The light-emitting devices include OLEDs and micro LEDs.

3. The pixel circuit suitable for a high-resolution display screen according to claim 1, characterized in that, The operation of the pixel circuit includes: P1 stage: The first scan signal, the third scan signal, and the second EM control signal EM2 are at low level, and the first TFT, the second TFT, the third TFT, the sixth TFT, and the seventh TFT are turned on; then the light-emitting device is reverse biased, and the ninth TFT is turned off; P2 stage: When the second and third scan signals are low, the third and fifth TFTs are turned on; P3 stage: The first EM control signal EM1 is low, and the fourth TFT is turned on; P4 stage: The first EM control signal EM1 and the second EM control signal EM2 are at low level, the fourth TFT continues to conduct, and the sixth TFT also conducts.

4. The pixel circuit suitable for a high-resolution display screen according to claim 3, characterized in that, In the P1 stage, the first scan signal, the third scan signal, and the second EM control signal EM2 are at low levels, and the first TFT, the second TFT, the third TFT, the sixth TFT, and the seventh TFT are turned on. At this time, Vdp=Vb=Vanode=Vgn=VINIT; the light-emitting device is reverse biased, the ninth TFT is turned off, and there is no current in the two driver TFTs. At this time, Vgp=VDATA, and the voltage difference across the first capacitor is VDATA-VINIT.

5. The pixel circuit suitable for a high-resolution display screen according to claim 3, characterized in that, In the P2 phase, the second and third scan signals are at low level, and the third and fifth TFTs are turned on. Vgn = ELVDD, Vs, Vdp, and Vgp are charged and discharged, Vs = Vgn - Vthn = ELVDD - Vthn. Vgp=Vs+Vthp=ELVDD-Vthn+Vthp; The voltage difference across the first capacitor remains constant. Vb=Vdp=Vgp+VINIT-VDATA=ELVDD-Vthn+Vthp+VINIT-VDATA; The voltage difference across the second capacitor is: Vgn-Vb=ELVDD-(ELVDD-Vthn+Vthp+VINIT-VDATA)=VDATA-VINIT+Vthn-Vthp.

6. The pixel circuit suitable for a high-resolution display screen according to claim 3, characterized in that, In the P3 stage, the first EM control signal EM1 is at a low level, the fourth TFT is turned on, and Vgp=Vb. Compared with the P2 stage, the voltages across the first capacitor and the second capacitor remain unchanged.

7. The pixel circuit suitable for a high-resolution display screen according to claim 3, characterized in that, In stage P4, the first EM control signal EM1 and the second EM control signal EM2 are at low levels, the fourth TFT continues to conduct, the sixth TFT also conducts, Vdp is pulled down to Vanode, Vanode is related to the voltage difference between ELVSS and OLED, Vgp=Vb, Vgn voltage changes, the voltage difference between the first capacitor and the second capacitor is the same as in stage P3, and the luminous current is related to the voltage difference between Vgn and Vgp.

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