A voltage generation circuit

Abstract

The application discloses a voltage generating circuit applied to the field of pipeline ADC. The circuit provided by the application is characterized in that the first end of a feedback capacitor is connected with an input signal, the second end of the feedback circuit is connected with the first end of a first switch and the first end of a second switch; the negative input end of a first operational amplifier is connected with the second end of the first switch, the positive input end of the first operational amplifier is connected with a first preset power signal, and the output end of the first operational amplifier is connected with the second end of the second switch, the input common mode point of a sample-and-hold circuit and / or the input common mode point of a gain digital-analog circuit. The circuit provided by the application is connected with the sample-and-hold circuit and / or the gain digital-analog circuit, and in different circuit states, the law of conservation of charge is followed, and in combination with the conservation of charge in the sample-and-hold circuit and / or the gain digital-analog circuit, the influence of the input signal and the reference voltage on the operational amplifier in the sample-and-hold circuit and / or the gain digital-analog circuit is eliminated, and the performance of the pipeline ADC is improved.

Description

Technical Field

[0001] This application relates to the field of pipelined ADCs, and in particular to a voltage generation circuit. Background Technology

[0002] In recent years, pipelined ADCs have often included sample-and-hold circuits and gain analog-to-digital converters (MDACs). In traditional sample-and-hold circuits and gain analog-to-digital converters (MDACs), the common-mode point of the operational amplifier input is affected by the input signal and / or reference voltage. When the common-mode voltage of the input signal fluctuates within a large range or the reference voltage is specially set, the MOSFETs in the input stage of the operational amplifier are prone to enter the cutoff region, especially in low power supply voltage applications, thus affecting the performance of the entire pipelined ADC.

[0003] In view of the above-mentioned technology, finding a voltage generation circuit is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a voltage generation circuit that is connected to a sample-and-hold circuit and a gain analog-to-digital circuit. Based on the law of conservation of charge, this circuit can eliminate the influence of input signals and / or reference voltages on the sample-and-hold circuit and the gain analog-to-digital circuit in the prior art.

[0005] To solve the above-mentioned technical problems, this application provides a voltage generating circuit, including: a first operational amplifier, a first switch, a second switch, and a feedback capacitor;

[0006] The first terminal of the feedback capacitor is connected to the input signal, and the second terminal of the feedback circuit is connected to the first terminal of the first switch and the first terminal of the second switch.

[0007] The negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to the first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain digital-to-analog circuit.

[0008] Preferably, the feedback capacitor includes: a first feedback capacitor and a second feedback capacitor;

[0009] The first end of the first feedback capacitor is connected to the first input signal, and the second end of the first feedback capacitor is connected to the first end of the first switch and the first end of the second switch.

[0010] The first terminal of the second feedback capacitor is connected to the second input signal, and the second terminal of the second feedback capacitor is connected to the second terminal of the first feedback capacitor, the first terminal of the first switch, and the first terminal of the second switch.

[0011] Preferably, when the output terminal of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in the first state;

[0012] The first input signal is the first sampled input signal of the sample-and-hold circuit;

[0013] The second input signal is the second sampling input signal of the sample-and-hold circuit.

[0014] Preferably, when the output terminal of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in the second state;

[0015] The first input signal is the second preset power signal;

[0016] The second input signal is the third preset power signal.

[0017] Preferably, when the output terminal of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in the first state;

[0018] The first input signal is the first digital-to-analog input signal of the gain digital-to-analog circuit;

[0019] The second input signal is the second digital-to-analog input signal added to the digital-to-analog circuit.

[0020] Preferably, when the output terminal of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in the second state;

[0021] The first input signal is half of the first reference input signal of the gain digital-to-analog circuit;

[0022] The second input signal is half of the second reference input signal of the gain digital-to-analog circuit.

[0023] Preferably, the sample-and-hold circuit includes: a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, and a second operational amplifier;

[0024] Among them, the first end of the third switch is connected to the first sampling input signal, and the second end of the third switch is connected to the first end of the first sampling capacitor and the first end of the fourth switch.

[0025] The second terminal of the first sampling capacitor is connected to the first input terminal of the second operational amplifier;

[0026] The second terminal of the fourth switch is connected to the first output terminal of the second operational amplifier;

[0027] The first terminal of the fifth switch is connected to the second sampling input signal, and the second terminal of the fifth switch is connected to the first terminal of the second sampling capacitor and the first terminal of the sixth switch.

[0028] The second terminal of the second sampling capacitor is connected to the second input terminal of the second operational amplifier and the second terminal of the first sampling capacitor;

[0029] The second terminal of the sixth switch is connected to the second output terminal of the second operational amplifier;

[0030] The second end of the first sampling capacitor and the second end of the second sampling capacitor are the input common-mode points of the sample-and-hold circuit.

[0031] Preferably, the sample-and-hold circuit further includes: a seventh switch, an eighth switch, and a ninth switch;

[0032] The first terminal of the seventh switch is connected to the second terminal of the first sampling capacitor and the first input terminal of the second operational amplifier; the second terminal of the seventh switch is connected to the first terminal of the eighth switch.

[0033] The second terminal of the eighth switch is connected to the second terminal of the second sampling capacitor and the second input terminal of the second operational amplifier;

[0034] The first terminal of the ninth switch is connected to the second terminal of the fourth switch and the first output terminal of the second operational amplifier; the second terminal of the ninth switch is connected to the second terminal of the sixth switch and the second output terminal of the second operational amplifier.

[0035] Among them, the second terminal of the seventh switch and the first terminal of the eighth switch are the input common-mode points of the sample-and-hold circuit.

[0036] Preferably, the gain digital-to-analog circuit includes: a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a third sampling capacitor, a fourth sampling capacitor, a fifth sampling capacitor, a sixth sampling capacitor, and a third operational amplifier;

[0037] Among them, the first terminal of the tenth switch is connected to the first digital-to-analog input signal and the first terminal of the eleventh switch, and the second terminal of the tenth switch is connected to the third sampling capacitor and the first terminal of the twelfth switch.

[0038] The second terminal of the eleventh switch is connected to the first terminal of the fourth sampling capacitor;

[0039] The second terminal of the third sampling capacitor is connected to the second terminal of the fourth sampling capacitor and the first input terminal of the third operational amplifier;

[0040] The second terminal of the twelfth switch is connected to the first output terminal of the third operational amplifier;

[0041] The first terminal of the thirteenth switch is connected to the first reference input signal, and the second terminal of the thirteenth switch is connected to the second terminal of the eleventh switch and the first terminal of the fourth sampling capacitor.

[0042] The first terminal of the fourteenth switch is connected to the second reference input signal, and the second terminal of the fourteenth switch is connected to the second terminal of the thirteenth switch, the second terminal of the eleventh switch, and the first terminal of the fourth sampling capacitor.

[0043] The first terminal of the fifteenth switch is connected to the second digital-to-analog input signal and the first terminal of the sixteenth switch, and the second terminal of the fifteenth switch is connected to the first terminal of the fifth sampling capacitor and the first terminal of the seventeenth switch.

[0044] The second terminal of the sixteenth switch is connected to the first terminal of the sixth sampling capacitor;

[0045] The second terminal of the fifth sampling capacitor is connected to the second terminal of the sixth sampling capacitor and the second input terminal of the third operational amplifier;

[0046] The second terminal of the seventeenth switch is connected to the second output terminal of the third operational amplifier;

[0047] The first terminal of the eighteenth switch is connected to the second reference input signal, and the second terminal of the eighteenth switch is connected to the second terminal of the sixteenth switch and the first terminal of the sixth sampling capacitor.

[0048] The first terminal of the nineteenth switch is connected to the first reference input signal, and the second terminal of the nineteenth switch is connected to the second terminal of the eighteenth switch, the second terminal of the sixteenth switch, and the first terminal of the sixth sampling capacitor.

[0049] Among them, the second terminals of the third, fourth, fifth, and sixth sampling capacitors are the input common-mode points of the gain digital-to-analog circuit.

[0050] Preferably, the gain digital-to-analog circuit further includes: a twentieth switch, a twenty-first switch, and a twenty-second switch;

[0051] Among them, the first terminal of the twentieth switch is connected to the second terminal of the third sampling capacitor, the second terminal of the fourth sampling capacitor and the first input terminal of the third operational amplifier, and the second terminal of the twentieth switch is connected to the first terminal of the twentieth switch.

[0052] The second terminal of the twenty-first switch is connected to the second terminal of the fifth sampling capacitor, the second terminal of the sixth sampling capacitor, and the second input terminal of the third operational amplifier.

[0053] The first terminal of the 22nd switch is connected to the second terminal of the 12th switch and the first output terminal of the third operational amplifier; the second terminal of the 22nd switch is connected to the second terminal of the 17th switch and the second output terminal of the third operational amplifier.

[0054] Among them, the second terminal of the twentieth switch and the first terminal of the twenty-first switch are the input common-mode points of the gain digital-to-analog circuit.

[0055] This application provides a voltage generation circuit, comprising: a first operational amplifier, a first switch, a second switch, and a feedback capacitor; a first terminal of the feedback capacitor is connected to an input signal, and a second terminal of the feedback circuit is connected to the first terminal of the first switch and the first terminal of the second switch; the negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to a first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain-digital-analog circuit. It is evident that the voltage generation circuit provided in this application is connected to the sample-and-hold circuit and / or the gain-digital-analog circuit. The states of different switches in the voltage generation circuit will cause changes in the state of the voltage generation circuit. Based on these changes, and following the law of conservation of charge, combined with the law of conservation of charge in the sample-and-hold circuit and / or the gain-digital-analog circuit, the influence of the input signal and reference voltage in the sample-and-hold circuit and / or the gain-digital-analog circuit on the input common-mode point of the operational amplifier will be eliminated, thereby improving the performance of the pipelined ADC. Attached Figure Description

[0056] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 A circuit diagram of the voltage generation circuit provided in an embodiment of this application;

[0058] Figure 2 A circuit diagram of a specific voltage generation circuit provided for an embodiment of this application;

[0059] Figure 3 A circuit diagram of the sample-and-hold circuit provided in the embodiments of this application;

[0060] Figure 4 A circuit diagram of the first state of the voltage generation circuit provided in the embodiments of this application;

[0061] Figure 5 A circuit diagram of the second state of the voltage generation circuit provided in the embodiments of this application;

[0062] Figure 6 A circuit diagram of the gain digital-to-analog circuit provided in the embodiments of this application;

[0063] Figure 7 A circuit diagram of the third state of the voltage generation circuit provided in the embodiments of this application;

[0064] Figure 8A circuit diagram of the fourth state of the voltage generation circuit provided in the embodiments of this application. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0066] The core of this application is to provide a voltage generation circuit.

[0067] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] In recent years, pipelined ADCs have often included sample-and-hold circuits and gain analog-to-digital converters (MDACs). In traditional sample-and-hold circuits and gain analog-to-digital converters (MDACs), the common-mode point of the operational amplifier input is affected by the input signal and / or reference voltage. When the common-mode voltage of the input signal fluctuates within a large range or the reference voltage is specially set, the MOSFETs in the input stage of the operational amplifier are prone to enter the cutoff region, especially in low power supply voltage applications, thus affecting the performance of the entire pipelined ADC.

[0069] To solve the above-mentioned technical problems, this application provides a voltage generating circuit, including: a first operational amplifier, a first switch, a second switch, and a feedback capacitor;

[0070] The first terminal of the feedback capacitor is connected to the input signal, and the second terminal of the feedback circuit is connected to the first terminal of the first switch and the first terminal of the second switch.

[0071] The negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to the first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain digital-to-analog circuit.

[0072] In specific embodiments, such as Figure 1As shown, the voltage generation circuit includes: a first operational amplifier Q1, a first switch K1, a second switch K2, and a feedback capacitor C; wherein, the first terminal of the feedback capacitor C is connected to the input signal, and the second terminal of the feedback circuit C is connected to the first terminal of the first switch K1 and the first terminal of the second switch K2; the negative input terminal of the first operational amplifier Q1 is connected to the second terminal of the first switch K1, the positive input terminal of the first operational amplifier Q1 is connected to the first preset power supply signal (V1), and the output terminal of the first operational amplifier Q1 is connected to the second terminal of the second switch K2, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain digital-to-analog circuit.

[0073] The voltage generation circuit is controlled by a first switch K1 and a second switch K2. When the first switch K1 is open and the second switch K2 is closed, the voltage generation circuit is in its first state. In this state, the output voltage of the first operational amplifier Q1 is transferred to the bottom plate of the feedback capacitor C in the form of charge. When the first switch K1 is closed and the second switch K2 is open, the voltage generation circuit is in its second state. In this state, the output signal of the first operational amplifier Q1 stored on the bottom plate of the feedback capacitor C from the previous state is fed back to the negative input terminal of the first operational amplifier Q1, forming negative feedback. Based on the charge conservation law of the first and second states, a first expression can be obtained. Combined with the second expression corresponding to the charge conservation law of the input common-mode point of the sample-and-hold circuit and / or the input common-mode point of the gain analog-to-digital converter connected to the output terminal of the first operational amplifier, the two expressions cancel out the variables of the input signal and / or reference voltage, avoiding the influence of the input signal and reference voltage in the sample-and-hold circuit and / or the gain analog-to-digital converter on the input common-mode point of the operational amplifier, thus preventing any impact on the performance of the pipelined ADC.

[0074] It should be noted that this application does not limit the specific structure of the sample-and-hold circuit and the gain digital-to-analog circuit. Therefore, based on the principle of charge conservation, this application does not limit the corresponding expressions, which can be set according to the specific circuit structure.

[0075] It should also be noted that the voltage generation circuit provided in this application can be connected to a sample-and-hold circuit, or to a gain digital-to-analog circuit, or two identical voltage generation circuit structures can be connected to both the sample-and-hold circuit and the gain digital-to-analog circuit simultaneously to improve pipeline performance.

[0076] This application provides a voltage generation circuit, comprising: a first operational amplifier, a first switch, a second switch, and a feedback capacitor; a first terminal of the feedback capacitor is connected to an input signal, and a second terminal of the feedback circuit is connected to the first terminal of the first switch and the first terminal of the second switch; the negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to a first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain-digital-analog circuit. It is evident that the voltage generation circuit provided in this application is connected to the sample-and-hold circuit and / or the gain-digital-analog circuit. The states of different switches in the voltage generation circuit will cause changes in the state of the voltage generation circuit. Based on these changes, and following the law of conservation of charge, combined with the law of conservation of charge in the sample-and-hold circuit and / or the gain-digital-analog circuit, the influence of the input signal and reference voltage in the sample-and-hold circuit and / or the gain-digital-analog circuit on the input common-mode point of the operational amplifier will be eliminated, thereby improving the performance of the pipelined ADC.

[0077] Based on the above embodiments, as a preferred embodiment, the feedback capacitor includes: a first feedback capacitor and a second feedback capacitor;

[0078] The first end of the first feedback capacitor is connected to the first input signal, and the second end of the first feedback capacitor is connected to the first end of the first switch and the first end of the second switch.

[0079] The first terminal of the second feedback capacitor is connected to the second input signal, and the second terminal of the second feedback capacitor is connected to the second terminal of the first feedback capacitor, the first terminal of the first switch, and the first terminal of the second switch.

[0080] In a specific embodiment, as a preferred option, such as Figure 2 As shown, the feedback capacitor C includes: a first feedback capacitor C1 and a second feedback capacitor C2; wherein the first terminal of the first feedback capacitor C1 is connected to the first input signal, and the second terminal of the first feedback capacitor C1 is connected to the first terminal of the first switch K1 and the first terminal of the second switch K2; the first terminal of the second feedback capacitor C2 is connected to the second input signal, and the second terminal of the second feedback capacitor C2 is connected to the second terminal of the first feedback capacitor C1, the first terminal of the first switch K1, and the first terminal of the second switch K2. Since the input signals of the sample-and-hold circuit and the gain analog-to-digital circuit in the pipelined ADC are both two signals, therefore, as a preferred embodiment, the feedback capacitor includes both the first and second feedback capacitors.

[0081] In the specific circuit implementation, when the output terminal of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit, both the first input signal and the second input signal are the input signals corresponding to the sample-and-hold circuit; when the output terminal of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit, both the first input signal and the second input signal are the input signals corresponding to the gain digital-to-analog circuit.

[0082] Based on the above embodiments, as a preferred embodiment, when the output terminal of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in the first state;

[0083] The first input signal is the first sampled input signal of the sample-and-hold circuit;

[0084] The second input signal is the second sampling input signal of the sample-and-hold circuit.

[0085] When the output of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in the second state;

[0086] The first input signal is the second preset power signal;

[0087] The second input signal is the third preset power signal.

[0088] The sample-and-hold circuit includes: a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, and a second operational amplifier.

[0089] Among them, the first end of the third switch is connected to the first sampling input signal, and the second end of the third switch is connected to the first end of the first sampling capacitor and the first end of the fourth switch.

[0090] The second terminal of the first sampling capacitor is connected to the first input terminal of the second operational amplifier;

[0091] The second terminal of the fourth switch is connected to the first output terminal of the second operational amplifier;

[0092] The first terminal of the fifth switch is connected to the second sampling input signal, and the second terminal of the fifth switch is connected to the first terminal of the second sampling capacitor and the first terminal of the sixth switch.

[0093] The second terminal of the second sampling capacitor is connected to the second input terminal of the second operational amplifier and the second terminal of the first sampling capacitor;

[0094] The second terminal of the sixth switch is connected to the second output terminal of the second operational amplifier;

[0095] The sample-and-hold circuit also includes: a seventh switch, an eighth switch, and a ninth switch;

[0096] The first terminal of the seventh switch is connected to the second terminal of the first sampling capacitor and the first input terminal of the second operational amplifier; the second terminal of the seventh switch is connected to the first terminal of the eighth switch.

[0097] The second terminal of the eighth switch is connected to the second terminal of the second sampling capacitor and the second input terminal of the second operational amplifier;

[0098] The first terminal of the ninth switch is connected to the second terminal of the fourth switch and the first output terminal of the second operational amplifier; the second terminal of the ninth switch is connected to the second terminal of the sixth switch and the second output terminal of the second operational amplifier.

[0099] Among them, the second terminal of the seventh switch and the first terminal of the eighth switch are the input common-mode points of the sample-and-hold circuit.

[0100] In specific embodiments, such as Figure 3 As shown, the sample-and-hold circuit includes: a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a first sampling capacitor C11, a second sampling capacitor C22, a second operational amplifier Q2, a seventh switch K7, an eighth switch K8, and a ninth switch K9. The circuit connections are as follows: the first terminal of the third switch K3 is connected to the first sampled input signal (INP1); the second terminal of the third switch K3 is connected to the first terminal of the first sampling capacitor C11 and the first terminal of the fourth switch K4; the second terminal of the first sampling capacitor C11 is connected to the first input terminal of the second operational amplifier Q2; the second terminal of the fourth switch K4 is connected to the first output terminal of the second operational amplifier Q2; the first terminal of the fifth switch K5 is connected to the second sampled input signal (INN1); the second terminal of the fifth switch K5 is connected to the first terminal of the second sampling capacitor C22 and the first terminal of the sixth switch K6; the second terminal of the second sampling capacitor C22 is connected to the second input terminal of the second operational amplifier Q2 and the second terminal of the first sampling capacitor C11; the second terminal of the sixth switch K6 is connected to the second output terminal of the second operational amplifier Q2. The output terminals are connected; the first terminal of the seventh switch K7 is connected to the second terminal of the first sampling capacitor C11 and the first input terminal of the second operational amplifier Q2, and the second terminal of the seventh switch K7 is connected to the first terminal of the eighth switch K8; the second terminal of the eighth switch K8 is connected to the second terminal of the second sampling capacitor C22 and the second input terminal of the second operational amplifier Q2; the first terminal of the ninth switch K2 is connected to the second terminal of the fourth switch K4 and the first output terminal of the second operational amplifier Q2, and the second terminal of the ninth switch K9 is connected to the second terminal of the sixth switch K6 and the second output terminal of the second operational amplifier Q2; wherein, the second terminal of the seventh switch K7 and the first terminal of the eighth switch K8 are the input common-mode point CM1 of the sample-and-hold circuit, that is, the endpoint between the seventh switch K7 and the eighth switch K8 is the input common-mode point CM1 of the sample-and-hold circuit.

[0101] The sample-and-hold circuit has two states: sampling and holding. In the sampling state, K3 and K5 are closed, K7 and K8 are closed, and K4 and K6 are open. The first sampling capacitor C1 samples the first sampled input signal INP1, and the second sampling capacitor C2 samples the second sampled input signal INN1. At this time, the second operational amplifier Q2 is not operating. Subsequently, K7 and K8 open first, followed by K3 and K5, and then K4 and K6 close, entering the holding state. In this state, the first and second sampling capacitors act as feedback capacitors, and the second operational amplifier Q2 operates. The first and second sampling capacitors C1 and C2 have the same specifications. By conserving charge at the bottom plates of the first and second sampling capacitors in the two states, the following equation can be derived:

[0102] (V CM1 -V INP1 )×C=(V - -V OUTP1 )×C;

[0103] (V CM1 -V INN1 )×C=(V + -V OUTN1 )×C;

[0104] Adding the two equations together, we get:

[0105] V OP1,CM1 =V CM1 -V IN1,CM1 +V OUT1,CM1 ;

[0106] Among them, V CM1 The common-mode voltage sampled for the bottom plate is set; V INP1 V is the voltage corresponding to the first sampled input signal; INN1 V represents the voltage corresponding to the second sampled input signal; C represents the capacitance of the first sampling capacitor C11 and the second sampling capacitor C22; V - V represents the voltage at the first input terminal of the second operational amplifier Q2 and the voltage at the negative input terminal of the first operational amplifier Q1; + V represents the voltage at the second input terminal of the second operational amplifier Q2 and the voltage at the positive input terminal of the first operational amplifier Q1; OUTP1 V is the voltage at the first output terminal of the second operational amplifier Q2; OUTN1 V is the voltage at the second output terminal of the second operational amplifier Q2; OP1,CM1 The voltage at the input common-mode point CM1 of the sample-and-hold circuit; V IN1,CM1 V is the common-mode voltage of the first sampled input signal INP1 and the second sampled input signal INN1. OUT1,CM1This is the common-mode voltage at the output of the second operational amplifier Q2. It can be seen that the voltage at the input common-mode point of the second operational amplifier Q2 is closely related to the common-mode voltage of the input signal.

[0107] Therefore, a voltage generation circuit is connected at the common-mode input point CM1 of the sample-and-hold circuit, meaning the output of the first operational amplifier is connected to the common-mode input point CM1 of the sample-and-hold circuit. At this point, the voltage generation circuit also operates in two states. For example... Figure 4 As shown, the circuit state at this time is that the voltage generation circuit is in the first state, that is, the first switch K1 is open and the second switch K2 is closed. At this time, the first input signal is the first sampling input signal INP1 of the sample-and-hold circuit; the second input signal is the second sampling input signal INN1 of the sample-and-hold circuit. Figure 5 As shown, the circuit state at this time is that the voltage generating circuit is in the second state, that is, the first switch K1 is closed and the second switch K2 is open. At this time, the first input signal is the second preset power supply signal V2; the second input signal is the third preset power supply signal V3. When the first switch K1 is open and the second switch K2 is closed, the voltage generating circuit is in the first state. At this time, the output voltage of the first operational amplifier Q1 is transferred to the bottom plate of the feedback capacitor C in the form of charge. When the first switch K1 is closed and the second switch K2 is open, the voltage generating circuit is in the second state. At this time, the output signal of the first operational amplifier Q1 stored on the bottom plate of the feedback capacitor C in the previous state is fed back to the negative input terminal of the first operational amplifier Q1, forming negative feedback. In the steady state, due to the existence of the negative feedback loop, the voltage at the input terminal of the first operational amplifier satisfies: V + +V - =V CM1 Based on the charge conservation in both states, we can obtain the following expression:

[0108] (V OUT1 -V INP1 )×C+(V OUT1 -V INN1 )×C=(V - -V CM1 )×2C;

[0109] Due to V + +V - =V CM1 Simplifying the above formula, we get:

[0110] V OUT1 =V IN1,CM1 ;

[0111] And because of V CM1 =V OUT1 =V IN1,CM1 Therefore, we can conclude that:

[0112] V OP1,CM1 =V OUT1,CM1 ;

[0113] Among them, V OUT1 This refers to the voltage at the output of the first operational amplifier Q1 when connected to the sample-and-hold circuit. It can be seen that this application, through the added voltage generation circuit, makes the input common-mode level of the second operational amplifier independent of the common-mode voltage of the input signal, and only related to the output common-mode voltage of the second operational amplifier. The output common-mode voltage can be adjusted by the designer, thus isolating the influence of the input signal's common-mode voltage on the operational amplifier's performance.

[0114] Based on the above embodiments, as a preferred embodiment, when the output terminal of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in the first state;

[0115] The first input signal is the first digital-to-analog input signal of the gain digital-to-analog circuit;

[0116] The second input signal is the second digital-to-analog input signal added to the digital-to-analog circuit.

[0117] When the output of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in the second state;

[0118] The first input signal is half of the first reference input signal of the gain digital-to-analog circuit;

[0119] The second input signal is half of the second reference input signal of the gain digital-to-analog circuit.

[0120] The gain digital-to-analog circuit includes: the tenth switch, the eleventh switch, the twelfth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, the sixteenth switch, the seventeenth switch, the eighteenth switch, the nineteenth switch, the third sampling capacitor, the fourth sampling capacitor, the fifth sampling capacitor, the sixth sampling capacitor, and the third operational amplifier.

[0121] Among them, the first terminal of the tenth switch is connected to the first digital-to-analog input signal and the first terminal of the eleventh switch, and the second terminal of the tenth switch is connected to the third sampling capacitor and the first terminal of the twelfth switch.

[0122] The second terminal of the eleventh switch is connected to the first terminal of the fourth sampling capacitor;

[0123] The second terminal of the third sampling capacitor is connected to the second terminal of the fourth sampling capacitor and the first input terminal of the third operational amplifier;

[0124] The second terminal of the twelfth switch is connected to the first output terminal of the third operational amplifier;

[0125] The first terminal of the thirteenth switch is connected to the first reference input signal, and the second terminal of the thirteenth switch is connected to the second terminal of the eleventh switch and the first terminal of the fourth sampling capacitor.

[0126] The first terminal of the fourteenth switch is connected to the second reference input signal, and the second terminal of the fourteenth switch is connected to the second terminal of the thirteenth switch, the second terminal of the eleventh switch, and the first terminal of the fourth sampling capacitor.

[0127] The first terminal of the fifteenth switch is connected to the second digital-to-analog input signal and the first terminal of the sixteenth switch. The second terminal of the fifteenth switch is connected to the first terminal of the fifth sampling capacitor, the first terminal of the seventeenth switch, and the tenth switch.

[0128] The second terminal of the sixteenth switch is connected to the first terminal of the sixth sampling capacitor;

[0129] The second terminal of the fifth sampling capacitor is connected to the second terminal of the sixth sampling capacitor and the second input terminal of the third operational amplifier;

[0130] The second terminal of the seventeenth switch is connected to the second output terminal of the third operational amplifier;

[0131] The first terminal of the eighteenth switch is connected to the second reference input signal, and the second terminal of the eighteenth switch is connected to the second terminal of the sixteenth switch and the first terminal of the sixth sampling capacitor.

[0132] The first terminal of the nineteenth switch is connected to the first reference input signal, and the second terminal of the nineteenth switch is connected to the second terminal of the eighteenth switch, the second terminal of the sixteenth switch, and the first terminal of the sixth sampling capacitor.

[0133] The gain digital-to-analog circuit also includes: the twentieth switch, the twenty-first switch, and the twenty-second switch;

[0134] Among them, the first terminal of the twentieth switch is connected to the second terminal of the third sampling capacitor, the second terminal of the fourth sampling capacitor and the first input terminal of the third operational amplifier, and the second terminal of the twentieth switch is connected to the first terminal of the twentieth switch.

[0135] The second terminal of the twenty-first switch is connected to the second terminal of the fifth sampling capacitor, the second terminal of the sixth sampling capacitor, and the second input terminal of the third operational amplifier.

[0136] The first terminal of the 22nd switch is connected to the second terminal of the 12th switch and the first output terminal of the third operational amplifier; the second terminal of the 22nd switch is connected to the second terminal of the 17th switch and the second output terminal of the third operational amplifier.

[0137] Among them, the second terminal of the twentieth switch and the first terminal of the twenty-first switch are the input common-mode points of the gain digital-to-analog circuit.

[0138] In specific embodiments, such as Figure 6As shown, the gain digital-to-analog circuit includes: the tenth switch K10, the eleventh switch K11, the twelfth switch K12, the thirteenth switch K13, the fourteenth switch K14, the fifteenth switch K15, the sixteenth switch K16, the seventeenth switch K17, the eighteenth switch K18, the nineteenth switch K19, the third sampling capacitor C33, the fourth sampling capacitor C44, the fifth sampling capacitor C55, the sixth sampling capacitor C66, the third operational amplifier Q3, the twentieth switch K20, the twenty-first switch K21, and the twenty-second switch K22. The connection relationships of the gain digital-to-analog circuit are as follows: the first terminal of the tenth switch K10 is connected to the first digital-to-analog input signal (INP2) and the first terminal of the eleventh switch K11; the second terminal of the tenth switch K10 is connected to the third sampling capacitor C33 and the first terminal of the twelfth switch K12; the second terminal of the eleventh switch K11 is connected to the first terminal of the fourth sampling capacitor C44; the second terminal of the third sampling capacitor C33, the second terminal of the fourth sampling capacitor C44, and the first input terminal of the third operational amplifier Q3 are connected; the second terminal of the twelfth switch K12 is connected to the first input terminal of the third operational amplifier Q3. The output terminals are connected; the first terminal of the thirteenth switch K13 is connected to the first reference input signal (REFP), and the second terminal of the thirteenth switch K13 is connected to the second terminal of the eleventh switch K11 and the first terminal of the fourth sampling capacitor C44; the first terminal of the fourteenth switch K14 is connected to the second reference input signal (REFN), and the second terminal of the fourteenth switch K14 is connected to the second terminal of the thirteenth switch K13, the second terminal of the eleventh switch K11, and the first terminal of the fourth sampling capacitor C44; the first terminal of the fifteenth switch K15 is connected to the second digital-to-analog input signal (INN2) and the sixteenth switch K16. The first terminal is connected; the second terminal of the fifteenth switch K15 is connected to the first terminal of the fifth sampling capacitor C55 and the first terminal of the seventeenth switch K17; the second terminal of the sixteenth switch K16 is connected to the first terminal of the sixth sampling capacitor C66; the second terminal of the fifth sampling capacitor C55, the second terminal of the sixth sampling capacitor C66, and the second input terminal of the third operational amplifier Q3 are connected; the second terminal of the seventeenth switch K17 is connected to the second output terminal of the third operational amplifier Q3; the first terminal of the eighteenth switch K18 is connected to the second reference input signal (REFN), and the second terminal of the eighteenth switch K18 is connected to the tenth... The second terminal of the sixth switch K16 is connected to the first terminal of the sixth sampling capacitor C66; the first terminal of the nineteenth switch K19 is connected to the first reference input signal (REFP), and the second terminal of the nineteenth switch K19 is connected to the second terminal of the eighteenth switch K18, the second terminal of the sixteenth switch K16, and the first terminal of the sixth sampling capacitor C66; the first terminal of the twentieth switch K20 is connected to the second terminal of the third sampling capacitor C33, the second terminal of the fourth sampling capacitor C44, and the first input terminal of the third operational amplifier Q3, and the second terminal of the twentieth switch K20 is connected to the first terminal of the twenty-first switch K21;The second terminal of the 21st switch K21 is connected to the second terminals of the fifth sampling capacitor C55, the sixth sampling capacitor C66, and the second input terminal of the third operational amplifier Q3; the first terminal of the 22nd switch K22 is connected to the second terminal of the 12th switch K12 and the first output terminal of the third operational amplifier Q3, and the second terminal of the 22nd switch K22 is connected to the second terminal of the 17th switch K17 and the second output terminal of the third operational amplifier Q3; the second terminal of the 20th switch K20 and the first terminal of the 21st switch K21 form the common-mode input point of the gain digital-to-analog circuit, that is, the midpoint between the 20th and 21st switches is the common-mode input point CM2 of the gain digital-to-analog circuit.

[0139] The gain-based analog-to-digital circuit is similar in structure to the sample-and-hold circuit, consisting of a switched-capacitor sampling circuit and an operational amplifier. It has two states: sampling state and holding state. In the sampling state, switches K10, K11, K15, K16, K22, K20, and K21 are closed, while switches K12, K13, K14, K15, K18, and K19 are open. The fourth sampling capacitor C44 samples the first analog-to-digital input signal (INP2), and the sixth sampling capacitor C66 samples the second analog-to-digital input signal (INN2). At the same time, the third sampling capacitor C33 and the fifth sampling capacitor C55 also sample. During this time, the third operational amplifier Q3 is not working. Subsequently, the twentieth switch K20 and the twenty-first switch K21 open first, followed by the tenth switch K10, the eleventh switch K11, the fifteenth switch K15, and the sixteenth switch K16 opening. The twelfth switch K12, the thirteenth switch K13, the fourteenth switch K14, the seventeenth switch K17, the eighteenth switch K18, and the nineteenth switch K19 closing, and the circuit enters a holding state. At this time, the fourth sampling capacitor C44 and the sixth sampling capacitor C66 are connected to the first reference input signal (REFP) and the second reference input signal (REFN), and the feedback path is activated. The third sampling capacitor and the fifth sampling capacitor act as feedback capacitors, and the third operational amplifier operates. Through charge conservation in the two states at the bottom plate, the following equation can be derived:

[0140] 2×(V CM2 -V INP2 )×C=(V - -V OUTP2 )×C+(V - -V REFP )×C;

[0141] 2×(V CM2 -V INN2 )×C=(V + -VOUTN2 )×C+(V + -V REFN )×C;

[0142] Adding the two equations together, we get:

[0143]

[0144] Among them, V CM2 The common-mode voltage sampled for the bottom plate is set; V INP2 V is the voltage corresponding to the first digital-to-analog input signal. INN2 V represents the voltage corresponding to the second digital-to-analog input signal; C represents the capacitance of the fourth sampling capacitor C44 and the sixth sampling capacitor C66; REFP V is the voltage corresponding to the first reference input signal. REFN V is the voltage corresponding to the second reference input signal. - This refers to the voltage core at the first input terminal of the third operational amplifier Q3 and the voltage at the negative input terminal of the first operational amplifier Q1; V + V represents the voltage at the second input terminal of the third operational amplifier Q3 and the voltage at the positive input terminal of the first operational amplifier Q1; OUTP2 V is the voltage at the first output terminal of the third operational amplifier Q3; OUTN2 V is the voltage at the second output terminal of the third operational amplifier. OP2,CM2 V is the voltage at the input common-mode point CM2 of the gain digital-to-analog circuit; IN2,CM2 V is the common-mode voltage of the first analog-to-digital input signal INP2 and the second analog-to-digital input signal INN2. OUT2,CM2 This is the common-mode voltage at the output of the third operational amplifier Q2. It can be seen that the voltage at the input common-mode point of the third operational amplifier Q3 is closely related to the input signal and the reference voltage. A special reference voltage value may cause the input common-mode point of the operational amplifier to be too high or too low, thereby affecting the performance of the operational amplifier.

[0145] Therefore, a voltage generation circuit is connected at the input common-mode point CM2 of the gain digital-to-analog circuit, that is, the output terminal of the first operational amplifier is connected to the input common-mode point CM2 of the gain digital-to-analog circuit. At this time, the voltage generation circuit also has two states. For example... Figure 6 As shown, the circuit state at this time is that the voltage generating circuit is in the first state, that is, the first switch K1 is open and the second switch K2 is closed. At this time, the first input signal is the first digital-to-analog input signal INP2 of the gain digital-to-analog circuit; the second input signal is the second digital-to-analog input signal INN2 of the gain digital-to-analog circuit. Figure 7As shown, the circuit state at this time is that the voltage generation circuit is in the second state, that is, the first switch K1 is closed and the second switch K2 is open. At this time, the first input signal is half of the first reference input signal of the gain digital-to-analog circuit, and the second input signal is half of the second reference input signal of the gain digital-to-analog circuit. When the first switch K1 is open and the second switch K2 is closed, the voltage generation circuit is in the first state. At this time, the output voltage of the first operational amplifier Q1 is transferred to the bottom plate in the form of charge. When the first switch K1 is closed and the second switch K2 is open, the voltage generation circuit is in the second state. At this time, the output signal of the first operational amplifier Q1 stored on the bottom plate in the previous state is fed back to the negative input terminal of the first operational amplifier Q1, forming negative feedback. In the steady state, due to the existence of the negative feedback loop, the voltage at the input terminal of the first operational amplifier satisfies: V + +V - =V CM2 Based on the charge conservation in both states, we can obtain the following expression:

[0146]

[0147] Due to V + +V - =V CM2 Simplifying the above formula, we get:

[0148]

[0149] And because of V CM2 =V OUT2 Therefore, we can conclude that:

[0150]

[0151] Among them, V OUT2 The voltage at the output terminal of the first operational amplifier Q1, which is connected to the gain digital-to-analog circuit, shows that this application, through the added voltage generation circuit, makes the input common-mode level of the third operational amplifier independent of the common-mode voltage of the input signal and the voltage of the reference signal. The output common-mode voltage can be adjusted by the designer, so that the voltage at the common-mode input terminal of the third operational amplifier falls within a suitable range.

[0152] In summary, the sample-and-hold circuit is typically used as the first stage of a pipelined ADC to directly face the input signal. However, the common-mode voltage of the input signal is often not fixed. Under different input common-mode voltages, the performance of traditional sample-and-hold circuits will be affected. This application can eliminate the influence of the input signal common-mode voltage on the operational amplifier's input common-mode voltage in the sample-and-hold circuit, thereby reducing the fluctuation of the operational amplifier's performance and stabilizing the overall performance of the sample-and-hold circuit. Similarly, in gain-based digital-to-analog circuits, if the reference voltage is set to a special value, using a traditional circuit structure, the operational amplifier's input common-mode point may exist in an unreasonable range. This application can also avoid this phenomenon. Since a pipelined ADC structure often includes a sample-and-hold circuit and several gain-based digital-to-analog units, this voltage generation circuit can widely solve the problem of the operational amplifier's input common-mode point.

[0153] This application provides a voltage generation circuit, comprising: a first operational amplifier, a first switch, a second switch, and a feedback capacitor; a first terminal of the feedback capacitor is connected to an input signal, and a second terminal of the feedback circuit is connected to the first terminal of the first switch and the first terminal of the second switch; the negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to a first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch, the input common-mode point of the sample-and-hold circuit, and / or the input common-mode point of the gain-digital-analog circuit. It is evident that the voltage generation circuit provided in this application is connected to the sample-and-hold circuit and / or the gain-digital-analog circuit. The states of different switches in the voltage generation circuit will cause changes in the state of the voltage generation circuit. Based on these changes, and following the law of conservation of charge, combined with the law of conservation of charge in the sample-and-hold circuit and / or the gain-digital-analog circuit, the influence of the input signal and reference voltage in the sample-and-hold circuit and / or the gain-digital-analog circuit on the input common-mode point of the operational amplifier will be eliminated, thereby improving the performance of the pipelined ADC.

[0154] The voltage generating circuit provided in this application has been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0155] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A voltage generating circuit, characterized in that, include: First operational amplifier, first switch, second switch, and feedback capacitor; The first end of the feedback capacitor is connected to the input signal, and the second end of the feedback capacitor is connected to the first end of the first switch and the first end of the second switch. The negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to the first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch and the input common-mode point of the sample-and-hold circuit. The feedback capacitor includes: a first feedback capacitor and a second feedback capacitor; The first end of the first feedback capacitor is connected to the first input signal, and the second end of the first feedback capacitor is connected to the first end of the first switch and the first end of the second switch. The first end of the second feedback capacitor is connected to the second input signal, and the second end of the second feedback capacitor is connected to the second end of the first feedback capacitor, the first end of the first switch, and the first end of the second switch. The sample-and-hold circuit includes: a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, a second operational amplifier, a seventh switch, an eighth switch, and a ninth switch; The first terminal of the third switch is connected to the first sampling input signal, and the second terminal of the third switch is connected to the first terminal of the first sampling capacitor and the first terminal of the fourth switch. The second terminal of the first sampling capacitor is connected to the first input terminal of the second operational amplifier and the first terminal of the seventh switch; The second end of the seventh switch is connected to the first end of the eighth switch; The second terminal of the fourth switch is connected to the first output terminal of the second operational amplifier and the first terminal of the ninth switch; The first terminal of the fifth switch is connected to the second sampling input signal, and the second terminal of the fifth switch is connected to the first terminal of the second sampling capacitor and the first terminal of the sixth switch. The second terminal of the second sampling capacitor is connected to the second input terminal of the second operational amplifier and the second terminal of the eighth switch; The second terminal of the sixth switch is connected to the second output terminal of the second operational amplifier and the second terminal of the ninth switch; Wherein, the second terminal of the seventh switch and the first terminal of the eighth switch are the input common-mode points of the sample-and-hold circuit; When the output of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in a first state, wherein the first state indicates that the first switch is open and the second switch is closed; The first input signal is the first sampling input signal of the sample-and-hold circuit, and the second input signal is the second sampling input signal of the sample-and-hold circuit. When the output of the first operational amplifier is connected to the input common-mode point of the sample-and-hold circuit and is in the second state, the second state indicates that the first switch is closed and the second switch is open. The first input signal is a second preset power signal; The second input signal is a third preset power signal; According to the charge conservation law of the first and second states of the sample-and-hold circuit, we can obtain: ； in, The voltage at the input common-mode point of the sample-and-hold circuit; This is the common-mode voltage at the output of the second operational amplifier.

2. A voltage generating circuit, characterized in that, include: First operational amplifier, first switch, second switch, and feedback capacitor; The first end of the feedback capacitor is connected to the input signal, and the second end of the feedback capacitor is connected to the first end of the first switch and the first end of the second switch. The negative input terminal of the first operational amplifier is connected to the second terminal of the first switch, the positive input terminal of the first operational amplifier is connected to the first preset power supply signal, and the output terminal of the first operational amplifier is connected to the second terminal of the second switch and the input common-mode point of the gain digital-to-analog circuit. The feedback capacitor includes: a first feedback capacitor and a second feedback capacitor; The first end of the first feedback capacitor is connected to the first input signal, and the second end of the first feedback capacitor is connected to the first end of the first switch and the first end of the second switch. The first end of the second feedback capacitor is connected to the second input signal, and the second end of the second feedback capacitor is connected to the second end of the first feedback capacitor, the first end of the first switch, and the first end of the second switch. The gain digital-to-analog circuit includes: a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a third sampling capacitor, a fourth sampling capacitor, a fifth sampling capacitor, a sixth sampling capacitor, a third operational amplifier, a twentieth switch, a twenty-first switch, and a twenty-second switch. Wherein, the first terminal of the tenth switch is connected to the first digital-to-analog input signal and the first terminal of the eleventh switch, and the second terminal of the tenth switch is connected to the third sampling capacitor and the first terminal of the twelfth switch; The second terminal of the eleventh switch is connected to the first terminal of the fourth sampling capacitor; The second terminal of the third sampling capacitor is connected to the second terminal of the fourth sampling capacitor, the first input terminal of the third operational amplifier, and the first terminal of the twentieth switch. The second terminal of the twentieth switch is connected to the first terminal of the twentieth eleventh switch; The second terminal of the twelfth switch is connected to the first output terminal of the third operational amplifier and the first terminal of the twelfth switch. The first terminal of the thirteenth switch is connected to the first reference input signal, and the second terminal of the thirteenth switch is connected to the second terminal of the eleventh switch and the first terminal of the fourth sampling capacitor. The first terminal of the fourteenth switch is connected to the second reference input signal, and the second terminal of the fourteenth switch is connected to the second terminal of the thirteenth switch, the second terminal of the eleventh switch, and the first terminal of the fourth sampling capacitor. The first terminal of the fifteenth switch is connected to the second digital-to-analog input signal and the first terminal of the sixteenth switch, and the second terminal of the fifteenth switch is connected to the first terminal of the fifth sampling capacitor and the first terminal of the seventeenth switch; The second terminal of the sixteenth switch is connected to the first terminal of the sixth sampling capacitor; The second terminal of the fifth sampling capacitor is connected to the second terminal of the sixth sampling capacitor, the second input terminal of the third operational amplifier, and the second terminal of the twenty-first switch; The second terminal of the seventeenth switch is connected to the second output terminal of the third operational amplifier and the second terminal of the twenty-second switch; The first terminal of the eighteenth switch is connected to the second reference input signal, and the second terminal of the eighteenth switch is connected to the second terminal of the sixteenth switch and the first terminal of the sixth sampling capacitor. The first terminal of the nineteenth switch is connected to the first reference input signal, and the second terminal of the nineteenth switch is connected to the second terminal of the eighteenth switch, the second terminal of the sixteenth switch, and the first terminal of the sixth sampling capacitor. Wherein, the second terminal of the twentieth switch and the first terminal of the twentieth eleventh switch are the input common-mode points of the gain digital-to-analog circuit; When the output of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in a first state, wherein the first state indicates that the first switch is open and the second switch is closed; the first input signal is the first digital-to-analog input signal of the gain digital-to-analog circuit. The second input signal is the second digital-to-analog input signal of the gain digital-to-analog circuit; When the output terminal of the first operational amplifier is connected to the input common-mode point of the gain digital-to-analog circuit and is in the second state, wherein the second state indicates that the first switch is closed and the second switch is open; the first input signal is half of the first reference input signal of the gain digital-to-analog circuit; and the second input signal is half of the second reference input signal of the gain digital-to-analog circuit. According to the charge conservation law of the first and second states of the gain digital-to-analog circuit, we can obtain: ； in, The voltage at the input common-mode point of the gain digital-to-analog circuit; The common-mode voltage is sampled for the bottom plate. This refers to the common-mode voltage at the output of the third operational amplifier.

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