A hybrid architecture analog-to-digital converter
By combining a first-order feedforward incremental ΔΣ ADC and a single-stage cyclic ADC in a hybrid ADC structure, the input signal is directly fed to the comparator and reset at the common-mode level, solving the problems of slow speed and low signal-to-noise ratio of traditional hybrid ADC structures, and achieving high signal-to-noise ratio and fast conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NORTHWESTERN POLYTECHNICAL UNIV
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-23
AI Technical Summary
Traditional hybrid ADCs have slow conversion speeds and low signal-to-noise ratios, mainly due to the slow speed of traditional incremental ΔΣ ADCs and the influence of non-ideal factors on the input signal when passing through the modulator loop.
A first-order feedforward incremental ΔΣ ADC is used to achieve 7-bit coarse quantization and a single-stage cyclolic ADC to achieve 8-bit fine quantization. By directly feeding the input signal at the comparator input and resetting it to the common-mode level during the integration and non-sampling stages, combined with two sets of two-phase non-overlapping clocks and delayed clock control, efficient switching of module functions is achieved.
The signal-to-noise ratio was improved and the conversion rate was significantly increased. The overall conversion cycle was reduced from 265 clock cycles to 139 clock cycles. The number of clock cycles was greatly reduced, which improved the overall conversion rate of the ADC.
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Figure CN122268362A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology, and specifically relates to a hybrid structure analog-to-digital converter. Background Technology
[0002] In applications such as radiation detectors, particle detectors, and image sensors, high resolution, low power consumption, and small-area multi-channel architecture are the future trends for analog-to-digital converters (ADCs). Due to their high cost and power consumption, traditional discrete-device-based electronic systems are no longer suitable for large-scale readout circuits in radiation detection. Dedicated high-precision, low-power, small-area multi-channel ADC chips have become a research hotspot. To address these issues, researchers have proposed methods such as reusing circuit modules and reducing analog circuitry to decrease the area and power consumption of the front-end system. Furthermore, given the requirements of high-energy-resolution multi-channel front-end readout systems, the optimized design of high-resolution multi-channel ADC chip architecture is a critical issue that urgently needs to be addressed. Hybrid ADCs can leverage the advantages of various ADC structures while overcoming the disadvantages of single ADC structures, and can share some circuit modules, saving power and area.
[0003] Reference Figure 1-4 The paper “Z. Zhang et al., “A low-power 14-bit two-stage hybrid ADC for infrared focal plane array detector,” 2016 IEEE Information Technology, Networking, Electronic and Automation Control Conference, Chongqing, China, 2016, pp. 386-390, doi: 10.1109 / ITNEC.2016.7560387.” discloses a 14-bit 10KS / s hybrid analog-to-digital converter. (See attached reference.) Figure 1 This analog-to-digital converter (ADC) employs a two-stage hybrid architecture. The first stage includes an incremental ΔΣ ADC, a digital filter, and a latch, achieving M-bit coarse quantization. The second stage includes a cyclic ADC and a shift register, achieving N-bit fine quantization. Since the output voltage of the first stage serves as the input voltage of the second stage, a redundant bit is provided between the two stages. Therefore, the final quantization bit length of the hybrid ADC is the sum of the M-bit quantized by the incremental ΔΣ ADC in the first stage and the N-bit quantized by the cyclic ADC, with one bit added to the result, i.e., M + N - 1 bits. (Appendix) Figure 2This is the circuit schematic of the mixed analog-to-digital converter, attached. Figure 3 This is the timing diagram of the mixed-signal analog-to-digital converter (ADC). The circuit first resets after two clock cycles. Then, the first-stage incremental ΔΣ ADC circuit begins operation, including sampling and integration, achieving 8-bit quantization after 256 clock cycles. Next, the second-stage cycloidal ADC begins operation, completing 7-bit quantization after 7 clock cycles. The ADC requires 265 clock cycles to complete one full conversion. The ADC's main clock frequency is 2.5 MHz, therefore the ADC conversion rate is 9.43 KS / s. (Attached) Figure 4 The output signal spectrum of the ADC is shown when the input signal frequency is a sine wave with a frequency of 300 Hz. The signal-to-noise ratio of the ADC is 84.686 dB and the effective bit is 13.77 bits.
[0004] Based on the timing diagram and spectrum of the ADC circuit above, it can be seen that to implement a 14-bit hybrid ADC using a traditional first-order incremental ΔΣ ADC for coarse quantization, the input signal passes through a modulator loop. Non-ideal factors in the modulator loop may affect the input signal, thus reducing the signal-to-noise ratio. Furthermore, after each sampling comparison, charge may accumulate on the parasitic capacitance of the traces at the comparator input, leading to a reduction in the effective bits of the overall circuit. Moreover, using a first-order incremental ΔΣ ADC to achieve 8-bit coarse quantization and a single-stage cyclolic ADC to achieve 7-bit fine quantization requires a total of 265 conversion cycles, resulting in a relatively slow overall ADC conversion speed. Summary of the Invention
[0005] To address the issues of slow speed and low signal-to-noise ratio when using traditional incremental ΔΣ ADCs in hybrid ADC structures, this invention provides a hybrid ADC structure, specifically a hybrid ADC structure that employs a first-order feedforward incremental ΔΣ ADC to achieve 7-bit coarse quantization and a single-stage cyclic ADC to achieve 8-bit fine quantization.
[0006] To achieve the above objectives, the present invention provides the following technical solution: A hybrid structure analog-to-digital converter (ADC) is provided, which is based on a traditional 14-bit hybrid ADC. The 8-bit incremental ΔΣ ADC and 7-bit cyclic ADC of the traditional 14-bit hybrid ADC are replaced with a 7-bit first-order feedforward incremental ΔΣ ADC and an 8-bit single-stage cyclic ADC, respectively. Specifically, the 7-bit first-order feedforward incremental ΔΣ ADC is formed by adding a feedforward path to the 7-bit incremental ΔΣ ADC, so that the input signal is directly fed to the comparator input terminal for comparison. The comparator input is reset to the common-mode level VCM during the Incremental ΔΣ ADC integration phase and the Cyclic ADC non-sampling phase. The 7-bit first-order feedforward incremental ΔΣ ADC and the 8-bit single-stage cycloidal ADC are controlled by two sets of two-phase non-overlapping clocks and delayed clocks to achieve module function switching in different modes.
[0007] Preferably, the feedforward path includes two sets of capacitors C4 and C5, which are distributed in differential pairs on both sides of the positive and negative input terminals of the comparator. One end of each of the two capacitors C5 is connected to a common-mode level VCM, and the other end is connected to one end of each of the two capacitors C4 and then connected to the positive and negative input terminals of the comparator, respectively. The other ends of the two capacitors C4 are connected to the positive differential analog input terminal VIP and the negative differential analog input terminal VIN, respectively, and the input signal is directly fed to the comparator input terminal for comparison through the feedforward path.
[0008] Preferably, the 7-bit first-order feedforward incremental ΔΣ ADC further includes a switched-capacitor integrator, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a first-order digital filter. The input signal is directly fed to the comparator input of the 1.5-bit sub-ADC via the feedforward path. The switched-capacitor integrator is connected to the 1.5-bit sub-ADC and the 1.5-bit sub-DAC. The 1.5-bit sub-DAC outputs a feedback voltage to the switched-capacitor integrator based on the comparison result of the 1.5-bit sub-ADC. The output of the switched-capacitor integrator is connected to the first-order digital filter. The amplifier output of the 7-bit first-order feedforward incremental ΔΣ ADC is a margin voltage output, which is connected to the input of the 8-bit single-stage cyclolic ADC.
[0009] Preferably, the 8-bit single-stage Cyclic ADC includes a 2x amplifier circuit, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a shift register; the margin voltage output of the 7-bit first-order feedforward incremental ΔΣ ADC is connected to the input of the ADC, and then sequentially connected to the 2x amplifier circuit and the 1.5-bit sub-ADC. The 1.5-bit sub-DAC outputs a feedback voltage to the 2x amplifier circuit based on the comparison result of the 1.5-bit sub-ADC. The output of the 2x amplifier circuit is fed back to its own input and is also connected to the shift register; the 7-bit first-order feedforward incremental ΔΣ ADC and the 8-bit single-stage Cyclic ADC multiplex the sampling / integration / amplification capacitor bank, the 1.5-bit sub-ADC, the 1.5-bit sub-DAC, the comparator, and the amplifier.
[0010] Preferably, the sampling / integration / amplification capacitor bank includes a sampling capacitor C1 and integration capacitors C2 and C3. The sampling capacitor C1 completes the charge storage during the sampling stage, and C1 also provides charge for the feedforward branch and the integration branch. The integration capacitors C2 and C3 are connected between the input and output terminals of the amplifier to complete the charge transfer and signal integration during the integration stage.
[0011] Preferably, during the sampling phase, the input differential signals VIP and VIN are directly connected to capacitor C4 in the feedforward path, while capacitor C5 is connected to the output of the amplifier that has undergone the first integration of the common-mode level VCM. By applying the law of conservation of charge, the input signal is directly fed to the positive and negative input terminals of the comparator, forming a physical path for the input signal to reach the input terminal of the 1.5-bit sub-ADC comparator without passing through the modulator loop. Furthermore, the feedforward path remains on during each sampling phase, and the input signal continuously participates in the comparison and determination of the comparator through this path.
[0012] Preferably, the reset clock CLK_RST of the hybrid structure analog-to-digital converter is connected to the reset switch of capacitor bank C1-C5, the reset terminal of the amplifier, and the reset terminal of the comparator, so as to reset the capacitors, amplifier, and comparator before each analog-to-digital conversion.
[0013] Preferably, the hybrid analog-to-digital converter adopts a two-stage hybrid structure. Before the overall conversion begins, the circuit is reset after two clock cycles. Then, the 7-bit first-order feedforward incremental ΔΣ ADC is processed by 2... 7An oversampling rate of 128 is obtained in one clock cycle. Oversampling and noise shaping techniques are used to achieve 7-bit quantization, and the input signal is directly fed to the comparator input during each sampling. After 7-bit coarse quantization, a margin voltage is obtained, which serves as the input signal of the Cyclic ADC. The 8-bit single-stage Cyclic ADC achieves 8-bit quantization in 8 clock cycles, and after one clock cycle after quantization, a resolution of 7 + 8 - 1 = 14 bits is achieved through digital interconnect circuitry.
[0014] Preferably, the two sets of non-overlapping two-phase clocks are DS and DI, CS and CA, and the two sets of non-overlapping two-phase delayed clocks are DSd and DId, CSd and CAd, respectively. In Incremental mode, clocks DS / DSd and DI / DId are valid, and the feedforward path and the modulator's integration loop operate in a time-division multiplexing manner. During the sampling phase, DS / DSd is high, and the feedforward path, sampling capacitor C1, comparator, and 1.5-bit sub-DAC form a connection path. The input signal is sampled by sampling capacitor C1, and simultaneously, the input signal is directly fed into the comparator via feedforward summing circuit capacitors C4 / C5. The quantization result of the sampled signal by the comparator is directly transmitted to the 1.5-bit sub-DAC. During the integration phase, DI / DId is high, the input of the comparator is reset to the common-mode level VCM, the feedforward path stops working, and sampling capacitor C1, integration capacitors C2 / C3, amplifier, and 1.5-bit sub-DAC form an independent modulator integration loop. The sub-DAC outputs the corresponding feedback voltage based on the quantization result. The charge on the sampling capacitor C1 is transferred to the integrating capacitors C2 / C3. The switched capacitor integrator with the amplifier as its core completes the integration operation on the difference between the input signal and the feedback voltage, and completes the integration accumulation of the difference signal. At this time, the integrated residual voltage at the amplifier output is ready for the next sampling. In Cyclic mode, clocks CS / CSd and CA / CAd are active, the feedforward path stops working, and the amplifier is the core, which, together with the multiplexed capacitors C1 / C3 and the clock-controlled switching transistors of CA / CAd, forms a 2x amplifier circuit. A 1.5-bit sub-ADC / sub-DAC provides quantization and feedback support for it. During the sampling phase, CS / CSd is high, and the margin voltage output in Incremental mode is directly used as the input of the Cyclic ADC. Under the control of the CS / CSd clock, capacitors C1 / C3 complete the charge sampling of the margin voltage. The comparator directly receives the margin voltage output from the amplifier and completes the quantization. The result is transmitted to the 1.5-bit sub-DAC in real time. During the amplification phase, CA / CAd is high, and the 1.5-bit sub-DAC outputs a feedback voltage. The amplifier achieves 2x amplification through C1 / C3. The amplified margin voltage is used as the input for the next sampling, until 8 sampling-amplification iterations are completed. The quantization result of each cycle is transmitted to the shift register in real time. Finally, the shift register performs shifting and addition to output an 8-bit fine quantization code.
[0015] The hybrid structure analog-to-digital converter provided by this invention has the following beneficial effects: The incremental ΔΣ ADC of this invention adopts a first-order feedforward structure, directly feeding the input signal to the comparator input for comparison. This avoids the input signal passing through the modulator loop, thus preventing the influence of non-ideal factors in the modulator loop on the input signal. Furthermore, the comparator input is connected to the common-mode level during the integral phase of the incremental ΔΣ ADC and the non-sampling phase of the cyclolic ADC, eliminating the influence of different discharge rates of parasitic capacitance at the comparator input after each sampling comparison, thereby improving the signal-to-noise ratio. Moreover, the first-order feedforward incremental ΔΣ ADC achieves 7-bit coarse quantization, and a single-stage cyclolic ADC achieves 8-bit fine quantization. Two sets of two-phase non-overlapping clocks and corresponding delayed clocks time-division control the two-stage ADC, enabling efficient switching of module functions and significantly reducing the overall conversion cycle to 139 clock cycles. This substantial reduction in clock cycles greatly improves the overall conversion rate of the ADC. Attached Figure Description
[0016] To more clearly illustrate the embodiments and design schemes of the present invention, the accompanying drawings required for this embodiment will be briefly described below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a block diagram of a mixed-signal analog-to-digital converter (ADC) combining a traditional incremental ΔΣ ADC and a Cyclic ADC. Figure 2 yes Figure 1 Schematic diagram of a mixed analog-to-digital converter (ADC) combining traditional incremental ΔΣ ADC and Cyclic ADC; Figure 3yes Figure 2 Timing diagram of an analog-to-digital converter; Figure 4 yes Figure 2 Output spectrum of the analog-to-digital converter; Figure 5 This is a schematic diagram of a hybrid analog-to-digital converter circuit combining a first-order feedforward incremental ΔΣ ADC and a single-stage Cyclic ADC, provided by the present invention. Figure 6 This is a timing diagram of the hybrid structure analog-to-digital converter provided by the present invention; Figure 7 This is a schematic diagram of the hybrid structure analog-to-digital converter provided by the present invention operating in Incremental mode; Figure 8 This is a schematic diagram of the hybrid structure analog-to-digital converter provided by the present invention operating in Cyclic mode; Figure 9 This is the output spectrum diagram of the hybrid structure analog-to-digital converter provided by the present invention. Detailed Implementation
[0018] To enable those skilled in the art to better understand and implement the technical solutions of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.
[0019] For traditional hybrid analog-to-digital converters (ADCs), the input signal of a first-order incremental ΔΣ ADC is not directly fed to the comparator input but enters the modulator loop. Non-ideal factors in the modulator loop can affect the input signal. Furthermore, after each sampling comparison, the comparator input is disconnected and discharges through parasitic capacitance on the traces. However, during layout design, it's impossible to guarantee that the traces at the two comparator inputs are perfectly aligned, leading to different voltage changes at both ends and consequently a decrease in the ADC's signal-to-noise ratio. Moreover, the first-order incremental ΔΣ ADC achieves M-bit quantization, requiring 2... M Because it takes one clock cycle, when used as a single-stage ADC in a hybrid analog-to-digital converter, the appropriate number of quantization bits must be selected by considering speed, accuracy, area, and power consumption.
[0020] Based on this, such as Figure 5As shown, the hybrid analog-to-digital converter (ADC) provided by this invention is based on a traditional 14-bit hybrid ADC. The 8-bit incremental ΔΣ ADC and 7-bit cyclic ADC of the traditional 14-bit hybrid ADC are replaced with a 7-bit first-order feedforward incremental ΔΣ ADC and an 8-bit single-stage cyclic ADC, respectively. The 7-bit first-order feedforward incremental ΔΣ ADC and the 8-bit single-stage cyclic ADC constitute a two-stage ADC. Simultaneously, the hybrid ADC of this invention also includes a differential input port, a sampling / integration / amplification capacitor bank, an amplifier, two comparators, digital processing and interfacing components, and a clock control component.
[0021] Specifically, the differential input port has a positive differential analog input terminal VIP and a negative differential analog input terminal VIN, which are the input sources of analog signals.
[0022] The sampling / integration / amplification capacitor bank includes C1 and integrating capacitors C2 and C3. Sampling capacitor C1 stores charge during the sampling phase and simultaneously provides charge to both the feedforward and integration branches. Integrating capacitors C2 and C3 are connected between the amplifier's input and output terminals, completing charge transfer and signal integration during the integration phase. In Incremental mode (7-bit first-order feedforward Incremental ΔΣ ADC), C1 is the sampling capacitor, responsible for sampling the input signal and storing charge. C2 and C3 are the integrating capacitors, receiving the charge transferred from C1 during the integration phase and completing the signal integration operation; they are the core capacitor components for achieving 7-bit coarse quantization. In Cyclic mode (8-bit single-stage Cyclic ADC operating phase): After the Incremental ΔΣ ADC completes coarse quantization, it outputs a margin voltage. At this time, C1 and C3 are multiplexed by the Cyclic ADC as the core capacitors for its sampling and amplification phases, participating in the sampling of the margin voltage and the 2x amplification operation. C2 also switches to the Cyclic mode operating logic along with the overall circuit.
[0023] The amplifier is used to amplify the signal and output a margin voltage, and is the core module of the two-stage ADC multiplexing. In this embodiment, the amplifier is a fully differential operational amplifier, which is the core analog gain component of the two-stage ADC. Its input is connected to the sampling capacitor C1, the feedforward path, and the 1.5-bit sub-DAC output. Its output is connected to the integrating capacitors C2 / C3 and the sampling terminal of the Cyclic ADC. At the same time, it outputs a margin voltage to the comparator. In Incremental mode, it implements the integration function, and in Cyclic mode, it implements the 2x amplification function.
[0024] Two comparators serve as multiplexed modules for the ΔΣ ADC and Cyclic ADC. Their inputs are connected to the outputs of the feedforward path and the amplifier, while their outputs are connected to the input of a 1.5-bit sub-ADC to perform signal level comparison and decision. Their inputs are also connected to the common-mode voltage (VCM) to support reset operations in non-operating states. In Incremental mode, the two comparators perform a 1.5-bit successive comparison of the sampled signal, providing the basic digital result for coarse quantization. In Cyclic mode, they perform a 1.5-bit successive comparison of the margin voltage, providing the basic digital result for fine quantization. The operating logic and threshold settings of the two comparators are completely identical in both modes. During non-sampling phases (the integration phase of the ΔΣ ADC and the gap between the amplification phases of the Cyclic ADC), they are reset to the common-mode voltage, eliminating inconsistencies in voltage changes caused by input trace mismatches and avoiding charge residue from the previous stage or crosstalk. This ensures the quantization accuracy of both 7-bit coarse quantization and 8-bit fine quantization while saving circuit power and area, meeting the design requirements of high resolution and low power consumption. Ultimately, while maintaining the total resolution at 14 bits, the signal-to-noise ratio (SNR) was significantly improved and the conversion rate was optimized.
[0025] Two comparators, paired with a fixed threshold voltage source (±0.25Vref), form a 1.5-bit sub-ADC, which is the core analog hardware for implementing 1.5-bit threshold quantization. A reference voltage source (VREFP=1.8V, VREFN=0V, VCM=0.9V), a switching transistor array, and a multiplexed capacitor bank form a 1.5-bit sub-DAC, which is the conversion carrier between digital code and analog feedback voltage. The 1.5-bit sub-DAC outputs the feedback voltage VREF based on the comparator results, completing the charge feedback during the integration phase.
[0026] The clock control unit includes a reset clock CLK_RST, a mode control clock DM, and two sets of two-phase non-overlapping clocks (DS / DI, CS / CA) and corresponding delay clocks (DSd / DId, CSd / CAd). All clock outputs are connected to the clock control terminals of the capacitor bank switches, amplifiers, comparators, and sub-ADCs / sub-DACs, respectively, to achieve timing coordination and mode switching of each component. At the same time, the delay clock eliminates channel charge injection errors.
[0027] Based on the above structural foundation, such as Figure 7As shown, the 7-bit first-order feedforward incremental ΔΣ ADC includes a feedforward path, a switched-capacitor integrator, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a first-order digital filter. The feedforward path includes two sets of capacitors C4 and C5, which are distributed in differential pairs on both sides of the positive and negative input terminals of the comparator. One end of each capacitor C5 is connected to a common-mode level VCM, and the other end is combined with one end of each capacitor C4 and then connected to the positive and negative input terminals of the comparator, respectively. The other ends of each capacitor C4 are connected to the positive differential analog input terminal VIP and the negative differential analog input terminal VIN, respectively, and the input signal is directly fed to the comparator input terminal for comparison through the feedforward path. During the sampling phase, the input differential signals VIP and VIN are directly connected to capacitor C4 in the feedforward path, while capacitor C5 is connected to the output of the amplifier that has undergone the first integration of the common-mode level VCM. By applying the law of charge conservation, the input signals are directly fed to the positive and negative inputs of the comparator, forming a physical path that allows the input signals to reach the input of the 1.5-bit sub-ADC comparator without passing through the modulator loop. Furthermore, the feedforward path remains active during each sampling phase, ensuring that the input signals continuously participate in the comparator's comparison and determination process.
[0028] The switched-capacitor integrator consists of capacitors C1 to C3, switches DS / DSd and DI / DId controlled by a dedicated clock for Incremental mode, and a multiplexed amplifier. The input signal is directly fed to the comparator input of the 1.5-bit sub-ADC via a feedforward path. The switched-capacitor integrator forms a closed-loop connection with the 1.5-bit sub-ADC and 1.5-bit sub-DAC. The 1.5-bit sub-DAC outputs a feedback voltage to the switched-capacitor integrator based on the comparison result of the 1.5-bit sub-ADC. The output of the switched-capacitor integrator is connected to a first-order digital filter. The amplifier output of the 7-bit first-order feedforward Incremental ΔΣ ADC serves as the margin voltage output, connected to the input of the 8-bit single-stage Cyclic ADC. The 7-bit first-order feedforward Incremental ΔΣ ADC, by adding a feedforward path in the loop, directly feeds the input signal to the comparator input, reducing the impact of non-ideal factors in the modulator loop on the input signal.
[0029] like Figure 8As shown, the 8-bit single-stage Cyclic ADC also includes a 2x amplifier circuit, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a shift register; the dedicated clock control switches for Cyclic mode are CS / CSd and CA / CAd; among them, CS / CSd is a two-phase non-overlapping clock driven switch during the sampling phase in Cyclic mode, and CSd is the delayed clock of CS. CSd is turned on first, and then CS is turned on, and vice versa when turned off, and the two have no conduction overlap; the other clock control switches in this embodiment can be understood with reference to CS / CSd. The margin voltage output of the 7-bit first-order feedforward incremental ΔΣ ADC is connected to the input of the ADC. After being processed by a 2x amplification circuit, it is sent to a 1.5-bit sub-ADC for quantization. The 1.5-bit sub-DAC outputs a feedback voltage to the 2x amplification circuit based on the comparison result of the 1.5-bit sub-ADC. The 2x amplification circuit amplifies the margin voltage, i.e., the result of the DAC feedback voltage, as the input for the next quantization (forming a closed loop of successive iterations). At the same time, the intermediate result of each quantization is transmitted to the shift register. Finally, the shift register outputs an 8-bit finely quantized digital code.
[0030] The most crucial circuit module in a Cyclic ADC is the precision 2x amplifier circuit. However, Cyclic ADCs lack noise shaping capabilities, meaning the noise introduced by the amplifier is amplified by a factor of two with each conversion cycle. This amplifier-introduced noise increases exponentially with the Cyclic ADC resolution; therefore, higher Cyclic ADC resolution places higher demands on amplifier design. Considering constraints such as speed, accuracy, area, power consumption, and circuit design complexity, this invention selects a first-order feedforward incremental ΔΣ ADC to achieve 7-bit coarse quantization, reducing the incremental ΔΣ ADC conversion clock cycle to 2... 7 The Cyclic ADC implements 8-bit fine quantization, and the Cyclic ADC conversion clock cycle is 8. Including the reset before each conversion and the connection of the digital codes output by the two ADC stages after conversion, a total of only 139 clock cycles are needed, with each clock cycle being 250 ns and the main clock frequency being 4 MHz.
[0031] The digital processing and connection components include a first-order digital filter on the Incremental ΔΣ ADC side, a shift register on the Cyclic ADC side, and a digital connection circuit. The output of the digital filter is connected to the high-order input port of the digital connection circuit, and the output of the shift register is connected to the low-order input port of the digital connection circuit. The digital connection circuit finally outputs a 14-bit complete digital code D13~D0.
[0032] Meanwhile, this embodiment uses the common-mode level VCM as the circuit reference level to provide a reference for the amplifier and comparator. The comparator input is reset to the common-mode level VCM during the Incremental ΔΣ ADC integration phase and the Cyclic ADC non-sampling phase. The two-stage ADC reuses hardware modules such as sampling / integration / amplification capacitor banks, 1.5-bit sub-ADC, 1.5-bit sub-DAC, comparator, and amplifier. The two-stage ADC uses two sets of two-phase non-overlapping clocks and delayed clock control to achieve module function switching in different modes.
[0033] The reset clock CLK_RST of the hybrid structure analog-to-digital converter is connected to the reset switches of capacitor banks C1-C5, the reset terminals of the amplifier and the comparator, and resets the capacitors, amplifier and comparator before each analog-to-digital conversion.
[0034] The working principle of the entire circuit is as follows: The circuit is controlled by two sets of non-overlapping two-phase clocks DS and DI, CS and CA, and their delayed clocks DSd and DId, CSd and CAd. The delayed clocks are used to eliminate channel charge injection. The first-order feedforward incremental ΔΣ ADC undergoes two stages: sampling and integration, while the cyclolic ADC undergoes two stages: sampling and amplification. The entire circuit is first reset under the control of the reset clock CLK_RST. Then, the first-order feedforward incremental ΔΣ ADC begins sampling under the control of clocks DSd and DS. During the sampling stage, the 1.5-bit sub-ADC begins comparison and obtains the comparison results d0 and d1. After the sampling stage ends, the sampling switch is turned off, and integration begins under the control of clocks DId and DI. The 1.5-bit sub-DAC determines V based on the comparator comparison results d1 and d0. DAC The magnitude of the value is determined at this stage, and the comparator input is connected to the common-mode level. After 128 clock cycles, the conversion ends, resulting in 128 sets of digital codes. These 128 digital codes are then converted into 7-bit binary digital codes D13~D7 by a digital filter. The operation of the 1.5-bit sub-ADC and 1.5-bit sub-DAC in the Cyclic ADC is the same as that in the Incremental ΔΣ ADC. When the Incremental ΔΣ ADC conversion is complete, a margin voltage is obtained at the amplifier output. The Cyclic ADC samples this margin voltage under the control of clocks CSd and CS. After the sampling phase, the sampling switch is turned off, and amplification begins under the control of clocks CAd and CA. After 8 clock cycles, the conversion ends, and the digital codes D7~D0 are obtained through a shift register circuit. Finally, the digital codes output by the two ADCs are superimposed by one bit, added, and the redundant bits are subtracted to obtain D13~D0.
[0035] The hybrid-structure analog-to-digital converter employs a two-stage hybrid architecture. Before the overall conversion begins, the circuit is reset after two clock cycles. Then, the 7-bit first-order feedforward incremental ΔΣ ADC undergoes two... 7 An oversampling rate of 128 is obtained in one clock cycle. Oversampling and noise shaping techniques are used to achieve 7-bit quantization, and the input signal is directly fed to the comparator input during each sampling. After 7-bit coarse quantization, a margin voltage is obtained, which serves as the input signal of the Cyclic ADC. The 8-bit single-stage Cyclic ADC achieves 8-bit quantization in 8 clock cycles, and after one clock cycle after quantization, a resolution of 7 + 8 - 1 = 14 bits is achieved through digital interconnect circuitry.
[0036] Specifically, the two sets of non-overlapping two-phase clocks are DS and DI, and CS and CA, respectively, and the two sets of non-overlapping two-phase delayed clocks are DSd and DId, and CSd and CAd, respectively. In Incremental mode, clocks DS / DSd and DI / DId are valid, and the feedforward path and the modulator's integration loop operate in a time-division multiplexing manner. During the sampling phase, DS / DSd is high, and the feedforward path, sampling capacitor C1, comparator, and 1.5-bit sub-DAC form a connection path. The input signal is sampled by sampling capacitor C1, and simultaneously, the input signal is directly fed into the comparator via feedforward summing circuit capacitors C4 / C5. The quantization result of the sampled signal by the comparator is directly transmitted to the 1.5-bit sub-DAC. During the integration phase, DI / DId is high, the comparator's input is reset to the common-mode level VCM, the feedforward path stops working, and sampling capacitor C1, integration capacitors C2 / C3, amplifier, and 1.5-bit sub-DAC form an independent modulator integration loop. The sub-DAC outputs the corresponding feedback voltage based on the quantization result. The charge on the sampling capacitor C1 is transferred to the integrating capacitors C2 / C3. The switched capacitor integrator with the amplifier as its core completes the integration operation on the difference between the input signal and the feedback voltage, and completes the integration accumulation of the difference signal. At this time, the integrated residual voltage at the amplifier output is ready for the next sampling.
[0037] In Cyclic mode, clocks CS / CSd and CA / CAd are active, the feedforward path stops working, and the amplifier, together with the multiplexed capacitors C1 / C3 and the clock-controlled switching transistors of CA / CAd, forms a 2x amplifier circuit. A 1.5-bit sub-ADC / sub-DAC provides quantization and feedback support for it.
[0038] During the sampling phase, CS / CSd is high, and the margin voltage output in Incremental mode is directly used as the input of the Cyclic ADC. Under the control of the CS / CSd clock, capacitors C1 / C3 complete the charge sampling of the margin voltage. The comparator directly receives the margin voltage output by the amplifier and completes the quantization. The result is transmitted to the 1.5-bit sub-DAC in real time.
[0039] During the amplification stage, CA / CAd is high, and the 1.5-bit sub-DAC output feedback voltage is used. The amplifier achieves 2x amplification through C1 / C3. The amplified residual voltage is used as the input for the next sampling until 8 sampling-amplification iterations are completed. The quantization result of each cycle is transmitted to the shift register in real time. Finally, the shift register performs shifting and addition to output an 8-bit fine quantization code.
[0040] Example 1 This embodiment is a 14-bit hybrid analog-to-digital converter (ADC). The circuit includes a first-order feedforward incremental ΔΣ ADC, a single-stage cyclolic ADC, and a digital interface circuit. Compared with the structure of traditional hybrid ADCs, the hybrid ADC of this invention uses a first-order feedforward incremental ΔΣ ADC to achieve 7-bit coarse quantization and a single-stage cyclolic ADC to achieve 8-bit fine quantization. The 15-bit digital codes output from the two stages are superimposed one bit, added, and a redundant bit of 10000000 is added to obtain the final 14-bit ADC digital code.
[0041] The hybrid structure analog-to-digital converter of the present invention is shown in the appendix. Figure 5 As shown. The circuit adopts a fully differential structure, and its operation is divided into Incremental mode and Cyclic mode. Each mode is further divided into two stages: sampling and integration, and sampling and amplification, where capacitors C1=C2=C3=C4=C5. The timing diagram of the hybrid structure analog-to-digital converter of this invention is attached. Figure 6 As shown in the diagram. CLK is the master clock signal with a frequency of 4 MHz. CLK_RST is the reset clock signal for the entire circuit, resetting the capacitors, integrator, and comparator before each conversion. DM is the control clock that controls different capacitors in the Incremental ΔΣ ADC and Cyclic ADC respectively. DS, DSd, DI, and DId are the control clocks and their delay clocks for the sampling and integration stages of the Incremental ΔΣ ADC. CS, CSd, CA, and CAd are the control clocks and their delay clocks for the sampling and amplification stages of the Cyclic ADC.
[0042] CLK_RST occupies 2 clock cycles. When the clock CLK_RST is high, the switch CLK_RST closes, the entire circuit is reset, and the amplifier's input and output voltages are reset to common-mode levels. VCM At this time, the total charge stored in all the capacitors is: ; in C This is the capacitance value. V This represents the voltage difference between the upper and lower plates of the capacitor. After the reset is complete, the circuit enters Incremental mode, as shown below. Figure 7 As shown, when clocks DS and DSd are high, control switches DS and DSd are closed, and the IncrementalΔΣ ADC begins sampling the input signal. At this time, the charge stored in capacitor C1 is:
[0043] ; ; in VIP , VIN These are represented as the differential input signals of the fully differential ADC. Meanwhile, according to the law of conservation of charge, the charge stored on the capacitor in the feedforward path is:
[0044] ; ; in V comp1+ 、V comp1- Let be the positive and negative input voltages of the comparator. The comparator input voltage can be obtained as follows:
[0045] ; ; ; in VI = VIP-VIN .
[0046] As can be seen from the formula, the input signal is directly fed to the input terminal of the comparator, and the comparator converts the input signal into a signal. V comp It is compared with two comparators of a 1.5-bit sub-ADC (one of which has a threshold voltage). V THcom+ It is 0.25 Vref One is a comparator threshold voltage. V THcom- -0.25 Vref , Vref Using the reference voltage, the comparison results d1 and d0 for the first clock cycle are obtained.
[0047] After the sampling phase ends, the sampling switch is opened, clocks DI and DId are high, and control switches DI and DId are closed, allowing the circuit to enter the integration phase. At this time, the 1.5-bit sub-DAC determines the DAC's output voltage based on the comparator comparison results d1 and d0. V DAC Feedback voltage VREF If the comparator outputs d1 and d0 are 11, then V DAC Feedback voltage VREF 1.8V (positive terminal connected to feedback voltage) VREFP =1.8V, negative terminal connected to feedback voltage VREFN =0V, VREF=VREFP-VREFN =1.8V), if the comparator outputs d1 and d0 are 0 and 1, then V DAC Feedback voltage VREF 0V (positive terminal connected to feedback voltage) VREFP =0.9V, negative terminal connected to feedback voltage VREFN =0.9V, VREF=VREFP-VREFN =0V), if the comparator outputs d1 and d0 are 00, then V DAC Feedback voltage VREF -1.8V (positive terminal connected to feedback voltage) VREFP =0V, negative terminal connected to feedback voltage VREFN =1.8V, VREF=VREFP-VREFN =-1.8V), at this time, the charge of the capacitors in the feedforward path is cleared to zero, and the charge stored in the sampling capacitor C1 is transferred to the integrating capacitors C2 and C3. The charge on C1, C2 and C3 at this time can be expressed as:
[0048] ; ; in, V res_D1+ , V res_D1- These are the positive and negative output voltages of the amplifier during the first integration, respectively. According to the law of conservation of charge, Q DS1 = Q DI1 The amplifier output voltage can be obtained as follows:
[0049] ; ; ; ; in VREF 1 When integrating for the first clock cycle, V DAC The feedback voltage value.
[0050] The second sampling is the same as the first sampling, and the charge stored in capacitor C1 is: ; ; Meanwhile, according to the law of conservation of charge, the charge stored in the capacitor in the feedforward path is: ; ; The input voltages at the positive and negative terminals of the comparator can be obtained as follows: ; ; ; ; Similarly, it can be seen that the input signal is again directly fed to the comparator input. After the sampling phase, the comparator obtains the comparison result for the second clock cycle. Then, the integration phase begins, and the second integration process is the same as the first. The charge on C1, C2, and C3 can be expressed as:
[0051] ; ; According to the law of conservation of charge Q DS2 = Q DI2 The amplifier output voltage can be obtained as follows: ; ; ; ; ; The sampling and integration process is repeated for the next 126 clock cycles, with the comparator's input voltage changing during each sampling phase. V compi for: ; During each sampling phase, the input signal is directly fed to the comparator input for comparison. At the end of each clock cycle, the amplifier output voltage is:
[0052] ; After 128 clock cycles, the amplifier's output voltage after the Incremental mode ends... V res_D128 for: ; in VREF Depending on the comparator's comparison result, the voltage could be 1.8V, 0V, or -1.8V. V res_D128 Expressed using the following formula:
[0053] ; in VREF 11 VREF 01 VREF 00 These represent 1.8V, 0V, and -1.8V respectively. N 11 、N 01 、N 00 These represent the number of times the comparator's comparison result is 11, 01, and 00, respectively. N 11 +N 01 +N 00 =2 7 Therefore, the above formula can also be expressed as: ; In a first-order incremental ΔΣ ADC using 1-bit sub-ADC quantization, a simple counter accumulating the "1"s at the modulator output enables low-pass filtering where the weighting coefficients are independent of the sample point order. For a 1.5-bit sub-ADC, the comparison results are encoded as 11, 01, and 00 respectively, and a calculator can be used to apply the formula... N = N 11 +N 01 / 2 Count the 11 and 01 outputs of the modulator, and... N Converting to 7-bit binary digital codes D13~D7 enables low-pass filtering of the digital filter, thus obtaining the encoding result of the coarse quantization incremental ΔΣ ADC.
[0054] Incremental mode ends after 128 clock cycles, at which point the amplifier output voltage... Vres_D128 As the input voltage of the Cyclic ADC, the circuit enters Cyclic mode, such as... Figure 8 As shown, when clocks CS and CSd are high, control switches CS and CSd are closed, and the Cyclic ADC begins sampling the input signal. At this time, the charge stored on the capacitor in the circuit is: ; ; in V res_C0+ 、V res_C0- The voltage at the output of the amplifier for the last conversion in Incremental mode is respectively. V res_D128+ 、V res_D128- Simultaneously with sampling, the 1.5-bit sub-ADC begins operation. The amplifier output voltage is directly connected to the comparator input for comparison, and the comparison process is the same as the comparator operation during the sampling phase of the Incremental ΔΣ ADC.
[0055] After the sampling phase ends, the sampling switch is opened, clocks CA and CAd are high, and control switches CA and CAd are closed, allowing the circuit to enter the amplification phase. At this point, the 1.5-bit sub-DAC operates in the same way as the 1.5-bit sub-DAC in an incremental ΔΣ ADC. The charge stored on the capacitor in the circuit at this time can be represented as:
[0056] ; ; According to the law of conservation of charge Q CS1 = Q CA1 The amplifier output voltage can be obtained as follows: ; ; ; ; After the first clock cycle, the amplifier output voltage becomes the input voltage for the second clock cycle, initiating the next sampling and amplification process. Subsequent clock cycles perform the same sampling and amplification as the first conversion cycle. Therefore, at the end of each clock cycle, the amplifier output can be expressed as:
[0057] ; After 8 clock cycles, Cyclic mode ends. The Cyclic ADC generates 8 sets of digital codes d1 and d0. These 8 sets of digital codes are shifted and added together by the shift register to finally obtain the 8-bit output code D7~D0.
[0058] The 7-bit code obtained from the Incremental mode is added to the 8-bit code obtained from the Cyclic mode by one bit, and then the redundant bits are subtracted to obtain the final 14-bit code D13~D0.
[0059] In summary, when the Incremental ΔΣ ADC is working, the input signal is directly fed to the comparator input for comparison in each sampling stage, without entering the modulator loop, thus reducing the impact of non-ideal factors in the modulator loop on the input signal. When the comparator is not working, the input is reset, avoiding the impact of different voltage changes caused by mismatched input traces. Furthermore, this invention uses an Incremental ΔΣ ADC to implement 7-bit coarse quantization and a Cyclic ADC to implement 8-bit fine quantization, significantly reducing the number of clock cycles and improving the overall ADC conversion rate. The hybrid structure analog-to-digital converter of this invention has a conversion rate of 28.7 KS / s. Figure 9 The output spectrum of the hybrid structure analog-to-digital converter of the present invention shows that, with an input signal frequency of 13.714 kHz, the signal-to-noise ratio (SNDR) is 85.63 dB and the effective number of bits (ENOB) is 13.925 bits.
[0060] The hybrid analog-to-digital converter (ADC) proposed in this invention precisely solves the core technical problems of low signal-to-noise ratio (SNR) and slow conversion speed of traditional 14-bit hybrid ADCs through targeted architecture and circuit design. Addressing the issues of the traditional Incremental ΔΣ ADC input signal being susceptible to interference from non-ideal factors in the modulator loop, and the accumulation of parasitic capacitance charge at the comparator input leading to a reduction in effective bits and SNR, this invention replaces the 8-bit Incremental ΔΣ ADC with a 7-bit first-order feedforward structure. By adding a feedforward path, the input signal is directly fed to the comparator input, avoiding the influence of non-ideal factors in the modulator loop. Simultaneously, the comparator input is reset to the common-mode level VCM during the Incremental ΔΣ ADC integration phase and the Cyclic ADC non-sampling phase, eliminating the voltage inconsistency caused by mismatched wiring between the two comparator inputs. This reduces quantization noise at the source and significantly improves the overall SNR of the circuit. To address the slow conversion speed of traditional 8-bit incremental ΔΣ ADC + 7-bit cyclic ADC configurations requiring 265 clock cycles, this invention employs an inverted quantization bit ratio of 7-bit first-order feedforward incremental ΔΣ ADC + 8-bit single-stage cyclic ADC. This reduces the quantization iteration cycle of the incremental ΔΣ ADC. Furthermore, it utilizes two sets of non-overlapping two-phase clocks (DS / DI and CS / CA) and corresponding delay clocks to time-division control the two-stage ADC, achieving efficient module function switching and significantly reducing the overall conversion cycle to 139 clock cycles. The two-stage ADCs reuse a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and an amplifier. Without adding additional circuitry, it maintains the 14-bit total resolution through a 7+8-1 stacking rule while significantly improving the conversion rate. Ultimately, this solution effectively improves the circuit's signal-to-noise ratio and signal-to-distortion ratio while maintaining 14-bit high resolution, significantly accelerating the conversion speed, and saving circuit power and area, thus meeting the application requirements of high resolution, low power consumption, and small area.
[0061] It should be noted that the specific embodiments described above enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail in this specification and embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention; and all technical solutions and improvements that do not depart from the spirit and scope of the present invention are covered within the protection scope of the present invention patent. No reference numerals in the claims should be construed as limiting the scope of the claims. Any simple variations or equivalent substitutions of technical solutions that can be readily obtained by those skilled in the art within the scope of the technology disclosed in the present invention are within the protection scope of the present invention.
Claims
1. A hybrid structure analog-to-digital converter, characterized in that, The hybrid structure analog-to-digital converter is based on a traditional 14-bit hybrid ADC. The 8-bit incremental ΔΣ ADC and 7-bit cyclic ADC of the traditional 14-bit hybrid ADC are replaced with a 7-bit first-order feedforward incremental ΔΣ ADC and an 8-bit single-stage cyclic ADC, respectively. Specifically, the 7-bit first-order feedforward incremental ΔΣ ADC adds a feedforward path to the 7-bit incremental ΔΣ ADC, so that the input signal is directly fed to the comparator input to participate in the comparison. The comparator input is reset to the common-mode level VCM during the Incremental ΔΣ ADC integration phase and the Cyclic ADC non-sampling phase. The 7-bit first-order feedforward incremental ΔΣ ADC and the 8-bit single-stage cycloidal ADC are controlled by two sets of two-phase non-overlapping clocks and delayed clocks to achieve module function switching in different modes.
2. The hybrid structure analog-to-digital converter according to claim 1, characterized in that, The feedforward path includes two sets of capacitors C4 and C5, which are distributed in differential pairs on both sides of the positive and negative input terminals of the comparator. One end of each of the two capacitors C5 is connected to a common-mode level VCM, and the other end is connected to one end of each of the two capacitors C4, and then connected to the positive and negative input terminals of the comparator, respectively. The other ends of the two capacitors C4 are connected to the positive differential analog input terminal VIP and the negative differential analog input terminal VIN, respectively, and the input signal is directly fed to the comparator input terminal for comparison through the feedforward path.
3. The hybrid structure analog-to-digital converter according to claim 1, characterized in that, The 7-bit first-order feedforward incremental ΔΣ ADC also includes a switched-capacitor integrator, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a first-order digital filter. The input signal is directly fed to the comparator input of the 1.5-bit sub-ADC via the feedforward path. The switched-capacitor integrator is connected to both the 1.5-bit sub-ADC and the 1.5-bit sub-DAC. The 1.5-bit sub-DAC outputs a feedback voltage to the switched-capacitor integrator based on the comparison result of the 1.5-bit sub-ADC. The output of the switched-capacitor integrator is connected to the first-order digital filter. The amplifier output of the 7-bit first-order feedforward incremental ΔΣ ADC is a margin voltage output, which is connected to the input of the 8-bit single-stage cyclic ADC.
4. The hybrid structure analog-to-digital converter according to claim 3, characterized in that, The 8-bit single-stage Cyclic ADC includes a 2x amplifier circuit, a 1.5-bit sub-ADC, a 1.5-bit sub-DAC, and a shift register. The margin voltage output of the 7-bit first-order feedforward incremental ΔΣ ADC is connected to the input of this ADC, and then sequentially connected to the 2x amplifier circuit and the 1.5-bit sub-ADC. The 1.5-bit sub-DAC outputs a feedback voltage to the 2x amplifier circuit based on the comparison result of the 1.5-bit sub-ADC. The output of the 2x amplifier circuit is fed back to its own input and is also connected to the shift register. The 7-bit first-order feedforward incremental ΔΣ ADC and the 8-bit single-stage Cyclic ADC multiplex the sampling / integration / amplification capacitor bank, the 1.5-bit sub-ADC, the 1.5-bit sub-DAC, the comparator, and the amplifier.
5. The hybrid structure analog-to-digital converter according to claim 4, characterized in that, The sampling / integration / amplification capacitor bank includes a sampling capacitor C1 and integrating capacitors C2 and C3. The sampling capacitor C1 completes the charge storage during the sampling stage, and C1 also provides charge for the feedforward branch and the integration branch. The integrating capacitors C2 and C3 are connected between the input and output terminals of the amplifier to complete the charge transfer and signal integration during the integration stage.
6. The hybrid structure analog-to-digital converter according to claim 5, characterized in that, During the sampling phase, the input differential signals VIP and VIN are directly connected to capacitor C4 in the feedforward path, while capacitor C5 is connected to the output of the amplifier that was integrated before the common-mode level VCM. By applying the law of conservation of charge, the input signal is directly fed to the positive and negative inputs of the comparator, forming a physical path for the input signal to reach the input of the 1.5-bit sub-ADC comparator without passing through the modulator loop. Furthermore, the feedforward path remains on during each sampling phase, and the input signal continuously participates in the comparator's comparison and determination through this path.
7. The hybrid structure analog-to-digital converter according to claim 6, characterized in that, The reset clock CLK_RST of the hybrid structure analog-to-digital converter is connected to the reset switches of capacitor banks C1-C5, the reset terminals of the amplifiers and the comparators, and resets the capacitors, amplifiers and comparators before each analog-to-digital conversion begins.
8. The hybrid structure analog-to-digital converter according to claim 1, characterized in that, The hybrid analog-to-digital converter (ADC) employs a two-stage hybrid structure. Before the overall conversion begins, the circuit is reset after two clock cycles. Then, the 7-bit first-order feedforward incremental ΔΣ ADC undergoes two... 7 An oversampling rate of 128 is obtained in one clock cycle. Oversampling and noise shaping techniques are used to achieve 7-bit quantization, and the input signal is directly fed to the comparator input during each sampling. After 7-bit coarse quantization, a margin voltage is obtained, which serves as the input signal of the Cyclic ADC. The 8-bit single-stage Cyclic ADC achieves 8-bit quantization in 8 clock cycles, and after one clock cycle after quantization, a resolution of 7 + 8 - 1 = 14 bits is achieved through a digital interconnect circuit.
9. The hybrid structure analog-to-digital converter according to claim 7, characterized in that, The two sets of non-overlapping two-phase clocks are DS and DI, and CS and CA, respectively. The two sets of non-overlapping two-phase delayed clocks are DSd and DId, and CSd and CAd, respectively. In Incremental mode, clocks DS / DSd and DI / DId are valid, and the feedforward path and the modulator's integration loop operate in a time-division multiplexing manner. During the sampling phase, DS / DSd is high, and the feedforward path, sampling capacitor C1, comparator, and 1.5-bit sub-DAC form a connection path. The input signal is sampled by sampling capacitor C1, and simultaneously, the input signal is directly fed into the comparator via feedforward summing circuit capacitors C4 / C5. The quantization result of the sampled signal by the comparator is directly transmitted to the 1.5-bit sub-DAC. During the integration phase, DI / DId is high, the comparator's input is reset to the common-mode level VCM, the feedforward path stops working, and sampling capacitor C1, integration capacitors C2 / C3, amplifier, and 1.5-bit sub-DAC form an independent modulator integration loop. The sub-DAC outputs the corresponding feedback voltage based on the quantization result. The charge on the sampling capacitor C1 is transferred to the integrating capacitors C2 / C3. The switched capacitor integrator with the amplifier as its core completes the integration operation on the difference between the input signal and the feedback voltage, and completes the integration accumulation of the difference signal. At this time, the integrated residual voltage at the amplifier output is ready for the next sampling. In Cyclic mode, clocks CS / CSd and CA / CAd are active, the feedforward path stops working, and the amplifier is the core, which, together with the multiplexed capacitors C1 / C3 and the clock-controlled switching transistors of CA / CAd, forms a 2x amplifier circuit. A 1.5-bit sub-ADC / sub-DAC provides quantization and feedback support for it. During the sampling phase, CS / CSd is high, and the margin voltage output in Incremental mode is directly used as the input of the Cyclic ADC. Under the control of the CS / CSd clock, capacitors C1 / C3 complete the charge sampling of the margin voltage. The comparator directly receives the margin voltage output from the amplifier and completes the quantization. The result is transmitted to the 1.5-bit sub-DAC in real time. During the amplification phase, CA / CAd is high, and the 1.5-bit sub-DAC outputs a feedback voltage. The amplifier achieves 2x amplification through C1 / C3. The amplified margin voltage is used as the input for the next sampling, until 8 sampling-amplification iterations are completed. The quantization result of each cycle is transmitted to the shift register in real time. Finally, the shift register performs shifting and addition to output an 8-bit fine quantization code.