A digital signal conversion circuit

Abstract

A digital signal conversion circuit includes a reference voltage source, a voltage-dividing resistor string connected in series between an output terminal of the reference voltage source and a ground, the voltage-dividing resistor string including N voltage-dividing output points, and N sampling comparators, one input terminal of each sampling comparator is connected to a voltage-dividing output point, the other output terminal of the sampling comparator is connected to an input analog voltage, the output terminal of each comparator is connected to a digital signal processor, and a compensation circuit for detecting a reference voltage is included, the digital signal processor performs addition and subtraction operations on the result output by the digital signal processor according to the detection result of the compensation circuit. The digital signal conversion circuit of the present invention improves the conversion output accuracy by detecting the reference voltage drift and compensating and adjusting the output digital signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits and relates to a technology for converting analog signals into digital signals; in particular, it relates to a digital signal conversion circuit. Background Art

[0002] Collect analog voltage signals and convert them into digital signals, so that the central processor can read the digital signals for analysis and processing. The analog-to-digital converter can convert analog signals into digital signals. According to its conversion principle, it is mainly divided into parallel comparison type, successive approximation type, double integral type, etc.

[0003] The main feature of the parallel comparison analog-to-digital conversion structure is its high speed. This structure is mostly used in high-speed applications. The parallel comparison structure uses resistor series voltage division to simultaneously detect the output of each comparator, and the conversion of all bits of the output digital signal is completed at the same time. In the parallel comparison structure, the reference voltage is used as the reference of the comparator. When the reference voltage drifts, it may cause deviations for low-bit detection. Summary of the invention

[0004] In order to overcome the defects in the prior art, the present invention discloses a digital signal conversion circuit.

[0005] The digital signal conversion circuit of the present invention comprises a reference voltage source, a voltage-dividing resistor string connected in series between an output end of the reference voltage source and ground, the voltage-dividing resistor string comprising N voltage-dividing output points, and N sampling comparators, wherein one input end of the sampling comparator is respectively connected to a voltage-dividing output point, the other output end of the sampling comparator is connected to an input analog voltage, the output end of each comparator is connected to a digital signal processor, and a compensation circuit for detecting a reference voltage is further included, wherein the digital signal processor performs addition and subtraction operations on a result output by the digital signal processor according to a detection result of the compensation circuit.

[0006] Preferably, the compensation circuit includes a first compensation comparator and a second compensation comparator, the other end of the grounding resistor connected to the ground in the voltage-dividing resistor string is connected to the non-inverting input end of the first compensation comparator and the inverting input end of the second compensation comparator, the two compensation comparators are rail-to-rail comparators, the other input ends are both grounded, the output ends of the two compensation comparators are connected to the digital signal processor, and the digital signal processor performs the following operations on the output results of the two compensation comparators:

[0007] When the output result of the first compensation comparator is at a high level, 1 is added to the output result of the digital signal processor; when the output result of the second compensation comparator is at a high level, 1 is subtracted from the output result of the digital signal processor.

[0008] Preferably, the output terminals of the two compensation comparators are connected with pull-down resistors.

[0009] Preferably, the grounding resistor is a resistor connected to the lowest output voltage point among the N voltage-dividing output points.

[0010] Preferably, the ratio of each resistor in the voltage-dividing resistor string from ground to the output end of the reference voltage source is 1:2:4...

[0011] The digital signal conversion circuit of the present invention detects the drift of the reference voltage and performs compensation adjustment on the output digital signal, thereby improving the conversion output accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a specific implementation of the digital signal conversion circuit of the present invention;

[0013] Figure 2 A schematic diagram of a specific implementation of the compensation circuit of the present invention;

[0014] Figure 3 It is a schematic diagram of a specific implementation of the rail-to-rail comparator of the present invention. Implementation

[0015] The specific implementation modes of the present invention are further described in detail below.

[0016] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely explained below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The digital signal conversion circuit of the present invention comprises a reference voltage source, a voltage-dividing resistor string connected in series between an output end of the reference voltage source and ground, wherein the voltage-dividing resistor string comprises N voltage-dividing output points, and is characterized in that it also comprises N sampling comparators, wherein one input end of the sampling comparator is respectively connected to a voltage-dividing output point, the other output end of the sampling comparator is connected to an input analog voltage, the output end of each comparator is connected to a digital signal processor, and further comprises a compensation circuit for detecting a reference voltage, wherein the digital signal processor performs addition and subtraction operations on a result output by the digital signal processor according to a detection result of the compensation circuit.

[0018] The present invention mainly solves the digital signal output value offset caused by the reference voltage source offset. For example, a 10-bit parallel comparison analog-to-digital conversion structure can achieve a detection accuracy of 1 / 1024. The ratio of each resistor in the voltage divider resistor string from the ground to the reference voltage source output end is a geometric progression of 1:2:4:8…2N-1 If the reference voltage output voltage drifts, for example by one percent, it may cause a one percent error.

[0019] The digital signal conversion circuit of the present invention comprises a reference voltage source, a voltage-dividing resistor string connected in series between an output end of the reference voltage source and ground, the voltage-dividing resistor string comprising N voltage-dividing output points, and N sampling comparators, wherein one input end of the sampling comparator is respectively connected to a voltage-dividing output point, the other output end of the sampling comparator is connected to an input analog voltage, the output end of each comparator is connected to a digital signal processor, and a compensation circuit for detecting a reference voltage is further included, wherein the digital signal processor performs addition and subtraction operations on a result output by the digital signal processor according to a detection result of the compensation circuit.

[0020] like Figure 1 As shown in FIG2 , the initial reference voltage VREF0 output by the reference voltage source is divided by four voltage-dividing resistors R1, R2, R3 and R4 connected in series to obtain different secondary reference voltages VREF1, VREF2 and VREF3, among which the secondary reference voltage output by the resistor directly connected to the ground is the lowest. To facilitate detection and verification, the compensation circuit of the present invention samples and detects the voltage from the resistor directly connected to the ground.

[0021] The input terminals of the first sampling comparator CP1, the second sampling comparator CP2, the third sampling comparator CP3, and the fourth sampling comparator CP4 are respectively the input analog voltage VIN and the initial reference voltage VREF0, the secondary reference voltage VREF1, VREF2, and VREF3. Through the comparison of each sampling comparator, a four-bit digital signal is output to represent the specific value of the analog voltage VIN.

[0022] Since the compensation circuit directly detects the secondary reference voltage with the lowest voltage value, and the output result of the digital signal processor is a multi-bit binary number, the last bit reflects the result of comparison with the lowest secondary reference voltage. Therefore, when adding or subtracting the results output by the digital signal processor, it is sufficient to add 1 or subtract 1 without converting to other bit numbers.

[0023] like Figure 2 As shown, the compensation circuit includes a first compensation comparator and a second compensation comparator, the other end of the grounding resistor connected to the ground in the voltage-dividing resistor string is connected to the non-inverting input end of the first compensation comparator and the inverting input end of the second compensation comparator, the two compensation comparators are rail-to-rail comparators, the other input end is grounded, the output ends of the two compensation comparators are connected to the digital signal processor, and the digital signal processor performs the following operations on the output results of the two compensation comparators:

[0024] When the output result of the first compensation comparator is at a high level, 1 is added to the output result of the digital signal processor; when the output result of the second compensation comparator is at a high level, 1 is subtracted from the output result of the digital signal processor.

[0025] Due to temperature, power supply voltage, etc., the reference voltage output by the reference voltage source may drift. Since the present invention is aimed at compensating for the reference voltage drift, the two compensation comparators no longer use the reference voltage source output voltage as a reference. Instead, the comparison end is directly grounded and the ground potential is used as a reference, so that they are not affected by the reference voltage drift.

[0026] When the reference voltage source works normally, by setting specific parameters of the two compensation comparators, for example, making the difference between the two input terminals of the first compensation comparator smaller than the offset voltage of the comparator, and making the difference between the two input terminals of the second compensation comparator larger than the offset voltage of the comparator, the output voltages can all be made low.

[0027] The other end of the grounding resistor connected to the ground in the voltage-dividing resistor string is connected to the non-inverting input end of the first compensation comparator and the inverting input end of the second compensation comparator. Through the voltage-dividing sampling of the voltage-dividing resistor string, the two compensation comparators sample the voltage of the reference voltage source through the grounding resistor.

[0028] When the voltage of the reference voltage source increases, the voltage at the non-inverting input terminal of the first compensation comparator CP5 increases. When it increases to a certain value, the voltage value becomes higher than the zero potential of the first compensation comparator, and the difference reaches the comparator offset voltage. At this time, the output voltage of the first compensation comparator CP5 changes from a low level to a high level. Since the inverting input terminal of the second compensation comparator is connected to a grounding resistor, the voltage of the reference voltage source increases, the difference between the two input terminals increases, and the output terminal of the second compensation comparator maintains a low level unchanged.

[0029] When the voltage of the reference voltage source decreases, the voltage at the inverting input terminal of the second compensation comparator CP6 decreases. When it decreases to a certain value, the voltage difference between the two input terminals of the second compensation comparator decreases from higher than the comparator offset voltage to lower than the comparator offset voltage. At this time, the output voltage of the second compensation comparator CP6 changes from a low level to a high level. Since the positive input terminal of the first compensation comparator is connected to a grounding resistor, the voltage of the reference voltage source decreases, and the output terminal of the second compensation comparator maintains a low level unchanged.

[0030] The change of the reference voltage can be detected by two compensation comparators. Since the offset voltage of the compensation comparator itself is extremely small, generally within a few to tens of millivolts, a small change of the reference voltage will be detected by the compensation comparator. Since the compensation comparator uses the ground voltage as a reference and only detects the difference between the other input terminal and the ground, the ground voltage does not change with the reference voltage, thereby avoiding the influence of the reference voltage on the detection result of the compensation comparator. Since the compensation comparator uses the ground voltage as an input signal, a rail-to-rail comparator must be used. The rail-to-rail comparator (RAIL TO RAIL) refers to a comparator whose input comparison voltage range can be detected from the power supply to the ground, which is a prior art in this field.

[0031] like Figure 3 As shown in the figure, a typical existing implementation of a rail-to-rail comparator is shown. In the figure, NMOS tubes are connected under the substrate, PMOS tubes are connected above the substrate, two input terminals IN1 and IN2 are connected to a pair of NMOS tubes and PMOS tubes respectively, bias voltage is provided by external voltages VBP and VBN, and finally output through the output terminal VO. In the figure, VDDD is the power supply, and the detection range is 0 to VDDD.

[0032] Figure 2 In the specific implementation shown, the output terminals of the two compensation comparators are connected to a first pull-down resistor R10 and a second pull-down resistor R11. Since the detection range in the present invention is concentrated close to the ground voltage and the voltage difference input to the two compensation comparators is usually small, in order to avoid the output terminal of the compensation comparator being suspended, a pull-down resistor is set so that the output terminal of the compensation comparator will be 1 unless there is a strong pull-up current, otherwise it will maintain a low level to avoid erroneous output of a high-level signal.

[0033] like Figure 2 As shown, the grounding resistor may be the fourth resistor R4 in the voltage-dividing resistor string, or may be a part of the fourth resistor R4. Figure 2 In the figure, the fourth resistor R4 is divided into two resistors R41 and R42. The voltage division sampling of the two resistors actually reduces the reference voltage change input to the compensation comparator. The grounding resistor can also be selected as the resistor formed by the third resistor R3 and the fourth resistor R4 in the voltage division resistor string, which actually increases the reference voltage change input to the compensation comparator. The compensation accuracy can be adjusted in two different ways.

[0034] In a specific embodiment, assuming that the reference voltage is 1V, a 4-bit parallel comparison analog-to-digital conversion structure is used, the detection accuracy reaches 1 / 16, the ratio of the voltage-dividing resistor string is 2, and the compensation comparator takes the value from the grounding resistor in the voltage-dividing resistor string, and the voltage-dividing ratio of the grounding resistor is 1 / 16.

[0035] The analog voltage input to the non-inverting input of the sampling comparator is 0.061V. In the fourth sampling comparator, the input secondary reference voltage VREF3 is 62.5 mV, so the output of the fourth sampling comparator is 0. When the reference voltage changes and drops by 50 mV, it is reflected at the input of the compensation comparator, and the voltage value drops by 50 / 16=3.1 mV to 59 mV, which is less than the input analog voltage. Then the input of the fourth sampling comparator is 1, and an error of positive 1 occurs.

[0036] After adopting the compensation circuit, assuming that the offset voltage of the compensation comparator is 60 mV, when the secondary reference voltage VREF3 input to the compensation comparator is 62.5 mV, it is higher than the offset voltage, and the second compensation comparator outputs a low level. After VREF3 is reduced from 62.5 mV to 59 mV, it is lower than the offset voltage, and the second compensation comparator outputs a high level. When the output result of the second compensation comparator is a high level, the result output by the digital signal processor is subtracted by 1, thereby correcting the positive 1 error that appeared previously in the last bit.

[0037] The digital signal processor detects the input level signals of the two compensation comparators, and performs addition or subtraction of 1 on the last bit of the multi-bit digital signal detected by the sampling comparator according to the detection result. This is the prior art in the art and can be realized by simple programming and then burning. For example, the digital signal processor can be realized by using a logic gate circuit or a burnable programmable logic device FPGA.

[0038] The digital signal conversion circuit of the present invention detects the drift of the reference voltage and performs compensation adjustment on the output digital signal, thereby improving the conversion output accuracy.

[0039] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital signal conversion circuit, comprising a reference voltage source, a voltage-dividing resistor string connected in series between an output terminal of the reference voltage source and ground, wherein the voltage-dividing resistor string comprises N voltage-dividing output points, characterized in that: It also includes N sampling comparators, one input end of each sampling comparator is connected to a voltage-dividing output point, the other output end of each sampling comparator is connected to an input analog voltage, and the output end of each comparator is connected to a digital signal processor, and also includes a compensation circuit for detecting a reference voltage, and the digital signal processor performs addition and subtraction operations on the result output by the digital signal processor according to the detection result of the compensation circuit; The compensation circuit includes a first compensation comparator and a second compensation comparator. The other end of the grounding resistor connected to the ground in the voltage-dividing resistor string is connected to the non-inverting input end of the first compensation comparator and the inverting input end of the second compensation comparator. The two compensation comparators are rail-to-rail comparators. The inverting input end of the first compensation comparator and the non-inverting input end of the second compensation comparator are both grounded. The output ends of the two compensation comparators are connected to the digital signal processor. The digital signal processor performs the following operations on the output results of the two compensation comparators: When the output result of the first compensation comparator is at a high level, 1 is added to the output result of the digital signal processor; when the output result of the second compensation comparator is at a high level, 1 is subtracted from the output result of the digital signal processor.

2. The digital signal conversion circuit according to claim 1, characterized in that: The outputs of the two compensation comparators are connected with pull-down resistors.

3. The digital signal conversion circuit according to claim 1, characterized in that: The grounding resistor is the resistor connected to the point with the lowest output voltage among the N voltage-dividing output points.

4. The digital signal conversion circuit according to claim 1, characterized in that: The ratio of each resistor in the voltage-dividing resistor string from ground to the output end of the reference voltage source is 1:2:4...

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