A bandwidth adjustment method and system

Abstract

The embodiment of the present application discloses a bandwidth adjustment method and system. The method is applied to a computing express link (CXL) system, the CXL system comprises at least one CXL device and a baseboard management controller (BMC), the at least one CXL device comprises a first CXL device, the first CXL device comprises at least two logical devices, the BMC acquires an average load state of each logical device in the first CXL device; according to the average load state, a target logical device in the first CXL device and an adjustment strategy are determined; and according to the adjustment strategy, the bandwidth of the target logical device is adjusted. By adopting the embodiment of the present application, the utilization rate of the bandwidth can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a bandwidth adjustment method and system. BACKGROUND

[0002] As an open industry standard, Compute Express Link (CXL) can provide high-bandwidth, low-latency connections between dedicated compute, memory, I / O, and storage elements within a data center. There are two modes for memory expansion using CXL-connected memory resources: one is local direct expansion of CXL memory, and the other is pooling of CXL memory resources. In the memory resource pooling mode, a host (Host) is connected to the pooled memory resources through a switch (CXL Switch), and the memory resources are re-allocated and deployed according to different workloads. However, since only the relationship between the business and the bandwidth on the Host is considered, the bandwidth utilization of multiple logical devices (MLD) is low. SUMMARY

[0003] Embodiments of the present application provide a bandwidth adjustment method and system, which adjusts the bandwidth of the LD in the CXL device to improve the bandwidth utilization of the CXL device.

[0004] In a first aspect, embodiments of the present application provide a bandwidth adjustment method, which is applied to a Compute Express Link (CXL) system, the CXL system comprising at least one CXL device and a Baseboard Management Controller (BMC), the at least one CXL device comprising a first CXL device, the first CXL device comprising at least two logical devices, the method comprising: obtaining, by the BMC, an average load state of each logical device in the first CXL device; determining, according to the average load state, a target logical device in the first CXL device and an adjustment strategy; and adjusting, according to the adjustment strategy, a bandwidth of the target logical device.

[0005] The BMC adjusts the bandwidth of the logical device in the first CXL device according to the average load state of each logical device in the first CXL device. In this way, even if the average load states of multiple logical devices in the same CXL device are different, the bandwidth of the logical device in the CXL device can be adjusted to improve the bandwidth utilization of the CXL device.

[0006] In one possible design, the first CXL device obtains an average load state of each logical device in the first CXL device, and sends the average load state to the BMC. The BMC counts the average load state of each logical device in the first CXL device based on the average load state sent by the first CXL device to the BMC, so as to adjust the bandwidth of each logical device in the first CXL device according to the average load state, and improve the bandwidth utilization of the CXL device.

[0007] In another possible design, the first CXL device obtains a number of times of each load state of each logical device in the first CXL device in a first time period, and obtains a total number of times of the load states in the first time period, and determines an average load state of each logical device in the first CXL device according to the number of times of each load state of each logical device in the first CXL device and the total number of times. The average load state of each LD in the same CXL device is determined by counting the proportion of each load state in the first time period, such as the ratio of the number of times of each load state to the total number of times, to ensure the accuracy of the determined average load state.

[0008] In another possible design, the first CXL device divides a number of times of a first load state of a first logical device in the first CXL device by a total number of times to calculate a ratio value corresponding to the first load state, where the first load state is any one of a light load, an optimal load, a moderate overload, and a serious overload. The ratio value corresponding to the first load state is compared with a first threshold value corresponding to the first load state. If the ratio value corresponding to the first load state is greater than or equal to the first threshold value corresponding to the first load state, the average load state of the first logical device is determined as the first load state. The average load state of each LD in the same CXL device is determined by counting the proportion of each load state in the first time period and comparing with the corresponding threshold value, to ensure the accuracy of the determined average load state.

[0009] In another possible design, the BMC sends an access request to each CXL device of at least one CXL device, where the access request is used to indicate to obtain an average load state of each logical device in each CXL device. The average load state of each logical device in each CXL device is counted by sending the access request to each CXL device, to ensure that the bandwidth of each logical device in each CXL device can be reasonably allocated.

[0010] In another possible design, the average load status includes an average light load, an average optimal load, an average moderate overload, and an average severe overload, the first CXL device includes a first logical device and a second logical device, and the BMC determines the target logical device as the first logical device and the second logical device when the average load status of the first logical device and the average load status of the second logical device are different. By determining whether the average load status of the logical devices in the same CXL device is the same, the target logical device that needs to be adjusted in bandwidth is determined, and adjustment in bandwidth of the target logical device with the same average load status is avoided under the premise that the bandwidth is fixed, thereby improving the efficiency of bandwidth adjustment.

[0011] In another possible design, the BMC determines whether the plurality of logical devices in the first CXL device are accessed by the plurality of hosts according to the mapping relationship between each logical device in the first CXL device and the hosts, and determines the target logical device in the first CXL device that needs to be adjusted in bandwidth according to the average load status of each logical device in the first CXL device. By determining whether the plurality of logical devices in the same CXL device are accessed by the plurality of hosts, it is determined whether the bandwidth of the plurality of logical devices in the CXL device needs to be adjusted, and adjustment in bandwidth of the CXL device that is not accessed by the plurality of hosts is avoided, thereby improving the efficiency of bandwidth adjustment.

[0012] In another possible design, when the severity of the average load status of the first logical device is higher than that of the second logical device, the BMC adjusts the bandwidth of the first logical device upward, and the BMC adjusts the bandwidth of the second logical device downward; or when the severity of the average load status of the first logical device is lower than that of the second logical device, the BMC adjusts the bandwidth of the first logical device downward, and the BMC adjusts the bandwidth of the second logical device upward. By allocating the redundant bandwidth of the logical device with the lower severity of the average load status to the logical device with the higher severity of the average load status, the bandwidth utilization rate of the MLD is improved.

[0013] In another possible design, the BMC configures the mapping relationship between the logical device and the host in each CXL device in the at least one CXL device, and configures the bandwidth of each logical device in each CXL device. By pre-configuring the mapping relationship and the bandwidth of each logical device, it is ensured that each logical device can work normally.

[0014] In another possible design, the BMC adjusts the bandwidth of the target logical device according to a preset adjustment range. By adjusting the bandwidth of the target logical device, the utilization rate of the bandwidth is improved.

[0015] In another possible design, the bandwidth includes an allocated bandwidth and an upper limit bandwidth, the BMC calculates a maximum adjustment range by subtracting the preconfigured allocated bandwidth from the preconfigured upper limit bandwidth, and adjusts the bandwidth of the target logical device according to the maximum adjustment range. The bandwidth utilization is improved by adjusting the bandwidth of the target logical device.

[0016] In another possible design, the BMC determines an adjustment range of the target logical device according to the average load state of the target logical device, and adjusts the bandwidth of the target logical device according to the adjustment range. The bandwidth utilization is improved by adjusting the bandwidth of the target logical device.

[0017] In a second aspect, an embodiment of the present application provides a computing fast link (CXL) system, the CXL system comprising at least one CXL device and a baseboard management controller (BMC), the at least one CXL device comprising a first CXL device, the first CXL device comprising at least two logical devices, and wherein:

[0018] The BMC is configured to acquire an average load state of each logical device in the first CXL device, determine a target logical device and an adjustment strategy in the first CXL device according to the average load state, and adjust a bandwidth of the target logical device according to the adjustment strategy.

[0019] In another possible design, the first CXL device is configured to acquire the average load state of each logical device in the first CXL device, and send the average load state to the BMC.

[0020] In another possible design, the first CXL device is further configured to acquire a number of times of each load state of each logical device in the first CXL device in a first time period, and acquire a total number of times of each load state in the first time period, and determine the average load state of each logical device in the first CXL device according to the number of times of each load state of each logical device in the first CXL device and the total number of times.

[0021] In another possible design, the BMC is further configured to send an access request to each CXL device in the at least one CXL device, the access request being configured to indicate to acquire the average load state of each logical device in each CXL device.

[0022] In another possible design, the average load state comprises an average light load, an average optimal load, an average moderate overload, and an average severe overload, and the first CXL device comprises a first logical device and a second logical device.

[0023] The BMC is further configured to determine the target logical device as the first logical device and the second logical device when the average load status of the first logical device and the average load status of the second logical device are different.

[0024] In another possible design, the BMC is further configured to increase the bandwidth of the first logical device and decrease the bandwidth of the second logical device when the severity of the average load status of the first logical device is higher than the average load status of the second logical device; or,

[0025] The BMC is further configured to decrease the bandwidth of the first logical device and increase the bandwidth of the second logical device when the severity of the average load status of the first logical device is lower than the average load status of the second logical device.

[0026] In another possible design, the BMC is further configured to configure a mapping relationship between a logical device and a host in each CXL device of the at least one CXL device, and configure the bandwidth of each logical device in each CXL device.

[0027] In another possible design, the BMC is further configured to adjust the bandwidth of the target logical device according to a preset adjustment range.

[0028] In another possible design, the BMC is further configured to subtract a preconfigured allocated bandwidth from a preconfigured upper limit bandwidth to obtain a maximum adjustment range, and adjust the bandwidth of the target logical device according to the maximum adjustment range.

[0029] In another possible design, the BMC is further configured to determine an adjustment range of the target logical device according to the average load status of the target logical device, and adjust the bandwidth of the target logical device according to the adjustment range.

[0030] The CXL system performs operations and has advantages as described in the method of the first aspect and the advantages, and details are not repeated.

[0031] In a third aspect, an embodiment of the present application provides a bandwidth adjustment apparatus, comprising:

[0032] A management module is configured to obtain an average load status of each logical device in the first CXL device, determine a target logical device and an adjustment strategy in the first CXL device according to the average load status, and adjust the bandwidth of the target logical device according to the adjustment strategy.

[0033] In a possible design, the apparatus further comprises:

[0034] The computing module is configured to acquire the average load state of each logical device in the first CXL device, and send the average load state to the BMC.

[0035] In another possible design, the computing module is further configured to acquire the number of times of each load state of each logical device in the first CXL device in a first time period, and acquire the total number of times of each load state in the first time period; and determine the average load state of each logical device in the first CXL device according to the number of times of each load state of each logical device in the first CXL device and the total number of times.

[0036] In another possible design, the management module is further configured to send an access request to each CXL device of the at least one CXL device, where the access request is used to instruct to acquire the average load state of each logical device in the each CXL device.

[0037] In another possible design, the management module is further configured to determine the target logical device as the first logical device and the second logical device when the average load state of the first logical device and the average load state of the second logical device are different.

[0038] In another possible design, the management module is further configured to increase the bandwidth of the first logical device and decrease the bandwidth of the second logical device when the severity of the average load state of the first logical device is higher than the average load state of the second logical device, or decrease the bandwidth of the first logical device and increase the bandwidth of the second logical device when the severity of the average load state of the first logical device is lower than the average load state of the second logical device.

[0039] In another possible design, the management module is further configured to configure the mapping relationship between a logical device and a host in each CXL device of the at least one CXL device, and configure the bandwidth of each logical device in the each CXL device.

[0040] In another possible design, the management module is further configured to adjust the bandwidth of the target logical device according to a preset adjustment range.

[0041] In another possible design, the management module is further configured to subtract a preconfigured allocated bandwidth from a preconfigured upper limit bandwidth to obtain a maximum adjustment range, and adjust the bandwidth of the target logical device according to the maximum adjustment range.

[0042] In another possible design, the management module is further configured to determine an adjustment range of the target logical device according to the average load status of the target logical device; and adjust the bandwidth of the target logical device according to the adjustment range.

[0043] The bandwidth adjustment apparatus performs the operations and has the advantages of the method described in the first aspect above. Details are not repeated here.

[0044] In a fourth aspect, the present application provides a switching device, which comprises a processor and a memory, the memory being configured to store computer-executed instructions; and the processor being configured to execute the computer-executed instructions stored in the memory, so that the switching device performs the method described in any one of the first aspect.

[0045] In a fifth aspect, the present application provides a computer-readable storage medium, which is configured to store a computer program, when the computer program is executed, so that the method described in any one of the first aspect is implemented.

[0046] In a sixth aspect, the present application provides a computer program product comprising a computer program, when the computer program is executed, so that the method described in any one of the first aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0048] Figure 1 is a schematic diagram of a CXL system provided by the embodiments of the present application;

[0049] Figure 2 is a flowchart of a bandwidth adjustment method provided by the embodiments of the present application;

[0050] Figure 3 is a flowchart of another bandwidth adjustment method provided by the embodiments of the present application;

[0051] Figure 4 is a structural diagram of a bandwidth adjustment apparatus provided by the embodiments of the present application;

[0052] Figure 5 is a structural diagram of a switching device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0053] The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0054] Figure 1is a schematic diagram of a CXL system provided by an embodiment of the present application. The CXL system can be a server, and the CXL system can include a host (Host), a CXL switch (CXL Switch), and at least one CXL device (CXL Device) and a board management controller (BMC), and the like. Among them, the CXL device can include a cache and an accessible memory, and the CXL device can receive an access request of the Host or return a response to the Host. The CXL device can also include a decoder (Decoder) for decoding the received access request. The CXL device can include multiple logical devices (Multiple Logical Device, MLD), and each MLD further includes multiple LDs. The CXL device can also include a single logical device (Single Logical Device, SLD). The LD or SLD is a virtual device with storage and statistical functions created on the CXL device. The CXL switch includes an upstream port (UpStream Port, UP) and a downstream port (DownStream Port, DP), which are respectively connected with the Host, the MLD and / or the SLD, and the UP of the CXL switch can also include the Decoder. The CXL switch can realize the mapping relationship between the SLD or the LD and the Host. The BMC can establish the mapping relationship between the LD and the Host, and can also configure the bandwidth of the LD or the SLD.

[0055] It should be noted that the BMC can be arranged on the CXL switch, or can be a separate device.

[0056] In an embodiment of the present application, a calculation unit is added in the CXL Device. The calculation unit can calculate the average load state (average DevLoad, AvrDevLoad) of each logical device, and then report the average load state of each logical device to the BMC. The BMC adjusts the bandwidth of each logical device according to the average load state. The following embodiments are described in detail, which will not be described here.

[0057] The expansion of CXL memory resources can include the following two modes: first, local direct expansion of CXL memory resources. Second, pooling of CXL memory resources. In the pooling mode of memory resources, the host is connected with the pooled memory resources through the CXL Switch, and the memory resources are re-allocated and allocated according to different workloads. After a work load is completed, the memory resources can be released and applied to the next work task. The pooling of memory resources can support multiple hosts and multiple memory resources at the same time.

[0058] In the application of pooling of memory resources, a Host accesses the LD corresponding to the Host through the uplink port and the downlink port of the CXL Switch. For example, the Host can send an access request to the CXL Switch, the CXL Switch receives the access request of the Host through the uplink port, and then determines the LD corresponding to the Host according to the mapping relationship between the SLD or the LD and the Host, and forwards the access request to the LD corresponding to the Host through the downlink port. After the LD receives the access request, it returns a response to the Host according to the access request. Wherein, the LD accessed by the Host can belong to different MLDs, or can belong to the same MLD.

[0059] Since the access traffic demand of the Host to the LD is constantly changing, the LD has different load states at different times. The CXL Standard Performance Evaluation Organization (Standard Performance Evaluation Corporation, SPEC) defines a Quality of Service (QoS) mechanism for CXL devices, which defines the load state (Devload) of the CXL device. The Host can obtain the load state of each CXL device and control the access request to the CXL device according to the load state.

[0060] In the QoS mechanism defined by CXL Spec, the bandwidth access load of the CXL device is divided into four load states. As shown in Table 1, the four load states include Light load, Optimal load, Moderate overload and Severe overload. Among them, the load state can represent the state of the queuing delay in the CXL device, or the resource utilization rate in the CXL device.

[0061] Table 1

[0062] Load state In-device queuing delay state Resource utilization Light load Lowest Handle more requests at any time Optimal load Moderate Optimal utilization Moderate overload Severe Limit throughput and / or reduce efficiency Severe overload Very severe Severe overload and / or reduce efficiency

[0063] The QoS mechanism defined by CXL spec is as follows:

[0064] (1) The BMC configures the mapping relationship between the Host and the CXL Device. For example, Figure 1As shown, LD1 of MLD_0, LD0 of MLD_1 and SLD_0 are mapped to Host1 (the bold part), LD0 of MLD_0, LD1 of MLD_1 are mapped to Host2 (the dotted line part). As shown in Table 2, the mapping relationship of LD1 of MLD_0 and LD0 of MLD_1 to Host1, and the mapping relationship of LD0 of MLD_0 and LD1 of MLD_1 to Host2 are configured. As shown in Table 3, the mapping relationship of SLD_0 to Host1 is configured.

[0065] Table 2

[0066]

[0067] Table 3

[0068] Host number SLD number Host 1 0

[0069] (2) The BMC configures the allocation bandwidth and the upper limit bandwidth of each LD and / or SLD according to the traffic size of the service requirement of each LD and / or SLD.

[0070] In the QoS mechanism defined by CXL, the bandwidth (BandWidth, BW) of LD and / or SLD includes: allocation bandwidth (Allocated BW) and upper limit bandwidth (Limit BW). Among them, Allocate BW can represent the guaranteed bandwidth that LD and / or SLD can allocate or use, and Limit BW can represent the maximum bandwidth that LD and / or SLD can allocate or use.

[0071] If the traffic of the service requirement of a certain LD and / or SLD is greater than the traffic of the service requirement of other LD and / or SLD, the allocation bandwidth and the upper limit bandwidth of the LD and / or SLD can be configured to be higher than the allocation bandwidth and the upper limit bandwidth of other LD and / or SLD. If the traffic of the service requirement of a certain LD and / or SLD is less than the traffic of the service requirement of other LD and / or SLD, the allocation bandwidth and the upper limit bandwidth of the LD and / or SLD can be configured to be lower than the allocation bandwidth and the upper limit bandwidth of other LD and / or SLD.

[0072] (3) Each LD calculates the current access traffic of the respective LD, and updates the load state of the LD according to the current access traffic of the respective LD.

[0073] Specifically, the LD can count the number of received access requests, determine the current access traffic of the Host accessing the LD according to the number of access requests, and update the load state of the LD according to the current access traffic, the allocated BW and the limit BW. For example, if the current access traffic bandwidth of the LD exceeds the limit BW, the current load state is adjusted to be higher. If the current access traffic bandwidth of the LD is lower than the allocated BW, the current load state is adjusted to be lower.

[0074] After updating the load state, the LD can send the updated load state to the Host. For example, the updated load state can be sent to the Host through a No Data Response (NDR) message, so that the Host adjusts the number of access requests.

[0075] As shown in Table 4, if the load state of a certain LD is Light load or Optimal load, and the current access traffic exceeds the limit BW, the LD adjusts its own load state from Light load or Optimal load to Moderate overload. If the load state of a certain LD is Moderate overload, and the current access traffic does not exceed the allocated BW and does not exceed the limit BW, the LD adjusts its own load state from Moderate overload to Optimal load. If the load state of a certain LD is Moderate overload, and the current access traffic exceeds the allocated BW and does not exceed the limit BW, the LD keeps the load state of the LD as Moderate overload. If the load state of a certain LD is Moderate overload, and the current access traffic exceeds the limit BW, the LD adjusts its own load state from Moderate overload to Severe overload. Other cases are shown in Table 4 and will not be described one by one.

[0076] Table 4

[0077]

[0078] (4) Host adjusts access requests to LD.

[0079] According to the definition of CXL specs, the Host can obtain the load state of the LD from the NDR message, and then adjust the number of access requests to the LD according to the load state of the LD, so as to control the bandwidth utilization of the LD.

[0080] In summary, if the LDs accessed by a Host all belong to the same MLD, the Host can adjust the access request to the LDs in time according to the load state of the LDs accessed by the Host, so as to realize the control of QoS. However, this scheme only considers the case of a single Host and does not consider the mutual influence between multiple Hosts. When the LDs accessed by different Hosts belong to the same MLD, or the LDs accessed by the same Host belong to different MLDs, for example, Figure 1 LD0 in MLD_0 in FIG. 1 maps to Host2 and LD1 maps to Host1, that is, MLD_0 is accessed by Host1 and Host2 at the same time. Since one of the Hosts does not know the load state of the LDs accessed by the other Host, there may be a case that the access bandwidth of the LDs accessed by one of the Hosts is idle while the access bandwidth of the LDs accessed by the other Host is overloaded, resulting in that the bandwidth of the MLD cannot be fully utilized.

[0081] To solve the above technical problems, the embodiments of the present application provide the following solutions.

[0082] As shown in Figure 2 Figure 2 is a flowchart of a bandwidth adjustment method provided by the embodiments of the present application. The method mainly includes the following steps:

[0083] S201, the BMC obtains the average load state of each logical device in the first CXL device.

[0084] Specifically, the BMC can send an access request to each CXL device in at least one CXL device, and the access request is used to indicate the acquisition of the average load state of each logical device in each CXL device. After receiving the access request, the first CXL device obtains the number of various load states of each logical device in the first CXL device within a first time period, and obtains the total number of various load states within the first time period; according to the number of various load states of each logical device in the first CXL device and the total number, the average load state of each logical device in the first CXL device is determined. And send the average load state to the BMC.

[0085] Among them, the average load state includes average light load, average optimal load, average moderate overload and average serious overload.

[0086] S202, the BMC determines the target logical device and the adjustment strategy in the first CXL device according to the average load state.

[0087] Among them, the first CXL device can include a first logical device and a second logical device. The adjustment strategy can include one or more of upward adjustment, downward adjustment and adjustment amplitude.​

[0088] Specifically, when the average load status of the first logical device and the average load status of the second logical device are different, the BMC determines the target logical device as the first logical device and the second logical device. When the severity of the average load status of the first logical device is higher than the average load status of the second logical device, the BMC increases the bandwidth of the first logical device, and the BMC decreases the bandwidth of the second logical device; or when the severity of the average load status of the first logical device is lower than the average load status of the second logical device, the BMC decreases the bandwidth of the first logical device, and the BMC increases the bandwidth of the second logical device.

[0089] S203, the BMC adjusts the bandwidth of the target logical device according to the adjustment strategy.

[0090] In an embodiment, the BMC can adjust the bandwidth of the target logical device according to a preset adjustment range.

[0091] In an embodiment, the BMC can calculate a maximum adjustment range by subtracting a preconfigured allocated bandwidth from a preconfigured upper limit bandwidth, and then adjust the bandwidth of the target logical device according to the maximum adjustment range.

[0092] In an embodiment, the BMC can determine an adjustment range of the target logical device according to the average load status of the target logical device, and then adjust the bandwidth of the target logical device according to the determined adjustment range.

[0093] In the embodiments of the present application, the BMC adjusts the bandwidth of the logical device in the first CXL device according to the average load status of each logical device in the first CXL device. In this way, even if multiple logical devices in the same CXL device are accessed by different hosts, the bandwidth utilization of the CXL device can be improved by adjusting the bandwidth of the logical device in the CXL device.

[0094] As shown in Figure 3 , FIG. 2 is a flow diagram of another bandwidth adjustment method provided by the embodiments of the present application. The method mainly includes the following steps: Figure 3

[0095] S301, the BMC configures the mapping relationship between the logical device in each CXL device and the host in at least one CXL device, and configures the bandwidth of each logical device in each CXL device. As shown in Figure 1 ​As shown, LD1 of MLD_0, LD0 of MLD_1 and SLD_0 are mapped to Host1 (the bold part), and LD0 of MLD_0 and LD1 of MLD_1 are mapped to Host2 (the dotted part). As shown in Table 5, the mapping relationship of LD1 of MLD_0 and LD0 of MLD_1 to Host1 and the mapping relationship of LD0 of MLD_0 and LD1 of MLD_1 to Host2 are configured.

[0096] Table 5

[0097]

[0098] As shown in Table 6, the mapping relationship of SLD_0 to Host1 is configured.

[0099] Table 6

[0100] Host number SLD number Host 1 0

[0101] Specifically, the BMC can configure the allocation bandwidth and the upper limit bandwidth of each LD and / or SLD according to the traffic size of the service requirement of each LD and / or SLD. The configured allocation bandwidth can be used as the initial allocation bandwidth, and the configured upper limit bandwidth can be used as the initial upper limit bandwidth.

[0102] For example, if the traffic of the service requirement of a certain LD and / or SLD is greater than the traffic of the service requirement of other LDs and / or SLDs, the allocation bandwidth and the upper limit bandwidth of the LD and / or SLD can be configured to be higher than the allocation bandwidth and the upper limit bandwidth of the other LDs and / or SLDs. If the traffic of the service requirement of a certain LD and / or SLD is less than the traffic of the service requirement of other LDs and / or SLDs, the allocation bandwidth and the upper limit bandwidth of the LD and / or SLD can be configured to be lower than the allocation bandwidth and the upper limit bandwidth of the other LDs and / or SLDs.

[0103] As shown in Table 7, Table 7 is a bandwidth allocation table of an MLD, the allocation bandwidth of LD0 of MLD_0 is 40%, and the upper limit bandwidth of LD0 of MLD_0 is 60%. The allocation bandwidth of LD1 of MLD_0 is 40%, and the upper limit bandwidth of LD1 of MLD_0 is 60%. The allocation bandwidth of LD0 of MLD_1 is 40%, and the upper limit bandwidth of LD0 of MLD_1 is 60%. The allocation bandwidth of LD1 of MLD_1 is 40%, and the upper limit bandwidth of LD1 of MLD_1 is 60%.

[0104] Table 7

[0105]

[0106] As shown in Table 8, Table 8 is a bandwidth allocation table of an SLD, the allocation bandwidth of the SLD is 40%, and the upper limit bandwidth of the SLD is 60%.

[0107] Table 8

[0108] SLD number Allocated bandwidth (%) Upper bandwidth limit (%) 1 40 60

[0109] S302, a computing unit in a first CXL device of the at least one CXL device counts the number of times each logical device in the first CXL device appears in various load states in a first time period, and obtains a total number of times of various load states in the first time period. The first CXL device can be any one of the plurality of MLD devices.

[0110] Specifically, the load state of each logical device can include Light load, Optimal load, Moderate overload, or Severe overload. The first time period can include N sampling periods. The computing unit can determine the load state of each logical device in each sampling period, and obtain the load state of each logical device in the N sampling periods. Then, the load state of each logical device in the N sampling periods is counted to determine the number of times each logical device appears in various load states. The total number of times can be equal to N, where N is an integer greater than or equal to 1.

[0111] For example, MLD_0 includes LD0 and LD1, and the first time period includes 5 sampling periods. In the first sampling period, the load state of LD0 is Light load, and the load state of LD1 is Optimal load. In the second sampling period, the load state of LD0 is Optimal load, and the load state of LD1 is Moderate overload; in the third sampling period, the load state of LD0 is Light load, and the load state of LD1 is Optimal load. In the fourth sampling period, the load state of LD0 is Light load, and the load state of LD1 is Optimal load. In the fifth sampling period, the load state of LD0 is Light load, and the load state of LD1 is Severe overload. Based on the statistics of the above 5 sampling periods, the number of times the load state of LD0 is Light load is 4, the number of times the load state of LD0 is Optimal load is 1, and the number of times the load state of LD0 appears in other load states is 0. The number of times the load state of LD1 is Optimal load is 3, the number of times the load state of LD1 is Moderate overload is 1, and the number of times the load state of LD1 is Severe overload is 1.

[0112] Optionally, the number of access requests received by each logical device in each sampling period ReqCnt and the number of completion responses CmpCnt are obtained, and the occupied bandwidth of each logical device is determined according to the number of access requests and the number of completion responses. Then, the load state of each logical device is determined according to the occupied bandwidth of each logical device and the pre-configured allocated bandwidth. The information length of the access request and the completion response is a fixed value.

[0113] Further, the sum of the number of access requests ReqCnt and the number of completion responses CmpCnt in each sampling period is calculated to obtain the occupied bandwidth of each logical device, and then the load state of each logical device is determined according to the ratio between the occupied bandwidth and the pre-configured allocated bandwidth.

[0114] For example, if the occupied bandwidth of LD0 in MLD_0 is 80MB / s and the pre-configured allocated bandwidth is 50MB / s in a certain sampling period, the ratio between the occupied bandwidth and the pre-configured allocated bandwidth is 1.6, and it can be determined that the load state of LD0 in the sampling period is Severe overload. If the occupied bandwidth of LD0 in MLD_0 is 50MB / s and the pre-configured allocated bandwidth is 50MB / s, the ratio between the occupied bandwidth and the pre-configured allocated bandwidth is 1.0, and it can be determined that the load state of LD0 in the sampling period is Optimal load.

[0115] S303, the computing unit in the first CXL device determines the average load state of each logical device in the first CXL device according to the number of times each logical device in the first CXL device appears in various load states and the total number of times.

[0116] Specifically, the number of times a first logical device in a plurality of logical devices appears in a first load state is divided by the total number of times to obtain a proportion value corresponding to the first load state, and then the proportion value corresponding to the first load state is compared with a first threshold value corresponding to the first load state. If the proportion value corresponding to the first load state is greater than or equal to the first threshold value corresponding to the first load state, the average load state of the first logical device is determined as the first load state. The first load state is any one of the light load, the optimal load, the moderate overload and the severe overload.

[0117] The average load state can include five states, i.e., an average light load (Avr Light load), an average optimal load (Avr Optimal load), an average moderate overload (Avr Moderate overload), an average severe overload (Avr Severe overload), and a variation (Vary). When the proportion of any one of the load states of the first logical device is less than the corresponding first threshold value, the average load state of the first logical device is determined as Vary. It should be noted that the four states, i.e., the average light load (Avr Light load), the average optimal load (Avr Optimal load), the average moderate overload (Avr Moderate overload), and the average severe overload (Avr Severe overload), are in ascending order of severity.

[0118] As shown in Table 9, Table 9 is a preconfigured table of determination threshold values. For example, the load state of LD0 of MLD_0 is Light load, and the corresponding first threshold value is 80%. When the proportion of the number of times that LD0 of MLD_0 appears in the Light load state to the total number of times is greater than or equal to 80%, the average load state of LD0 of MLD_0 is determined as Avr Light load. For another example, the load state of LD0 of MLD_0 is Moderate overload, and the corresponding first threshold value is 70%. When the proportion of the number of times that LD0 of MLD_0 appears in the Moderate overload state to the total number of times is greater than or equal to 70%, the average load state of LD0 of MLD_0 is determined as Avr Moderate overload. For another example, when the proportion of the number of times that LD0 of MLD_0 appears in the Light load state to the total number of times is less than 80%, the proportion of the number of times that LD0 of MLD_0 appears in the Optimal load state to the total number of times is less than 80%, the proportion of the number of times that LD0 of MLD_0 appears in the Moderate overload state to the total number of times is less than 70%, and the proportion of the number of times that LD0 of MLD_0 appears in the Severe overload state to the total number of times is less than 70%, the average load state of LD0 of MLD_0 is determined as Vary.

[0119] Table 9

[0120]

[0121] S304, the BMC counts the average load state of each logical device in each CXL device.

[0122] Specifically, the BMC can send an access request to the computing units in each CXL device, and after the computing units in each CXL device receive the access request, the average load state of each logical device is reported to the BMC, and the BMC aggregates the average load state of each logical device reported by each CXL device.

[0123] As shown in Table 10, Table 10 is an aggregation table of the average load state of each logical device in the MLD. The average load state of LD0 of MLD_0 is Avr Light load, and the average load state of LD1 of MLD_0 is Avr Moderate overload. The average load state of LD0 of MLD_1 is Avr Light load, and the average load state of LD1 of MLD_1 is Avr Severe overload.

[0124] Table 10

[0125]

[0126] As shown in Table 11, Table 11 is an aggregation table of the average load state of the SLD. The average load state of SLD_0 is Avr Light load.

[0127] Table 11

[0128] Host number SLD number Average load state 1 0 Average light load

[0129] S305, the BMC determines a target logical device in each CXL device that needs to adjust the bandwidth according to the average load state of each logical device in each CXL device, and adjusts the bandwidth of the target logical device.

[0130] Specifically, when there are at least two LDs with different average load states in one CXL device, the BMC can determine these LDs as target logical devices that need to adjust the bandwidth, and adjust the bandwidth of the LD with lower severity of the average load state downward and adjust the bandwidth of the LD with higher severity of the average load state upward.

[0131] Exemplarily, as shown in Table 10, MLD_0 includes two logical devices LD0 and LD1, when the average load state of LD0 is Avr Light load and the average load state of LD1 is Avr Severe overload, LD0 and LD1 of MLD_0 can be determined as target devices, and the BMC adjusts the bandwidth of LD0 downward and adjusts the bandwidth of LD1 upward. Figure 1

[0132] ​For example, when the average load state of LD0 is Avr Light load, the average load state of LD1 is Avr Optimal load, and the average load state of LD2 is Avr Severe overload, the LD0, LD1 and LD2 of the MLD_0 can be determined as the target devices, and the bandwidth of the LD0 is adjusted downward, and the bandwidth of the LD1 and LD2 is adjusted upward.

[0133] Alternatively, for example, when the average load state of LD0 is Avr Light load, and the average load state of LD1 is Avr Optimal load, the LD0 and LD1 of the MLD_0 can also be determined as the target devices, and the bandwidth of the LD0 is adjusted downward, and the bandwidth of the LD1 is adjusted upward, so that the bandwidth utilization between the two LDs is more balanced.

[0134] It should be noted that when the average load states of all the LDs in a CXL device are the same, the BMC can not need to adjust the bandwidth of the LDs in the CXL device. In addition, if the average load state of a certain LD in the MLD is Vary, indicating that the average load state of the LD varies frequently, no adjustment can be made to the LD.

[0135] In an embodiment, the LDs in the MLD whose average load states are Avr Light load or Avr Severe overload can be determined as the target logical devices first, and the bandwidth of the target logical devices whose average load states are Avr Light load or Avr Severe overload is adjusted. Then, the LDs in the MLD whose average load states are Avr Optimal load or Avr Moderate overload can be determined as the target logical devices, and the bandwidth of the target logical devices whose average load states are Avr Optimal load or Avr Moderate overload is adjusted. That is, the LDs whose average load states are Avr Light load or Avr Severe overload are adjusted preferentially.

[0136] Further, if the average load state of the target logical device is Avr Light load or Avr Optimal load, the bandwidth of the target logical device can be adjusted downward. If the average load state of the target logical device is Avr Moderate overload or Avr Severe overload, the bandwidth of the target logical device can be adjusted upward. Thus, redundant bandwidth is allocated to the LDs whose average load state is Avr Moderate overload or Avr Severe overload, and the bandwidth utilization of the MLD is improved.

[0137] For example, as shown in Table 8, LD1 of MLD_0, LD0 of MLD_1 and SLD_0 are mapped to Host 1, and LD0 of MLD_0, LD1 of MLD_1 are mapped to Host 2. That is, MLD_0 is accessed by both Host 1 and Host 2, and MLD_1 is also accessed by both Host 1 and Host 2. As shown in Table 8, since the average load state of LD0 of MLD_1 is Avr Light load and the average load state of LD1 of MLD_1 is Avr Severe overload, LD0 and LD1 of MLD_1 can be determined as target logical devices. The bandwidth of LD0 of MLD_1 is adjusted downward, and the bandwidth of LD1 of MLD_1 is adjusted upward. Figure 1

[0138] In another embodiment, the LDs in the MLD whose average load state is Avr Light load can be determined as first target logical devices, and the bandwidth of the first target logical devices is adjusted downward. Then the LDs in the MLD whose average load state is Avr Moderate overload or Avr Severe overload can be determined as second target logical devices, and the bandwidth of the second target logical devices is adjusted upward.

[0139] For example, as shown in Table 8, LD1 of MLD_0, LD0 of MLD_1 and SLD_0 are mapped to Host 1, and LD0 of MLD_0, LD1 of MLD_1 are mapped to Host 2. That is, MLD_0 is accessed by both Host 1 and Host 2, and MLD_1 is also accessed by both Host 1 and Host 2. As shown in Table 8, since the average load state of LD0 of MLD_1 is Avr Light load and the average load state of LD1 of MLD_1 is Avr Severe overload, LD0 and LD1 of MLD_1 can be determined as target logical devices. The bandwidth of LD0 of MLD_1 is adjusted downward, and the bandwidth of LD1 of MLD_1 is adjusted upward. Figure 1 ​As shown in Table 8, LD1 of MLD_0, LD0 of MLD_1 and SLD_0 are mapped to Host1, LD0 of MLD_0, LD1 of MLD_1 are mapped to Host2. That is, MLD_0 is accessed by both Host1 and Host2, and MLD_1 is also accessed by both Host1 and Host2. As shown in Table 8, since the average load state of LD0 of MLD_0 is Avr Light load, LD0 of MLD_0 can be determined as the first target device, and the bandwidth of LD0 of MLD_0 can be adjusted downward. Since the average load state of LD1 of MLD_0 is Avr Moderate overload, LD1 of MLD_0 can be determined as the second target logical device, and the bandwidth of LD1 of MLD_0 can be adjusted upward.

[0140] Optionally, the BMC can also determine whether the LDs accessed by different Hosts belong to the same MLD, or whether the LDs accessed by the same Host belong to different MLDs according to the mapping relationship between each logical device and the Host. If a certain MLD is accessed by multiple Hosts, one or more LDs in the MLD that need to be adjusted in bandwidth can be determined and adjusted in priority according to the average load state of each LD in the MLD.

[0141] Further, the bandwidth of the target logical device can be adjusted in the following manner.

[0142] In an embodiment, the bandwidth of the target logical device can be adjusted according to a preset adjustment range.

[0143] In an embodiment, the maximum adjustment range can be calculated by subtracting the preconfigured allocated bandwidth from the preconfigured upper limit bandwidth, and then the bandwidth of the target logical device can be adjusted according to the maximum adjustment range. Further, the bandwidth of the target logical device can be adjusted without exceeding the maximum adjustment range.

[0144] For example, if a same MLD includes two LDs (LD1 and LD2), the average load state of LD1 is Avr Light load, the average load state of LD2 is Avr Severe overload, the preconfigured upper limit bandwidth of LD1 and LD2 is 60%, and the preconfigured allocated bandwidth of LD1 and LD2 is 40%, the maximum adjustment range is calculated to be 20% (60%-40%). Therefore, the bandwidth of LD1 can be adjusted downward by 20%, and the bandwidth of LD2 can be adjusted upward by 20%.

[0145] In one embodiment, the adjustment range of the target logical device can be determined according to the average load status of the target logical device, and then the bandwidth of the target logical device is adjusted according to the determined adjustment range.

[0146] For example, if there are 3 LDs (LD1, LD2 and LD3) in the same MLD, the average load status of LD1 is Avr Light load, the average load status of LD2 is Avr Optimal load, and the average load status of LD3 is Avr Severe overload. Therefore, it is determined to adjust the bandwidth of LD1 and LD2 downward and adjust the bandwidth of LD3 upward. However, since the average load status of LD1 is better than that of LD2, it is determined that the adjustment range of LD1 is greater than that of LD2. For example, the bandwidth of LD1 can be adjusted downward by 10%, the bandwidth of LD2 can be adjusted downward by 5%, and the bandwidth of LD3 can be adjusted upward by 15%.

[0147] It should be understood that if the average load status of multiple LDs in the same MLD is Avr Moderate overload or Avr Severe overload, the bandwidth of the multiple LDs can be adjusted upward simultaneously according to a certain distribution ratio. If the average load status of multiple LDs in the same MLD is Avr Light load or Avr Optimal load, the bandwidth of the multiple LDs can be adjusted downward simultaneously according to a certain distribution ratio. For example, a certain MLD includes 4 LDs, and the maximum adjustment range of the bandwidth of each LD is 20%, among which the average load status of 2 LDs is Avr Severe overload, and the average load status of the other 2 LDs is Avr Light load. The bandwidth of the 2 LDs with Avr Severe overload can be adjusted upward by 10% respectively, and the bandwidth of the other 2 LDs with Avr Light load can be adjusted downward by 10% respectively.

[0148] Further, the bandwidth of the target logical device includes a pre-configured distribution bandwidth and an upper limit bandwidth, and the pre-configured distribution bandwidth or / and the upper limit bandwidth of the target logical device can be adjusted respectively.

[0149] For example, if the average load status of the first LD in the MLD is Avr Light load, and the average load status of the second LD is Avr Severe overload, the allocated bandwidth and the upper limit bandwidth of the first LD can be adjusted downward, and the allocated bandwidth and the upper limit bandwidth of the second LD can be adjusted upward. Thus, the bandwidth of the first LD is fully allocated to the second LD, which not only ensures that the first LD has no redundant bandwidth, but also ensures that the second LD has sufficient bandwidth to handle traffic. If the average load status of the first LD in the MLD is Avr Light load, and the average load status of the second LD is Avr Moderate overload, the allocated bandwidth of the first LD can be adjusted downward, and the allocated bandwidth of the second LD can be adjusted upward, so that the first LD and the second LD can obtain guaranteed bandwidth to handle traffic. If the average load status of the second LD is not improved after adjusting the allocated bandwidth of the first LD and the second LD, the upper limit bandwidth of the first LD and the second LD can be further adjusted, and more bandwidth of the first LD is allocated to the second LD.

[0150] It should be noted that for the same LD, the allocated bandwidth and the upper limit bandwidth can be adjusted according to different adjustment amplitudes, or the allocated bandwidth and the upper limit bandwidth can be adjusted according to the same adjustment amplitude. For different LDs, the bandwidth can be adjusted upward or downward according to different adjustment amplitudes, or the bandwidth can be adjusted upward or downward according to the same adjustment amplitude.

[0151] For example, as shown in Table 7, the pre-configured allocated bandwidth of LD0 and LD1 of MLD_1 is 40%, and the pre-configured upper limit bandwidth of LD0 and LD1 of MLD_1 is 60%. Since the average load status of LD0 of MLD_1 is Avr Light load, and the average load status of LD1 of MLD_1 is Avr Severe overload, it is determined to adjust the upper limit bandwidth and the allocated bandwidth of LD0 of MLD_1 downward, and adjust the upper limit bandwidth and the allocated bandwidth of LD1 of MLD_1 upward. Then, the pre-configured upper limit bandwidth 60% is subtracted by the pre-configured allocated bandwidth 40%, and the maximum adjustment amplitude 20% is calculated.

[0152] Table 12 is to re-adjust the bandwidths of LD0 and LD1 of MLD_1 based on the pre-configured bandwidths shown in Table 7. As shown in Table 12, the upper limit bandwidth of LD0 of MLD_1 is adjusted downward from 60% to 45% according to an adjustment range of 15% (not more than the maximum adjustment range 20%); the allocated bandwidth of LD0 of MLD_1 is adjusted downward from 40% to 30% according to an adjustment range of 10%. The upper limit bandwidth of LD0 of MLD_1 is adjusted upward from 60% to 75% according to an adjustment range of 15%; the allocated bandwidth of LD0 of MLD_1 is adjusted downward from 40% to 60% according to an adjustment range of 20%. The bandwidths of LD0 and LD1 of MLD_0 are not adjusted.

[0153] Table 12

[0154]

[0155] It should be noted that after step 301 is performed, steps 302-305 can be executed multiple times so that the BMC can timely adjust the bandwidth according to the actual working state of the logical device in the CXL device. For example, steps 302-305 can be periodically executed.

[0156] It should be noted that other methods of determining the target logical device and adjusting the bandwidth of the target logical device are also within the scope of protection of the present application.

[0157] In the embodiments of the present application, by adding a calculation unit in the CXL device, the calculation unit is used to count the proportion of various load states in the first time period, to determine the average load state of each LD in the same CXL device, and to adjust the bandwidth of different LDs in the same CXL device according to the average load state. In this way, even when multiple LDs in the CXL device are accessed by different hosts, the bandwidth utilization of the CXL device can be improved by adjusting the bandwidth of the LDs in the CXL device.

[0158] The embodiments of the present application can divide the CXL system into functional modules according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, another division method can be used. The following will be described taking the division of each functional module according to each function as an example.

[0159] As shown in FIG. 13, the CXL device includes a calculation unit 1301, a bandwidth adjustment unit 1302, and a bandwidth adjustment unit 1303. Figure 4 As shown in FIG. 13, the CXL device includes a calculation unit 1301, a bandwidth adjustment unit 1302, and a bandwidth adjustment unit 1303. Figure 4Figure 1 is a schematic diagram of a bandwidth adjustment device provided by an embodiment of the present application. The bandwidth adjustment device can include a management module 401 and a calculation module 402. Wherein

[0160] The management module 401 is configured to acquire an average load state of each logical device in the first CXL device; determine a target logical device and an adjustment strategy in the first CXL device according to the average load state; and adjust the bandwidth of the target logical device according to the adjustment strategy.

[0161] Optionally, the calculation module 402 is configured to acquire the average load state of each logical device in the first CXL device; and send the average load state to the BMC.

[0162] Optionally, the calculation module 402 is further configured to acquire a number of times of each load state of each logical device in the first CXL device within a first time period, and acquire a total number of times of each load state within the first time period; and determine the average load state of each logical device in the first CXL device according to the number of times of each load state of each logical device in the first CXL device and the total number of times.

[0163] Optionally, the management module 401 is further configured to send an access request to each CXL device of the at least one CXL device, the access request being configured to indicate to acquire the average load state of each logical device in each CXL device.

[0164] Optionally, the management module 401 is further configured to determine the target logical device as the first logical device and the second logical device when the average load state of the first logical device and the average load state of the second logical device are different.

[0165] Optionally, the management module 401 is further configured to adjust the bandwidth of the first logical device upwards and adjust the bandwidth of the second logical device downwards when the severity of the average load state of the first logical device is higher than the average load state of the second logical device; or adjust the bandwidth of the first logical device downwards and adjust the bandwidth of the second logical device upwards when the severity of the average load state of the first logical device is lower than the average load state of the second logical device.

[0166] Optionally, the management module 401 is further configured to configure a mapping relationship between a logical device and a host in each CXL device of the at least one CXL device, and configure the bandwidth of each logical device in each CXL device.

[0167] Optionally, the management module 401 is further configured to adjust the bandwidth of the target logical device according to a preset adjustment range.

[0168] Optionally, the management module 401 is further configured to subtract the preconfigured allocated bandwidth from the preconfigured upper limit bandwidth to obtain a maximum adjustment range, and adjust the bandwidth of the target logical device according to the maximum adjustment range.

[0169] Optionally, the management module 401 is further configured to determine the adjustment range of the target logical device according to the average load state of the target logical device, and adjust the bandwidth of the target logical device according to the adjustment range.

[0170] It should be noted that the above-mentioned computing module 402 is configured to perform the actions or steps performed by the computing unit in the CXL device in the above method embodiments. The above-mentioned management module 401 is configured to perform the actions or steps performed by the BMC in the above method embodiments. The implementation of each module can also correspond to the description of the corresponding method embodiments of the Figure 2 or Figure 3 above-mentioned method embodiments performed by the computing unit and the BMC in the CXL device.

[0171] Figure 5 is a structural schematic diagram of a switching device provided by an embodiment of the present application. The switching device can be applied to a CXL system as shown in Figure 1 , performs the functions of the CXL switch in the above method embodiments, and can implement the steps or processes performed by the BMC in the above method embodiments.

[0172] As shown in Figure 5 , the switching device includes a processor 501, a transceiver 502. Optionally, the switching device further includes a memory 503. The processor 501, the transceiver 502 and the memory 503 can communicate with each other through internal connection paths to transfer control and / or data signals. The memory 503 is configured to store a computer program, and the processor 501 is configured to call and run the computer program from the memory 503 to control the transceiver 502 to transceive signals. The above-mentioned processor 501 can correspond to the management module 401 in Figure 4 . The above-mentioned processor 501 and the memory 503 can be combined into one processing device, and the processor 501 is configured to execute the program code stored in the memory 503 to implement the above-mentioned functions. In specific implementation, the memory 503 can be integrated in the processor 501 or independent of the processor 501.

[0173] The transceiver 502 can also be referred to as a transceiving unit or a transceiving module. The transceiver 502 can include a receiver (or receiver circuit) and a transmitter (or transmitter circuit). The receiver is configured to receive signals, and the transmitter is configured to transmit signals. The transceiver 502 is configured to communicate with a host or a CXL device.

[0174] It should be understood that, Figure 5 The illustrated switching device can implement Figure 2 or Figure 3 The various processes in the illustrated method embodiments involve the CXL switch and the BMC. The operations and / or functions of the various modules in the switching device are implemented to implement the corresponding processes in the above-described method embodiments. For details, refer to the description in the above-described method embodiments, and the detailed description is appropriately omitted here to avoid repetition.

[0175] The processor 501 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, or other programmable logic device, transistor logic, hardware component, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in conjunction with the disclosure of the present application. The processor 501 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of digital signal processors and microprocessors, and the like. The communication bus 504 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5The bus 504 is used to realize the connection communication between the components. In the embodiment of the present application, the transceiver 502 is used to communicate signaling or data with other node devices. The memory 503 can include volatile memory, such as non-volatile random access memory (NVRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), etc., and can also include non-volatile memory, such as at least one disk storage device, electrically erasable programmable read-only memory (EEPROM), a flash memory device, such as NOR flash memory or NAND flash memory, a semiconductor device, such as a solid state disk (SSD), etc. The memory 503 can also be at least one storage device located away from the processor 501. The memory 503 can also optionally store a set of computer program codes or configuration information. The processor 501 can also optionally execute the program stored in the memory 503. The processor can cooperate with the memory and the transceiver to execute any of the methods and functions of the CXL system in the embodiments of the present application.

[0176] The embodiment of the present application also provides another switching device. The switching device can be applied in the CXL system as shown in Figure 1 The switching device can perform the functions of the BMC in the method embodiments and realize the steps or processes performed by the BMC in the method embodiments.

[0177] The switching device includes a processor and a transceiver. Optionally, the switching device also includes a memory. The processor, the transceiver and the memory can communicate with each other through internal connection paths to transmit control and / or data signals. The memory is used to store computer programs, and the processor is used to call and run the computer programs from the memory to control the transceiver to transceive signals. The processor can correspond to the management module 401 in the CXL switch, and the transceiver is used to communicate with the CXL switch. The processor and the memory can be integrated into one processing device, and the processor is used to execute the program codes stored in the memory to realize the above functions. In specific implementation, the memory can be integrated in the processor or independent of the processor. Figure 4

[0178] It should be understood that the switching device can realize the functions of the BMC in the method embodiments​Figure 2 or Figure 3 The various processes involving the BMC in the method embodiments are described above. The operations and / or functions of the various modules in the switching device are respectively implemented in order to implement the corresponding processes in the above method embodiments. For details, refer to the descriptions in the above method embodiments, and appropriate detailed descriptions are omitted here to avoid repetition.

[0179] The embodiments of the present application also provide a server, which includes a processor, a CXL switching module, and at least one CXL module and a board management controller (BMC), etc. The CXL module is integrated on the server and can include a cache and an accessible memory. The CXL switching module can be a chip integrated on the server with the CXL switch function in the CXL system in the above embodiment, and the CXL switching module is connected with the processor, the CXL module, and the BMC respectively. The processor can create a virtual device with storage and statistical functions, which is used to connect with different CXL modules respectively and complete different services. Figure 1 The embodiments of the present application also provide a server, which includes a processor, a CXL switching module, and at least one CXL module and a board management controller (BMC), etc. The CXL module is integrated on the server and can include a cache and an accessible memory. The CXL switching module can be a chip integrated on the server with the CXL switch function in the CXL system in the above embodiment, and the CXL switching module is connected with the processor, the CXL module, and the BMC respectively. The processor can create a virtual device with storage and statistical functions, which is used to connect with different CXL modules respectively and complete different services.

[0180] It should be noted that the BMC can also be arranged on the CXL switching module. Figure 1 The host in the CXL system in the above embodiment.

[0181] The embodiments of the present application also provide a chip system, which includes a processor, and is used for the CXL system to implement the functions involved in any of the above embodiments, such as determining the average load state involved in the above method. In a possible design, the chip system can also include a memory, and the memory is used for the necessary program instructions and data of the CXL system. The chip system can be composed of a chip, or can include a chip and other discrete devices. The input and output of the chip system correspond to the receiving and sending operations of the CXL system in the method embodiments respectively.

[0182] According to the method provided by the embodiments of the present application, the present application also provides a computer program product, which includes a computer program, and when the computer program runs on a computer, the computer program causes the computer to execute the method of any one of the embodiments shown in the above embodiments. Figure 2 or Figure 3 the method of any one of the embodiments shown in the above embodiments.

[0183] According to the method provided by the embodiments of the present application, the present application also provides a computer readable medium, which stores a computer program, and when the computer program runs on a computer, the computer program causes the computer to execute the method of any one of the embodiments shown in the above embodiments. Figure 2 or Figure 3 the method of any one of the embodiments shown in the above embodiments.

[0184] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as high-density digital video disc (digital video disc, DVD)), or semiconductor media (such as solid state disc (solid state disc, SSD)) and the like.

[0185] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A bandwidth adjustment method, characterized by, The method is applied to a computing express link (CXL) system, the CXL system comprising at least one CXL device and a baseboard management controller (BMC), the at least one CXL device comprising a first CXL device, the first CXL device comprising at least two logical devices, the method comprising: The BMC obtains an average load state of each of the logical devices in the first CXL device, comprising: obtaining a number of times of each load state of each of the logical devices in a first time period and a total number of times of the load states in the first time period, dividing a number of times of a first load state of a first logical device in the at least two logical devices by the total number of times of the first load state, determining a proportion value corresponding to the first load state, and if the proportion value corresponding to the first load state is greater than or equal to a first threshold value corresponding to the first load state, regarding the first load state as the average load state of the first logical device; The BMC determines a target logical device and an adjustment strategy in the first CXL device according to the average load state; The BMC adjusts a bandwidth of the target logical device according to the adjustment strategy.

2. The method of claim 1, wherein, The BMC obtains an average load state of each of the logical devices in the first CXL device, comprising: The first CXL device obtains the average load state of each of the logical devices in the first CXL device; The first CXL device sends the average load state to the BMC.

3. The method of claim 1 or 2, wherein, The average load state comprises an average light load, an average optimal load, an average moderate overload and an average severe overload, the first CXL device comprises a first logical device and a second logical device; the BMC determines a target logical device and an adjustment strategy in the first CXL device according to the average load state, comprising: When the average load state of the first logical device and the average load state of the second logical device are different, the BMC determines the target logical device as the first logical device and the second logical device.

4. The method of claim 3, wherein, The BMC determines a target logical device and an adjustment strategy in the first CXL device according to the average load state, comprising: When a severity of the average load state of the first logical device is higher than the average load state of the second logical device, the BMC adjusts a bandwidth of the first logical device upward, and the BMC adjusts a bandwidth of the second logical device downward; or, When a severity of the average load state of the first logical device is lower than the average load state of the second logical device, the BMC adjusts a bandwidth of the first logical device downward, and the BMC adjusts a bandwidth of the second logical device upward.

5. The method of claim 1 or 2, wherein, The BMC adjusts a bandwidth of the target logical device according to the adjustment strategy, comprising: The BMC adjusts the bandwidth of the target logical device according to a preset adjustment amplitude.

6. The method of claim 1 or 2, wherein, The BMC adjusts a bandwidth of the target logical device according to the adjustment strategy, comprising: The BMC calculates a maximum adjustment range by subtracting a pre-configured allocation bandwidth from a pre-configured upper bandwidth; The BMC adjusts the bandwidth of the target logical device according to the maximum adjustment range.

7. The method of claim 1 or 2, wherein, The adjusting of the bandwidth of the target logical device according to the adjustment strategy by the BMC comprises: The BMC determines an adjustment range of the target logical device according to the average load state of the target logical device; The BMC adjusts the bandwidth of the target logical device according to the adjustment range.

8. A compute express link (CXL) system, comprising: The CXL system comprises at least one CXL device and a BMC, the at least one CXL device comprises a first CXL device, the first CXL device comprises at least two logical devices, wherein: The BMC is configured to acquire an average load state of each logical device in the first CXL device, comprising: acquiring a number of times of each load state of each logical device in a first time period and a total number of times of all load states in the first time period, dividing a number of times of a first load state of a first logical device in the at least two logical devices by the total number of times of the first load state to determine a proportion value corresponding to the first load state, and taking the first load state as the average load state of the first logical device if the proportion value corresponding to the first load state is greater than or equal to a first threshold value corresponding to the first load state. According to the average load state, a target logical device in the first CXL device and an adjustment strategy are determined, and the bandwidth of the target logical device is adjusted according to the adjustment strategy.

9. The system of claim 8, wherein The first CXL device is configured to acquire the average load state of each logical device in the first CXL device and send the average load state to the BMC.

10. The system of claim 8 or 9, wherein, The average load state comprises an average light load, an average optimal load, an average moderate overload and an average severe overload, and the first CXL device comprises a first logical device and a second logical device. The BMC is further configured to determine the target logical device as the first logical device and the second logical device when the average load state of the first logical device and the average load state of the second logical device are different.

11. The system of claim 10, wherein The BMC is further configured to adjust the bandwidth of the first logical device upwards and the bandwidth of the second logical device downwards when the severity of the average load state of the first logical device is higher than the average load state of the second logical device; or The BMC is further configured to adjust the bandwidth of the first logical device downwards and the bandwidth of the second logical device upwards when the severity of the average load state of the first logical device is lower than the average load state of the second logical device.

12. The system of claim 8 or 9, wherein The BMC is further configured to adjust the bandwidth of the target logical device according to a preset adjustment range.

13. The system of claim 8 or 9, wherein, The BMC is further configured to calculate a maximum adjustment range by subtracting the preconfigured allocated bandwidth from a preconfigured upper limit bandwidth, and adjust the bandwidth of the target logical device according to the maximum adjustment range.

14. The system of claim 8 or 9, wherein, The BMC is further configured to determine an adjustment range of the target logical device according to the average load state of the target logical device, and adjust the bandwidth of the target logical device according to the adjustment range.

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