A high withstand voltage GaN HEMT device

Abstract

The present invention discloses a high withstand voltage GaN HEMT device, comprising a substrate layer, a buffer layer, a channel layer, a barrier layer, a SIPOS material layer, a first insulating dielectric layer, a second insulating dielectric layer, an insulating gate dielectric, a gate groove, a source, a drain and a gate, wherein the substrate layer, the buffer layer, the channel layer and the barrier layer are arranged in sequence from bottom to top; the source and the drain are respectively at the left and right ends of the barrier layer, the first insulating dielectric layer is on the left above the barrier layer, and the SIPOS material layer is on the right above the barrier layer; the second insulating dielectric layer is above the SIPOS material layer and forms a connection channel with the first insulating dielectric layer, the upper right part of the source extends to the right and is connected to the SIPOS material layer; the gate groove is provided on the barrier layer, and the gate is arranged in the gate groove through the insulating gate dielectric. The present invention aims to realize a high voltage HEMT device of more than 650V without sacrificing the specific on-resistance, and achieves the purpose of being applied to high voltage and high current scenarios.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a high-voltage GaN HEMT device. Background Art

[0002] Currently, high electron mobility transistors (HEMTs) made of AlGaN and GaN materials can form high-mobility free electrons (2DEG) at the heterojunction interface through polarization effects. Due to their high electron concentration, large electron mobility, and electron saturation velocity, they are suitable for high-frequency, high-power applications. However, since GaN high electron mobility transistors have 2DEG even at zero gate voltage, the device threshold voltage is negative, which makes the gate drive circuit design of HEMT devices complex and costly. At the same time, since HEMT devices do not have a PN junction structure inside, the electric field is concentrated at the gate edge, and the device's breakdown voltage strength depends on the gate-drain spacing, which greatly limits the breakdown voltage of HEMT devices. As a result, they are often used in scenarios below 650V and cannot be used in high-voltage scenarios above 650V.

[0003] To improve the performance of HEMT devices, patent publication CN114725214A discloses a multi-layer passivated recessed gate MIS-HEMT device and its fabrication method. The device comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The barrier layer is provided with a source and a drain on its left and right sides, respectively. A recessed gate region is provided in the center of the barrier layer, near the source, and a multi-layer passivation layer is provided on the recessed gate region. The multi-layer passivation layer comprises a first passivation layer, a transition layer, a mask layer, and a second passivation layer. The first passivation layer is selectively grown at the bottom of the recessed gate region of the barrier layer and contacts the upper surface of the channel layer. The transition layer is located on the upper surface of the first passivation layer. The mask layer is located on the barrier layer on both sides of the recessed gate region. The second passivation layer is located on the transition layer and extends upward to the upper surface of the mask layer. By combining a multi-layer passivation structure with selective growth technology, this patented technology enables efficient, precisely controlled deposition of the passivation layer in the gate region, improving dielectric interface defects and, to a certain extent, improving device performance. However, this patent only uses the gate-drain spacing to measure withstand voltage. When the device is in the withstand voltage state, an electric field peak will appear at the bottom of the gate near the drain, causing the device to break down prematurely. To increase the breakdown voltage of the device, the gate-drain spacing needs to be increased accordingly, but increasing the gate-drain spacing will sacrifice the specific on-resistance. Even if the patent compromises the breakdown voltage and specific on-resistance, it is still difficult to achieve a high-voltage, high-current device above 650V. Summary of the Invention

[0004] The present invention provides a high-voltage GaN HEMT device, which aims to achieve a high-voltage HEMT device of more than 650V without sacrificing specific on-resistance, thereby achieving the purpose of being applied in high-voltage and high-current scenarios.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A high withstand voltage GaN HEMT device, characterized by comprising: a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, a SIPOS material layer, a first insulating dielectric layer, a second insulating dielectric layer, an insulating gate dielectric, a gate trench, a source electrode, a drain electrode, and a gate electrode; wherein:

[0007] The substrate layer, GaN buffer layer, unintentionally doped GaN channel layer and AlGaN barrier layer are arranged in sequence from bottom to top;

[0008] The source electrode is arranged at the left end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer, and the drain electrode is arranged at the right end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer;

[0009] The first insulating dielectric layer is arranged on the left side above the AlGaN barrier layer, and the SIPOS material layer is arranged on the right side above the AlGaN barrier layer and connected to the drain;

[0010] The second insulating dielectric layer is disposed above the SIPOS material layer, and a connection channel is formed between the second insulating dielectric layer and the first insulating dielectric layer. The upper right portion of the source electrode extends rightward from above the first insulating dielectric layer and is connected to the SIPOS material layer through the connection channel.

[0011] The gate trench is opened on the AlGaN barrier layer and is located below the first insulating dielectric layer. The gate is arranged in the gate trench through the insulating gate dielectric.

[0012] A passivation layer is provided above the AlGaN barrier layer, and the first insulating dielectric layer and the SIPOS material layer are respectively located on the left and right sides of the passivation layer.

[0013] The gate trench is etched from the passivation layer downward to the AlGaN barrier layer.

[0014] The gate is located above the insulating gate dielectric, and the upper left end of the insulating gate dielectric extends horizontally to the left to the source.

[0015] A High-k material layer is provided above the AlGaN barrier layer. Both ends of the High-k material layer are connected to the source and drain respectively. The first insulating dielectric layer and the SIPOS material layer are respectively located on the left and right sides of the High-k material layer.

[0016] The gate trench is etched downward from the High-k material layer to the AlGaN barrier layer.

[0017] The gate is completely wrapped in the insulating gate dielectric.

[0018] The upper surfaces of the first insulating dielectric layer and the second insulating dielectric layer are located on the same horizontal plane.

[0019] The advantages of adopting the present invention are:

[0020] 1. The GaN HEMT device described in the present invention utilizes a recessed gate MIS structure and incorporates a semi-insulating polysilicon (SIPOS) material layer and / or a high-k material layer. The introduction of the semi-insulating polysilicon (SIPOS) material layer optimizes the gate-to-drain electric field and lateral electric field distribution of the HEMT device, and improves the device's breakdown characteristics. The introduction of the high-k material layer optimizes the gate-to-drain electric field and lateral electric field distribution of the HEMT device, and improves the device's breakdown characteristics, mitigates the current collapse effect, and mitigates dynamic resistance degradation.

[0021] In summary, the present invention innovatively combines the recessed gate MIS structure with the SIPOS and / or High-k structure, significantly improving the forward conduction and reverse withstand voltage characteristics of the HEMT device. It can also significantly increase the breakdown voltage (specifically, it can be increased to 650V-1400V) without sacrificing the specific on-resistance, resulting in superior product performance and reliability. This not only achieves the goal of application in high-voltage and high-current scenarios, but also fills the gap in high-voltage GaN HEMT devices while also reducing costs to a certain extent.

[0022] 2. The present invention facilitates protecting the HEMT device interface and buffering through the passivation layer.

[0023] 3. The present invention extends rightward from the top of the first insulating dielectric layer through the upper right portion of the source electrode, and then links the source electrode to the SIPOS layer, realizing the SIPOS field plate connection between the source electrode and the drain electrode. When the device is in a withstand voltage state, the drain electrode is at a high potential, and the source electrode is at a low potential. The potential difference between the drain and the source electrode on the SIPOS layer is evenly distributed, so that the device surface electric field is optimized and the breakdown characteristics are improved. In addition, the breakdown voltage of the terminal region is less affected by the junction depth, and it is not necessary to increase the gate-drain spacing to improve the breakdown voltage, thus saving chip area. At the same time, the upper right portion of the source electrode of the present invention extends rightward from the top of the first insulating dielectric layer, straddling the gate and being connected to SIPOS, without affecting the reliability of the device gate.

[0024] 4. The gate leakage of the present invention is small, does not affect the reliability of the gate oxide layer, improves the breakdown voltage, and saves chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic structural diagram of Example 1;

[0026] Figure 2 This is a schematic structural diagram of Example 2;

[0027] Figure 3 This is a diagram showing the forward conduction characteristic simulation test results of Example 1;

[0028] Figure 4 This is a breakdown voltage test result diagram of Example 1;

[0029] Figure 5 This is a diagram showing the forward conduction characteristic simulation test results of Example 2;

[0030] Figure 6 This is a diagram showing the breakdown voltage test results of Example 2.

[0031] The markings in the figure are: 1-1, substrate layer, 1-2, GaN buffer layer, 1-3, unintentionally doped GaN channel layer, 1-4, AlGaN barrier layer, 1-5, source, 1-6, insulating gate dielectric, 1-7, gate, 1-8.1, first insulating dielectric layer, 1-8.2, second insulating dielectric layer, 1-9, SIPOS material layer, 1-10, passivation layer, 1-11, drain, 1-12, High-k material layer. DETAILED DESCRIPTION

[0032] It should be noted that the product described in this invention is one of the products currently under development by the applicant. Since this product involves different specifications and models, on the one hand, due to the different product structures, a single patent cannot fully summarize the various structures. On the other hand, in order to better protect the products, the applicant has combined the various structures into two and filed patent applications simultaneously. This will be explained below with reference to specific embodiments.

[0033] Example 1

[0034] This embodiment provides a high voltage GaN HEMT device, such as Figure 1 As shown, it includes a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, a SIPOS material layer, a first insulating dielectric layer, a second insulating dielectric layer, an insulating gate dielectric, a gate trench, a source, a drain and a gate; wherein,

[0035] The substrate layer, the GaN buffer layer, the unintentionally doped GaN channel layer and the AlGaN barrier layer are arranged in sequence from bottom to top.

[0036] The source electrode is arranged at the left end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer, and the drain electrode is arranged at the right end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer.

[0037] The first insulating dielectric layer is disposed on the left side above the AlGaN barrier layer, and the SIPOS material layer is disposed on the right side above the AlGaN barrier layer. The left side of the first insulating dielectric layer is connected to the source electrode, the right side of the SIPOS material layer is connected to the drain electrode, and the right side of the first insulating dielectric layer is connected to the left side of the SIPOS material layer.

[0038] The second insulating dielectric layer is disposed above the SIPOS material layer, and the second insulating dielectric layer and the upper surface of the second insulating dielectric layer are preferably located at the same horizontal plane. In addition, the right side of the second insulating dielectric layer is connected to the drain electrode, and a connection channel is formed between the left side of the second insulating dielectric layer and the first insulating dielectric layer.

[0039] The upper right portion of the source electrode extends rightward from above the first insulating dielectric layer and covers the first insulating dielectric layer. When extending to the connection channel, the source electrode bends downward and is connected to the SIPOS material layer through the connection channel.

[0040] The gate trench is opened on the AlGaN barrier layer near the source and located below the first insulating dielectric layer, specifically between the first insulating dielectric layer and the AlGaN barrier layer. The gate is arranged in the gate trench through the insulating gate dielectric.

[0041] Preferably, to protect the HEMT device interface and provide a buffer, a passivation layer is provided above the AlGaN barrier layer in this embodiment. Accordingly, the first insulating dielectric layer and the SIPOS material layer are located on the left and right sides of the passivation layer, respectively, and the gate trench is etched from the passivation layer down to the AlGaN barrier layer.

[0042] Preferably, the insulating gate dielectric in this embodiment is disposed within the gate trench and covers the bottom and sidewalls of the gate trench, and the gate is located above the insulating gate dielectric. Furthermore, the left upper end of the insulating gate dielectric extends horizontally to the left and extends from between the passivation layer and the first insulating dielectric layer to the source electrode.

[0043] Preferably, the substrate layer in this embodiment is a Si substrate or a sapphire substrate.

[0044] The working principle of this embodiment is as follows:

[0045] This embodiment forms 2DEG conduction through the polarization effect, forming an electron channel from the source to the drain on the surface of the unintentionally doped GaN channel layer. The SIPOS material layer between the drain and the source forms a resistive field plate, which improves the surface electric field and optimizes the electric field distribution of the GaN region at the bottom of the gate and the bottom of the drain, thereby improving the breakdown characteristics and reliability of the HEMT device. This structure uses the gate trench to reduce the thickness of the AlGaN barrier layer under the gate, depleting the 2DEG concentration under the gate, achieving a positive threshold voltage, and reducing reverse conduction losses. The remaining portion is still relatively thick to ensure a high concentration of 2DEG concentration, thereby obtaining a larger saturation current. In addition, the MIS trench gate structure can also adjust the threshold voltage by controlling the depth of the gate trench. When the potential difference between the gate and the source is less than the threshold voltage of the device, the 2DEG under the gate is depleted, the current path is turned off, and the HEMT device is in a blocking state. At the blocking voltage of the drain, the two sides of the SIPOS material layer are connected to the source electrode and the metal drain to realize a resistive field plate and introduce a uniform lateral distributed electric field. The introduction of the SIPOS field plate effectively reduces the electric field strength in the drain region and increases the breakdown voltage of the HEMT device. Below the SIPOS material layer is a passivation layer deposited by LPCVD, which plays a protective interface and buffering role; the first insulating dielectric layer above the SIPOS material layer plays a role in protecting the SIPOS film.

[0046] The applicant conducted simulation tests on this embodiment. Figure 3 、 4 The forward conduction curve and voltage breakdown characteristic curve of the product were simulated respectively. Figure 3 、 4 It can be seen that its specific on-resistance is 0.75mΩ·cm 2 , and its breakdown voltage can reach 1480 V. By comparison, it can be seen that this embodiment can push the device's withstand voltage level to 1200 V, greatly enhancing and improving the device's breakdown characteristics.

[0047] Example 2

[0048] This embodiment provides a high voltage GaN HEMT device, such as Figure 2 As shown, it includes a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, a SIPOS material layer, a first insulating dielectric layer, a second insulating dielectric layer, an insulating gate dielectric, a gate trench, a source, a drain and a gate; wherein,

[0049] The substrate layer, the GaN buffer layer, the unintentionally doped GaN channel layer and the AlGaN barrier layer are arranged in sequence from bottom to top.

[0050] The source electrode is arranged at the left end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer, and the drain electrode is arranged at the right end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer.

[0051] The first insulating dielectric layer is disposed on the left side above the AlGaN barrier layer, and the SIPOS material layer is disposed on the right side above the AlGaN barrier layer. The left side of the first insulating dielectric layer is connected to the source electrode, the right side of the SIPOS material layer is connected to the drain electrode, and the right side of the first insulating dielectric layer is connected to the left side of the SIPOS material layer.

[0052] The second insulating dielectric layer is disposed above the SIPOS material layer, and the second insulating dielectric layer and the upper surface of the second insulating dielectric layer are preferably located at the same horizontal plane. In addition, the right side of the second insulating dielectric layer is connected to the drain electrode, and a connection channel is formed between the left side of the second insulating dielectric layer and the first insulating dielectric layer.

[0053] The upper right portion of the source electrode extends rightward from above the first insulating dielectric layer and covers the first insulating dielectric layer. When extending to the connection channel, the source electrode bends downward and is connected to the SIPOS material layer through the connection channel.

[0054] The gate trench is opened on the AlGaN barrier layer near the source and located below the first insulating dielectric layer, specifically between the first insulating dielectric layer and the AlGaN barrier layer. The gate is arranged in the gate trench through the insulating gate dielectric.

[0055] Preferably, to improve the current collapse effect of the HEMT device and optimize the dynamic resistance degradation phenomenon, this embodiment provides a high-k material layer above the AlGaN barrier layer. Accordingly, the two ends of the high-k material layer are connected to the source and drain, respectively. The first insulating dielectric layer and the SIPOS material layer are located on the left and right sides of the high-k material layer, respectively. The gate trench is etched from the high-k material layer down to the AlGaN barrier layer.

[0056] Preferably, the gate in this embodiment is completely wrapped in the insulating gate dielectric.

[0057] Preferably, the substrate layer in this embodiment is a Si substrate or a sapphire substrate.

[0058] The working principle of this embodiment is as follows:

[0059] This embodiment forms 2DEG conduction through the polarization effect, forming an electron channel from the source to the drain on the surface of the unintentionally doped GaN channel layer. During blocking, as the drain-source bias increases, the electric field 2DEG at the gate end is depleted, and the electric field lines emitted by the remaining fixed polarized positive charges will be concentrated toward the gate end, resulting in an increase in the curvature of the electric field lines there. The High-k material layer between the drain and source is located above the AlGaN barrier layer, attracting surface electrons, depleting the 2DEG in the unintentionally doped GaN channel layer, optimizing the electric field below the gate, optimizing the breakdown characteristics of the device, and improving the reliability of the device. In addition, the SIPOS material layer is a resistive field plate that connects the drain electrode to the source electrode, uniformizing the drain-source electric field and alleviating the electric field below the drain. This structure reduces the thickness of the AlGaN barrier layer below the gate through the gate trench, depleting the 2DEG concentration below the gate, achieving a positive threshold voltage, and reducing reverse conduction losses, while the remaining relatively thick structure ensures a high concentration of 2DEG, thereby obtaining a larger saturation current. In addition, the MIS trench gate structure can also adjust the threshold voltage by controlling the depth of the gate trench. When the potential difference between the gate and the source is less than the threshold voltage of the HEMT device, the 2DEG below the gate is depleted, the current path is shut off, and the HEMT device is in a blocking state. It should be noted that traditional HEMT devices do not have a PN junction structure and cannot withstand high avalanche resistance. After the peak reaches the critical breakdown electric field, the device breaks down prematurely. After the electric field 2DEG at the gate end is depleted, the electric field lines emitted by the remaining fixed polarization positive charge will be concentrated towards the gate end and the drain end. The introduction of the High-k material layer and the SIPOS material layer in this solution optimizes the surface electric field, attracts the electric field lines emitted by the fixed polarization positive charge, and alleviates the curvature effect at the gate edge, thus achieving better results.

[0060] The applicant conducted simulation tests on this embodiment. Figure 5 、 6 The forward conduction curve and voltage breakdown characteristic curve of the product were simulated respectively. Figure 5 、 6 It can be seen that its specific on-resistance is 0.73mΩ·cm 2 , and its breakdown voltage can reach 1600 V. By comparison, it can be seen that this embodiment can push the device's withstand voltage level to 1600 V, greatly enhancing and improving the device's breakdown characteristics.

[0061] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A high withstand voltage GaN HEMT device, characterized in that: It includes a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, a SIPOS material layer, a first insulating dielectric layer, a second insulating dielectric layer, an insulating gate dielectric, a gate trench, a source electrode, a drain electrode and a gate electrode; wherein, The substrate layer, the GaN buffer layer, the unintentionally doped GaN channel layer and the AlGaN barrier layer are arranged in sequence from bottom to top; The source electrode is arranged at the left end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer, and the drain electrode is arranged at the right end of the AlGaN barrier layer and forms an ohmic contact with the AlGaN barrier layer; The first insulating dielectric layer is arranged on the left side above the AlGaN barrier layer, and the SIPOS material layer is arranged on the right side above the AlGaN barrier layer and connected to the drain; The second insulating dielectric layer is arranged above the SIPOS material layer, and a connection channel is formed between the second insulating dielectric layer and the first insulating dielectric layer, and the upper right portion of the source electrode extends rightward from the top of the first insulating dielectric layer and is connected to the SIPOS material layer through the connection channel; The gate groove is opened on the AlGaN barrier layer and is located below the first insulating dielectric layer, and the gate is arranged in the gate groove through the insulating gate dielectric; A High-k material layer is disposed above the AlGaN barrier layer, two ends of the High-k material layer are connected to the source and the drain respectively, and the first insulating dielectric layer and the SIPOS material layer are respectively located on the left and right sides above the High-k material layer.

2. The high withstand voltage GaN HEMT device according to claim 1, characterized in that: A passivation layer is disposed above the AlGaN barrier layer, and the first insulating dielectric layer and the SIPOS material layer are respectively located on the left and right sides of the passivation layer.

3. The high withstand voltage GaN HEMT device according to claim 2, characterized in that: The gate trench is etched from the passivation layer downward to the AlGaN barrier layer.

4. The high withstand voltage GaN HEMT device according to claim 2, characterized in that: The gate is located above the insulating gate dielectric, and the upper left end of the insulating gate dielectric horizontally extends leftward to the source.

5. The high withstand voltage GaN HEMT device according to claim 1, characterized in that: The gate trench is etched downward from the High-k material layer to the AlGaN barrier layer.

6. The high withstand voltage GaN HEMT device according to claim 1, characterized in that: The gate is completely wrapped in an insulating gate dielectric.

7. The high withstand voltage GaN HEMT device according to claim 1, characterized in that: The upper surfaces of the first insulating dielectric layer and the second insulating dielectric layer are located on the same horizontal plane.

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