A high-voltage pulse capacitor and its production method

Abstract

The present invention provides a high-voltage pulse capacitor and a production method thereof, comprising a plurality of ceramic chip groups, a frame, a spacer, a first potting layer, and a plurality of printed resistors. The ceramic chip groups include a plurality of ceramic chips connected in parallel, and the printed resistors are connected in parallel with each ceramic chip. The first welding plate group of the frame includes two first welding plates and a plurality of second welding plates spaced between the two first welding plates. The second welding plate group of the frame includes a plurality of second welding plates spaced apart. The first welding plates are welded to one ceramic chip group, and the second welding plates are welded to two ceramic chip groups. The first potting layer is located between two adjacent ceramic chips. The series connection of multiple ceramic chip groups enables the pulse capacitor to be used in higher voltage applications. The chip resistors lower the resistance of each ceramic chip group, and also provide more uniform voltage division for each ceramic chip group.

Description

Technical Field

[0001] The invention relates to a high-voltage pulse capacitor and a production method thereof. Background Art

[0002] The withstand voltage of existing ceramic pulse capacitor chips is generally several thousand to ten thousand volts. Affected by the existing pulse capacitor materials and processes, the capacitor chips have a withstand voltage limit. If the withstand voltage limit is designed to be higher, it will have a negative impact on the reliability of the capacitor chip. Therefore, this limits the high-voltage applications in which existing pulse capacitors can be used. Summary of the Invention

[0003] The purpose of the present invention is to provide a high-voltage pulse capacitor and a production method thereof. Multiple groups of ceramic chip groups are connected in series, so that the pulse capacitor can be used in higher voltage situations. The chip resistors make the resistance of each ceramic chip group lower and also make the voltage division of each ceramic chip group more uniform, thereby extending the service life of the pulse capacitor.

[0004] The present invention is achieved through the following technical solutions:

[0005] A high-voltage pulse capacitor includes several ceramic chip groups, a frame, an isolator, a first potting layer, and several printed resistors corresponding to each ceramic chip group. The ceramic chip group includes several ceramic chips arranged vertically at intervals and in parallel. The printed resistors are connected in parallel with each ceramic chip to lower the total resistance of the ceramic chip group and make the total resistance of each ceramic chip group equivalent. The frame includes a first welding plate group and a second welding plate group arranged relatively vertically. The first welding plate group includes two first welding plates and several second welding plates arranged at intervals between the two first welding plates. The second welding plate group includes several second welding plates arranged at intervals. The first welding plate is welded to one ceramic chip group, and the second welding plate is welded to two ceramic chip groups to achieve series connection of the ceramic chip groups. The isolator is located between two adjacent ceramic chip groups and extends to the adjacent first welding plate and second welding plate or between two adjacent second welding plates. The first potting layer is located between two adjacent ceramic chips. In this way, the series connection between the ceramic chip groups is achieved. When used in higher voltage situations, the ceramic chip groups can be divided, thereby reducing the voltage borne by each ceramic chip, ensuring the reliability of the ceramic chip and the pulse capacitor. After the chip resistors are connected in parallel with the ceramic chips, they can lower the resistance of each ceramic chip group, reduce fluctuations, and make the voltage division of each ceramic chip group more uniform, thereby extending the service life of the pulse capacitor.

[0006] Furthermore, the printed resistor is a strip-shaped sheet flatly placed on a ceramic chip in a ceramic chip set. The ends of the strip are connected to the ends of the ceramic chip, and the strip is bent multiple times to achieve a sufficiently high resistance value. Due to the limited length of the ceramic chip, the strip is bent multiple times to obtain a resistor that meets the required resistance value. The number of bends is determined based on the specific application scenario.

[0007] Furthermore, the ratio of the printed resistor resistance to the ceramic chipset resistance is in the range of 1 / 40-1 / 20.

[0008] Furthermore, the thickness of the printed resistor is not greater than 0.15 mm.

[0009] Furthermore, it also includes a second potting layer and an outer shell, wherein the second potting layer is located outside the frame, and the outer shell is located outside the second potting layer.

[0010] Furthermore, the two first welding pieces each have a lead end.

[0011] The present invention is also achieved through the following technical solutions:

[0012] A method for producing a high-voltage pulse capacitor based on any of the above-described high-voltage pulse capacitors is produced using a welding jig, the welding jig including a download plate and an upload plate, the download plate being provided with a plurality of chip limiting plate groups corresponding to each ceramic chip group, a plurality of lower chip baffles, the chip limiting plate group including a plurality of chip limiting plates arranged at intervals, and the upload plate being provided with a plurality of upper chip baffles, the production method comprising the following steps:

[0013] Step S1: Mount the second soldering sheet assembly on the download board and apply solder paste on the upper side of the soldering sheet assembly. The first and second soldering sheets are both provided with clearance holes for the chip limiting plate to pass upward. The lower chip baffle of the download board passes upward through the gap between two adjacent second soldering sheets.

[0014] Step S2: placing each ceramic chip group in each chip limiting plate group so that two adjacent ceramic chips are located on both sides of a chip limiting plate, and connecting the chip resistor in parallel with the ceramic chip of the corresponding ceramic chip group;

[0015] Step S3: Apply solder paste to the lower side of the first welding sheet group and place it on the mounting plate, which is located above each ceramic chip group;

[0016] Step S4, placing the upper carrier plate on the upper end of the first welding plate group and performing reflow soldering, wherein the upper chip baffle of the upper carrier plate passes downward through the gap between the first welding plate and the adjacent second welding plate, and between the two adjacent second welding plates;

[0017] Step S5: After welding is completed, a spacer is provided between two adjacent ceramic chip groups, and the gap between the ceramic chips is encapsulated to obtain a first encapsulation layer, wherein the spacer extends between the two adjacent welding sheets to isolate the two adjacent welding sheets;

[0018] Step S6: assemble the shell and perform overall potting to obtain a second potting layer.

[0019] Furthermore, the welding fixture also includes two fasteners, which are arranged on the download board at intervals along the extension direction of each ceramic chip group. Each ceramic chip group and the corresponding printed resistor are located between the two fasteners, and the fasteners are made of high-temperature rubber material.

[0020] Furthermore, in step S5, when the gaps between the ceramic chips are encapsulated, tape is pasted on the clearance holes of the first welding plate and the second welding plate of the first welding plate group, and the encapsulation material enters the gaps between the two adjacent ceramic chips from the clearance holes of the second welding plate of the second welding plate group, or tape is pasted on the clearance holes of the second welding plate of the second welding plate group, and the encapsulation material enters the gaps between the two adjacent ceramic chips from the clearance holes of the first welding plate and the second welding plate of the first welding plate group. After the encapsulation is completed, the tape is removed.

[0021] Furthermore, the download board is also provided with two support plates at intervals, the first welding sheet is vertically bent to form a lead-out surface that is spaced apart from the outer side surface of the ceramic chip group located at the edge, and the lower end of the lead-out surface is horizontally bent outward to form the lead-out end. When the first welding sheet group is placed on the download board, the support plate is located in the gap between the outer side surface of the ceramic chip group at the edge and the lead-out surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be described in further detail below with reference to the accompanying drawings.

[0023] Figure 1 It is a structural schematic diagram of the present invention.

[0024] Figure 2 It is a schematic cross-sectional structural diagram of the present invention.

[0025] Figure 3 This is a schematic structural diagram of the present invention without the outer shell, the first potting layer and the second potting layer.

[0026] Figure 4 This is another structural schematic diagram of the present invention without the outer shell, the first potting layer and the second potting layer.

[0027] Figure 5 This is a schematic diagram of the structure of the present invention after removing the outer shell, the first potting layer, the second potting layer and the second welding sheet.

[0028] Figure 6This is a schematic diagram of the structure of the printed resistor and ceramic chip set of the present invention.

[0029] Figure 7 It is a structural schematic diagram of the framework of the present invention.

[0030] Figure 8 Schematic diagram of another structure of the framework of the present invention.

[0031] Figure 9 Schematic diagram of the exploded structure of the welding jig of the present invention.

[0032] Figure 10 This is a schematic structural diagram of the download plate of the welding jig of the present invention.

[0033] Figure 11 Schematic diagram of the structure of the upper loading plate of the welding jig of the present invention.

[0034] Figure 12 This is a schematic structural diagram of the second welding sheet assembly of the present invention after being installed on the download board.

[0035] Figure 13 It is a structural schematic diagram of the ceramic chipset of the present invention after being installed on a download board.

[0036] Figure 14 This is a schematic structural diagram of the first welding sheet assembly of the present invention after being installed on the download board.

[0037] Figure 15 This is a schematic diagram of the structure of the welding jig of the present invention after assembly.

[0038] Among them, 11. Ceramic chip; 2. Frame; 21. First welding plate; 22. Second welding plate; 23. Clearance hole; 24. Lead-out surface; 25. Lead-out end; 26. First vent hole; 27. Second vent hole; 3. Isolator; 4. First potting layer; 5. Second potting layer; 6. Printed resistor; 7. Housing; 81. Upper loading board; 811. Upper chip baffle; 82. Download board; 821. Lower chip baffle; 822. Chip limiting plate; 823. Support plate; 824. Limiting part; 83. Fastener; 831. Bolt; 84. Exhaust hole. DETAILED DESCRIPTION

[0039] like Figures 1 to 11As shown, the high-voltage pulse capacitor includes four ceramic chip groups, a frame 2, a spacer 3, a first potting layer 4, four printed resistors 6 corresponding to each ceramic chip group, a second potting layer 5, and a housing 7. The second potting layer 5 is located outside the frame 2, and the housing 7 is located outside the second potting layer 5. The housing 7 is made of plastic material to protect the product. The frame 2 includes a first welding plate group and a second welding plate group arranged relatively vertically. The first welding plate group includes two first welding plates 21 and a second welding plate 22 arranged at intervals between the two first welding plates 21. The second welding plate group includes two second welding plates 22 arranged at intervals. The first welding plate 21 is welded to one end of each ceramic chip 11 of a group of ceramic chip groups, and a part of the second welding plate 22 corresponding to the first welding plate 21 is welded to the other end of each ceramic chip 11 of the ceramic chip group, and the other part of the second welding plate 22 is welded to one end of each ceramic chip 11 of another group of ceramic chip groups. In this way, the parallel connection of each ceramic chip 11 in each ceramic chip group is realized, and the series connection of each ceramic chip group is also realized. In this embodiment, the ceramic chip group includes ten ceramic chips 11 arranged vertically at intervals and in parallel. Thus, if the high-voltage pulse capacitor is a 20,000V product, by separating it into four ceramic chip groups, each ceramic chip 11 can use a 5,000V product to meet the electrical performance requirements. If it is used in higher voltage applications or uses lower voltage ceramic chips 11, the number of second welding plates 22 can be increased to increase the number of ceramic chip groups connected in series. Accordingly, the number of second welding plates 22 can also be reduced where necessary. For example, in another embodiment, the first welding plate group may include only two first welding plates 21 spaced apart, and the second welding plate group may include only one second welding plate 22. The two ends of one ceramic chip group are respectively welded between one first welding plate 21 and the second welding plate 22, and the two ends of the other ceramic chip group are respectively welded between the other first welding plate 21 and the second welding plate 22, thereby achieving the series connection of the two ceramic chip groups.

[0040] More specifically, each of the first and second welding tabs 21 and 22 is provided with a plurality of clearance holes 23 spaced apart, the positions of which correspond to the gaps between two vertically adjacent ceramic chips 11. A plurality of second air holes 27 are provided laterally between adjacent clearance holes 23 on each of the first and second welding tabs 21 and 22, and a plurality of first air holes 26 are provided vertically spaced apart in the middle of the second welding tab 22. The two first welding tabs 21 are located on either side of the high-voltage pulse capacitor. The outer sides of the first welding tabs 21 are vertically bent to form lead surfaces 24 that face the outer sides of the ceramic chipset at the edge. The lower ends of the lead surfaces 24 are horizontally bent outward to form lead terminals 25, which extend beyond the second potting layer 5 and the outer shell 7 to enable soldering of the high-voltage pulse capacitor to a circuit board. The lower ends of the lead terminals 24 are lower than the lower ends of the first and second welding tabs 21 and 22.

[0041] The printed resistor 6 is a strip-shaped piece laid flat on the bottommost ceramic chip 11 of the corresponding ceramic chip group. The two ends of the strip are connected to the two ends of the ceramic chip 11, and the strip is bent multiple times to ensure a sufficiently high resistance value for the printed resistor 6. In this embodiment, the strip's bending paths are horizontal and vertical. This not only ensures that the length of the printed resistor 6 is sufficiently long, thereby ensuring a sufficiently high resistance value, but also reduces the impact of the printed resistor 6's shape on the entire circuit. The printed resistor 6 can serve as a bleeder resistor. When connected in parallel with each ceramic chip 11, it can lower the total resistance of the ceramic chip group and make the total resistance of each ceramic chip group equal, achieving an average voltage division. Because the resistance of the ceramic chip 11 in a DC power supply ranges from several thousand to over ten thousand megohms, with large fluctuations, a parallel resistor of approximately 300 megohms is required to ensure an average voltage division for each parallel ceramic chip 11. According to the resistor parallel formula 1 / R = 1 / R1 + 1 / R2 + ... 1 / Rn, the parallel resistance can be approximately over 300 megohms, thus achieving a relatively uniform voltage division. Generally, the ratio of the resistance of the printed resistor 6 to the resistance of the ceramic chipset is in the range of 1 / 40 to 1 / 20. In order to ensure the simplicity of the frame 2 and the entire product, the parallel resistor is a printed resistor 6 with a thickness of no more than 0.15 mm.

[0042] Isolators 3 are positioned between two adjacent ceramic chip groups to isolate them. They also extend between adjacent first and second welding pads 21, 22, or between two adjacent second welding pads 22, to isolate them from each other, or to prevent short circuits or high-voltage breakdown of the potting compound. Isolators 3 are also positioned outside the edge of the ceramic chip groups. A first potting layer 4 is positioned between two adjacent ceramic chips 11. The first and second potting compounds ensure the internal insulation strength and provide stress buffering for the entire product.

[0043] To facilitate welding between the ceramic chipset and the frame 2, specifically to secure the position of the chipset and frame 2 for more precise welding, a corresponding welding jig is designed. The jig comprises an upper loading plate 81, a lower loading plate 82, and two fasteners 83. The upper loading plate 81 is provided with two upper chip retaining plates 811. The lower loading plate 82 is spaced apart and comprises four chip retaining plates 822 corresponding to each ceramic chipset, a plurality of lower chip retaining plates 821, and two spaced support plates 823. The chip retaining plate 822 comprises a plurality of spaced apart chip retaining plates 822, each provided with stress holes. The two fasteners 83 are spaced apart on the lower loading plate 82 along the extension direction of each ceramic chipset. In this embodiment, the fasteners 83 are strip-shaped and made of high-temperature rubber material. They are removably secured between the two support plates 823 via bolts 831. Both the upper loading plate 81 and the lower loading plate 82 are provided with vent holes 84. The width of the upper loading plate 81 is greater than the distance between the two support plates 823 of the lower loading plate 82.

[0044] The production method of high-voltage pulse capacitors based on the welding jig includes the following steps:

[0045] Step S1: Figure 12 As shown, first, two fasteners 83 are fixed to the download plate 82 by bolts 831, and then the second welding plate group is installed on the download plate 82 and solder paste is applied on the upper side of the welding plate group. The first welding plate 21 and the second welding plate 22 are both provided with a clearance hole 23 for the chip limiting plate 822 to pass upward. The lower chip baffle 821 of the download plate 82 passes upward through the gap between the two adjacent second welding plates 22;

[0046] Step S2: Figure 13 As shown, each ceramic chip group is placed in each chip limiting plate 822 group, so that two adjacent ceramic chips 11 are located on both sides of a chip limiting plate 822 and the chip limiting plate 822 is clamped, and the chip resistor is connected in parallel with the ceramic chip 11 at the bottom of the corresponding ceramic chip group. The ceramic chip 11 at the upper end is located between a fastener 83 and the chip limiting plate 822 at the upper end, and the ceramic chip 11 and the chip resistor at the lower end are located between another fastener 83 and the chip limiting plate 822 at the lower end. That is, during the assembly process, the fastener 83 plays a limiting role. During the welding process, the fastener 83 softens and expands due to heat, which can provide compressive stress for the welding of the ceramic chip 11, that is, clamping each ceramic chip group to ensure welding quality;

[0047] Step S3, as Figure 14 As shown, the lower side of the first welding sheet group is coated with solder paste and then placed on the download plate 82, which is located at the upper end of each ceramic chip group. At this time, the support plate 823 is located in the gap between the outer side of the edge of the ceramic chip group and the lead surface 24, and the upper end of the first welding sheet 21 is against the limit portion 824;

[0048] Step S4: Figure 15 As shown, the upper carrier plate 81 is placed on the upper end of the first welding sheet group and then subjected to reflow soldering, wherein the upper chip baffle 811 of the upper carrier plate 81 passes downward through the gap between the first welding sheet 21 and the adjacent second welding sheet 22, and between the two adjacent second welding sheets 22;

[0049] Step S5: After welding is completed, a spacer 3 is provided between two adjacent ceramic chip groups, and the gap between the ceramic chips 11 is encapsulated to obtain a first encapsulation layer 4. The spacer 3 extends between the two adjacent welding sheets to isolate the two adjacent welding sheets.

[0050] Specifically, when potting the gaps between the ceramic chips 11, adhesive tape is applied to the clearance holes 23 of the first welding sheet 21 and the second welding sheet 22 of the first welding sheet group, and the potting material enters the gaps between the two adjacent ceramic chips 11 from the clearance holes 23 of the second welding sheet 22 of the second welding sheet group. Alternatively, adhesive tape is applied to the clearance holes 23 of the second welding sheet 22 of the second welding sheet group, and the potting material enters the gaps between the two adjacent ceramic chips 11 from the clearance holes 23 of the first welding sheet 21 and the second welding sheet 22 of the first welding sheet group. After potting is completed, the tape is removed.

[0051] Step S6: Assemble the housing 7 and perform overall potting to obtain the second potting layer 5. Potting the first potting layer 4 first and then potting the entire housing can achieve a better potting effect.

[0052] The above description is merely a preferred embodiment of the present invention and therefore cannot be used to limit the scope of the present invention. In other words, equivalent changes and modifications made according to the scope of the patent application and the contents of the specification should still fall within the scope of the patent of the present invention.

Claims

1. A high-voltage pulse capacitor, characterized in that: It includes several ceramic chip groups, a frame, an isolating member, a first potting layer and several printed resistors corresponding to each ceramic chip group. The ceramic chip group includes several ceramic chips arranged vertically at intervals and in parallel. The printed resistors are connected in parallel with each ceramic chip to lower the total resistance of the ceramic chip group and make the total resistance of each ceramic chip group equivalent. The frame includes a first welding plate group and a second welding plate group arranged relatively vertically. The first welding plate group includes two first welding plates and several second welding plates arranged at intervals between the two first welding plates. The second welding plate group includes several second welding plates arranged at intervals. The first welding plate is welded to one group of ceramic chip groups, and the second welding plate is welded to two groups of ceramic chip groups to realize the series connection of each ceramic chip group. The isolating member is located between two adjacent ceramic chip groups and extends to the adjacent first welding plate and the second welding plate or between two adjacent second welding plates. The first potting layer is located between two adjacent ceramic chips.

2. The high-voltage pulse capacitor according to claim 1, characterized in that: The printed resistor is a strip-shaped piece flatly arranged on a ceramic chip of a ceramic chip group, two ends of the strip-shaped piece are respectively connected to two ends of the ceramic chip, and the strip-shaped piece is bent multiple times.

3. The high-voltage pulse capacitor according to claim 2, characterized in that: The ratio of the printed resistor value to the ceramic chip group resistance value is in the range of 1 / 40-1 / 20.

4. A high-voltage pulse capacitor according to claim 1, 2 or 3, characterized in that: The thickness of the printed resistor is no more than 0.15 mm.

5. A high-voltage pulse capacitor according to claim 1, 2 or 3, characterized in that: It also includes a second potting layer and an outer shell, wherein the second potting layer is located outside the frame, and the outer shell is located outside the second potting layer.

6. A high-voltage pulse capacitor according to claim 1, 2 or 3, characterized in that: The two first welding pieces both have lead ends.

7. A method for producing a high-voltage pulse capacitor according to any one of claims 1 to 6, characterized in that: Production is carried out using a welding jig, which includes a download plate and an upload plate. The download plate is provided with a plurality of chip limiting plate groups corresponding to each ceramic chip group and a plurality of lower chip baffles. The chip limiting plate group includes a plurality of chip limiting plates arranged at intervals. The upload plate is provided with a plurality of upper chip baffles. The production method includes the following steps: Step S1: Mount the second soldering pad assembly on the download board and apply solder paste on the upper side of the soldering pad assembly. The first and second soldering pads are both provided with clearance holes for the chip limiting plate to pass upward. The lower chip baffle of the download board passes upward through the gap between two adjacent second soldering pads. Both first soldering pads have lead ends. Step S2: placing each ceramic chip group in each chip limiting plate group so that two adjacent ceramic chips are located on both sides of a chip limiting plate, and connecting the chip resistor in parallel with the ceramic chip of the corresponding ceramic chip group; Step S3: Apply solder paste to the lower side of the first welding sheet group and place it on the mounting plate, which is located above each ceramic chip group; Step S4, placing the upper carrier plate on the upper end of the first welding plate group and performing reflow soldering, wherein the upper chip baffle of the upper carrier plate passes downward through the gap between the first welding plate and the adjacent second welding plate, and between the two adjacent second welding plates; Step S5: After welding is completed, a spacer is provided between two adjacent ceramic chip groups, and the gap between the ceramic chips is encapsulated to obtain a first encapsulation layer, wherein the spacer extends between the two adjacent welding sheets to isolate the two adjacent welding sheets; Step S6: assemble the shell and perform overall potting to obtain a second potting layer.

8. The method for producing a high-voltage pulse capacitor according to claim 7, wherein: The welding fixture further includes two fasteners, which are spaced apart on the download board along the extension direction of each ceramic chip group. Each ceramic chip group and the corresponding printed resistor are located between the two fasteners, and the fasteners are made of high-temperature rubber material.

9. The method for producing a high-voltage pulse capacitor according to claim 7, wherein: In step S5, when the gaps between the ceramic chips are encapsulated, tape is affixed to the clearance holes of the first welding sheet and the second welding sheet of the first welding sheet group, and the encapsulation material enters the gaps between the two adjacent ceramic chips from the clearance holes of the second welding sheet of the second welding sheet group, or tape is affixed to the clearance holes of the second welding sheet of the second welding sheet group, and the encapsulation material enters the gaps between the two adjacent ceramic chips from the clearance holes of the first welding sheet and the second welding sheet of the first welding sheet group. After the encapsulation is completed, the tape is removed.

10. The method for producing a high-voltage pulse capacitor according to claim 7, 8 or 9, characterized in that: The download board is also provided with two support plates at intervals. The first welding sheet is vertically bent to form a lead-out surface that is spaced apart from the outer side surface of the ceramic chip group located at the edge. The lower end of the lead-out surface is horizontally bent outward to form the lead-out end. When the first welding sheet group is placed on the download board, the support plate is located in the gap between the outer side surface of the ceramic chip group at the edge and the lead-out surface.

Images