Array substrate and liquid crystal panel

Abstract

Embodiments of the present application disclose an array substrate and a liquid crystal panel. The array substrate has a first opening in the opening area with a first barrier layer, and the first barrier layer is at least correspondingly disposed in the thin film transistor setting area and the gate driving circuit area. The first barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the substrate towards the active layer, the depth of the alkaline cations entering the first barrier layer is less than or equal to 20 angstroms. Since the first barrier layer avoids the opening area, the light transmittance of the opening area is improved; and the first barrier layer is disposed in the thin film transistor setting area and the gate driving circuit area to block alkaline cations from entering the active layer, thereby improving the stability of the thin film transistors in the thin film transistor setting area and the gate driving circuit area.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate and a liquid crystal panel. Background Art

[0002] Liquid crystal display panels are mainly divided into a pixel display area (Active Area, AA), a gate driver circuit (Gate Driver On Array, GOA) area, a demultiplexing circuit (DEMUX) area, etc. according to functions. The AA area is the display screen area for mobile phones, TVs, etc., and this area has sensitive requirements for light transmittance; the GOA area is the gate signal control area for thin film transistors in the AA area, and the requirements for the stability of thin film transistors in this area are particularly prominent; the DEMUX area is the signal control area for the source and drain electrodes of thin film transistors in the AA area, and this area has higher requirements for the rapid turn-on of thin film transistors.

[0003] The current product line is usually a whole-surface structure, that is, the film layer structures of thin film transistors prepared on a glass substrate are basically the same. At the same scale, this makes the characteristics of all thin film transistors almost the same, and thus it is impossible to meet the unique requirements for each area. Summary of the Invention

[0004] Embodiments of the present application provide an array substrate and a liquid crystal panel, which can improve the light transmittance of the pixel display area while improving the stability of thin film transistors in the gate driver circuit area and the pixel display area.

[0005] Embodiments of the present application provide an array substrate, including a pixel display area and a gate driver circuit area. The gate driver circuit area is located on at least one side of the pixel display area. The pixel display area includes an opening area and a thin film transistor setting area. The opening area is located on one side of the thin film transistor setting area. The opening area is used to transmit the light of the backlight module. The array substrate includes:

[0006] A substrate;

[0007] A first barrier layer, the first barrier layer is disposed on the substrate, the first barrier layer has a first opening in the opening area, and the first barrier layer is at least correspondingly disposed in the thin film transistor setting area and the gate driver circuit area;

[0008] A buffer layer, the buffer layer is disposed on a side of the first barrier layer away from the substrate, and the buffer layer covers the opening area, the thin film transistor setting area, and the gate driver circuit area;

[0009] The thin film transistor structure layer is disposed on a side of the buffer layer away from the substrate. The thin film transistor structure layer includes a first thin film transistor and a second thin film transistor. The first thin film transistor is located in the thin film transistor setting area, and the second thin film transistor is disposed in the gate driving circuit area;

[0010] The first barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the active layer from the substrate, the depth of the alkaline cations entering the first barrier layer is less than or equal to 20 angstroms.

[0011] Optionally, in some embodiments of the present application, the thin film transistor structure layer includes an active layer, a gate insulating layer, and a first metal layer. The active layer is disposed on a side of the buffer layer away from the substrate. The gate insulating layer is disposed on a side of the active layer away from the buffer layer. The first metal layer includes a gate, and the first metal layer is disposed on a side of the gate insulating layer away from the active layer. The first metal layer is disposed at least in the thin film transistor setting area and the gate driving circuit area;

[0012] The array substrate further includes a second barrier layer disposed between the first metal layer and the gate insulating layer. The second barrier layer has a second opening in the opening area and the thin film transistor setting area, and the second barrier layer is correspondingly disposed in the gate driving circuit area;

[0013] The second barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the active layer from the first metal layer, the depth of the alkaline cations entering the second barrier layer is less than or equal to 20 angstroms.

[0014] Optionally, in some embodiments of the present application, the array substrate further includes a demultiplexing circuit area located at at least one end of the pixel display area;

[0015] The first barrier layer, the buffer layer, the active layer, the gate insulating layer, and the first metal layer are also correspondingly disposed in the demultiplexing circuit area. The thin film transistor structure layer further includes a third thin film transistor located in the demultiplexing circuit area;

[0016] The thickness of the gate insulating layer disposed in the demultiplexing circuit area is less than the thickness of the gate insulating layer disposed in the gate driving circuit area.

[0017] Optionally, in some embodiments of the present application, the thickness of the gate insulating layer disposed in the pixel display area is less than the thickness of the gate insulating layer disposed in the gate driving circuit area.

[0018] Optionally, in some embodiments of the present application, the thickness of the gate insulating layer disposed in the pixel display area is greater than the thickness of the gate insulating layer disposed in the demultiplexing circuit area.

[0019] Optionally, in some embodiments of the present application, the second barrier layer has a third opening in the demultiplexing circuit area.

[0020] Optionally, in some embodiments of the present application, the dielectric constant of the gate insulating layer is greater than or equal to 6.8.

[0021] Optionally, in some embodiments of the present application, the light transmittance of both the gate insulating layer and the buffer layer is greater than or equal to 90%.

[0022] Optionally, in some embodiments of the present application, the gate insulating layer is a single-layer structure or a multi-layer stacked structure, and the buffer layer is a single-layer structure or a multi-layer stacked structure.

[0023] Optionally, in some embodiments of the present application, the array substrate further includes a light-shielding layer. The light-shielding layer and the first barrier layer are disposed on the same side of the substrate. The light-shielding layer has a fourth opening in the opening area. The light-shielding layer is at least correspondingly disposed in the thin-film transistor setting area, and the light-shielding layer overlaps with the active layer at least located in the thin-film transistor setting area.

[0024] Optionally, in some embodiments of the present application, the light-shielding layer is disposed between the buffer layer and the first barrier layer, or the light-shielding layer is disposed between the substrate and the first barrier layer.

[0025] Optionally, in some embodiments of the present application, the material of the gate insulating layer includes at least one of silicon oxide, silicon oxynitride, hafnium oxide, and aluminum oxide, and the material of the buffer layer includes at least one of silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, polyvinyl alcohol, polyethylene glycol, and polydimethylsiloxane.

[0026] Optionally, in some embodiments of the present application, the thin-film transistor structure layer further includes:

[0027] A source-drain insulating layer disposed on a surface of the first metal layer away from the buffer layer and covering the gate insulating layer; and

[0028] A second metal layer disposed on a surface of the source-drain insulating layer away from the gate insulating layer. The second metal layer is at least disposed in the thin-film transistor setting area and the gate driving circuit area. The second metal layer includes a source electrode and a drain electrode. In a thin-film transistor, the source electrode is connected to the source contact area of the active layer, and the drain electrode is connected to the drain contact area of the active layer.

[0029] Among them, the gate, the active layer, the source electrode, and the drain electrode located in the thin film transistor setting area are used to form the first thin film transistor, the gate, the active layer, the source electrode, and the drain electrode located in the gate driving circuit area are used to form the second thin film transistor, and the gate, the active layer, the source electrode, and the drain electrode located in the demultiplexing circuit area are used to form the third thin film transistor.

[0030] An embodiment of the present application further provides a liquid crystal panel, which includes the array substrate described in any of the above embodiments.

[0031] The array substrate and the liquid crystal panel according to the embodiment of the present application adopt a first barrier layer having a first opening in the opening area, and are at least correspondingly disposed in the thin film transistor setting area and the gate driving circuit area. The first barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the substrate towards the active layer, the depth of the alkaline cations entering the first barrier layer is less than or equal to 20 angstroms.

[0032] Since the first barrier layer avoids the opening area through the first opening, the light transmittance of the opening area is improved; and the first barrier layer is disposed in the thin film transistor setting area and the gate driving circuit area to block alkaline cations from entering the active layer, thereby improving the stability of the thin film transistors in the thin film transistor setting area and the gate driving circuit area. In addition, after the preparation of the array substrate is completed, the depth of the alkaline cations diffusing into the first barrier layer is less than or equal to 20 angstroms, which can ensure that the alkaline cations will not diffuse into the active layer, and will not diffuse into the active layer even for a long time in the future, achieving the improvement of the stability of the thin film transistors while improving the duration of the stability of the thin film transistors and appropriately reducing the thickness of the first barrier layer. Description of the Drawings

[0033] Figure 1 is a schematic structural diagram of the array substrate provided by the embodiment of the present application;

[0034] Figure 2 is another schematic structural diagram of the array substrate provided by the embodiment of the present application;

[0035] Figure 3 is yet another schematic structural diagram of the array substrate provided by the embodiment of the present application;

[0036] Figure 4 is a schematic diagram of step B1 of the preparation method of the array substrate provided by the embodiment of the present application;

[0037] Figure 5 is a schematic diagram of step B2 of the preparation method of the array substrate provided by the embodiment of the present application;

[0038] Figure 6It is a schematic diagram of step B3 of the method for preparing an array substrate provided by an embodiment of the present application;

[0039] Figure 7 It is a schematic diagram of step B4 of the method for preparing an array substrate provided by an embodiment of the present application;

[0040] Figure 8 It is a schematic diagram of step B5 of the method for preparing an array substrate provided by an embodiment of the present application;

[0041] Figure 9 It is a schematic diagram of step B6 of the method for preparing an array substrate provided by an embodiment of the present application;

[0042] Figure 10 It is a schematic diagram of step B7 of the method for preparing an array substrate provided by an embodiment of the present application;

[0043] Figure 11 It is a schematic diagram of step B8 of the method for preparing an array substrate provided by an embodiment of the present application;

[0044] Figure 12 It is another schematic diagram of the structure of the array substrate provided by an embodiment of the present application;

[0045] Figure 13 It is a schematic diagram of the structure of the liquid crystal panel provided by an embodiment of the present application;

[0046] Figure 14 It is the present application Figure 2 The perspective-chromaticity relative intensity curve comparison diagram of the corresponding embodiment and the conventional technology of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are only used as labels and do not impose numerical requirements or establish an order.

[0048] Embodiments of the present application provide an array substrate and a liquid crystal panel, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0049] Please refer to Figure 1 , embodiments of the present application provide an array substrate 100, including a pixel display area AA and a gate driving circuit area GOA. The gate driving circuit area GOA is located on at least one side of the pixel display area AA. The pixel display area AA includes an opening area A1 and a thin film transistor setting area A2, and the opening area A1 is located on one side of the thin film transistor setting area A2. The opening area A1 is used to transmit the light of the backlight module. The array substrate 100 includes a substrate 11, a first barrier layer 12, a buffer layer 13, and a thin film transistor structure layer, and the thin film transistor structure layer includes a first thin film transistor T1 and a second thin film transistor T2. The first thin film transistor T1 is located in the thin film transistor setting area A2, and the second thin film transistor T2 is arranged in the gate driving circuit area GOA.

[0050] The film layer of the thin film transistor structure layer includes an active layer 14, a gate insulating layer 15, a first metal layer 16, a source-drain insulating layer 17, and a second metal layer 18.

[0051] The first barrier layer 12 is disposed on the substrate 11. The first barrier layer 12 has a first opening k1 in the opening area A1, and the first barrier layer 12 is at least correspondingly disposed in the thin film transistor setting area A2 and the gate driving circuit area. The buffer layer 13 is disposed on the side of the first barrier layer 12 away from the substrate 11. The buffer layer 13 covers the opening area A1, the thin film transistor setting area A2, and the gate driving circuit area GOA.

[0052] The active layer 14 is disposed on the surface of the buffer layer 13 away from the substrate 11. The gate insulating layer 15 is disposed on the surface of the active layer 14 away from the buffer layer 13.

[0053] The first metal layer 16 includes a gate 161. The first metal layer 16 is disposed on the surface of the gate insulating layer 15 away from the active layer 14. The first metal layer 16 avoids the opening area A1 and is at least disposed in the thin film transistor setting area A2 and the gate driving circuit area GOA. The source-drain insulating layer 17 is disposed on the surface of the first metal layer 16 away from the buffer layer 13 and covers the gate insulating layer 15.

[0054] The second metal layer 18 is disposed on the surface of the source-drain insulating layer 17 away from the gate insulating layer 15. The second metal layer 18 avoids the opening area A1 and is at least disposed in the thin film transistor setting area A2 and the gate driving circuit area GOA. The second metal layer 18 includes a source 181 and a drain 182. In a thin film transistor, the source 181 is connected to the source contact area of the active layer 14, and the drain 182 is connected to the drain contact area of the active layer 14.

[0055] Among them, the gate 161, the active layer 14, the source 181, and the drain 182 located in the thin film transistor setting area A2 are used to form the first thin film transistor T1. The gate 161, the active layer 14, the source 181, and the drain 182 located in the gate driving circuit area GOA are used to form the second thin film transistor T2.

[0056] The first barrier layer 12 is used to block the diffusion of alkaline cations in the direction of the active layer 14. In the direction perpendicular to the substrate 11 towards the active layer 14, the depth of the alkaline cations entering the first barrier layer 12 is less than or equal to 20 angstroms. In the array substrate 100 of this embodiment, the first opening k1 is provided in the opening area A1, that is, the first barrier layer 12 avoids the opening area A1. Since the first barrier layer 12 avoids the opening area A1, the light of the backlight module irradiated to the opening area A1 does not need to penetrate the first barrier layer 12, reducing light loss and improving the light transmission performance of the opening area A1; while the first barrier layer 12 is provided in the thin film transistor setting area A2 and the gate driving circuit area GOA to block alkaline cations from entering the active layer 14, improving the stability of the thin film transistors (T1 / T2) in the thin film transistor setting area A2 and the gate driving circuit area GAO. In addition, after the preparation of the array substrate 100 is completed, the depth of the alkaline cations diffusing into the first barrier layer 12 is less than or equal to 20 angstroms, which can ensure that the alkaline cations will not diffuse into the active layer 14, and will not diffuse into the active layer 14 even for a long time in the future, achieving the improvement of the stability of the thin film transistors (T1 / T2) while increasing the duration of the stability of the thin film transistors (T1 / T2) and appropriately reducing the thickness of the first barrier layer 12.

[0057] It should be noted that the opening area A1 only corresponds to the area of the pixel electrode in the array substrate 100. In the liquid crystal panel, a black matrix is used to be correspondingly arranged on the periphery of the opening area A1, that is, the area in the pixel display area AA that is not blocked by the black matrix layer is the opening area A1.

[0058] Optionally, in the embodiments of the present application, the thin film transistor in the thin film transistor structure layer is a top-gate thin film transistor. However, in some embodiments, the thin film transistor in the thin film transistor structure layer can also be a bottom-gate or double-gate type. In some embodiments, on the basis of Figure 1 the embodiment, the source, drain, and gate arranged in the same layer are formed by using the same photomask to save the second metal layer 18 and the source-drain insulating layer 17.

[0059] Optionally, the alkaline cations include Na + and K + etc.

[0060] In the direction perpendicular to the active layer 14 from the substrate 11, the depth of the alkaline cations entering the first barrier layer 12 is less than or equal to 20 angstroms, such as 20 angstroms, 19 angstroms, 18 angstroms, 17 angstroms, 16 angstroms, 15 angstroms, 14 angstroms, 13 angstroms, 12 angstroms, 11 angstroms, 10 angstroms, 9 angstroms, 8 angstroms, 7 angstroms, 6 angstroms or 5 angstroms, and so on.

[0061] It can be understood that the shallower the depth of the alkaline cations diffusing into the first barrier layer 12, the stronger the blocking performance of the first barrier layer 12 against the alkaline cations, and the stronger the stability of the second thin film transistor T2.

[0062] Optionally, the material of the first barrier layer 12 may include at least one of silicon nitride, hafnium oxide, aluminum oxide and zirconium oxide.

[0063] In this embodiment, the material of the first barrier layer 12 is silicon nitride. After the silicon nitride film is formed, the film layer has high density, strong blocking performance, can thin the second barrier layer 19, and the cost of silicon nitride is low, which is convenient for mass production.

[0064] Optionally, the thickness of the first barrier layer 12 is between 200 angstroms and 2000 angstroms, such as 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms or 2000 angstroms.

[0065] It can be understood that since ions have a certain diffusion ability at room temperature, the thicker the first barrier layer 12, the greater the difficulty for ions to diffuse through the first barrier layer 12, the better the effect of the first barrier layer 12 in blocking alkaline cations, and the longer the time for blocking alkaline cations, but at the same time, the process cost will be increased.

[0066] Optionally, the light transmittance of the gate insulating layer 15 and the buffer layer 13 is greater than or equal to 90%, such as 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98% or 99%.

[0067] In this embodiment, the light transmittance of the gate insulating layer 15 and the buffer layer 13 is selected to be greater than or equal to 90% to ensure high light transmittance in the opening area A1.

[0068] The material of the buffer layer 13 may include at least one of silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, polyvinyl alcohol, polyethylene glycol and polydimethylsiloxane.

[0069] In this embodiment, the material of the buffer layer 13 is silicon oxide. The transmittance of the silicon oxide film layer is greater than 92%, which can ensure the light transmittance. The silicon oxide film layer can improve the interface of the active layer 14, enhance the stability of the active layer 14, and the cost of silicon oxide is relatively low, which is convenient for mass production.

[0070] Optionally, the thickness of the buffer layer 13 ranges from 1000 angstroms to 3000 angstroms, for example, it can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms, 2000 angstroms, 2100 angstroms, 2200 angstroms, 2300 angstroms, 2400 angstroms, 2500 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms or 3000 angstroms.

[0071] Optionally, the light transmittance of the gate insulating layer 15 is greater than 90%.

[0072] The material of the gate insulating layer 15 includes at least one of silicon oxide, silicon oxynitride, hafnium oxide, and aluminum oxide. Optionally, the gate insulating layer 15 has a single-layer structure or a multi-layer stacked structure, and the buffer layer 13 has a single-layer structure or a multi-layer stacked structure.

[0073] In this embodiment, when the gate insulating layer 15 has a single-layer structure, the material of the gate insulating layer 15 is silicon oxide. The transmittance of the silicon oxide film layer is greater than 92%, which can ensure the light transmittance. The cost of silicon oxide is relatively low, which is convenient for mass production. In addition, the dielectric constant of silicon oxide is relatively low, which can improve the startup speed of the third thin film transistor T3.

[0074] In some embodiments, the gate insulating layer 15 can also be an insulating layer with a dielectric constant greater than or equal to 6.8 to ensure that the gate insulating layer has strong insulating performance.

[0075] Optionally, the first metal layer 16 and the second metal layer 18 can be formed using metal elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, alloys composed of any of the above metal elements, or alloys combining any of the above metal elements, etc. In addition, the first metal layer 16 and the second metal layer 18 can have a single-layer structure or a stacked structure of two or more layers.

[0076] Optionally, the material of the active layer 14 can include single-crystalline silicon, polycrystalline silicon (poly-Si), or an oxide semiconductor.

[0077] Optionally, the material of the source-drain insulating layer 17 can include at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and an organic transparent material. The organic transparent materials include transparent photoresist, epoxy resin, polyimide, polyvinyl alcohol, polymethyl methacrylate, polystyrene, etc.

[0078] In some embodiments, the material of the source-drain insulating layer 17 does not include silicon nitride. Since the light transmittance of silicon nitride is between 80% and 85%, the material of the source-drain insulating layer 17 is not silicon nitride, which can improve the light transmittance of the opening region A1. For example, the material of the source-drain insulating layer 17 can be silicon oxynitride, which has good light transmittance, ion blocking performance, and a relatively large dielectric constant. The light transmittance, ion blocking performance, and dielectric constant can all be properly adapted by adjusting the content of nitrogen and oxygen, which can meet the requirements of various functions and the cost is controllable.

[0079] Optionally, in one embodiment, the array substrate 100 further includes a second barrier layer 19 disposed between the first metal layer 16 and the gate insulating layer 15. The second barrier layer 19 has a second opening k2 in the opening region A1 and the thin-film transistor setting region A2, and the second barrier layer 19 is correspondingly disposed in the gate driving circuit region GOA.

[0080] The second barrier layer 19 is used to block the diffusion of alkaline cations in the direction of the active layer 14. In the direction perpendicular to the first metal layer 16 towards the active layer 14, the depth of the alkaline cations entering the second barrier layer 19 is less than or equal to 20 angstroms.

[0081] It can be understood that the shallower the depth of the alkaline cations diffusing into the second barrier layer 19, the stronger the blocking performance of the second barrier layer 19 on the alkaline cations, and the stronger the stability of the second thin-film transistor T2.

[0082] In addition, the second barrier layer 19 has a second opening k2 in the opening region A1, that is, the second barrier layer 19 avoids the opening region A1 through the second opening k2, which improves the light transmittance of the opening region A1.

[0083] Optionally, the material of the second barrier layer 19 may include at least one of silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide.

[0084] In this embodiment, the material of the second barrier layer 19 is silicon nitride. After the silicon nitride film is formed, the film layer has high density, strong blocking performance, the second barrier layer 19 can be thinned, and the cost of silicon nitride is relatively low, which is convenient for mass production.

[0085] Optionally, the thickness of the second barrier layer 19 is between 200 angstroms and 2000 angstroms, for example, it can be 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms, or 2000 angstroms.

[0086] It can be understood that since ions have a certain diffusion ability at room temperature, the thicker the second barrier layer 19 is, the more difficult it is for ions to diffuse through the second barrier layer 19, and thus the better the second barrier layer 19 blocks alkaline cations, and the longer the time it can block alkaline cations. However, this will increase the process cost at the same time.

[0087] In addition, since the second barrier layer 19 is added between the gate 161 and the active layer 14 of the first thin-film transistor T1, the gate breakdown resistance of the first thin-film transistor T1 is improved, and the stability of the first thin-film transistor T1 is enhanced.

[0088] It should be explained that breakdown resistance means that when a voltage is applied to the gate insulating layer, the gate insulating layer exhibits insulating characteristics and no large current passes through the gate insulating layer.

[0089] Among them, after the array substrate 100 is fabricated, the first barrier layer 12 and the second barrier layer 19 can be tested by SIMS (Secondary Ion Mass Spectrometry) to obtain the diffusion situation of alkaline cations in the first barrier layer 12 and the second barrier layer 19.

[0090] Optionally, in one embodiment, the corners of the second barrier layer 10 are connected by rounded corners.

[0091] Optionally, in one embodiment, the array substrate 100 further includes a demultiplexing circuit region DE, and the demultiplexing circuit region DE is located at at least one end of the pixel display region AA.

[0092] The first barrier layer 12, the buffer layer 13, the active layer 14, the gate insulating layer 15, the first metal layer 16, the source-drain insulating layer 17, and the second metal layer 18 are also correspondingly disposed in the demultiplexing circuit region DE. The gate 161, the active layer 14, the source 181, and the drain 182 located in the demultiplexing circuit region DE are used to form a third thin-film transistor T3.

[0093] The thickness d1 of the gate insulating layer 15 disposed in the demultiplexing circuit region DE is less than the thickness d2 of the gate insulating layer 15 disposed in the gate driving circuit region GOA.

[0094] Among them, the first barrier layer 12 is correspondingly disposed in the demultiplexing circuit region DE, which can block the diffusion of alkaline cations to the active layer 14 and improve the stability of the third thin-film transistor.

[0095] In addition, the thickness d1 of the gate insulating layer 15 disposed in the demultiplexing circuit region DE is less than the thickness d2 of the gate insulating layer 15 disposed in the gate driving circuit region GOA, so that the distance between the gate 161 of the third thin-film transistor T3 and the channel of the active layer 14 is shorter, and the threshold voltage Vth required for the third thin-film transistor T3 becomes smaller, thereby improving the turn-on speed of the third thin-film transistor T3 to meet the requirements of the demultiplexing circuit.

[0096] Optionally, the thickness of the gate insulating layer 15 provided in the pixel display area AA is equal to the thickness d2 of the gate insulating layer 15 provided in the gate driving circuit area GOA, which improves the stability of the first thin film transistor T1 and the second thin film transistor T2 and reduces the process difficulty.

[0097] Optionally, in one embodiment, the thickness of the gate insulating layer 15 provided in the pixel display area AA is greater than the thickness d1 of the gate insulating layer 15 provided in the demultiplexing circuit area DE.

[0098] That is to say, in the present application, by thinning the thickness d1 of the gate insulating layer 15 provided in the demultiplexing circuit area DE, the required stability requirements of the first thin film transistor T1 and the second thin film transistor T2 and the requirement for the rapid startup of the third thin film transistor T3 can be achieved, and the process steps are simplified.

[0099] Optionally, in some embodiments, the thickness of the gate insulating layer 15 provided in the pixel display area AA is less than the thickness of the gate insulating layer 15 provided in the gate driving circuit area GOA, which can further improve the stability of the second thin film transistor T2.

[0100] Optionally, in one embodiment, the second barrier layer 19 has a third opening k3 in the demultiplexing circuit area DE, that is, the second barrier layer 19 avoids the demultiplexing circuit area DE, shortening the distance between the gate 161 and the active layer 14, which can further improve the startup speed of the third thin film transistor T3.

[0101] Optionally, in one embodiment, the array substrate 100 further includes a light shielding layer zg1, and the light shielding layer zg1 and the first barrier layer 12 are provided on the same side of the substrate 11. The light shielding layer zg1 has a fourth opening k4 in the opening area A1, the light shielding layer zg1 is at least correspondingly provided in the thin film transistor setting area A2, and the light shielding layer zg1 overlaps with the active layer 14 at least located in the thin film transistor setting area A2.

[0102] Optionally, in one embodiment, the light shielding layer zg1 is provided between the buffer layer 13 and the first barrier layer 12.

[0103] Wherein, the light shielding layer zg1 sets a fourth opening k4 in the opening area A1 to avoid the opening area A1, so as to improve the light transmittance of the opening area A1. Secondly, the light shielding layer zg1 shields the active layer 14 of the first thin film transistor T1, which can avoid the influence of light on the first thin film transistor T1.

[0104] Optionally, please refer to Figure 2 , in one embodiment, the light shielding layer zg1 also overlaps with the active layer 14 located in the gate driving circuit area GOA. That is, the light shielding layer zg1 also shields the active layer 14 of the second thin film transistor T2, which can avoid the influence of light on the second thin film transistor T2.

[0105] Please refer to Figure 14 , it should be noted that for the panel corresponding to the array substrate of the conventional technology, a stack of a silicon nitride film layer and a silicon oxide film layer is used as the buffer layer, and the silicon nitride film layer and the silicon oxide film layer are provided over the entire surface; the material of the gate insulating layer is silicon oxide, and it is laid evenly over the entire surface. Figure 2 In the corresponding embodiment, the buffer layer is a silicon oxide film layer, the first barrier layer and the second barrier layer are silicon nitride, and the gate insulating layer is silicon oxide.

[0106] Under the same test conditions and environmental conditions, Figure 14 the viewing angle-color shift curve graph is obtained. According to Figure 14 it can be seen that the optical stability of the overall horizontal viewing angle in the panel corresponding to the embodiment of the present application Figure 2 is better than that of the conventional technology.

[0107] In addition, the light transmittance of the panel of the conventional technology is 95.31%, while Figure 2 the light transmittance of the corresponding panel is about 99.9%, almost approaching 100%.

[0108] Therefore, when the corresponding embodiment of the present Figure 2 is used for the panel, it has excellent optical stability and light transmittance.

[0109] Optionally, please refer to Figure 3 , in one embodiment, the light-shielding layer zg1 also overlaps with the active layer 14 located in the demultiplexing circuit region DE. That is, the light-shielding layer zg1 also shields the active layer 14 of the third thin-film transistor T3, and the influence of light on the third thin-film transistor T3 can be avoided.

[0110] The array substrate 100 of this embodiment is Figure 3 illustrated by taking the embodiment of

[0111] Step B1, please refer to Figure 4 , deposit a first barrier material layer p1 and a light-shielding material layer p2 on the substrate 11 in sequence.

[0112] Step B2, please refer to Figure 5 , pattern the light-shielding material layer p2 and retain the first barrier material layer p1 to form the light-shielding layer zg1. The light-shielding layer zd1 avoids the opening area A1 and is correspondingly arranged in the thin-film transistor setting area A2, the gate driving circuit area GOA, and the demultiplexing circuit area DE.

[0113] Step B3, please refer to Figure 6, the first barrier material layer p1 is patterned to form the first barrier layer 12. The first barrier layer 12 avoids the opening area A1 and is correspondingly disposed in the thin film transistor setting area A2, the gate driving circuit area GOA, and the demultiplexing circuit area DE.

[0114] Subsequently, a buffer layer 13 and an active layer 14 are sequentially formed on the light shielding layer zg1. The buffer layer 13 is disposed over the entire surface. The active layer 14 is correspondingly disposed in the thin film transistor setting area A2, the gate driving circuit area GOA, and the demultiplexing circuit area DE. A part of the active layer 14 may also be correspondingly disposed in the opening area A1.

[0115] Step B4, please refer to Figure 7 , a gate insulating layer 15 and a second barrier material layer p3 are sequentially formed on the active layer 14.

[0116] Step B5, please refer to Figure 8 , a part of the second barrier material layer p3 corresponding to the demultiplexing circuit area DE is removed.

[0117] Step B6, please refer to Figure 9 , a part of the second barrier material layer p3 corresponding to the pixel display area AA is removed to form the second barrier layer 19, and a part of the gate insulating layer 15 corresponding to the demultiplexing circuit area DE is thinned.

[0118] Step B7, please refer to Figure 10 , a patterned first metal layer 16 is formed on the gate insulating layer 15. The first metal layer 16 includes a gate 161.

[0119] Step B8, please refer to Figure 11 , a source-drain insulating layer 17 and a second metal layer 18 are sequentially formed on the first metal layer 16. The second metal layer 18 includes a source 181 and a drain 182.

[0120] Optionally, the array substrate 100 further includes a pixel electrode (not shown in the figure). The pixel electrode is correspondingly disposed in the opening area A1. The pixel electrode is connected to the first thin film transistor T1.

[0121] Optionally, please refer to Figure 12 , in some embodiments, the light shielding layer zg1 is disposed between the substrate 11 and the first barrier layer 12.

[0122] Please refer to Figure 13 , an embodiment of the present application further provides a liquid crystal panel 1000, which includes the array substrate 100, the counter substrate 200, and the liquid crystal 300 disposed between the array substrate 100 and the counter substrate 200 as described in any of the above embodiments.

[0123] Among them, the structure of the array substrate of the liquid crystal surface 1000 in the embodiment of the present application is similar to or the same as the structure of the array substrate 100 in any of the above embodiments, so it will not be described in detail here.

[0124] Optionally, the counter substrate 200 has a black matrix layer, and the black matrix layer is correspondingly arranged around the opening area A1.

[0125] Optionally, in some embodiments, the black matrix layer can also be integrated into the array substrate 100.

[0126] Optionally, in some embodiments, the black matrix layer can also be replaced by stacked color resist blocks of different colors.

[0127] The liquid crystal panel in the embodiment of the present application uses a first barrier layer to avoid the opening area, and is at least correspondingly arranged in the thin film transistor setting area and the gate driving circuit area. The first barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction from the substrate perpendicular to the active layer, the depth of the alkaline cations entering the first barrier layer is less than or equal to 20 angstroms.

[0128] Since the first barrier layer avoids the opening area, the light transmittance of the opening area is improved; and the first barrier layer is arranged in the thin film transistor setting area and the gate driving circuit area to block alkaline cations from entering the active layer, improving the stability of the thin film transistors in the thin film transistor setting area and the gate driving circuit area. In addition, after the preparation of the array substrate is completed, the depth of the alkaline cations diffusing into the first barrier layer is less than or equal to 20 angstroms, which can ensure that the alkaline cations will not diffuse into the active layer, and will not diffuse into the active layer even for a long time in the future, achieving the improvement of the stability of the thin film transistors while improving the duration of the stability of the thin film transistors and appropriately reducing the thickness of the first barrier layer.

[0129] The above has introduced in detail an array substrate and a liquid crystal panel provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate includes a pixel display area, a demultiplexing circuit area, and a gate driving circuit area. The gate driving circuit area is located on at least one side of the pixel display area, and the demultiplexing circuit area is located at at least one end of the pixel display area. The pixel display area includes an opening area and a thin-film transistor setting area. The opening area is located on one side of the thin-film transistor setting area and is used to transmit the light of the backlight module. Characterized in that, The array substrate includes: A substrate; A first barrier layer, which is disposed on the substrate. The first barrier layer has a first opening in the opening area, and the first barrier layer is at least correspondingly disposed in the thin-film transistor setting area, the demultiplexing circuit area, and the gate driving circuit area; A buffer layer, which is disposed on the side of the first barrier layer away from the substrate. The buffer layer covers the opening area, the thin-film transistor setting area, and the gate driving circuit area; A thin-film transistor structure layer, which is disposed on the surface of the buffer layer away from the substrate. The thin-film transistor structure layer includes a first thin-film transistor and a second thin-film transistor. The first thin-film transistor is located in the thin-film transistor setting area, and the second thin-film transistor is disposed in the gate driving circuit area. The thin-film transistor structure layer includes an active layer, a gate insulating layer, and a first metal layer. The active layer is disposed on the surface of the buffer layer away from the substrate. The gate insulating layer is disposed on the surface of the active layer away from the buffer layer. The first metal layer includes a gate, and the first metal layer is disposed on the surface of the gate insulating layer away from the active layer. The first metal layer is at least disposed in the thin-film transistor setting area and the gate driving circuit area; A second barrier layer, which is disposed between the first metal layer and the gate insulating layer; The first barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the active layer from the substrate, the depth of the alkaline cations entering the first barrier layer is less than or equal to 20 angstroms; The second barrier layer has a second opening in the opening area and the thin-film transistor setting area, and has a third opening in the demultiplexing circuit area. The second barrier layer is correspondingly disposed in the gate driving circuit area. The second barrier layer is used to block the diffusion of alkaline cations in the direction of the active layer. In the direction perpendicular to the active layer from the first metal layer, the depth of the alkaline cations entering the second barrier layer is less than or equal to 20 angstroms.

2. The array substrate according to claim 1, Characterized in that, The buffer layer, the active layer, the gate insulating layer, and the first metal layer are also correspondingly disposed in the demultiplexing circuit area, and the thin-film transistor structure layer further includes a third thin-film transistor located in the demultiplexing circuit area; The thickness of the gate insulating layer disposed in the demultiplexing circuit area is less than the thickness of the gate insulating layer disposed in the gate driving circuit area.

3. The array substrate according to claim 2, Characterized in that, The thickness of the gate insulating layer provided in the pixel display area is less than the thickness of the gate insulating layer provided in the gate driving circuit area.

4. The array substrate according to claim 3, wherein, the thickness of the gate insulating layer provided in the pixel display area is greater than the thickness of the gate insulating layer provided in the demultiplexing circuit area.

5. The array substrate according to any one of claims 1-4, wherein, the dielectric constant of the gate insulating layer is greater than or equal to 6.

8.

6. The array substrate according to any one of claims 1-4, wherein, the light transmittance of both the gate insulating layer and the buffer layer is greater than or equal to 90%.

7. The array substrate according to claim 6, wherein, the gate insulating layer is a single-layer structure or a multi-layer stacked structure, and the buffer layer is a single-layer structure or a multi-layer stacked structure.

8. The array substrate according to any one of claims 1-4, wherein, the array substrate further includes a light-shielding layer. The light-shielding layer and the first barrier layer are provided on the same side of the substrate. The light-shielding layer has a fourth opening in the opening area. The light-shielding layer is at least correspondingly provided in the thin-film transistor setting area, and the light-shielding layer overlaps with the active layer at least located in the thin-film transistor setting area.

9. The array substrate according to claim 8, wherein, the light-shielding layer is provided between the buffer layer and the first barrier layer, or the light-shielding layer is provided between the substrate and the first barrier layer.

10. The array substrate according to any one of claims 1-4, wherein, the material of the gate insulating layer includes at least one of silicon oxide, silicon oxynitride, hafnium oxide, and aluminum oxide, and the material of the buffer layer includes at least one of silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, polyvinyl alcohol, polyethylene glycol, and polydimethylsiloxane.

11. The array substrate according to claim 2, wherein, the thin-film transistor structure layer further includes: a source-drain insulating layer provided on a surface of the first metal layer away from the buffer layer and covering the gate insulating layer; and a second metal layer provided on a surface of the source-drain insulating layer away from the gate insulating layer. The second metal layer is at least provided in the thin-film transistor setting area and the gate driving circuit area. The second metal layer includes a source electrode and a drain electrode. In a thin-film transistor, the source electrode is connected to the source contact area of the active layer, and the drain electrode is connected to the drain contact area of the active layer; wherein, the gate, the active layer, the source electrode, and the drain electrode located in the thin-film transistor setting area are used to form the first thin-film transistor, the gate, the active layer, the source electrode, and the drain electrode located in the gate driving circuit area are used to form the second thin-film transistor, and the gate, the active layer, the source electrode, and the drain electrode located in the demultiplexing circuit area are used to form the third thin-film transistor.

12. A liquid crystal panel, wherein, Comprising the array substrate according to any one of claims 1-11.

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