Design method of time-to-digital converter based on negative feedback time error amplifier

Abstract

The application discloses a design method of a time-to-digital converter based on a negative feedback time error amplifier, and relates to the field of semiconductor integrated circuit chip design. Specifically, the application is characterized in that: a traditional time-to-digital converter with a single delay chain is analyzed, the relative error of two delays is taken as the conversion precision, a high-precision time-to-digital converter with a Vernier delay chain is designed, coarse adjustment is realized, a time-to-digital converter with a multi-stage phase interpolation technology is used to improve the precision, fine adjustment is realized, the coarse adjustment and the fine adjustment are combined, a time error amplifier is inserted, a high-precision time-to-digital converter based on a time error amplifier is obtained, and the output signal of an SR latch is fed back to the input, and a plurality of time-to-digital converters based on the time error amplifier are cascaded. According to the method that the output signal of the SR latch is fed back to the input, the overall linearity of the time error amplifier is improved, and the design freedom of the time-to-digital converter can be greatly improved by using the time error amplifier based on the negative feedback.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit chip design technology, and in particular to a design method for a time-to-digital converter based on a negative feedback time error amplifier. Background Technology

[0002] A time-to-digital converter (TDC) is a circuit that quantizes the time difference between two electrical signals into a digital signal. The main applications of time-to-digital converters are as follows:

[0003] 1) Instrument testing field: In physical testing, the measurement of the time difference between two signals requires the use of a time-to-digital converter to digitize the time interval before the desired result can be obtained through digital signal processing.

[0004] 2) In the field of clock phase-locked loops and frequency synthesizers: there is a time difference between the rising edges of the reference clock and the feedback clock of the phase-locked loop. The digital control word obtained by digitization after being a time amplifier is filtered by a digital filter, and the resulting digital signal is used to digitally control the voltage-controlled oscillator.

[0005] To improve the accuracy of time-to-digital converters (TD-SCDMA), several methods are employed, including: 1. Vernier delay chain method; 2. Phase interpolation method; and 3. Time error amplifier (TDA) method. The Vernier delay chain is a relatively easy-to-implement method for improving accuracy. It utilizes the relative error between two delays as the conversion precision (Delay2 - Delay1), improving relative accuracy by an order of magnitude. However, it also doubles the mismatch between the two delays. Phase interpolation uses passive circuits or active inverters / current units to achieve intermediate phase, increasing quantization accuracy. However, this method drastically increases the number of interpolation units, leading to increased area and power consumption. The TDA method involves amplifying the time difference between two electrical signals before using a time-to-digital converter with the same precision for digital quantization. Summary of the Invention

[0006] Based on this, this application provides a design method for a time-to-digital converter based on a negative feedback time error amplifier to address the problem of how to improve the linearity of the time error amplifier and thus reduce the impact of nonlinear amplification on quantization accuracy.

[0007] This application provides a design method for a time-to-digital converter based on a negative feedback time error amplifier, including:

[0008] This paper analyzes the traditional time-to-digital converter with a single delay chain and designs a high-precision time-to-digital converter with a Vernier delay chain by using the relative error of the two delays as the conversion accuracy. The Vernier delay chain enables coarse adjustment.

[0009] A time-to-digital converter employing multi-stage phase interpolation technology improves accuracy, enabling fine adjustment of the Vernier delay chain;

[0010] By combining the coarse and fine adjustments and inserting a time error amplifier, a high-precision time-to-digital converter based on the time error amplifier is obtained.

[0011] By employing a balanced SR latch and feeding the output signal of the SR latch back to the input, the linearity of the time error amplifier with negative feedback is improved.

[0012] By leveraging the high linearity of time error amplifiers with negative feedback, multiple stages of time-to-digital converters based on time error amplifiers are cascaded.

[0013] The conventional time-to-digital converter with a single delay chain quantizes the rise time difference between the feedback voltage signal DIV and the reference input signal REF using a single delay unit, Delay.

[0014] The time quantization precision of the Vernier delay chain is determined by the relative difference between Delay and Delay2, Delay-Delay2.

[0015] The phase interpolation technique achieves higher quantization accuracy by interpolating between adjacent rising edges of the signal.

[0016] include,

[0017] If it is an active circuit for phase interpolation, a buffer is used to achieve phase averaging;

[0018] If it is a passive circuit for phase interpolation, then a resistor is used to achieve phase averaging.

[0019] By employing a balanced SR latch and feeding its output signal back to the input, the linearity of the time error amplifier with negative feedback is improved. Specifically, this includes...

[0020] An analysis is conducted on the unbalanced SR latch, in which the NAND gates use two sizes, N1 and N2, to achieve an equivalent input time difference T. OFF To improve the flexibility of the time error amplifier, a balanced SR latch is used instead of an unbalanced SR latch. The NAND gate uses a single size for N and T. OFF It is implemented by two inverters.

[0021] The gain of the time error amplifier can be controlled according to the quantization accuracy.

[0022] The calculation of the gain of the time error amplifier includes,

[0023] Recovery time ΔT of the time error amplifier OUT The time difference ΔT between the input signal and the input signal SR The logarithmic function expression between them is:

[0024] △T OUT =τ×[ln(A(t))-ln(α×△T)] SR (1)

[0025]

[0026] Where α represents the scaling factor, τ represents the recovery time constant, C represents the capacitive load, and g m A(t) represents the transconductance of the transistor, and A(t) represents the output voltage difference of the SR latch.

[0027] When -T OFF <ΔT SR <T OFF When the time error of the two input signals of the time error amplifier is zero, that is, the piecewise function near the zero point can be treated as linearization, therefore at -T OFF <ΔT SR <T OFF Under these conditions, the small-signal gain A of the time error amplifier T The expression is:

[0028]

[0029] Among them, T OFF This represents the equivalent input time difference.

[0030] Beneficial effects: This application improves the overall linearity of the time error amplifier by feeding back the output signal of the SR latch to the input. Through multi-stage cascading, the bit requirement of a single-stage time-to-digital converter is reduced, thereby greatly reducing the chip size of high-bit, high-precision time-to-digital converters. Ultimately, a time-to-digital converter with a relatively small area and low power consumption can be designed with a high bit count and high precision.

[0031] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0032] The accompanying drawings are provided for a better understanding of this solution and do not constitute a limitation of this application. Wherein:

[0033] Figure 1 It is based on the phase-locked loop circuit schematic provided in this application;

[0034] Figure 2(a) is a schematic diagram of a conventional time-to-digital converter based on a single delay chain according to the present application;

[0035] Figure 2(b) is a schematic diagram of a high-precision time-to-digital converter based on a Vernier delay chain provided in this application;

[0036] Figure 3(a) is a schematic diagram of a conventional time-to-digital converter based on a delay chain and a D flip-flop array according to the present application;

[0037] Figure 3(b) is a schematic diagram of a time-to-digital converter with improved accuracy based on phase interpolation technology according to this application;

[0038] Figure 4(1) is a schematic diagram of the implementation method of the active circuit and passive circuit of phase interpolation according to the present application;

[0039] Figure 4(2) is a complete implementation circuit diagram of the phase interpolation circuit using active circuit provided in this application;

[0040] Figure 5(a) is a simplified schematic diagram of a time-to-digital converter based on phase interpolation provided in this application;

[0041] Figure 5(b) is a schematic diagram of a time-to-digital converter based on multi-stage phase interpolation technology to improve accuracy according to the present application.

[0042] Figure 6(a) is a circuit schematic diagram of a time-to-digital converter based on a delay chain for coarse adjustment and a Vernier delay chain for fine adjustment, according to the present application.

[0043] Figure 6(b) is a circuit schematic diagram of a high-precision time-to-digital converter based on a time error amplifier according to the present application.

[0044] Figure 7(a) is a schematic diagram of an unbalanced SR latch provided in this application;

[0045] Figure 7(b) is a schematic diagram of a balanced SR latch provided in this application;

[0046] Figure 7(c) shows the recovery time ΔT of the time error amplifier provided in this application. OUT and the time difference ΔT between the input signals S and R SR The relationship is represented by a logarithmic function graph;

[0047] Figure 7(d) shows the recovery time ΔT of the time error amplifier provided in this application. OUTWith the time difference ΔT between the input signals S and R SR A schematic diagram illustrating the changes;

[0048] Figure 8(a) is a schematic diagram of improving the linearity of a latch by feeding back the output signal of the SR latch to the input according to the method provided in this application;

[0049] Figure 8(b) is a circuit schematic diagram of the negative feedback provided in this application implemented by using a resistor R;

[0050] Figure 8(c) is a schematic diagram of a self-biased time amplifier circuit with negative feedback according to the present application;

[0051] Figure 9 This is a schematic diagram of a 4-stage cascaded time-to-digital converter implemented based on a self-biased time amplifier circuit with feedback, as provided in this application. Detailed Implementation

[0052] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of this application, including various details to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0053] This application provides a design method for a time-to-digital converter based on a negative feedback time error amplifier, including:

[0054] S1: This paper analyzes a traditional time-to-digital converter with a single delay chain. By utilizing the relative error of the two delays as the conversion accuracy, a high-precision time-to-digital converter with a Vernier delay chain is designed. The Vernier delay chain enables coarse adjustment. It should be noted that:

[0055] The conventional time-to-digital converter with a single delay chain quantizes the rise time difference between the feedback voltage signal DIV and the reference input signal REF using a single delay unit, Delay.

[0056] The time quantization precision of the Vernier delay chain is determined by the relative difference between Delay and Delay2, Delay-Delay2.

[0057] S2: A time-to-digital converter employing multi-stage phase interpolation technology to improve accuracy, enabling fine adjustment of the Vernier delay chain. It should be noted that:

[0058] The phase interpolation technique achieves higher quantization accuracy by interpolating between adjacent rising edges of the signal.

[0059] include,

[0060] If it is an active circuit for phase interpolation, a buffer is used to achieve phase averaging;

[0061] If it is a passive circuit for phase interpolation, then a resistor is used to achieve phase averaging.

[0062] To further improve quantization accuracy, multi-stage phase interpolation is required.

[0063] S3: Combine the coarse and fine adjustments and insert a time error amplifier to obtain a high-precision time-to-digital converter based on the time error amplifier.

[0064] S4: A balanced SR latch is used, and the output signal of the SR latch is fed back to the input to improve the linearity of the time error amplifier with negative feedback. It should be noted that:

[0065] By employing a balanced SR latch and feeding its output signal back to the input, the linearity of the time error amplifier with negative feedback is improved. Specifically, this includes...

[0066] An analysis is conducted on the unbalanced SR latch, in which the NAND gates use two sizes, N1 and N2, to achieve an equivalent input time difference T. OFF To improve the flexibility of the time error amplifier, a balanced SR latch is used instead of an unbalanced SR latch. The NAND gate uses a single size for N and T. OFF It is implemented by two inverters.

[0067] The gain of the time error amplifier can be controlled according to the quantization accuracy.

[0068] The calculation of the gain of the time error amplifier includes,

[0069] Recovery time ΔT of the time error amplifier OUT The time difference ΔT between the input signal and the input signal SR The logarithmic function expression between them is:

[0070] △T OUT =τ×[ln(A(t))-ln(α×△T)] SR (1)

[0071]

[0072] Where α represents the scaling factor, τ represents the recovery time constant, C represents the capacitive load, and g m A(t) represents the transconductance of the transistor, and A(t) represents the output voltage difference of the SR latch.

[0073] When -T OFF<△T SR <T OFF When the time error of the two input signals of the time error amplifier is zero, that is, the piecewise function near the zero point can be treated as linearization, therefore at -T OFF <△T SR <T OFF Under these conditions, the small-signal gain A of the time error amplifier T The expression is:

[0074]

[0075] Among them, T OFF This represents the equivalent input time difference.

[0076] S5: Cascade multiple stages of time-to-digital converters based on time error amplifiers by utilizing the high linearity of time error amplifiers with negative feedback.

[0077] First, as shown in Figure 2(a), a schematic diagram of a traditional time-to-digital converter based on a single delay chain is presented. The rise time difference between the input signals DIV and REF is quantized using a single delay unit, Delay. Here, the DIV signal refers to... Figure 1 The feedback voltage signal, i.e., the output signal V of the frequency divider. FB REF signal refers to, for example Figure 1 The reference input signal in (a), i.e., the output signal V IN .

[0078] Because the quantization accuracy of a single-delay-chain time-to-digital converter is limited by the accuracy of a single delay unit, i.e., by the size of the silicon semiconductor process, the quantization accuracy is limited. Therefore, this type of time-to-digital converter is also defined as a gate-delay time-to-digital converter (GD-TDC).

[0079] To improve quantization accuracy, a schematic diagram of a high-precision time-to-digital converter based on a Vernier delay chain is shown in Figure 2(b). The time quantization accuracy of the Vernier delay chain is determined by the relative difference between Delay and Delay2, Delay-Delay2. Compared with the traditional case where the quantization accuracy is determined by the delay unit itself, the circuit performance is greatly improved.

[0080] Alternatively, a sub-gate delay time-to-digital converter (SGD-TDC) with sub-gate delay quantization precision can also be obtained using phase interpolation technology. Figure 3(a) shows the schematic diagram of a traditional time-to-digital converter based on a delay chain and a D flip-flop array (DFF array); Figure 3(b) shows a time-to-digital converter with improved precision based on phase interpolation technology, defined as a phase interpolator time-to-digital converter (PI-TDC).

[0081] As shown in Figure 4, phase interpolation technology achieves higher quantization accuracy by interpolating between adjacent rising edge signals A and B. Among them, Figure 4(1), (a) shows the active circuit implementation method of phase interpolation, that is, using a buffer to achieve phase averaging; (b) shows the passive circuit implementation method of phase interpolation, using a resistor to achieve phase averaging; finally, Figure 4(2) provides the complete implementation circuit of phase interpolation circuit using active circuit.

[0082] To further improve quantization accuracy, multi-stage phase interpolation is required, as shown in Figure 5. Figure 5(a) shows a simplified schematic of a time-to-digital converter based on phase interpolation; while Figure 5(b) shows a schematic of a time-to-digital converter based on multi-stage phase interpolation to improve accuracy.

[0083] Figure 6(a) shows the circuit schematic of a two-stage time-to-digital converter that uses a delay chain for coarse adjustment and a Vernier delay chain for fine adjustment. A wide quantization range and high quantization accuracy can be achieved by cascading the two stages for coarse and fine quantization accuracy. However, due to the influence of the Vernier delay chain, the area of ​​the Vernier delay chain will increase dramatically if the quantization accuracy is to be further improved.

[0084] To better reduce the area of ​​the delay chain, a high-precision time-to-digital converter based on a time error amplifier is a good choice. As shown in Figure 6(b), the circuit schematic of a high-precision time-to-digital converter based on a time error amplifier (TDA) is given.

[0085] The advantages of a time-to-digital converter based on a time error amplifier are as follows: 1) It achieves sub-gate level delay quantization accuracy; 2) It reduces chip area by using a single delay chain, a time error amplifier, and a folded single delay chain; 3) The gain of the time error amplifier can be controlled according to the quantization accuracy.

[0086] As shown in Figure 7(a), the traditional method uses an unbalanced SR latch, in which the NAND gates use two sizes, N1 and N2, to achieve an equivalent input time difference T. OFF .

[0087] Figure 7(b) shows the use of a balanced SR latch, where the NAND gate uses one size for N and T. OFF It is implemented using two inverters. The time error amplifier using a balanced SR latch offers greater flexibility compared to implementations using unbalanced N1 and N2 sizes, while also being less sensitive to process voltage and temperature (PVT), resulting in a more stable and reliable circuit.

[0088] Figure 7(c) shows the recovery time ΔT of the time error amplifier. OUT and the time difference ΔT between the input signals S and R SR The relationship, recovery time △T OUT The time difference ΔT between the input signal and the input signal SR The relationship between them is a logarithmic function, and as ΔT... SR The increase of △T OUT decline.

[0089] As shown in Figure 7(d), the recovery time ΔT of the time error amplifier OUT With the time difference ΔT between the input signals S and R SR The decrease in S and the increase in R can be observed from the time difference ΔT between the input signals S and R. SR1 Reduced to △T SR2 The output recovery time ΔT OUT1 Increase to △T OUT2 Obtained. Recovery time △T OUT The time difference ΔT between the input signal and the input signal SR The expression for the logarithmic function is as follows:

[0090] △T OUT =τ×[ln(A(t))-ln(α×△T)] SR (1)

[0091]

[0092] Where α represents the scaling factor, τ represents the recovery time constant, C represents the capacitive load, and gm A(t) represents the transconductance of the transistor, and A(t) represents the output voltage difference of the SR latch.

[0093] When -T OFF <△T SR <T OFF When the time error of the two input signals of the time error amplifier is zero, that is, the piecewise function near the zero point can be treated as linearization, therefore at -T OFF <△T SR <T OFF Under these conditions, the small-signal gain A of the time error amplifier T The expression is:

[0094]

[0095] Among them, T OFF This represents the equivalent input time difference.

[0096] Traditional time error amplifiers based on balanced SR latches are similar to amplifiers in open-loop operation. Due to their high gain, the input time difference is very small, but the linearity is relatively poor. To improve the linearity of time error amplifiers based on balanced SR latches, a time error amplifier with negative feedback was designed. This method uses the output signal of the SR latch to feed back to the input, thereby improving the linearity of the latch and thus the overall linearity of the time error amplifier, as shown in Figure 8(a). In the actual implementation, the circuit diagram using resistor R to implement the feedback function is shown in Figure 8(b). Finally, the proposed self-biased time amplifier circuit with negative feedback is shown in Figure 8(c). The benefits of the negative feedback time error amplifier include: 1) improved stability of the overall gain and increased linear range of the gain; 2) reduced output signal distortion; and 3) increased bandwidth.

[0097] By utilizing the high linearity of time error amplifiers with negative feedback, multiple stages of time-to-digital converters based on time error amplifiers can be cascaded. For example... Figure 9 As shown, a schematic diagram of a 4-stage cascaded time-to-digital converter based on a self-biased time amplifier circuit with feedback is presented.

[0098] By cascading multiple stages, the bit requirement for a single-stage time-to-digital converter is reduced, thereby greatly reducing the chip size of high-bit, high-precision time-to-digital converters. Ultimately, a time-to-digital converter with a relatively small area and low power consumption can be designed with a high bit count and high precision.

[0099] For example, if designing a 12-bit time-to-digital converter based on a traditional delay chain requires 2 12= 4096 delay units. According to this requirement, if a two-stage time-to-digital converter based on a traditional time error amplifier is used, at least 2*2... 6 = 128 delay units.

[0100] Although the number of delay units has decreased exponentially, there is still room for optimization. If a 4-stage cascaded time-to-digital converter is used, the required number of delay units is 4*2. 3 = 32.

[0101] Similarly, if a 6-stage cascaded time-to-digital converter is used, the required number of delay units is 6*2. 2 =24, which is also the minimum number of delay units required to design a 12-bit time-to-digital converter.

[0102] Therefore, using a time error amplifier with negative feedback can greatly improve the design freedom of the time-to-digital converter, while achieving a higher bit count and higher accuracy with a smaller area and lower power consumption.

[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A design method for a time-to-digital converter based on a negative feedback time error amplifier, characterized in that, include: This paper analyzes a traditional time-to-digital converter with a single delay chain and designs a high-precision time-to-digital converter with a Vernier delay chain by using the relative error of the two delays as the conversion accuracy. The Vernier delay chain enables coarse adjustment. A time-to-digital converter with improved accuracy by using multi-stage phase interpolation technology enables fine adjustment of the Vernier delay chain. A wide quantization range and high quantization accuracy can be achieved by cascading coarse and fine quantization precision. The time quantization precision of the Vernier delay chain is determined by the relative difference between Delay and Delay2, Delay-Delay2; The phase interpolation technique achieves higher quantization accuracy by interpolating between adjacent rising edges of the signal; If it is an active circuit for phase interpolation, a buffer is used to achieve phase averaging; If it is a passive circuit for phase interpolation, then a resistor is used to achieve phase averaging; By combining the coarse and fine adjustments and inserting a time error amplifier, a high-precision time-to-digital converter based on the time error amplifier is obtained. By employing a balanced SR latch and feeding the output signal of the SR latch back to the input, the linearity of the time error amplifier with negative feedback is improved. An analysis is conducted on the unbalanced SR latch, in which the NAND gates use two sizes, N1 and N2, to achieve an equivalent input time difference T. OFF To improve the flexibility of the time error amplifier, a balanced SR latch is used instead of an unbalanced SR latch. The NAND gate uses a single size for N and T. OFF Implemented by two inverters; By leveraging the high linearity of time error amplifiers with negative feedback, multiple stages of time-to-digital converters based on time error amplifiers are cascaded.

2. The design method of the time-to-digital converter based on the negative feedback time error amplifier according to claim 1, characterized in that: The conventional time-to-digital converter with a single delay chain quantizes the rise time difference between the feedback voltage signal DIV and the reference input signal REF using a single delay unit, Delay.

3. The design method of the time-to-digital converter based on the negative feedback time error amplifier according to claim 2, characterized in that: The gain of the time error amplifier can be controlled according to the quantization accuracy.

4. The design method of the time-to-digital converter based on the negative feedback time error amplifier according to claim 3, characterized in that: The calculation of the gain of the time error amplifier includes, Recovery time of time error amplifier Time difference with input signal The logarithmic function expression between them is: （1） = （2） in, Indicates the scaling factor. Represents the recovery time constant, C represents the capacitive load, and g represents the recovery time constant. m A(t) represents the transconductance of the transistor, and A(t) represents the output voltage difference of the SR latch. when When the time error of the two input signals of the time error amplifier is zero, that is, the piecewise function near the zero point can be treated as linearization, therefore in In this case, the small-signal gain of the time error amplifier The expression is: （3） Among them, T OFF This represents the equivalent input time difference.

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