Layout structure determination method and device, equipment and storage medium

Abstract

The present disclosure provides a layout structure determination method and device, equipment and a storage medium, relates to the technical field of computers, in particular to the technical field of quantum computers, quantum chips and quantum simulation. The specific implementation scheme is: obtaining a target search range of a geometric parameter of a chip layout structure to be designed based on a target parameter required by the chip layout structure to be designed; the target search range represents a value range of the geometric parameter of the chip layout structure to be designed; the value of the geometric parameter can affect a capacitance parameter of the chip layout structure; obtaining a target value of the geometric parameter of the chip layout structure to be designed in the target search range based on the target parameter; obtaining a target chip layout structure based on the target value of the geometric parameter; the value of the geometric parameter of the target chip layout structure is the target value, and difference information between a simulation parameter corresponding to the target chip layout structure and the target parameter satisfies a preset difference requirement.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computers, quantum chips, and quantum simulation technology. Background Technology

[0002] The design of a quantum chip layout (e.g., a superconducting quantum chip layout) refers to the process of arranging and laying out qubits and other related components (such as couplers and readout cavities) on a chip to achieve a specific quantum computing task. This design process involves physical and engineering considerations to ensure that the interactions, control, and readout between qubits can be performed effectively, thereby achieving stable and high-quality quantum computing. Therefore, how to design quantum chip layouts efficiently, accurately, and automatically has become a crucial issue. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for determining the layout structure.

[0004] According to one aspect of this disclosure, a method for determining a layout structure is provided, comprising:

[0005] Based on the target parameters required for the chip layout structure to be designed, the target search range of the geometric parameters of the chip layout structure to be designed is obtained; wherein, the target search range represents the value range of the geometric parameters of the chip layout structure to be designed; the value of the geometric parameters can affect the target parameters of the chip layout structure;

[0006] Based on the target parameters, the target values ​​of the geometric parameters of the chip layout structure to be designed are obtained within the target search range;

[0007] Based on the target values ​​of the geometric parameters, the target chip layout structure is obtained; wherein, the geometric parameters of the target chip layout structure are the target values, and the difference information between the simulation parameters corresponding to the target chip layout structure and the target parameters meets the preset difference requirements.

[0008] According to another aspect of this disclosure, a layout structure determining apparatus is provided, comprising:

[0009] The first acquisition unit is used to obtain the target search range of the geometric parameters of the chip layout structure to be designed based on the target parameters required for the chip layout structure to be designed; wherein, the target search range represents the value range of the geometric parameters of the chip layout structure to be designed; the value of the geometric parameters can affect the target parameters of the chip layout structure;

[0010] The search unit is used to obtain the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range based on the target parameters.

[0011] The second acquisition unit is used to obtain the target chip layout structure based on the target values ​​of the geometric parameters; wherein the geometric parameters of the target chip layout structure are the target values, and the difference information between the simulation parameters corresponding to the target chip layout structure and the target parameters meets the preset difference requirements.

[0012] According to another aspect of this disclosure, a computing device is provided, comprising:

[0013] At least one quantum processing unit (QPU);

[0014] A memory, coupled to the at least one QPU and used to store executable instructions,

[0015] The instruction is executed by the at least one QPU to enable the at least one QPU to perform the method described above;

[0016] Or, including:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above.

[0020] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above.

[0021] Alternatively, the computer instructions may be used to cause the computer to perform the methods described above.

[0022] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by at least one quantum processing unit, implements the methods described above.

[0023] Alternatively, the computer program may implement the above-described method when executed by a processor.

[0024] In this way, the disclosed solution can obtain the target search range of the geometric parameters of the chip layout structure to be designed based on the target parameters required by the chip layout structure to be designed. Then, within the target search range, it can efficiently search for the target values ​​of the geometric parameters of the chip layout structure to be designed. This provides data support for obtaining a chip layout structure that can achieve the target parameters, thereby effectively improving the design efficiency of the chip layout structure. Moreover, since the above process is automated and requires no manual intervention, it can also effectively save human resources.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0026] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0027] Figure 1 This is a schematic diagram of the implementation flow of the layout structure determination method according to the embodiments of this disclosure. Figure 1 ;

[0028] Figure 2 This is a schematic diagram of the implementation flow of the layout structure determination method according to the embodiments of this disclosure. Figure 2 ;

[0029] Figure 3 This is a schematic diagram of the implementation flow of the layout structure determination method according to the embodiments of this disclosure. Figure 3 ;

[0030] Figure 4 This is a schematic diagram of the QCQ structure according to an embodiment of the present disclosure;

[0031] Figure 5 This is a flowchart illustrating a layout structure determination method according to an embodiment of the present disclosure in one example;

[0032] Figure 6 This is a flowchart illustrating an example of the search grid reduction algorithm according to an embodiment of the present disclosure;

[0033] Figure 7 This is a schematic diagram of a chip layout structure in one example according to an embodiment of the present disclosure;

[0034] Figure 8 This is a schematic diagram of the structure of the apparatus for determining the layout according to an embodiment of the present disclosure;

[0035] Figure 9 This is a block diagram of a computing device used to implement the layout structure determination method of the embodiments of this disclosure. Detailed Implementation

[0036] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0037] As a logical inevitable breakthrough in chip size beyond the limits of classical physics and a landmark technology of the post-Moore's Law era, quantum computing has garnered significant attention. Currently, quantum computing is developing rapidly at the algorithm, application, and hardware levels. It is noteworthy that the realization of quantum algorithms and applications is highly dependent on the development and advancement of quantum hardware. In terms of quantum hardware implementation, the industry possesses various technical solutions, such as superconducting circuits, ion traps, and optical quantum systems. Benefiting from its excellent scalability and mature semiconductor manufacturing processes, superconducting quantum circuits are considered one of the most promising technological routes. In recent years, with the development of superconducting quantum computing technology and micro-nano fabrication processes, the number of qubits integrated on superconducting quantum chips has increased dramatically, resulting in richer and more comprehensive chip structures.

[0038] The design of a quantum chip layout (e.g., a superconducting quantum chip layout) refers to the process of arranging and laying out qubits and other related components (such as couplers and readout cavities) on a chip to achieve a specific quantum computing task. This design process involves physical and engineering considerations to ensure that the interaction, control, and readout between qubits can be performed effectively, thereby achieving stable and high-quality quantum computing. The qubit-coupler-qubit (QCQ) structure is one of the most important structures in a superconducting quantum chip (e.g., a superconducting quantum chip layout), which enables the on and / or off of the equivalent coupling strength between two qubits.

[0039] Currently, the design of QCQ structures in superconducting quantum chip layouts primarily involves deriving the target capacitance parameters based on the desired characteristic parameters of the superconducting quantum chip (e.g., the anharmonicity of qubits, the coupling strength between qubits, etc.). Then, based on these target capacitance parameters, the dimensions of the QCQ structure on the superconducting quantum chip layout (also known as the specific values ​​of geometric parameters) are deduced manually using experience. Subsequently, the simulated capacitance parameters of the QCQ structure under the deduced geometric parameters are verified. If the verification fails, the geometric parameters are manually modified again based on experience, and this process is iterated. This process is highly dependent on the engineer's professional experience, and even for an engineer with extensive experience in QCQ structure design, this process requires a significant amount of time and effort, severely impacting the R&D and iteration efficiency of superconducting quantum chips. Therefore, how to achieve efficient and automated design of quantum chip layouts (e.g., chip layouts containing QCQ structures) has become a crucial issue.

[0040] Based on this, the present disclosure provides a layout structure determination method that can significantly improve the design efficiency of chip layout structure and no longer rely on the experience of engineers, thus greatly promoting the research and development and iteration efficiency of quantum chip layout.

[0041] Figure 1 This is a schematic diagram of the implementation flow of the layout structure determination method according to the embodiments of this disclosure. Figure 1 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices. For example, it can be applied to electronic devices with classical computing capabilities such as personal computers, servers, and server clusters, or it can be directly applied to quantum computers. This disclosure does not impose any restrictions on this method.

[0042] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 1 As shown, the method for determining the layout structure includes:

[0043] Step S101: Based on the target parameters (such as target capacitance parameters) required for the chip layout structure to be designed, obtain the target search range for the geometric parameters of the chip layout structure to be designed.

[0044] Here, the target search range refers to the range of values ​​for the geometric parameters of the chip layout structure to be designed. In practical applications, the values ​​of the geometric parameters can affect the capacitance parameters of the chip layout structure.

[0045] Step S102: Based on the target parameters (such as the target capacitance parameters), obtain the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range.

[0046] Step S103: Based on the target values ​​of the geometric parameters, the target chip layout structure is obtained.

[0047] Here, the geometric parameters of the target chip layout structure are taken as target values, and the difference information between the simulation parameters (such as simulation capacitor parameters) and the target parameters (such as target capacitor parameters) corresponding to the target chip layout structure meets the preset difference requirements.

[0048] It should be noted that once the target chip layout structure is obtained, a quantum chip can be manufactured based on the target chip layout structure.

[0049] In this way, the disclosed solution can obtain the target search range of the geometric parameters of the chip layout structure to be designed based on the target parameters required by the chip layout structure to be designed. Then, within the target search range, it can efficiently search for the target values ​​of the geometric parameters of the chip layout structure to be designed. This provides data support for obtaining a chip layout structure that can achieve the target parameters, thereby effectively improving the design efficiency of the chip layout structure. Moreover, since the above process is automated and requires no manual intervention, it can also effectively save human resources.

[0050] In a specific example of the present disclosure, the chip layout structure to be designed includes at least one QCQ structure; wherein the QCQ structure includes two qubits and a coupler for coupling the two qubits. Accordingly, the target chip layout structure designed by the present disclosure also includes at least one QCQ structure. Thus, the present disclosure can be applied to chip layout design processes that include QCQ structures, enriching the application scenarios of the present disclosure.

[0051] Furthermore, when the chip layout structure to be designed includes at least one QCQ structure, the target search range can specifically represent the range of values ​​for the geometric parameters of the QCQ structure in the chip layout structure to be designed. Correspondingly, the target parameters, such as the target capacitance parameters, can specifically be the capacitance parameters that the QCQ structure needs to achieve. Since the values ​​of the geometric parameters of the QCQ structure in the chip layout structure can affect the values ​​of the capacitance parameters, the QCQ structure can be designed to satisfy the target parameters, such as the target capacitance parameters, based on the scheme disclosed herein. This significantly improves the design efficiency of the chip layout structure and eliminates reliance on the engineer's experience, thereby greatly promoting the research and iteration efficiency of quantum chip layouts.

[0052] Here, it can be understood that the target value of the geometric parameters of the QCQ structure to satisfy the target parameters (such as satisfying the target capacitance parameters) can specifically refer to the difference information between the simulation parameters obtained by simulation and the target parameters (such as the difference information between the simulation capacitance parameters obtained by simulation and the target capacitance parameters) when the geometric parameters of the QCQ structure are the target values, which meets the preset difference requirements.

[0053] In one example, the chip layout structure to be designed described above can be the layout structure of a superconducting quantum chip; here, a superconducting quantum chip refers to a quantum chip made of superconducting materials. For example, all components in a superconducting quantum chip (e.g., qubits, coupling devices, etc.) are made of superconducting materials. This allows the disclosed solution to be applied to the layout structure design of superconducting quantum chips, enriching the application scenarios of the disclosed solution.

[0054] In a specific example of the disclosed solution, the target search range can be obtained in the following manner. Specifically, the target search range for the geometric parameters of the chip layout structure to be designed, based on the target parameters required by the chip layout structure to be designed (for example, step S101 mentioned above), specifically includes:

[0055] Step S101-1: Obtain the first target boundary of the geometric parameters of the chip layout structure to be designed, and the second target boundary of the geometric parameters of the chip layout structure to be designed.

[0056] Here, the simulation parameter corresponding to the first target boundary is less than the target parameter (for example, the simulation capacitance parameter corresponding to the first target boundary is less than the target capacitance parameter). More specifically, in one example, the first target boundary can be the minimum search boundary of the geometric parameters of the chip layout structure to be designed. Correspondingly, the simulation parameter corresponding to the second target boundary is greater than the target parameter (for example, the simulation capacitance parameter corresponding to the second target boundary is greater than the target capacitance parameter). More specifically, in one example, the second target boundary can be the maximum search boundary of the geometric parameters of the chip layout structure to be designed.

[0057] Here, the simulation parameters corresponding to the first target boundary (e.g., simulation capacitance parameters) are obtained by simulating the chip layout structure with the geometric parameters of the first target boundary; the simulation parameters corresponding to the second target boundary (e.g., simulation capacitance parameters) are obtained by simulating the chip layout structure with the geometric parameters of the second target boundary.

[0058] Furthermore, in one example, electromagnetic simulation software can be used to simulate the chip layout structure with the geometric parameters of the first target boundary to obtain the simulation parameters (e.g., simulation capacitor parameters) corresponding to the first target boundary. Similarly, electromagnetic simulation software can be used to simulate the chip layout structure with the geometric parameters of the second target boundary to obtain the simulation parameters (e.g., simulation capacitor parameters) corresponding to the second target boundary.

[0059] Step S101-2: Based on the first target boundary and the second target boundary, obtain the target search range of the geometric parameters of the chip layout structure to be designed.

[0060] It should be noted that the target search range is the minimum search range of the geometric parameters of the chip layout structure to be designed, which can be specifically [first target boundary, second target boundary]. Searching within this minimum search range allows for a quick and efficient acquisition of the target values ​​of the geometric parameters that meet the target parameters (such as target capacitance parameters).

[0061] Thus, this disclosed solution provides a specific method for obtaining the minimum search range (i.e., the target search range), which facilitates efficient and rapid searching within the target search range to obtain the target values ​​of the geometric parameters of the chip layout structure that can achieve the target parameters. Moreover, this process no longer relies on the engineer's experience, greatly promoting the research and development and iteration efficiency of quantum chip layouts.

[0062] Figure 2 This is a flowchart illustrating the layout structure determination method according to embodiments of this disclosure. Figure 2 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any limitations on these applications. It is understood that the above... Figure 1 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0063] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 2 As shown, the method for determining the layout structure includes:

[0064] Step S201: Perform the i-th range reduction process to obtain the first target boundary of the geometric parameters of the chip layout structure to be designed, and the second target boundary of the geometric parameters of the chip layout structure to be designed.

[0065] Here, the i-th range reduction process includes:

[0066] Step S201-1, obtain the i-th step length; i is a positive integer greater than or equal to 1.

[0067] Here, the i-th step size is related to the i-th candidate boundary; the simulation parameters corresponding to the i-th candidate boundary are smaller than the target parameters (for example, the simulation capacitance parameters corresponding to the i-th candidate boundary are smaller than the target capacitance parameters). The simulation parameters corresponding to the i-th candidate boundary (e.g., the simulation capacitance parameters) are obtained by simulating the chip layout structure with the geometric parameters of the i-th candidate boundary.

[0068] For example, in one instance, electromagnetic simulation software can be used to simulate the chip layout structure with geometric parameters of the i-th candidate boundary, and obtain the simulation parameters (such as simulation capacitor parameters) corresponding to the i-th candidate boundary.

[0069] In a specific example, the i-th step size can be obtained in the following way. Specifically, the above-described method of obtaining the i-th step size (e.g., step S201-1 above) can specifically include: obtaining the i-th step size based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, as well as the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary.

[0070] In one example, electromagnetic simulation software can be used to simulate the chip layout structure with geometric parameters of the (i-1)th candidate boundary, obtaining the simulation parameters corresponding to the (i-1)th candidate boundary. Similarly, electromagnetic simulation software can be used to simulate the chip layout structure with geometric parameters of the ith candidate boundary, obtaining the simulation parameters corresponding to the ith candidate boundary. Thus, with all four parameters known, the ith step size can be obtained.

[0071] Here, since the simulation parameters corresponding to the (i-1)th candidate boundary, the (i-1)th candidate boundary, and the simulation parameters corresponding to the i-th and i-th candidate boundaries are all deterministic values ​​and relatively easy to obtain, the execution time of the i-th range reduction process can be effectively reduced, thereby further improving the design efficiency of the chip layout structure. Moreover, since the (i-1)th and i-th candidate boundaries are two consecutive candidate boundaries, it can also ensure that the i-th step size has a small granularity, which facilitates the rapid acquisition of the minimum search range (i.e., the target search range), thereby further improving the design efficiency of the chip layout structure.

[0072] Furthermore, in a specific example, the i-th step size can also be calculated in the following way. Specifically, the above-described method of obtaining the i-th step size based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, as well as the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary, can specifically include:

[0073] Step S201-1-1: Obtain the i-th slope. The i-th slope is obtained based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, as well as the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary.

[0074] In this example, the simulation parameter corresponding to the i-th candidate boundary is less than the target parameter. For example, the simulation capacitance parameter corresponding to the i-th candidate boundary is less than the target capacitance parameter.

[0075] Furthermore, in one example, the i-th slope is obtained based on the simulated capacitance parameters corresponding to the (i-1)-th and (i-1)-th candidate boundaries, as well as the simulated capacitance true parameters corresponding to the i-th and i-th candidate boundaries. For example, by using the (i-1)-th and i-th candidate boundaries as input values ​​to a vector function, and correspondingly using the simulated capacitance parameters corresponding to the (i-1)-th and i-th candidate boundaries as output values, the i-th slope can be obtained through the vector function, and thus the i-th step size can be obtained, providing effective support for quickly obtaining the minimum search range.

[0076] Furthermore, in one example, the chip layout structure with geometric parameters of the (i-1)th candidate boundary can be modeled using electromagnetic simulation software, and the modeled chip layout structure can be simulated to obtain the simulation parameters corresponding to the (i-1)th candidate boundary. Similarly, the chip layout structure with geometric parameters of the ith candidate boundary can be modeled using electromagnetic simulation software, and the modeled chip layout structure can be simulated to obtain the simulation parameters corresponding to the ith candidate boundary.

[0077] Furthermore, in one example, when i is 1, the first slope can be obtained based on the simulation parameters corresponding to the 0th candidate boundary and the 1st candidate boundary. Alternatively, when i is greater than or equal to 2, the second slope can be obtained based on the candidate boundaries obtained in the previous iteration, and so on.

[0078] Here, the 0th candidate boundary and the 1st candidate boundary can be initialized with values. For example, the 1st candidate boundary and the 2nd candidate boundary can be initialized in the following way:

[0079] A first layout and a second layout are randomly generated to achieve the target parameters (such as the target capacitance parameters). The values ​​of the geometric parameters of the first layout and the second layout are used as candidate boundaries for initialization. For example, the values ​​of the geometric parameters of the first layout can be used as the 0th candidate boundary, and the values ​​of the geometric parameters of the second layout can be used as the 1st candidate boundary.

[0080] It should be noted that the above initialization methods are merely illustrative examples. In practical applications, other initialization methods can also be used, and this disclosure does not impose any restrictions on them.

[0081] Step S201-1-2: Obtain the i-th difference between the simulation parameters and the target parameters corresponding to the i-th candidate boundary.

[0082] Here, the execution order of steps S201-1-1 and S201-1-2 can be interchanged, and this disclosure does not impose specific restrictions on this.

[0083] Step S201-1-3: Take the ratio of the i-th difference to the i-th slope as the i-th...

[0084] Step length.

[0085] Thus, this disclosed solution provides a specific calculation method for obtaining the i-th step length, and this method is simple, efficient, and highly interpretable. Therefore, it can reduce the step length of the i-th step.

[0086] This reduces the execution time of the process by narrowing down the scope, thereby further improving the design efficiency of the chip layout structure.

[0087] Step S201-2: Based on the i-th step length, obtain the (i+1)-th candidate boundary.

[0088] In one example, the sum of the i-th candidate boundary and the i-th step size can be used as the (i+1)-th candidate boundary.

[0089] Step S201-3: Determine whether the simulation parameter corresponding to the (i+1)th candidate boundary is greater than the target parameter (e.g., determine whether the simulation capacitor parameter corresponding to the (i+1)th candidate boundary is greater than the target capacitor parameter). If yes, that is, if the simulation parameter corresponding to the (i+1)th candidate boundary is greater than the target parameter, execute step S201-4. If no, that is, if the simulation parameter corresponding to the (i+1)th candidate boundary is less than or equal to the target parameter, enter the (i+1)th range reduction process. For example, after i+1, return to step S201-1, and repeat this process until the first target boundary of the geometric parameters of the chip layout structure to be designed and the second target boundary of the geometric parameters of the chip layout structure to be designed are obtained.

[0090] Step S201-4: If the simulation parameters corresponding to the (i+1)th candidate boundary are greater than the target parameters, the i-th candidate boundary is taken as the first target boundary of the geometric parameters of the chip layout structure to be designed, and the (i+1)th candidate boundary is taken as the second target boundary of the geometric parameters of the chip layout structure to be designed.

[0091] Here, the simulation parameters corresponding to the (i+1)th candidate boundary (e.g., simulation capacitance parameters) are obtained by simulating the chip layout structure with geometric parameters of the (i+1)th candidate boundary. For example, the chip layout structure with geometric parameters of the (i+1)th candidate boundary can be modeled using electromagnetic simulation software, and the modeled chip layout structure can be simulated to obtain the (i+1)th candidate boundary.

[0092] The simulation parameters (e.g., simulation capacitance parameters) corresponding to the i+1 candidate boundary.

[0093] Step S202: Based on the first target boundary and the second target boundary, the target search range of the geometric parameters of the chip layout structure to be designed is obtained.

[0094] Step S203: Based on the target parameters (such as the target capacitance parameters), obtain the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range.

[0095] Step S204: Based on the target values ​​of the geometric parameters, the target chip layout structure is obtained.

[0096] Here, the geometric parameters of the target chip layout structure are taken as target values, and the difference information between the simulation parameters (such as simulation capacitor parameters) and the target parameters (such as target capacitor parameters) corresponding to the target chip layout structure meets the preset difference requirements.

[0097] Thus, this disclosure provides a specific method for obtaining the target search range. This method is simple and efficient, and can quickly obtain the minimum search range. This provides favorable support for the subsequent rapid design of the target values ​​of geometric parameters that can achieve the target parameters.

[0098] Figure 3 This is a flowchart illustrating the layout structure determination method according to embodiments of this disclosure. Figure 3 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any limitations on these applications. It is understood that the above... Figure 1 and Figure 2 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0099] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 3 As shown, the method for determining the layout structure includes:

[0100] Step S301: Based on the target parameters required for the chip layout structure to be designed, obtain the target search range of the geometric parameters of the chip layout structure to be designed.

[0101] Step S302: Using a neural network model, obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed; j is a positive integer greater than or equal to 1.

[0102] Here, the j-th candidate value is obtained based on the target parameter and the target search range.

[0103] It should be noted that the neural network model described in this disclosure can express the relationship between the geometric parameters of the chip layout structure and the target parameters (such as capacitance parameters) of the chip layout structure. For example, this neural network model is obtained by training an improved neural network algorithm.

[0104] It should be noted that this disclosure does not impose specific restrictions on the specific neural network model.

[0105] Furthermore, it should be noted that, theoretically, there is a functional relationship between the geometric parameters of the chip layout structure and the target parameters (such as capacitance parameters) of the chip layout structure. This functional relationship cannot be explicitly expressed by a simple logical expression. Therefore, a neural network model can be trained to fit the functional relationship between the geometric parameters of the chip layout structure and the target parameters (such as capacitance parameters). In this way, the neural network model obtained after training can express the relationship between the geometric parameters of the chip layout structure and the target parameters (such as capacitance parameters).

[0106] In a specific example, the j-th candidate value of the geometric parameters of the chip layout structure to be designed can be obtained using a neural network model (e.g., step S302 mentioned above), specifically including:

[0107] When j is 1, the target parameter (such as the target capacitance parameter) and the target search range are input into the neural network model to obtain the first candidate values ​​of the geometric parameters of the chip layout structure to be designed. At this time, the output of the neural network model is the first candidate value of the geometric parameters of the chip layout structure to be designed. In other words, in the first iteration, the target parameter and the target search range are input into the neural network model. At this time, the neural network model can search for values ​​of geometric parameters that meet (i.e., can achieve) the target parameters within the target search range, thus facilitating the rapid acquisition of the target values ​​of the geometric parameters.

[0108] And / or, when j is a positive integer greater than or equal to 2, the (j-1)th difference information (also known as the (j-1)th distance) between the simulation parameters (such as simulation capacitor parameters) corresponding to the (j-1)th candidate value and the target parameters (such as target capacitor parameters) is input into the neural network model to obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed. At this time, the output of the neural network model is the j-th candidate value of the geometric parameters of the chip layout structure to be designed.

[0109] It should be noted that the simulation parameters (such as simulated capacitor parameters) corresponding to the (j-1)th candidate value are obtained by simulating the chip layout structure with geometric parameters of the (j-1)th candidate value. For example, in one example, an electromagnetic simulation software can be used to model the chip layout structure with geometric parameters of the (j-1)th candidate value, and the modeled chip layout structure can be simulated to obtain the simulation parameters (such as simulated capacitor parameters) corresponding to the (j-1)th candidate value.

[0110] In other words, during the iteration process, if the values ​​of the geometric parameters output by the neural network model in the previous iteration do not meet the requirements (for example, the difference between the simulation parameters corresponding to the geometric parameters output in the previous iteration and the target parameters does not meet the preset difference requirement), the difference information (such as the difference or distance) can be re-inputted into the neural network model. This allows the neural network model to continue its precise search within the target search range based on the difference information, thereby making the simulation parameters corresponding to the geometric parameters output by the neural network model closer to the target parameters. This process is repeated iteratively until the target values ​​of the geometric parameters that meet the target parameters are finally obtained. This optimization iteration process can be called an adaptive process.

[0111] In this way, the disclosed scheme can adaptively adjust the values ​​of geometric parameters, so that the simulation parameters corresponding to the values ​​of geometric parameters output by the neural network model are closer to the target parameters. This enables automated searching to obtain specific values ​​of geometric parameters of the chip layout structure that meet the target parameters (such as the target capacitance parameters). This improves the automation level of chip layout structure design and effectively enhances the accuracy of the results, providing effective support for achieving stable and high-quality quantum computing.

[0112] Step S303: Determine whether the j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter (e.g., determine whether the j-th difference information between the simulation capacitor parameter corresponding to the j-th candidate value and the target capacitor parameter) meets the preset difference requirement. If yes, that is, if the j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter meets the preset difference requirement (e.g., if the j-th difference information between the simulation capacitor parameter corresponding to the j-th candidate value and the target capacitor parameter meets the preset difference requirement), proceed to step S304. If no, that is, if the j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter does not meet the preset difference requirement (e.g., if the j-th difference information between the simulation capacitor parameter corresponding to the j-th candidate value and the target capacitor parameter does not meet the preset difference requirement), use a neural network model to obtain the (j+1)-th candidate value. For example, after j+1, return to step S302 to iterate until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

[0113] In other words, after j+1, return to step S302. In this way, the neural network model is used to obtain the (j+1)th candidate value. For example, the j-th difference information between the simulation parameter and the target parameter corresponding to the j-th candidate value (e.g., the difference between the simulation capacitor parameter and the target capacitor parameter corresponding to the j-th candidate value) is input into the neural network model. At this time, the output of the neural network model is the (j+1)th candidate value of the geometric parameters of the chip layout structure to be designed. This process is repeated until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

[0114] It should be noted that the simulation parameters corresponding to the j-th candidate value (e.g., simulation capacitance parameters) are obtained by simulating the chip layout structure with the j-th candidate value as its geometric parameters. For example, in one example, an electromagnetic simulation software can be used to model the chip layout structure with the j-th candidate value as its geometric parameters, and then the modeled chip layout structure can be simulated to obtain the simulation parameters corresponding to the j-th candidate value.

[0115] It should be noted that the preset difference requirement can be determined according to the accuracy requirements of the chip layout structure. For example, the preset difference requirement is that the difference between the simulation parameters and the target parameters is less than a preset threshold (which can be an empirical value). This disclosed solution does not impose any restrictions on this.

[0116] Step S304: If the difference information between the simulation parameters corresponding to the j-th candidate value and the target parameters meets the preset difference requirements, the j-th candidate value is used as the target value of the geometric parameters of the chip layout structure to be designed.

[0117] Step S305: Based on the target values ​​of the geometric parameters, the target chip layout structure is obtained.

[0118] Here, the geometric parameters of the target chip layout structure are taken as target values, and the difference information between the simulation parameters (such as simulation capacitor parameters) and the target parameters (such as target capacitor parameters) corresponding to the target chip layout structure meets the preset difference requirements.

[0119] In one example, the target chip layout structure includes a QCQ structure with the target geometric parameters, and the QCQ structure with the target geometric parameters can achieve the target parameters, such as the target capacitance parameters.

[0120] Thus, this embodiment of the present disclosure can utilize a neural network model and, based on the target parameters, obtain the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range. Since the neural network model has self-learning capabilities and the ability to quickly find optimal solutions, it can rapidly obtain the target values ​​of the geometric parameters of the chip layout structure to be designed, thereby further improving the design efficiency of the chip layout structure.

[0121] The following detailed explanation of this disclosure is provided with specific examples. This disclosure offers a method for automatically designing quantum chip layouts with coupler architectures (i.e., the chip layout structure described above). Specifically, after determining the target capacitance parameters to be achieved (which can be determined by the characteristic parameters of the coupler-containing qubits (i.e., QCQ structures), the method first estimates the target search range of the geometric parameters of the QCQ structure based on the target capacitance parameters. Then, an adaptive framework and neural network model are applied to the design and development of the quantum chip layout. For example, a neural network model is used to obtain the values ​​of the geometric parameters within the target search range. The QCQ structure (e.g., a quantum chip layout containing QCQ structures) with geometric parameters within the target search range is modeled and simulated. Based on the simulation results and by adjusting the values ​​of the geometric parameters using the adaptive framework, the method automatically searches for specific values ​​of the geometric parameters of the QCQ structure that conform to the target capacitance parameters. Thus, the design of the quantum chip layout is automatically realized. This disclosed solution can significantly improve the design efficiency of chip layout structure and no longer rely on the experience of engineers, which greatly promotes the research and development and iteration efficiency of quantum chip layout.

[0122] It should be noted that the target capacitance parameter required for the quantum chip layout of this disclosure is only an example. In practical applications, it can also be other parameters required for the quantum chip layout during the design phase. As long as the change in geometric parameters can affect other parameters (such as parameters representing external losses, such as the Q value, which represents a parameter type rather than a specific parameter, and the Q value is proportional to the reciprocal of the bandwidth), they can all be applied to this disclosure to design the target value of the geometric parameters that meets the parameter requirements of other parameters.

[0123] The present invention will be described in detail in three parts. The first part briefly introduces the relevant background knowledge of superconducting quantum chips and clarifies the practical problem that the present invention aims to solve. The second part elaborates on the specific content of the present invention, including the process flow and the search grid reduction algorithm. The third part presents practical use cases to verify the effectiveness of the present invention.

[0124] Part 1: Introduction to the architecture of quantum chip layouts containing coupler qubits

[0125] In superconducting quantum chip design, the design of qubits is crucial. Qubit design relates to single-qubit and two-qubit gate operations; therefore, qubit design should include determining the parameters of individual qubits as well as the coupling parameters between qubits. In practical applications, to achieve this design, the industry commonly uses a tunable coupler architecture. This involves placing a frequency-tunable coupler between two qubits. By adjusting the coupler's frequency, the equivalent coupling strength between the two qubits can be turned on and off. The basic unit of this coupling architecture can be called a "qubit-coupler-qubit," or simply a QCQ structure.

[0126] For example, Figure 4 This is a conceptual diagram of a QCQ structure. The cross-shaped structure represents a qubit, and the rectangular structure represents a coupler. In practical applications, the QCQ structure in a superconducting quantum chip is characterized by a series of characteristic parameters, such as the anharmonicity of the qubits and the equivalent coupling strength between qubits. The designer's task is to design the specific structure of the quantum chip layout based on the determined characteristic parameters.

[0127] In one example, the QCQ structure can be composed of a series of metal plates. In this case, the characteristic parameters are determined by the capacitance parameters of the metal plates. Based on this, after giving a set of characteristic parameters, the optimal capacitance parameters that meet the characteristic parameters (i.e., the target capacitance parameters mentioned above) can be obtained.

[0128] Furthermore, the target capacitance parameter is actually determined by the geometric parameters of the QCQ structure. Typically, given the geometric parameters of a QCQ structure, its capacitance parameter can be obtained through simulation. However, conversely, given the target capacitance parameter, designing the specific values ​​of the geometric parameters of the QCQ structure that can achieve the target capacitance parameter is extremely challenging.

[0129] Current solutions require experienced quantum chip designers to manually approximate the target capacitance parameters, a tedious and time-consuming process that doesn't guarantee a feasible solution for micro / nano fabrication. Therefore, finding a specific method to automatically derive the geometric parameters from the target capacitance parameters is crucial.

[0130] It should be noted that this disclosure uses the geometric parameters of the QCQ architecture as an example for illustration. In practical applications, this disclosure can also be applied to the design process of other architectures. In this case, only the corresponding specific parameters need to be adjusted adaptively, which will not be elaborated here.

[0131] Part Two: Overall Process Framework

[0132] This disclosed solution uses a streamlined method (or "program") to automatically find a chip layout structure that meets the target capacitance parameters (i.e., to find the target values ​​of the geometric parameters of the chip layout structure). Users only need to input the target capacitance parameters into the program and let the program iterate to obtain a chip layout structure that meets the target capacitance parameters.

[0133] The procedural method described in this disclosure mainly includes two technical modules: First, an adaptive framework for the entire program (i.e., the overall process). Through iteration, real simulation data provides real-time feedback to the neural network model, making the chip layout structure obtained next time closer to the target capacitance parameters. Here, by improving the neural network algorithm, the neural network model can output a chip layout structure that better matches the target capacitance parameters. For example, the neural network model outputs the values ​​of geometric parameters, and the chip layout structure under these values ​​is closer to the target capacitance parameters. Second, a search grid reduction algorithm. Through iteration, the target search range of geometric parameters is obtained, which facilitates the neural network model to search within the target search range for the target values ​​of geometric parameters that match the target capacitance parameters.

[0134] It should be noted that, for computers, the iterative task of the adaptive framework is carried out in a high-dimensional data grid. However, the high-dimensional data grid is too large, resulting in extremely low execution efficiency of search algorithms for high-dimensional data grids. Therefore, the scheme disclosed in this paper adopts a search grid reduction algorithm to obtain a smaller target search range compared to the high-dimensional data grid. This allows the neural network model to search within the target search range to obtain the target values ​​of geometric parameters that conform to the target capacitance parameters. This improves the execution efficiency of the algorithm and provides effective support for promoting the development of quantum chip layouts and improving iterative efficiency.

[0135] (I) Overall process, such as Figure 5 As shown, the overall implementation steps of this disclosure embodiment include:

[0136] Step S501: Obtain the target capacitance parameters required for the chip layout structure to be designed.

[0137] Here, the chip layout structure to be designed may include at least one QCQ structure; wherein, the QCQ structure includes two qubits (e.g., two adjacent qubits) and a coupler for coupling the two qubits; in practical applications, by adjusting the frequency of the coupler, the equivalent coupling strength between the two qubits can be turned on and / or off. In one example, the QCQ structure may be specifically as described above. Figure 4 The structure shown will not be described in detail here.

[0138] Step S502: Based on the target capacitance parameters required for the chip layout structure to be designed, obtain the target search range for the geometric parameters of the chip layout structure to be designed.

[0139] Here, the target search range represents the range of values ​​for the geometric parameters of the chip layout structure. In practical applications, the values ​​of the geometric parameters of the chip layout structure can affect the capacitance parameters of the chip layout structure. Further, in one example, the target search range can represent the range of values ​​for the geometric parameters of the QCQ structure within the chip layout structure. In this case, the values ​​of the geometric parameters of the QCQ structure within the chip layout structure can affect the capacitance parameters of the QCQ structure within the chip layout structure.

[0140] Step S503: Using a neural network model, obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed.

[0141] Here, the j-th candidate value is obtained based on the target capacitance parameter and the target search range; j is a positive integer greater than or equal to 1.

[0142] It should be noted that the neural network model described in this disclosure can express the relationship between the geometric parameters of the chip layout structure and the capacitance parameters of the chip layout structure. For example, this neural network model is obtained by training an improved neural network algorithm.

[0143] It should be noted that this disclosure does not impose specific restrictions on the specific neural network model.

[0144] Furthermore, it should be noted that, theoretically, there is a functional relationship between the geometric parameters and capacitance parameters of a chip layout structure. This functional relationship cannot be explicitly expressed by a simple logical expression. Therefore, a neural network model can be trained to fit the functional relationship between the geometric parameters and capacitance parameters of the chip layout structure. In this way, the neural network model obtained after training can express the relationship between the geometric parameters and capacitance parameters of the chip layout structure.

[0145] Furthermore, in a specific example, when j is 1, the target capacitance parameter and the target search range can be input into the neural network model to obtain the output of the neural network model. The output of this neural network model is then the first candidate value for the geometric parameters of the chip layout structure to be designed. In other words, during the first iteration, the target capacitance parameter and the target search range are input into the neural network model. This allows the neural network model to search for geometric parameter values ​​that match the target capacitance parameter within the target search range, thus facilitating the rapid acquisition of the target values ​​for the geometric parameters.

[0146] Furthermore, in another specific example, when j is a positive integer greater than or equal to 2, the (j-1)th difference information (also called the (j-1)th distance) between the simulated capacitance parameter corresponding to the (j-1)th candidate value and the target capacitance parameter can be input into the neural network model to obtain the output of the neural network model. In this case, the output of the neural network model is the j-th candidate value of the geometric parameters of the chip layout structure to be designed. That is, during the iteration process, if the value of the geometric parameter output by the neural network model in the previous iteration does not meet the requirements (for example, the difference between the simulated capacitance parameter corresponding to the value of the geometric parameter output in the previous iteration and the target capacitance parameter does not meet the preset difference requirement), the difference information (such as the difference or distance) can be re-input into the neural network model. This allows the neural network model to continue to perform a precise search within the target search range based on the difference information, thereby making the simulated capacitance parameter corresponding to the value of the geometric parameter output by the neural network model closer to the target capacitance parameter. This iteration continues until the target value of the geometric parameter that meets the target capacitance parameter is finally obtained. The above optimization iteration process can be called an adaptive process.

[0147] For example, when j=2, the first difference information between the simulated capacitance parameter corresponding to the first candidate value and the target capacitance parameter can be input into the neural network model. At this time, the output of the neural network model can be used as the second candidate value.

[0148] It should be noted that the simulated capacitance parameter corresponding to the (j-1)th candidate value is obtained by simulating the chip layout structure with geometric parameters of the (j-1)th candidate value. For example, an electromagnetic simulation software can be used to model the chip layout structure with geometric parameters of the (j-1)th candidate value, and then the modeled chip layout structure can be simulated to obtain the simulated capacitance parameter corresponding to the (j-1)th candidate value.

[0149] Step S504: Simulate the chip layout structure with the j-th candidate geometric parameter to obtain the simulated capacitor parameter corresponding to the j-th candidate value.

[0150] For example, electromagnetic simulation software can be used to model the chip layout structure with the j-th candidate geometric parameter, and then the modeled chip layout structure can be simulated to obtain the simulated capacitor parameters corresponding to the j-th candidate value.

[0151] Step S505: Determine whether the j-th difference information between the simulated capacitor parameter corresponding to the j-th candidate value and the target capacitor parameter meets the preset difference requirement; if yes, that is, if the preset difference requirement is met, execute step S506; if no, that is, if the preset difference requirement is not met, process j+1 and return to step S503 to iterate and obtain new candidate values ​​for the geometric parameters.

[0152] In other words, after j+1, return to step S503 to use the neural network model to obtain the (j+1)th candidate value. For example, input the j-th difference information (e.g., the difference between the simulated capacitor parameter and the target capacitor parameter corresponding to the j-th candidate value) into the neural network model to obtain the (j+1)th candidate value. Repeat this process until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

[0153] Here, the preset difference requirement can be determined according to the accuracy requirements of the chip layout structure. For example, the preset difference requirement is that the difference between the simulated capacitor parameter and the target capacitor parameter is less than a preset threshold (which can be an empirical value). This disclosed solution does not impose any restrictions on this.

[0154] Step S506: The j-th candidate value is used as the target value for the geometric parameters of the chip layout structure to be designed. Proceed to step S507.

[0155] Step S507 yields the target chip layout structure with the target geometric parameters.

[0156] In one example, a target chip layout structure can be output based on the target value; the target chip layout structure includes a QCQ structure with geometric parameters equal to the target value.

[0157] It should be noted that the target capacitance parameters described in this disclosure can specifically be a set of capacitance parameter values ​​required to achieve the QCQ structure, such as, but not limited to: the self-capacitance of the qubit, the self-capacitance of the coupler, the mutual capacitance between qubits, and the mutual capacitance between the coupler and the qubit. Correspondingly, the geometric parameters of the chip layout structure can also be a set of structural parameters representing the QCQ structure, such as, but not limited to: the length of the metal arm of the qubit, the width of the metal arm of the qubit, the distance between the centers of the qubits, the closest distance between the qubit and the coupler, the length of the coupler, and the width of the coupler rod. Furthermore, this disclosure does not limit the specific parameters included in the target capacitance parameters or the specific parameters included in the geometric parameters. In other words, this disclosure is applicable to any scenario where the target capacitance parameters to be achieved are known and the geometric parameters of the chip layout structure need to be designed automatically.

[0158] Furthermore, in one example, the number of capacitance parameter values ​​included in the target capacitance parameters of the chip layout structure to be designed is less than the number of structural parameters included in the geometric parameters of the chip layout structure. In this scenario, predicting the geometric parameters of a chip layout structure using a neural network model is essentially a prediction process from low-dimensional data to high-dimensional data. Neural network models often cannot fit this data well (this can be described as information loss). To address this issue, this disclosure simulates a chip layout structure with geometric parameters that are the values ​​output by the neural network model (e.g., the j-th candidate value), and obtains the corresponding simulated capacitance parameters (e.g., for the case where the geometric parameters output by the network model are the j-th candidate value, simulation can obtain the simulated capacitance parameters corresponding to the j-th candidate value). Then, based on the simulated capacitance parameters obtained from the simulation, fine-tuning is performed. For example, if the j-th difference between the simulated capacitance parameters corresponding to the j-th candidate value and the target capacitance parameters does not meet the preset difference requirements, the j-th difference information is input into the neural network model for timely feedback. This feedback mechanism effectively compensates for information loss, making the simulated capacitance parameters corresponding to the (j+1)-th candidate value predicted by the neural network model closer to the target capacitance parameters.

[0159] Furthermore, it should be noted that when the target capacitance parameters can be specifically a set of capacitance parameter values ​​required to achieve the QCQ structure, a precision list can be set based on each capacitance parameter value included in the target capacitance parameters. This precision list contains the precision requirements corresponding to each capacitance parameter value. Accordingly, the aforementioned preset difference requirement can be specifically defined as each simulated value included in the simulated capacitance parameters meeting the precision requirements indicated by the precision list. In other words, after all simulated values ​​in the simulated capacitance parameters corresponding to the candidate values ​​of the geometric parameters predicted by the neural network model meet the precision requirements indicated by the precision list, the iteration can be terminated, and the target values ​​of the geometric parameters of the chip layout structure to be designed can be obtained.

[0160] Furthermore, in one example, the geometric parameters output by the neural network model take a set of specific values, that is, a set of candidate values. Alternatively, multiple sets of candidate values ​​can be output. In this case, the designer can select a set of candidate values ​​from the multiple sets of output candidate values ​​as the target values ​​of the geometric parameters of the chip layout structure to be designed.

[0161] (ii) Search grid reduction algorithm, which is the specific steps of obtaining the target search range of the geometric parameters of the chip layout structure to be designed based on the target capacitance parameters required by the chip layout structure to be designed (i.e., the steps of step S502 mentioned above).

[0162] Here, the purpose of the search grid reduction algorithm is to obtain the minimum search boundary of the geometric parameters of the chip layout structure to be designed, that is, to obtain the first target boundary (the simulated capacitance parameter corresponding to the first target boundary is less than the target capacitance parameter) and the second target boundary (the simulated capacitance parameter corresponding to the second target boundary is greater than the target capacitance parameter), and then to obtain the minimum search range of the geometric parameters of the chip layout structure to be designed (that is, the target search range mentioned above, which can be specifically [first target boundary, second target boundary]). In this way, it is convenient for the neural network model to make predictions within a smaller search range, so as to quickly predict the target values ​​of the geometric parameters.

[0163] Specifically, such as Figure 6 As shown, the specific steps of the search grid reduction algorithm are as follows:

[0164] Step S601: Initialize; for example, randomly generate a first layout and a second layout of the chip layout structure that can achieve the target capacitance parameters, and use the values ​​of the geometric parameters of the first layout and the second layout as candidate boundaries for initialization. For example, the values ​​of the geometric parameters of the first layout can be used as the 0th candidate boundary, and the values ​​of the geometric parameters of the second layout can be used as the 1st candidate boundary.

[0165] Step S602: Simulate the first layout to obtain the simulated capacitance parameters corresponding to the 0th candidate boundary; and simulate the second layout to obtain the simulated capacitance parameters corresponding to the 1st candidate boundary.

[0166] In one example, electromagnetic simulation software can be used to simulate the first layout to obtain the simulated capacitance parameters corresponding to the 0th candidate boundary. Similarly, electromagnetic simulation software can be used to simulate the second layout to obtain the simulated capacitance parameters corresponding to the 1st candidate boundary.

[0167] After executing steps S601 and S602, the i-th range reduction process begins; here, i is a positive integer greater than or equal to 1, and the i-th range reduction process includes:

[0168] Step S603: Execute the range reduction process (also known as the iterative process of the grid reduction algorithm) to obtain the target search range.

[0169] The i-th range reduction process includes:

[0170] Step S603-1: Obtain the i-th slope.

[0171] In one example, the i-th slope is obtained based on the simulated capacitance parameters corresponding to the (i-1)-th and (i-1)-th candidate boundaries, as well as the simulated capacitance parameters corresponding to the i-th and i-th candidate boundaries. For instance, the (i-1)-th and i-th candidate boundaries can be used as input values ​​to a vector function, and correspondingly, the simulated capacitance parameters corresponding to the (i-1)-th and i-th candidate boundaries can be used as output values ​​to the vector function. In this case, the i-th slope can be obtained by solving the vector function.

[0172] It should be noted that the simulated capacitance parameter corresponding to the i-th candidate boundary is smaller than the target capacitance parameter.

[0173] Furthermore, in one example, electromagnetic simulation software can be used to model the chip layout structure with geometric parameters of the (i-1)th candidate boundary, and the modeled chip layout structure can be simulated to obtain the simulated capacitance parameters corresponding to the (i-1)th candidate boundary. Similarly, electromagnetic simulation software can be used to model the chip layout structure with geometric parameters of the ith candidate boundary, and the modeled chip layout structure can be simulated to obtain the simulated capacitance parameters corresponding to the ith candidate boundary.

[0174] Step S603-2: Obtain the i-th difference between the simulated capacitance parameter and the target capacitance parameter corresponding to the i-th candidate boundary.

[0175] Step S603-3: The ratio of the i-th difference to the i-th slope is taken as the i-th step size.

[0176] Step S603-4: Based on the i-th step length, obtain the (i+1)-th candidate boundary.

[0177] In one example, the sum of the i-th candidate boundary and the i-th step size can be used as the (i+1)-th candidate boundary.

[0178] Step S603-5: Simulate the chip layout structure with geometric parameters of the (i+1)th candidate boundary to obtain the simulated capacitance parameters corresponding to the (i+1)th candidate boundary.

[0179] In one example, electromagnetic simulation software can be used to model the chip layout structure with geometric parameters of the (i+1)th candidate boundary, and the modeled chip layout structure can be simulated to obtain the simulated capacitance parameters corresponding to the (i+1)th candidate boundary.

[0180] Step S603-6: Determine whether the simulated capacitance parameter corresponding to the (i+1)th candidate boundary is greater than the target capacitance parameter. If yes, that is, if the simulated parameter corresponding to the (i+1)th candidate boundary is greater than the target parameter, execute step S603-7. If no, that is, if the simulated parameter corresponding to the (i+1)th candidate boundary is less than or equal to the target parameter, enter the (i+1)th range reduction process. For example, after i+1, return to step S603-1. Repeat this process until the first target boundary of the geometric parameters of the chip layout structure to be designed and the second target boundary of the geometric parameters of the chip layout structure to be designed are obtained.

[0181] Step S603-7: The i-th candidate boundary is used as the first target boundary of the geometric parameters of the chip layout structure to be designed, and the (i+1)-th candidate boundary is used as the second target boundary of the geometric parameters of the chip layout structure to be designed. Based on the first target boundary and the second target boundary, the target search range of the geometric parameters of the chip layout structure to be designed is obtained.

[0182] In other words, in this disclosed scheme, when the simulated capacitance parameter corresponding to the i-th candidate boundary is less than the target capacitance parameter, and the simulated capacitance parameter corresponding to the (i+1)-th candidate boundary is greater than the target capacitance parameter, the i-th candidate boundary is used as the first target boundary for the geometric parameters of the chip layout structure to be designed, and the (i+1)-th candidate boundary is used as the second target boundary for the geometric parameters of the chip layout structure to be designed. This results in a smaller target search range, thus providing support for quickly estimating the target values ​​of the geometric parameters.

[0183] Part Three: Validation

[0184] This section uses the design of an actual quantum chip layout as an example to illustrate the effectiveness of the disclosed solution.

[0185] First, the coupled qubit (QCQ structure) is modeled, for example, by parameterization, to represent the chip layout structure mathematically. This facilitates adaptive modifications to the chip layout. In this example, the configuration of the QCQ structure is as follows: Figure 7 As shown, the cross-shaped structure represents a qubit, and the double-arrow structure represents a coupler. For design simplicity, this example assumes the two qubits have identical structures, with the coupler located between them. In this case, the geometric parameters of the QCQ structure can include 10, namely:

[0186] (1) Geometric parameters of qubit: arm length of qubit (labeled 1, which can be denoted as ql), arm width of qubit (labeled 2, which can be denoted as qw), and distance between qubit and ground metal (labeled 3, which can be denoted as qs).

[0187] (2) Geometric parameters of the coupler: the length of the arrow section (label 4, which can be denoted as cl1), the width of the arrow section (label 5, which can be denoted as cw1), the distance between the arrow section and the ground metal (label 6, which can be denoted as cs1), the width of the coupler rod (label 7, which can be denoted as cw2), the distance between the coupler rod and the ground metal (label 8, which can be denoted as cs2), and the length of the entire coupler (label 9, which can be denoted as cl2).

[0188] (3) Geometric parameters between two qubits: the distance between two qubits (labeled 10, which can be denoted as qqd).

[0189] Furthermore, in this example, the target capacitance parameters of the QCQ structure may include four: the self-capacitance of the qubit, the self-capacitance of the coupler, the mutual capacitance between the two qubits, and the mutual capacitance between the qubit and the coupler.

[0190] Furthermore, a set of target capacitor parameters required for the QCQ structure in the chip layout are given in Table 1, including four target capacitor values.

[0191] Table 1

[0192]

[0193] In this example, the four target capacitance values ​​shown in Table 1 are used as a list of target capacitance parameters and as input to the present invention. At the same time, electromagnetic simulation software is called to predict multiple sets of candidate values ​​for the geometric parameters of the QCQ structure, as shown in Tables 2a and 2b.

[0194] In this example, sapphire can be selected as the substrate for modeling the chip layout structure in electromagnetic simulation software. The substrate thickness can be set to 400 micrometers (µm), and the relative permittivity can be set to 10.75. It is worth emphasizing that, using this disclosed solution, the design parameters of the quantum chip layout can also be freely constrained in the electromagnetic simulation software. For example, the design goal can be constrained to long-distance qubits, thus allowing the entire chip layout structure to have a wider wiring space. In this case, the distance parameters between qubits can be constrained, such as requiring the distance between two adjacent qubits to be greater than 800µm. It is understood that designers can add other physical constraints according to personalized design requirements, and this disclosed solution does not impose any restrictions on this.

[0195] Table 2a

[0196]

[0197] Table 2b

[0198]

[0199]

[0200] Here, Tables 2a and 2b give three sets of candidate values ​​for the geometric parameters of the QCQ structure. At this time, one set can be randomly selected for electromagnetic simulation verification. For example, the first set of candidate values ​​can be selected for simulation verification, and the simulation capacitor parameters are shown in Table 3.

[0201] Table 3

[0202]

[0203] As shown in Table 1, the simulated capacitor parameters of the QCQ structure in the chip layout generated by the automated program of this disclosure (the simulated capacitor parameters corresponding to the first group of candidate values) are very close to the design values ​​(i.e., the target capacitor parameters that the QCQ structure in the chip layout needs to achieve), and the difference between the two meets the preset difference requirements. Electromagnetic simulation verification shows that the simulated capacitor parameters corresponding to the second and third groups of candidate values ​​are also very close to the design values.

[0204] In practical applications, if the development process is strictly followed according to the disclosed scheme, an automated program for designing quantum bit architectures with couplers will be obtained.

[0205] In summary, this disclosure proposes a method for automating the design of chip layout structures with couplers, which can significantly improve the design efficiency of chip layout structures and no longer rely on the experience of engineers, thus greatly promoting the research and development and iteration efficiency of quantum chip layouts.

[0206] Furthermore, this disclosed solution is applicable to the mapping from geometric parameters to capacitance parameters in any quantum chip field; only appropriate adjustments to the process are needed for specific tasks. Therefore, it has a wide range of applications. Simultaneously, this disclosed solution also offers the following advantages:

[0207] (1) High degree of automation, minimizing manual operation. Users only need to develop the program according to the process given in this disclosure. Once developed, designers only need to input the corresponding target capacitance parameters when designing the QCQ structure, which greatly reduces manual operation and brings important value to the automation of subsequent quantum chip design.

[0208] (2) It has a more significant advantage in the design of complex chip layout structures. For example, for the highly challenging floating qubit-floating coupler-floating qubit configuration, the number of capacitance parameters included in the target capacitance parameters and the number of structural parameters included in the geometric parameters are very large. If manual debugging is used, it is very difficult. However, the target values ​​of the geometric parameters can be obtained accurately and efficiently using the scheme disclosed in this paper, thus greatly improving the design efficiency.

[0209] (3) High degree of design freedom. Manual debugging can only solve for one set of candidate values ​​for geometric parameters at a time, while the scheme disclosed in this paper can easily obtain multiple sets of candidate values ​​for geometric parameters. In this way, greater freedom can be provided for constraints and limitations in micro-nano and measurement and control.

[0210] This disclosure also provides a layout structure determination device, such as... Figure 8 As shown, it includes:

[0211] The first acquisition unit 801 is used to obtain the target search range of the geometric parameters of the chip layout structure to be designed based on the target parameters required for the chip layout structure to be designed; wherein, the target search range represents the value range of the geometric parameters of the chip layout structure to be designed; the value of the geometric parameters can affect the target parameters of the chip layout structure.

[0212] Search unit 802 is used to obtain target values ​​of geometric parameters of the chip layout structure to be designed within the target search range based on the target parameters.

[0213] The second acquisition unit 803 is used to obtain a target chip layout structure based on the target values ​​of geometric parameters; wherein, the values ​​of the geometric parameters in the target chip layout structure are the target values, and the difference information between the simulation parameters corresponding to the target chip layout structure and the target parameters meets the preset difference requirements.

[0214] In a specific example of the disclosed solution, the first acquisition unit 801 is specifically used for:

[0215] A first target boundary and a second target boundary for the geometric parameters of the chip layout structure to be designed are obtained; wherein, the simulation parameter corresponding to the first target boundary is smaller than the target parameter; the simulation parameter corresponding to the first target boundary is obtained by simulating the chip layout structure with the geometric parameters of the first target boundary; the simulation parameter corresponding to the second target boundary is larger than the target parameter; the simulation parameter corresponding to the second target boundary is obtained by simulating the chip layout structure with the geometric parameters of the second target boundary.

[0216] Based on the first target boundary and the second target boundary, the target search range of the geometric parameters of the chip layout structure to be designed is obtained.

[0217] In a specific example of the disclosed solution, the first acquisition unit 801 is specifically used for:

[0218] Execute the i-th range reduction process; wherein, the i-th range reduction process includes:

[0219] The i-th step size is obtained; wherein the i-th step size is related to the i-th candidate boundary; the simulation parameter corresponding to the i-th candidate boundary is less than the target parameter; the simulation parameter corresponding to the i-th candidate boundary is obtained by simulating the chip layout structure with the geometric parameters of the i-th candidate boundary; and i is a positive integer greater than or equal to 1.

[0220] Based on the i-th step size, the (i+1)-th candidate boundary is obtained;

[0221] If the simulation parameters corresponding to the (i+1)th candidate boundary are greater than the target parameters, the i-th candidate boundary is taken as the first target boundary of the geometric parameters of the chip layout structure to be designed, and the (i+1)-th candidate boundary is taken as the second target boundary of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (i+1)-th candidate boundary are obtained by simulating the chip layout structure with the geometric parameters of the (i+1)-th candidate boundary.

[0222] In a specific example of the disclosed solution, the first acquisition unit 801 is specifically used for:

[0223] If the simulation parameters corresponding to the (i+1)th candidate boundary are less than or equal to the target parameters, the (i+1)th range reduction process is entered until the first target boundary of the geometric parameters of the chip layout structure to be designed and the second target boundary of the geometric parameters of the chip layout structure to be designed are obtained.

[0224] In a specific example of the disclosed solution, the first acquisition unit 801 is specifically used for:

[0225] Based on the (i-1)th candidate boundary and the simulation parameters corresponding to the (i-1)th candidate boundary, and the ith candidate boundary and the simulation parameters corresponding to the ith candidate boundary, the ith step size is obtained.

[0226] In a specific example of the disclosed solution, the first acquisition unit 801 is specifically used for:

[0227] The i-th slope is obtained; wherein the i-th slope is obtained based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, and the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary.

[0228] The i-th difference between the simulation parameters corresponding to the i-th candidate boundary and the target parameters is obtained;

[0229] The ratio of the i-th difference to the i-th slope is taken as the i-th step size.

[0230] In a specific example of the disclosed solution, the search unit 802 is specifically used for:

[0231] Using a neural network model, the j-th candidate value of the geometric parameters of the chip layout structure to be designed is obtained, wherein the j-th candidate value is obtained based on the target parameters and the target search range; and j is a positive integer greater than or equal to 1.

[0232] If the difference between the simulation parameter corresponding to the j-th candidate value and the target parameter satisfies a preset difference requirement, the j-th candidate value is used as the target value of the geometric parameter of the chip layout structure to be designed; wherein, the simulation parameter corresponding to the j-th candidate value is obtained by simulating the chip layout structure with the j-th candidate value as the geometric parameter.

[0233] In a specific example of the scheme disclosed herein, the search unit 802 is further configured to:

[0234] If the difference between the simulation parameters corresponding to the j-th candidate value and the target parameter does not meet the preset difference requirement, a neural network model is used to obtain the (j+1)-th candidate value, until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

[0235] In a specific example of the disclosed solution, the search unit 802 is specifically used for:

[0236] The j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter is input into the neural network model to obtain the (j+1)-th candidate value.

[0237] In a specific example of the disclosed solution, the search unit 802 is specifically used for:

[0238] When j is 1, the target parameter and the target search range are input into the neural network model to obtain the first candidate value of the geometric parameter of the chip layout structure to be designed;

[0239] And / or,

[0240] When j is a positive integer greater than or equal to 2, the (j-1)th difference information between the simulation parameters corresponding to the (j-1)th candidate value and the target parameter is input into the neural network model to obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (j-1)th candidate value are obtained by simulating the chip layout structure with the geometric parameters of the (j-1)th candidate value.

[0241] In a specific example of the scheme disclosed herein, the chip layout structure to be designed includes at least one QCQ structure; wherein, the QCQ structure includes two qubits and a coupler for coupling the two qubits.

[0242] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.

[0243] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above using a quantum computing device.

[0244] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described above for use in classical computing devices.

[0245] Alternatively, the computer program, when executed by at least one quantum processing unit, implements the method applied to a quantum computing device.

[0246] This disclosure also provides a quantum computing device, the quantum computing device comprising:

[0247] At least one quantum processing unit;

[0248] A memory, coupled to the at least one QPU and used to store executable instructions,

[0249] The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

[0250] It is understood that the quantum processing unit (QPU) used in the present disclosure may also be referred to as a quantum processor or quantum chip, and may involve a physical chip comprising multiple qubits interconnected in a specific manner.

[0251] Furthermore, it is understood that the qubit described in this disclosure can refer to the basic information unit of a quantum computing device. The qubit is contained within the QPU and extends the concept of the classical digital bit.

[0252] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0253] Figure 9 A schematic block diagram of an example computing device 900 that can be used to implement embodiments of the present disclosure is shown. The computing device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0254] like Figure 9 As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 902 or a computer program loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0255] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0256] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the layout determination method. For example, in some embodiments, the layout determination method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the layout determination method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the layout determination method by any other suitable means (e.g., by means of firmware).

[0257] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0258] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0259] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0260] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0261] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0262] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0263] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0264] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for determining layout structure, comprising: Based on the target parameters required for the chip layout structure to be designed, the target search range of the geometric parameters of the chip layout structure to be designed is obtained; wherein, the target search range represents the value range of the geometric parameters of the chip layout structure to be designed; the value of the geometric parameters can affect the target parameters of the chip layout structure; Based on the target parameters, the target values ​​of the geometric parameters of the chip layout structure to be designed are obtained within the target search range; Based on the target values ​​of the geometric parameters, the target chip layout structure is obtained; wherein, the geometric parameters of the target chip layout structure are the target values, and the difference information between the simulation parameters corresponding to the target chip layout structure and the target parameters meets the preset difference requirements; The target search range for obtaining the geometric parameters of the chip layout structure to be designed, based on the target parameters required for the chip layout structure to be designed, includes: A first target boundary and a second target boundary for the geometric parameters of the chip layout structure to be designed are obtained; wherein, the simulation parameter corresponding to the first target boundary is smaller than the target parameter; the simulation parameter corresponding to the first target boundary is obtained by simulating the chip layout structure with the geometric parameters of the first target boundary; the simulation parameter corresponding to the second target boundary is larger than the target parameter; the simulation parameter corresponding to the second target boundary is obtained by simulating the chip layout structure with the geometric parameters of the second target boundary. Based on the first target boundary and the second target boundary, the target search range of the geometric parameters of the chip layout structure to be designed is obtained.

2. The method according to claim 1, wherein, The first target boundary for obtaining the geometric parameters of the chip layout structure to be designed, and the second target boundary for obtaining the geometric parameters of the chip layout structure to be designed, include: Execute the i-th range reduction process; wherein, the i-th range reduction process includes: The i-th step size is obtained; wherein the i-th step size is related to the i-th candidate boundary; the simulation parameter corresponding to the i-th candidate boundary is less than the target parameter; the simulation parameter corresponding to the i-th candidate boundary is obtained by simulating the chip layout structure with the geometric parameters of the i-th candidate boundary; and i is a positive integer greater than or equal to 1. Based on the i-th step size, the (i+1)-th candidate boundary is obtained; If the simulation parameters corresponding to the (i+1)th candidate boundary are greater than the target parameters, the i-th candidate boundary is taken as the first target boundary of the geometric parameters of the chip layout structure to be designed, and the (i+1)-th candidate boundary is taken as the second target boundary of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (i+1)-th candidate boundary are obtained by simulating the chip layout structure with the geometric parameters of the (i+1)-th candidate boundary.

3. The method according to claim 2, wherein, The i-th range reduction process also includes: If the simulation parameters corresponding to the (i+1)th candidate boundary are less than or equal to the target parameters, the (i+1)th range reduction process is entered until the first target boundary of the geometric parameters of the chip layout structure to be designed and the second target boundary of the geometric parameters of the chip layout structure to be designed are obtained.

4. The method according to claim 2, wherein, Obtaining the i-th step length includes: Based on the (i-1)th candidate boundary and the simulation parameters corresponding to the (i-1)th candidate boundary, and the ith candidate boundary and the simulation parameters corresponding to the ith candidate boundary, the ith step size is obtained.

5. The method according to claim 4, wherein, The step size is obtained based on the (i-1)th candidate boundary and the simulation parameters corresponding to the (i-1)th candidate boundary, and the ith candidate boundary and the simulation parameters corresponding to the ith candidate boundary, including: The i-th slope is obtained; wherein the i-th slope is obtained based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, and the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary. The i-th difference between the simulation parameters corresponding to the i-th candidate boundary and the target parameters is obtained; The ratio of the i-th difference to the i-th slope is taken as the i-th step size.

6. The method according to any one of claims 1-5, wherein, The step of obtaining the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range based on the target parameters includes: Using a neural network model, the j-th candidate value of the geometric parameters of the chip layout structure to be designed is obtained, wherein the j-th candidate value is obtained based on the target parameters and the target search range; and j is a positive integer greater than or equal to 1. If the difference between the simulation parameter corresponding to the j-th candidate value and the target parameter satisfies a preset difference requirement, the j-th candidate value is used as the target value of the geometric parameter of the chip layout structure to be designed; wherein, the simulation parameter corresponding to the j-th candidate value is obtained by simulating the chip layout structure with the j-th candidate value as the geometric parameter.

7. The method according to claim 6, further comprising: If the difference between the simulation parameters corresponding to the j-th candidate value and the target parameter does not meet the preset difference requirement, a neural network model is used to obtain the (j+1)-th candidate value, until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

8. The method according to claim 7, wherein, The process of using a neural network model to obtain the (j+1)th candidate value to be designed includes: The j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter is input into the neural network model to obtain the (j+1)-th candidate value.

9. The method according to claim 6, wherein, The process of using a neural network model to obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed includes: When j is 1, the target parameter and the target search range are input into the neural network model to obtain the first candidate value of the geometric parameter of the chip layout structure to be designed; And / or, When j is a positive integer greater than or equal to 2, the (j-1)th difference information between the simulation parameters corresponding to the (j-1)th candidate value and the target parameter is input into the neural network model to obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (j-1)th candidate value are obtained by simulating the chip layout structure with the geometric parameters of the (j-1)th candidate value.

10. The method according to any one of claims 1-5, wherein, The chip layout structure to be designed includes at least one QCQ structure; wherein the QCQ structure includes two qubits and a coupler for coupling the two qubits.

11. A layout structure determining device, comprising: The first acquisition unit is used to obtain the target search range of the geometric parameters of the chip layout structure to be designed based on the target parameters required for the chip layout structure to be designed; wherein, the target search range represents the value range of the geometric parameters of the chip layout structure to be designed; the value of the geometric parameters can affect the target parameters of the chip layout structure; The search unit is used to obtain the target values ​​of the geometric parameters of the chip layout structure to be designed within the target search range based on the target parameters. The second acquisition unit is used to obtain a target chip layout structure based on the target values ​​of geometric parameters; wherein, the geometric parameters of the target chip layout structure are the target values, and the difference information between the simulation parameters corresponding to the target chip layout structure and the target parameters meets a preset difference requirement; The first acquisition unit is specifically used for: A first target boundary and a second target boundary for the geometric parameters of the chip layout structure to be designed are obtained; wherein, the simulation parameter corresponding to the first target boundary is smaller than the target parameter; the simulation parameter corresponding to the first target boundary is obtained by simulating the chip layout structure with the geometric parameters of the first target boundary; the simulation parameter corresponding to the second target boundary is larger than the target parameter; the simulation parameter corresponding to the second target boundary is obtained by simulating the chip layout structure with the geometric parameters of the second target boundary. Based on the first target boundary and the second target boundary, the target search range of the geometric parameters of the chip layout structure to be designed is obtained.

12. The apparatus according to claim 11, wherein, The first acquisition unit is specifically used for: Execute the i-th range reduction process; wherein, the i-th range reduction process includes: The i-th step size is obtained; wherein the i-th step size is related to the i-th candidate boundary; the simulation parameter corresponding to the i-th candidate boundary is less than the target parameter; the simulation parameter corresponding to the i-th candidate boundary is obtained by simulating the chip layout structure with the geometric parameters of the i-th candidate boundary; and i is a positive integer greater than or equal to 1. Based on the i-th step size, the (i+1)-th candidate boundary is obtained; If the simulation parameters corresponding to the (i+1)th candidate boundary are greater than the target parameters, the i-th candidate boundary is taken as the first target boundary of the geometric parameters of the chip layout structure to be designed, and the (i+1)-th candidate boundary is taken as the second target boundary of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (i+1)-th candidate boundary are obtained by simulating the chip layout structure with the geometric parameters of the (i+1)-th candidate boundary.

13. The apparatus according to claim 12, wherein, The first acquisition unit is specifically used for: If the simulation parameters corresponding to the (i+1)th candidate boundary are less than or equal to the target parameters, the (i+1)th range reduction process is entered until the first target boundary of the geometric parameters of the chip layout structure to be designed and the second target boundary of the geometric parameters of the chip layout structure to be designed are obtained.

14. The apparatus according to claim 12, wherein, The first acquisition unit is specifically used for: Based on the (i-1)th candidate boundary and the simulation parameters corresponding to the (i-1)th candidate boundary, and the ith candidate boundary and the simulation parameters corresponding to the ith candidate boundary, the ith step size is obtained.

15. The apparatus according to claim 14, wherein, The first acquisition unit is specifically used for: The i-th slope is obtained; wherein the i-th slope is obtained based on the simulation parameters corresponding to the (i-1)-th candidate boundary and the (i-1)-th candidate boundary, and the simulation parameters corresponding to the i-th candidate boundary and the i-th candidate boundary. The i-th difference between the simulation parameters corresponding to the i-th candidate boundary and the target parameters is obtained; The ratio of the i-th difference to the i-th slope is taken as the i-th step size.

16. The apparatus according to any one of claims 11-15, wherein, The search unit is specifically used for: Using a neural network model, the j-th candidate value of the geometric parameters of the chip layout structure to be designed is obtained, wherein the j-th candidate value is obtained based on the target parameters and the target search range; and j is a positive integer greater than or equal to 1. If the difference between the simulation parameter corresponding to the j-th candidate value and the target parameter satisfies a preset difference requirement, the j-th candidate value is used as the target value of the geometric parameter of the chip layout structure to be designed; wherein, the simulation parameter corresponding to the j-th candidate value is obtained by simulating the chip layout structure with the j-th candidate value as the geometric parameter.

17. The apparatus according to claim 16, wherein, The search unit is also used for: If the difference between the simulation parameters corresponding to the j-th candidate value and the target parameter does not meet the preset difference requirement, a neural network model is used to obtain the (j+1)-th candidate value, until the target value of the geometric parameters of the chip layout structure to be designed is obtained.

18. The apparatus according to claim 17, wherein, The search unit is specifically used for: The j-th difference information between the simulation parameter corresponding to the j-th candidate value and the target parameter is input into the neural network model to obtain the (j+1)-th candidate value.

19. The apparatus according to claim 16, wherein, The search unit is specifically used for: When j is 1, the target parameter and the target search range are input into the neural network model to obtain the first candidate value of the geometric parameter of the chip layout structure to be designed; And / or, When j is a positive integer greater than or equal to 2, the (j-1)th difference information between the simulation parameters corresponding to the (j-1)th candidate value and the target parameter is input into the neural network model to obtain the j-th candidate value of the geometric parameters of the chip layout structure to be designed; wherein, the simulation parameters corresponding to the (j-1)th candidate value are obtained by simulating the chip layout structure with the geometric parameters of the (j-1)th candidate value.

20. The apparatus according to any one of claims 11-15, wherein, The chip layout structure to be designed includes at least one QCQ structure; wherein the QCQ structure includes two qubits and a coupler for coupling the two qubits.

21. A computing device, comprising: At least one quantum processing unit (QPU); A memory, coupled to the at least one QPU and used to store executable instructions, The instructions are executed by the at least one QPU to enable the at least one QPU to perform the method of any one of claims 1-10; Or, including: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of any one of claims 1-10.

22. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, When at least one quantum processing unit is executed, the computer instructions cause the at least one quantum processing unit to perform the method according to any one of claims 1-10; Alternatively, the computer instructions are used to cause the computer to perform the method according to any one of claims 1-10.

23. A computer program product comprising a computer program that, when executed by at least one quantum processing unit, implements the method according to any one of claims 1-10; Alternatively, the computer program may, when executed by a processor, implement the method according to any one of claims 1-10.

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