Array substrate and preparation method thereof

Abstract

An embodiment of the present application discloses an array substrate and a preparation method thereof, wherein the array substrate includes a substrate, a gate layer, a source / drain layer, a first passivation layer, a common electrode layer, a second passivation layer, and a pixel electrode layer. The array substrate also includes a plurality of vias that are arranged at least through the second passivation layer, and any via includes a deep hole area and a shallow hole area. The vias in the deep hole area are arranged through the second passivation layer and the first passivation layer, and the vias in the shallow hole area are arranged through the second passivation layer. In the deep hole area, the pixel electrode is connected to the drain electrode, and in the shallow hole area, the common electrode layer is electrically connected to the compensation electrode through the first connecting electrode and the second connecting electrode. By realizing not only the connection between the pixel electrode and the drain electrode but also the connection between the common electrode layer and the compensation electrode of the first metal layer in one via hole, the number of vias is reduced and the aperture ratio is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a method for preparing the same. Background Art

[0002] See also Figure 1 In the IGZO HFS display mode of LCD, a large area of ​​common electrode layer 80 is provided, resulting in a large resistance of the common electrode layer 80, which easily causes uneven signals in the common electrode layer 80, and thus causes display abnormalities. This abnormality is particularly obvious in products with high refresh rates and high resolutions. To solve this problem, the current main solution is to adopt the M1 COM solution. The M1 COM solution adds a compensation electrode 202 to the gate layer 20, and uses the compensation electrode 202 to connect to the common electrode layer 80, thereby reducing the impedance and voltage drop of the common electrode layer 80. Since the number of vias is increased in this solution to achieve the connection between the common electrode layer and the compensation electrode, that is, Figure 1 As shown, there are multiple vias penetrating the passivation layer, which are used to connect the common electrode layer and the compensation electrode, and the pixel electrode and the drain. The vias have a minimum size due to the limitation of process precision, so the increase in the number of vias will result in a decrease in the aperture ratio.

[0003] Therefore, the existing array substrate has a technical problem of a large number of via holes leading to a low aperture ratio. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a method for manufacturing the same, which can alleviate the technical problem of a large number of via holes in existing array substrates resulting in a low aperture ratio.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a gate layer, the gate layer being disposed above the substrate, the gate layer comprising a gate and a compensation electrode;

[0008] a source-drain electrode layer, the source-drain electrode layer being arranged on a side of the gate layer away from the substrate, the source-drain electrode layer comprising a source electrode, a drain electrode, and a first connecting electrode;

[0009] a first passivation layer, the first passivation layer being disposed on a side of the source and drain electrode layer away from the substrate;

[0010] a common electrode layer, the common electrode layer being disposed on a side of the first passivation layer away from the substrate;

[0011] a second passivation layer, the second passivation layer being disposed on a side of the common electrode layer away from the substrate;

[0012] a pixel electrode layer, the pixel electrode layer being disposed on a side of the second passivation layer away from the substrate, the pixel electrode layer comprising a pixel electrode and a second connecting electrode;

[0013] In which, the array substrate also includes a plurality of via holes set at least through the second passivation layer, and any of the via holes includes a deep hole area and a shallow hole area. The via holes in the deep hole area are set through the second passivation layer and the first passivation layer, and the via holes in the shallow hole area are set through the second passivation layer. In the deep hole area, the pixel electrode is connected to the drain electrode, and in the shallow hole area, the common electrode layer is electrically connected to the compensation electrode through the first connecting electrode and the second connecting electrode.

[0014] Optionally, in some embodiments of the present application, an active layer is arranged on a side of the gate layer away from the substrate, the active layer includes an active pattern and a semiconductor pattern, the active pattern is connected to the source and the drain, the drain and the first connecting electrode are spaced apart to form a spacing area, and the semiconductor pattern at least covers the spacing area.

[0015] Optionally, in some embodiments of the present application, the array substrate includes a plurality of pixel units, and the pixel units are arranged in a one-to-one correspondence with the compensation electrodes.

[0016] Optionally, in some embodiments of the present application, the compensation electrodes are arranged in an array.

[0017] Optionally, in some embodiments of the present application, in the shallow hole area, the common electrode layer is arranged to cover the inner wall of the via hole.

[0018] Optionally, in some embodiments of the present application, the second connecting electrode is in surface contact with the common electrode layer, and the second connecting electrode at least covers the common electrode layer located on the inner wall of the via hole.

[0019] Optionally, in some embodiments of the present application, the compensation electrode is electrically connected in parallel to the common electrode layer.

[0020] Optionally, in some embodiments of the present application, one end of the second connecting electrode is connected to the common electrode layer, the other end of the second connecting electrode is connected to one end of the first connecting electrode, and the other end of the first connecting electrode is connected to the compensation electrode.

[0021] Optionally, in some embodiments of the present application, the array substrate further includes a gate insulation layer, the gate insulation layer is arranged on a side of the gate layer away from the substrate, and the active layer is arranged on a side of the gate insulation layer away from the substrate, wherein the gate insulation layer includes a connecting through hole, and the first connecting electrode is connected to the compensation electrode through the connecting through hole.

[0022] The present invention provides a method for preparing an array substrate, comprising:

[0023] Providing a substrate, depositing a layer of metal material on the substrate, and preparing the metal material by a yellow light process to obtain a gate layer, wherein the gate layer includes a gate and a compensation electrode;

[0024] Sequentially forming a gate insulating layer, an active layer, and a source-drain electrode layer on the gate layer, wherein the source-drain electrode layer includes a source electrode, a drain electrode, and a first connecting electrode;

[0025] Depositing a first layer of inorganic material on a side of the source and drain electrode layer away from the substrate, and depositing a first layer of transparent electrode material on the first layer of inorganic material, preparing the first layer of transparent electrode material by a yellow light process to obtain a common electrode layer, and depositing a second layer of inorganic material on a side of the common electrode layer away from the substrate;

[0026] The first layer of inorganic material and the second layer of inorganic material are etched using a photomask to prepare a plurality of via holes that penetrate at least the second passivation layer, and only the second passivation layer is penetrated in an area where a common electrode layer is provided to block etching, thereby forming a shallow hole region within the via hole; and the second passivation layer and the first passivation layer are penetrated in an area where no common electrode layer is provided, thereby forming a deep hole region within the via hole; thus preparing a first passivation layer and a second passivation layer;

[0027] A second layer of transparent electrode material is deposited, and a pixel electrode layer is prepared on the second layer of transparent electrode material using a yellow light process. The pixel electrode layer includes a pixel electrode and a second connecting electrode. In the deep hole area, the pixel electrode is connected to the drain electrode. In the shallow hole area, the common electrode layer is electrically connected to the compensation electrode through the first connecting electrode and the second connecting electrode.

[0028] Beneficial effect: by realizing not only the connection between the pixel electrode and the drain electrode but also the connection between the common electrode layer and the compensation electrode of the first metal layer in one via hole, the number of via holes is reduced and the aperture ratio is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a cross-sectional schematic diagram of an array substrate in the prior art;

[0031] Figure 2 This is a first cross-sectional schematic diagram of the array substrate provided in this application;

[0032] Figure 3 This is a second cross-sectional schematic diagram of the array substrate provided in this application;

[0033] Figure 4 It is a flow chart of the method for preparing an array substrate provided in this application.

[0034] Description of reference numerals:

[0035] DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0037] See also Figure 2The array substrate provided in the present application includes a substrate 10, a gate layer 20, an active layer 40, a source-drain layer 50, a first passivation layer 60, a common electrode layer 80, a second passivation layer 90, and a pixel electrode layer 100. The gate layer 20 is arranged above the substrate 10, and the gate layer 20 includes a gate 201 and a compensation electrode 202. The source-drain layer 50 is arranged on a side of the gate layer 20 away from the substrate 10. The source-drain layer 50 includes a source 501, a drain 502, and a first connecting electrode 503. The first passivation layer 60 is arranged on a side of the source-drain layer away from the substrate 10. The common electrode layer 80 is arranged on a side of the first passivation layer 60 away from the substrate 10. The second passivation layer 90 is arranged on a side of the common electrode layer 80 away from the substrate 10. Layer 100 is arranged on the side of the second passivation layer 90 away from the substrate 10, and the pixel electrode layer 100 includes a pixel electrode 1001 and a second connecting electrode 1002; wherein, the array substrate also includes a plurality of vias 110 arranged at least through the second passivation layer 90, and any of the vias 110 includes a deep hole area H1 and a shallow hole area H2. The via 110 in the deep hole area H1 is arranged through the second passivation layer 90 and the first passivation layer 60, and the via 110 in the shallow hole area H2 is arranged through the second passivation layer 90. In the deep hole area H1, the pixel electrode 1001 is connected to the drain 502, and in the shallow hole area H2, the common electrode layer 80 is electrically connected to the compensation electrode 202 through the second connecting electrode 1002 and the first connecting electrode 503 in sequence.

[0038] A PFA organic film layer 70 is further provided on a side of the first passivation layer 60 away from the substrate 10 , and the common electrode layer 80 is provided on a side of the PFA organic film layer 70 away from the substrate 10 .

[0039] In this embodiment, by connecting not only the pixel electrode 1001 and the drain electrode 502 but also the common electrode layer 80 and the compensation electrode 202 of the first metal layer in one via hole 110 , the number of via holes 110 is reduced and the aperture ratio is improved.

[0040] The technical solution of this application is now described in conjunction with specific embodiments.

[0041] This application uses a bottom-gate array substrate as an example for description, but is also applicable to other types of array substrates such as a top-gate array substrate.

[0042] In one embodiment, a gate insulating layer 30 is further provided on a side of the gate layer 20 away from the substrate 10 , and the active layer 40 is provided on a side of the gate insulating layer 30 away from the substrate 10 .

[0043] In one embodiment, the active layer 40 is arranged on a side of the gate layer 20 away from the substrate 10, and the active layer 40 includes an active pattern 401 and a semiconductor pattern 402. The active pattern 401 is connected to the source 501 and the drain 502. The drain 502 and the first connecting electrode 503 are spaced apart to form a spacing area, and the semiconductor pattern 402 at least covers the spacing area.

[0044] The active pattern 401 includes a first doped region connected to the source 501 and a second doped region connected to the drain 502. The active pattern 401 in the first doped region and the second doped region is a conductor, and the active pattern 401 located between the first doped region and the second doped region is a semiconductor.

[0045] The semiconductor of the active pattern 401 and the semiconductor pattern 402 are made of the same material.

[0046] It can be understood that the semiconductor pattern 402 is non-conductive and can block the etching of the gate insulation layer 30, thereby avoiding the gate insulation layer 30 in the spacing area being excessively etched and causing defects when the first passivation layer 60 and the second passivation layer 90 are subjected to the yellow light process due to the presence of a spacing area between the drain 502 and the first connecting electrode 503.

[0047] It is understandable that the semiconductor pattern 402 and the active pattern 401 are prepared in the same layer, which can also simplify the process and reduce costs.

[0048] In this embodiment, the active layer 40 further includes a semiconductor pattern 402, which is insulated from the active pattern 401 and covers at least the spacing area between the drain 502 and the first connecting electrode 503, thereby preventing the gate insulation layer 30 in the spacing area from being over-etched.

[0049] In one embodiment, the array substrate includes a plurality of pixel units, and the pixel units are arranged in a one-to-one correspondence with the compensation electrodes 202 .

[0050] It can be understood that since multiple holes in the prior art are merged into one via 110, the via 110 has a minimum aperture due to process precision limitations, and multiple vias 110 in the prior art result in a low aperture ratio. Therefore, in the prior art, most pixel units do not have holes connecting the common electrode layer 80 to the compensation electrode 202, and only a very small number of pixel units have holes connecting the common electrode layer 80 to the compensation electrode 202, which makes it difficult to alleviate the signal unevenness of the common electrode layer 80 and the aperture ratio cannot be further improved. However, the present application merges multiple holes in the prior art into one via 110, and utilizes the via 110 to not only connect the pixel electrode 1001 to the drain 502, but also connect the common electrode layer 80 to the compensation electrode 202 of the first metal layer, thereby reducing the number of vias 110 and improving the aperture ratio.

[0051] It should be noted that since only one via hole 110 is provided in each pixel unit, compared with the prior art in which multiple via holes are provided in each pixel unit, the area occupied by the opening can be reduced, and the aperture ratio can be significantly improved. In addition, a compensation electrode 202 connected to the common electrode layer 80 is provided in any pixel unit, thereby reducing the voltage drop of the common electrode layer 80 and improving the uniformity of the common electrode signal.

[0052] In this embodiment, by providing the compensation electrode 202 in each pixel unit, the contact impedance of the common electrode layer 80 can be better reduced, and it is also beneficial to achieve uniform voltage drop of the common electrode layer 80 .

[0053] In another embodiment, the pixel unit includes a plurality of sub-pixel units, and the compensation electrodes 202 are disposed in a one-to-one correspondence with the sub-pixel units.

[0054] Furthermore, any sub-pixel unit includes at least one via hole 110 .

[0055] In one embodiment, the compensation electrodes 202 are arranged in an array.

[0056] Furthermore, the sizes and shapes of adjacent compensation electrodes 202 may be the same.

[0057] In this embodiment, the compensation electrodes 202 are arranged in an array, which facilitates the process of preparing the compensation electrodes 202 .

[0058] In one embodiment, in the shallow hole region H2 , the common electrode layer 80 is disposed to cover the inner wall of the via hole 110 .

[0059] It can be understood that in the shallow hole area H2, due to the obstruction of the common electrode layer 80, the first passivation layer 60 located on the side of the common electrode layer 80 facing the substrate 10 is not etched, and the common electrode layer 80 covers the inner wall of the via hole 110, which can further increase the contact area between the common electrode layer 80 and the second connecting electrode 1002, thereby reducing the contact resistance between the two.

[0060] In this embodiment, the common electrode layer 80 in the shallow hole area H2 is arranged to cover the inner wall of the via hole 110 , so that a larger contact area between the second connection electrode 1002 and the common electrode layer 80 can be achieved, thereby reducing contact resistance.

[0061] Furthermore, in one embodiment, a concave-convex structure may be provided in the via hole 110, and the concave-convex structure is in surface contact with at least the common electrode layer 80, thereby increasing the bonding force between the common electrode layer 80 and other film layers in the via hole 110 and avoiding the phenomenon of detachment between film layers.

[0062] Among them, see Figure 2 The concave-convex structure 120 may be integrated with the PFA organic film layer 70 , and the concave-convex structure is provided on the contact surface between the PFA organic film layer 70 and the common electrode layer 80 .

[0063] In another embodiment, see Figure 3 The surface of the common electrode layer 80 on the side in contact with the second connecting electrode 1002 is provided with a concave-convex structure, so that the surface in contact with the second connecting electrode 1002 is roughened, thereby increasing the contact area between the common electrode layer 80 and the second connecting electrode 1002, thereby further reducing the contact resistance between the common electrode layer 80 and the second connecting electrode 1002.

[0064] In one embodiment, the second connection electrode 1002 is in surface contact with the common electrode layer 80 , and the second connection electrode 1002 is disposed to cover at least the common electrode layer 80 on the inner wall of the via hole 110 .

[0065] It can be understood that in the shallow hole area H2, the common electrode layer 80 is arranged to cover the inner wall of the via hole 110, and the second connecting electrode 1002 is arranged to cover the common electrode layer 80 along the inner wall of the via hole 110; the second connecting electrode 1002 is in surface contact with the common electrode layer 80.

[0066] In this embodiment, the second connecting electrode 1002 is arranged to cover the common electrode layer 80 on the inner wall of the via hole 110, so that the contact area between the second connecting electrode 1002 and the common electrode layer 80 located on the inner wall of the via hole 110 is maximized, thereby achieving the minimum contact impedance between the second connecting electrode 1002 and the common electrode layer 80.

[0067] In one embodiment, the compensation electrode 202 is electrically connected in parallel to the common electrode layer 80 .

[0068] In this embodiment, the compensation electrode 202 is connected in parallel with the common electrode layer 80 , thereby reducing the impedance of the common electrode layer 80 .

[0069] Furthermore, in another embodiment, the resistance of the compensation electrode 202 is smaller than the resistance of the common electrode layer 80 .

[0070] The resistance of the compensation electrode 202 may also be smaller than the resistance of the first connection electrode 503 .

[0071] The resistance of the compensation electrode 202 may also be smaller than the resistance of the second connection electrode 1002 .

[0072] In one embodiment, one end of the second connection electrode 1002 is connected to the common electrode layer 80 , the other end of the second connection electrode 1002 is connected to one end of the first connection electrode 503 , and the other end of the first connection electrode 503 is connected to the compensation electrode 202 .

[0073] It can be understood that the second connecting electrode 1002 and the compensation electrode 202 are respectively connected by connecting the two ends of the first connecting electrode 503, that is, the common electrode layer 80 is electrically connected to the compensation electrode 202 by using the via 110 and the connecting through hole 130, so that the depth of the via 110 does not need to be too deep, that is, multiple holes "connected in series" are formed through multiple digging processes, avoiding the defects of a single digging that is too deep, and alleviating the technical problem that the metal wiring in the via 110 is prone to breakage due to the excessive depth of the via 110.

[0074] The connecting through hole 130 may be provided through the gate insulating layer 30 . The connecting through hole 130 is filled with the first connecting electrode 503 . The first connecting electrode is connected 503 to the compensation electrode 202 through the connecting through hole 130 .

[0075] In one embodiment, the array substrate further includes a gate insulating layer 30 , which is disposed on a side of the gate layer 20 away from the substrate 10 , and the active layer 40 is disposed on a side of the gate insulating layer 30 away from the substrate 10 .

[0076] See also Figure 4 , an embodiment of the present application provides a method for preparing an array substrate, comprising:

[0077] S1: providing a substrate 10, depositing a layer of metal material on the substrate 10, and preparing the metal material by a yellow light process to obtain a gate layer 20, wherein the gate layer 20 includes a gate 201 and a compensation electrode 202;

[0078] S2: sequentially preparing a gate insulating layer 30 , an active layer 40 , and a source-drain electrode layer 50 on the gate layer 20 , wherein the source-drain electrode layer 50 includes a source electrode 501 , a drain electrode 502 , and a first connection electrode 503 ;

[0079] S3: depositing a first layer of inorganic material on a side of the source / drain electrode layer 50 away from the substrate 10, and depositing a first layer of transparent electrode material on the first layer of inorganic material, preparing the first layer of transparent electrode material by a yellow light process to obtain a common electrode layer 80, and depositing a second layer of inorganic material on a side of the common electrode layer 80 away from the substrate 10;

[0080] S4: etching the first layer of inorganic material and the second layer of inorganic material using a photomask to prepare a plurality of via holes 110 that penetrate at least the second passivation layer 90. In an area where the common electrode layer 80 is provided to block etching, only the second passivation layer 90 is penetrated, thereby forming a shallow hole area H2 in the via hole 110. In an area where the common electrode layer 80 is not provided, the second passivation layer 90 and the first passivation layer 60 are penetrated, thereby forming a deep hole area H1 in the via hole 110. Thus, the first passivation layer 60 and the second passivation layer 90 are prepared.

[0081] S5: Deposit a second layer of transparent electrode material, and use a yellow light process to prepare the pixel electrode layer 100 on the second layer of transparent electrode material. The pixel electrode layer 100 includes a pixel electrode 1001 and a second connecting electrode 1002. In the deep hole area H1, the pixel electrode 1001 is connected to the drain 502. In the shallow hole area H2, the common electrode layer 80 is electrically connected to the compensation electrode 202 through the second connecting electrode 1002 and the first connecting electrode 503 in sequence.

[0082] It can be understood that since multiple holes in the prior art are merged into one via hole 110, the aperture of the via hole 110 can be larger than the hole in the prior art, so that the contact area between the common electrode layer 80 in the via hole 110 and the second connecting electrode 1002 can also be larger. Therefore, the present application also has the technical effect of increasing the contact area between the common electrode layer 80 and the second connecting electrode 1002, thereby reducing the contact impedance between the common electrode layer 80 and the second connecting electrode 1002.

[0083] It should be noted that the present application can also increase the contact area between the first connecting electrode 503 and the second connecting electrode 1002, thereby reducing the contact impedance between the first connecting electrode 503 and the second connecting electrode 1002; and whether the contact impedance between the common electrode layer 80 and the second connecting electrode 1002 is reduced, or the contact impedance between the first connecting electrode 503 and the second connecting electrode 1002 is reduced, the contact impedance between the compensation electrode 202 and the common electrode layer 80 can be reduced, thereby further reducing the impedance of the common electrode layer 80.

[0084] In this embodiment, in step S4, the via 110 is prepared by a mask. The via 110 can not only connect the pixel electrode 1001 with the drain 502, but also connect the common electrode layer 80 with the compensation electrode 202 of the first metal layer, thereby reducing the number of vias 110 and improving the aperture ratio.

[0085] In each embodiment of the present application, since there is only one via hole 110 , there is no need to consider the spacing requirements between multiple holes in the traditional solution, thus saving more space and improving the aperture ratio.

[0086] Specifically, by merging two or more traditional holes into one via 110, the functions of pixel charging and connecting the common electrode layer 80 to the compensation electrode 202 are realized at the same time. The area of ​​the via 110 after the merger is less than or equal to the sum of the areas of the two traditional holes. Therefore, when the area of ​​the via 110 after the merger is less than the sum of the areas of the two traditional holes, the area occupied by the hole is reduced, and the aperture ratio is significantly improved. At the same time, when the area of ​​the via 110 after the merger is equal to the sum of the areas of the two or more traditional holes, when the vias occupy the same area, the solution provided by this patent is adopted, and the contact area between the pixel electrode 1001 and the source and drain layer 50, and the common electrode layer 80 and the second connection electrode 1002 is larger, so that the charging resistance of the pixel electrode 1001 and the resistance of the common electrode layer 80 are both lower.

[0087] The present application also proposes a display panel, a display module, and a display device. The display panel, the display module, and the display device all include the above-mentioned array substrate, which will not be described in detail here.

[0088] The array substrate provided in this embodiment includes a substrate, a gate layer, an active layer, a source-drain electrode layer, a first passivation layer, a common electrode layer, a second passivation layer, and a pixel electrode layer. The gate layer is arranged above the substrate, the gate layer includes a gate and a compensation electrode, the active layer is arranged on a side of the gate layer away from the substrate, the source-drain electrode layer is arranged on a side of the active layer away from the substrate, the source-drain electrode layer includes a source electrode, a drain electrode, and a first connecting electrode, the first passivation layer is arranged on a side of the source-drain electrode layer away from the substrate, the common electrode layer is arranged on a side of the first passivation layer away from the substrate, the second passivation layer is arranged on a side of the common electrode layer away from the substrate, and the pixel electrode layer is arranged on a side of the second passivation layer away from the substrate On one side, the pixel electrode layer includes a pixel electrode and a second connecting electrode; wherein, the array substrate further includes a plurality of via holes arranged at least through the second passivation layer, any of the via holes includes a deep hole area and a shallow hole area, the via holes in the deep hole area are arranged through the second passivation layer and the first passivation layer, and the via holes in the shallow hole area are arranged through the second passivation layer, in the deep hole area, the pixel electrode is connected to the drain, and in the shallow hole area, the common electrode layer is electrically connected to the compensation electrode through the first connecting electrode and the second connecting electrode; by realizing not only the connection between the pixel electrode and the drain but also the connection between the common electrode layer and the compensation electrode of the first metal layer in one via hole, the number of via holes is reduced and the aperture ratio is improved.

[0089] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0090] The above is a detailed introduction to the array substrate and array substrate preparation method provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a gate layer, the gate layer being disposed above the substrate, the gate layer comprising a gate and a compensation electrode; a source-drain electrode layer, the source-drain electrode layer being arranged on a side of the gate layer away from the substrate, the source-drain electrode layer comprising a source electrode, a drain electrode, and a first connecting electrode; a first passivation layer, the first passivation layer being disposed on a side of the source and drain electrode layer away from the substrate; a common electrode layer, the common electrode layer being disposed on a side of the first passivation layer away from the substrate; a second passivation layer, the second passivation layer being disposed on a side of the common electrode layer away from the substrate; a pixel electrode layer, the pixel electrode layer being disposed on a side of the second passivation layer away from the substrate, the pixel electrode layer comprising a pixel electrode and a second connecting electrode; The array substrate further includes a plurality of via holes at least penetrating the second passivation layer, and any of the via holes includes a deep hole region and a shallow hole region. The via holes in the deep hole region penetrate the second passivation layer and the first passivation layer, and the via holes in the shallow hole region penetrate the second passivation layer. In the deep hole region, the pixel electrode is connected to the drain electrode, and in the shallow hole region, the common electrode layer is electrically connected to the compensation electrode through the first connection electrode and the second connection electrode. In the shallow hole area, the common electrode layer is arranged to cover the inner wall of the via hole; The second connecting electrode is in surface contact with the common electrode layer, and the second connecting electrode at least covers the common electrode layer located on the inner wall of the via hole.

2. The array substrate according to claim 1, wherein: An active layer is arranged on a side of the gate layer away from the substrate, and the active layer includes an active pattern and a semiconductor pattern. The active pattern is connected to the source and the drain. The drain and the first connecting electrode are spaced apart to form a spacing area, and the semiconductor pattern at least covers the spacing area.

3. The array substrate according to claim 1, wherein: The array substrate includes a plurality of pixel units, and the pixel units are arranged in a one-to-one correspondence with the compensation electrodes.

4. The array substrate according to claim 3, wherein: The compensation electrodes are arranged in an array.

5. The array substrate according to claim 1, wherein: The compensation electrode is electrically connected to the common electrode layer in parallel.

6. The array substrate according to claim 2, wherein: One end of the second connection electrode is connected to the common electrode layer, the other end of the second connection electrode is connected to one end of the first connection electrode, and the other end of the first connection electrode is connected to the compensation electrode.

7. The array substrate according to claim 6, wherein: The array substrate also includes a gate insulation layer, which is arranged on a side of the gate layer away from the substrate, and the active layer is arranged on a side of the gate insulation layer away from the substrate, wherein the gate insulation layer includes a connecting through-hole, and the first connecting electrode is connected to the compensation electrode through the connecting through-hole.

8. A method for preparing an array substrate, characterized in that: include: Providing a substrate, depositing a layer of metal material on the substrate, and preparing the metal material by a yellow light process to obtain a gate layer, wherein the gate layer includes a gate and a compensation electrode; Sequentially forming a gate insulating layer, an active layer, and a source-drain electrode layer on the gate layer, wherein the source-drain electrode layer includes a source electrode, a drain electrode, and a first connecting electrode; Depositing a first layer of inorganic material on a side of the source and drain electrode layer away from the substrate to obtain a first passivation layer, depositing a first layer of transparent electrode material on the first layer of inorganic material, preparing a common electrode layer on the first layer of transparent electrode material using a yellow light process, and depositing a second layer of inorganic material on a side of the common electrode layer away from the substrate to obtain a second passivation layer; The first layer of inorganic material and the second layer of inorganic material are etched using a photomask to prepare a plurality of via holes that penetrate at least the second passivation layer, and only penetrate the second passivation layer in an area where a common electrode layer is provided to block etching, thereby forming a shallow hole region within the via hole, wherein the common electrode layer covers the inner wall of the via hole; and penetrate the second passivation layer and the first passivation layer in an area where no common electrode layer is provided, thereby forming a deep hole region within the via hole; A second layer of transparent electrode material is deposited, and a yellow light process is used to prepare the pixel electrode layer on the second layer of transparent electrode material. The pixel electrode layer includes a pixel electrode and a second connecting electrode. In the deep hole area, the pixel electrode is connected to the drain electrode. In the shallow hole area, the common electrode layer is electrically connected to the compensation electrode through the first connecting electrode and the second connecting electrode. The second connecting electrode is in surface contact with the common electrode layer, and the second connecting electrode at least covers the common electrode layer located on the inner wall of the via hole.

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