Array substrate, display panel

Abstract

Embodiments of the present application disclose an array substrate and a display panel. The array substrate includes a substrate, a first metal layer, an active layer, a gate insulating layer, a second metal layer, a first transparent electrode layer, and a second transparent electrode layer, which are arranged in sequence. A first undercut structure and a second undercut structure are formed on the first surface and the second surface of the gate insulating layer, respectively. The first transparent electrode layer includes a first portion, a second portion, and a third portion. The first portion and the third portion are disconnected at the first undercut structure, and the second portion and the third portion are disconnected at the second undercut structure. Two ends of the first portion are respectively connected to the first overlapping surface and the source electrode of the active layer, and two ends of the second portion are respectively connected to the second overlapping surface and the drain electrode of the active layer. The source electrode and the drain electrode are connected to the two ends of the active layer through the first transparent electrode layer. Since the first transparent electrode layer itself is a conductor, the active layer in the overlapping area does not need to undergo a conductorization process, thereby reducing costs.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] MLEDs, with their superior display performance, are considered one of the most competitive next-generation display technologies. Oxide semiconductor materials are the preferred material for large-scale MLED array substrate development due to their unique advantages, including high mobility, large-area uniformity, and low process temperature. Top-gate array substrates are highly favored within the industry due to their low parasitic capacitance, strong stability, and ability to achieve narrow channels. However, in top-gate array substrates, the active layer is made of semiconductor material and has poor inherent conductivity. The active layer in the areas where it overlaps with the source and drain electrodes requires a conductive process to improve contact resistance. Common conductive processes include ion implantation, plasma treatment, and metal reaction. These processes inevitably increase costs, and some technologies have poor conductive stability, which can also affect device performance.

[0003] Therefore, the existing array substrate has a technical problem that the active layer needs to be partially conductive, which leads to high costs. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can alleviate the technical problem of high cost caused by the need to partially conduct the active layer of the existing array substrate.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A first metal layer, the first metal layer is disposed on one side of the substrate, and the first metal layer includes a source electrode and a drain electrode;

[0008] an interlayer insulating layer, the interlayer insulating layer being arranged on a side of the first metal layer away from the substrate;

[0009] an active layer, the active layer being arranged on a side of the interlayer insulating layer away from the first metal layer;

[0010] a gate insulating layer, the gate insulating layer being disposed on a side of the active layer away from the substrate;

[0011] a second metal layer, the second metal layer being disposed on a side of the gate insulating layer away from the substrate, the second metal layer comprising a gate;

[0012] a first transparent electrode layer, wherein the first transparent electrode layer is disposed on a side of the gate layer away from the substrate;

[0013] In which, the first surface and the second surface of the gate insulation layer are respectively formed with a first undercut structure and a second undercut structure, the first transparent electrode layer includes a first part, a second part, and a third part, the first part and the third part are disconnected at the first undercut structure, the second part and the third part are disconnected at the second undercut structure, the two ends of the first part are respectively connected to the first overlapping surface of the active layer and the source electrode, and the two ends of the second part are respectively connected to the second overlapping surface of the active layer and the drain electrode.

[0014] Optionally, in some embodiments of the present application, the first surface of the gate insulation layer and the first overlapping surface of the active layer form the first undercut structure, and the second surface of the gate insulation layer and the second overlapping surface of the active layer form the second undercut structure.

[0015] Optionally, in some embodiments of the present application, the first surface of the gate insulation layer and the surface of the gate electrode on the side away from the first transparent electrode layer form the first undercut structure, and the second surface of the gate insulation layer and the surface of the gate electrode on the side away from the first transparent electrode layer form the second undercut structure.

[0016] Optionally, in some embodiments of the present application, the projection of the gate on the substrate falls within the projection range of the gate insulation layer on the substrate, and the projection of the gate insulation layer on the substrate falls within the projection range of the active layer on the substrate.

[0017] Optionally, in some embodiments of the present application, the projection of the source or the drain in the direction of the substrate covers the projection of the active layer on the substrate.

[0018] Optionally, in some embodiments of the present application, the array substrate further includes a passivation layer, a flat layer, and a second electrode layer, the passivation layer is arranged on a side of the first transparent electrode layer away from the substrate, the flat layer is arranged on a side of the passivation layer away from the substrate, the second electrode layer is arranged on a side of the flat layer away from the substrate, and the second electrode layer is connected to the first part or the second part through a via hole passing through the passivation layer and the flat layer.

[0019] Optionally, in some embodiments of the present application, the second electrode layer includes a third metal layer and a second transparent electrode layer, and the third metal layer is directly connected to the first part or the second part.

[0020] Optionally, in some embodiments of the present application, the third metal layer is continuously disposed on a side of the second transparent electrode layer facing the substrate, and the third metal layer at least covers the inner wall and bottom of the first via hole.

[0021] Optionally, in some embodiments of the present application, the third metal layer is any one of a molybdenum single-layer structure, a molybdenum / aluminum stacked structure, a molybdenum / copper stacked structure, a molybdenum-titanium / copper stacked structure, a molybdenum-titanium / copper / molybdenum-titanium stacked structure, a titanium / aluminum / titanium stacked structure, and a titanium / copper / titanium stacked structure.

[0022] An embodiment of the present application provides a display panel, comprising the array substrate described in any of the above embodiments.

[0023] Beneficial effect: The first metal layer is arranged on the side of the active layer close to the substrate, and the source and drain are overlapped with the two ends of the active layer through the first transparent electrode layer. Since the first transparent electrode layer itself is a conductor, the active layer in the overlapping area does not need to undergo a conductorization process, which reduces costs and alleviates the technical problem of high costs caused by the need for partial conductorization of the active layer in existing array substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 This is a first cross-sectional schematic diagram of the array substrate provided in this application;

[0026] Figure 2 This is a second cross-sectional schematic diagram of the array substrate provided in this application;

[0027] Figures 3A to 3F This is a schematic diagram of the process state of the array substrate preparation method provided in this application;

[0028] Figure 4 This is a flow chart of the array substrate preparation method provided in this application.

[0029] Description of reference numerals:

[0030]

[0031] DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0033] See also Figure 1 、 Figure 2 The array substrate 1 provided in the present application includes a substrate 10, a first metal layer 20, an interlayer insulating layer 30, an active layer 40, a gate insulating layer 50, a second metal layer 60, and a first transparent electrode layer 70. The first metal layer is arranged on one side of the substrate, the first metal layer includes a source electrode and a drain electrode, the interlayer insulating layer is arranged on a side of the first metal layer away from the substrate, the active layer is arranged on a side of the interlayer insulating layer away from the first metal layer, the gate insulating layer is arranged on a side of the active layer away from the substrate, the second metal layer is arranged on a side of the gate insulating layer away from the substrate, the second metal layer includes a gate electrode, and the first transparent electrode layer 70 is provided. A transparent electrode layer is arranged on the side of the gate layer away from the substrate; wherein, the first surface and the second surface of the gate insulating layer are respectively formed with a first undercut structure and a second undercut structure, and the first transparent electrode layer 70 includes a first part 701, a second part 702, and a third part 703, the first part and the third part are disconnected at the first undercut structure 120, and the second part and the third part are disconnected at the second undercut structure 130, the two ends of the first part are respectively connected to the first overlapping surface of the active layer and the source, and the two ends of the second part are respectively connected to the second overlapping surface of the active layer and the drain.

[0034] In this embodiment, the first metal layer 20 is disposed on a side of the active layer 40 close to the substrate 10, and the source electrode 201 and the drain electrode 202 are overlapped with both ends of the active layer 40 through the first transparent electrode layer 70. Since the first transparent electrode layer 70 itself is a conductor, the active layer 40 in the overlapped area does not need to undergo a conductorization process, thereby reducing costs and alleviating the technical problem of the existing array substrate 1 that the active layer 40 needs to be partially conductorized, resulting in high costs.

[0035] The technical solution of this application is now described in conjunction with specific embodiments.

[0036] The embodiment of the present application is described by taking the top gate array substrate 1 as an example.

[0037] In addition, the process sequence, the method of forming the bottom cut structure 2, the type of laminated or single-layer structure, the selected materials, etc. of this application are only described with the best or better implementation method. Other methods that can meet the inventive concept of this application should also fall within the scope of protection of the present invention and will not be repeated here.

[0038] In one embodiment, see Figure 1 The first surface S1 of the gate insulating layer 50 and the first overlapping surface of the active layer 40 form the first undercut structure 120 , and the second surface S2 of the gate insulating layer and the second overlapping surface of the active layer form the second undercut structure 130 .

[0039] In one embodiment, see Figure 2 The first surface S1 of the gate insulating layer 50 and the surface of the gate electrode 60 away from the first transparent electrode layer 70 form the first undercut structure 120, and the second surface S2 of the gate insulating layer and the surface of the gate electrode away from the first transparent electrode layer 70 form the second undercut structure 130.

[0040] In one embodiment, the source electrode 201 or the drain electrode 202 is arranged to cover the active layer 40 in a direction perpendicular to the substrate 10 .

[0041] It can be understood that a light-shielding layer is usually required to be provided on the side of the active layer 40 close to the substrate 10 to prevent light incident from the side of the substrate 10 from irradiating the active layer 40 and affecting the active layer 40; by arranging the source 201 or the drain 202 on the side of the active layer 40 close to the substrate 10, and making the source 201 or the drain 202 cover the active layer 40 in a direction perpendicular to the substrate 10, the first metal layer 20 is utilized to replace the light-shielding layer, thereby preventing light irradiated from the side of the substrate 10 from affecting the active layer 40.

[0042] In this embodiment, no additional light shielding layer is required, thereby further simplifying the preparation process of the array substrate 1 and reducing the cost.

[0043] In one embodiment, the array substrate 1 further includes an interlayer insulating layer 30 disposed on the side of the first metal layer 20 away from the substrate 10, and the active layer 40 is disposed on the side of the interlayer insulating layer 30 away from the substrate 10, wherein a second via H2 and a third via H3 are disposed through the interlayer insulating layer 30, one end of the first part 701 is connected to the source 201 through the second via H2, and a section of the second part 702 is connected to the drain 202 through the third via H3.

[0044] It can be understood that the first metal layer 20 and the active layer 40 are separated by the interlayer insulating layer 30 to prevent the channel region of the active layer 40 from overlapping with the first metal layer 20 .

[0045] It can be understood that, since the present application arranges the first metal layer 20 on the side of the active layer 40 close to the substrate 10, and an interlayer insulating layer 30 is provided between the two to separate them, a second via H2 and a third via H3 are formed in the interlayer insulating layer 30 above the source 201 and the drain 202. The second via H2 and the third via H3 are used to allow the first metal layer 20 to overlap with the active layer 40 through the first transparent electrode layer 70.

[0046] In this embodiment, by forming a second via hole H2 and a third via hole H3 in the interlayer insulating layer 30 above the source 201 and the drain 202, the first metal layer 20 can be overlapped with both ends of the active layer 40 through the first transparent electrode layer 70, thereby eliminating the conductor process for the overlapping positions at both ends of the active layer 40 and reducing costs.

[0047] In one embodiment, the third portion 703 is connected to the second metal layer 60 , and the third portion 703 is separated from the first portion 701 and the second portion 702 by the undercut structure 2 .

[0048] It can be understood that by disconnecting the third part 703 connected to the second metal layer 60 relative to the first part 701 and the second part 702, the second metal layer 60 is prevented from being electrically connected to the source 201, the drain 202, and the active layer 40 below, so that the array substrate 1 can operate normally without affecting the device characteristics.

[0049] It should be noted that the third part 703 is disconnected from the first part 701 and the second part 702 . Therefore, the third part 703 can serve as a compensation electrode relative to the second metal layer 60 , and is used to connect to the second metal layer 60 , thereby reducing the impedance of the second metal layer 60 .

[0050] In this embodiment, the first transparent electrode layer 70 only needs to be vapor-deposited with a layer of transparent electrode material on the entire surface. The transparent electrode material will be disconnected at the undercut structure 2, and there is no need to perform a patterning process on the first transparent electrode layer 70. Compared with the prior art in which the first transparent electrode layer 70 requires a mask for patterning, the present application can further achieve cost reduction.

[0051] In one embodiment, the array substrate 1 further includes a passivation layer 80, a planar layer 90, and a second transparent electrode layer 110. The passivation layer 80 is arranged on a side of the first transparent electrode layer 70 away from the substrate 10. The planar layer 90 is arranged on a side of the passivation layer 80 away from the substrate 10. The second transparent electrode layer 110 is arranged on a side of the planar layer 90 away from the substrate 10. The second transparent electrode layer 110 is connected to the first portion 701 or the second portion 702 via a first via hole H1 that penetrates the passivation layer 80 and the planar layer 90.

[0052] The second transparent electrode layer 110 is electrically connected to the first transparent electrode layer 70 through the first via hole H1.

[0053] In one embodiment, the array substrate 1 further includes a third metal layer 100 , which is continuously disposed on the side of the second transparent electrode layer 110 facing the substrate 10 , and the third metal layer 100 at least covers the inner wall and bottom of the first via hole H1 .

[0054] It can be understood that the first transparent electrode layer 70 at the first via hole H1 is easily invaded by water and oxygen. Therefore, the third metal layer 100 is provided in the first via hole H1. It can not only block the invasion of water and oxygen on the side away from the substrate 10, but also, since the third metal layer 100 is made of metal material, its conductive performance can be better than the second transparent electrode layer 110 and the first transparent electrode layer 70. The third metal layer 100 can also improve the electrical connection effect between the first transparent electrode layer 70 and the second transparent electrode layer 110.

[0055] It should be noted that the third metal layer 100 and the second transparent electrode layer 110 can be prepared using the same photomask. Specifically, the third metal layer 100 and the second transparent electrode layer 110 are overlapped in a direction perpendicular to the substrate 10 .

[0056] In this embodiment, by providing the third metal layer 100 at least on the inner wall and bottom of the first via hole H1, not only can water and oxygen on the side of the first transparent electrode layer 70 facing away from the substrate 10 be blocked from invading the surface along the first via hole H1, but also the electrical conductivity of the third metal layer 100 can be made better than that of the second transparent electrode layer 110 and the first transparent electrode layer 70, thereby improving the electrical connection effect between the first transparent electrode layer 70 and the second transparent electrode layer 110.

[0057] Specifically, in some embodiments, the third metal layer 100 may also include a first third metal layer 100 for blocking water and oxygen, and a second third metal layer 100 for improving the electrical connection effect, and the first third metal layer 100 and the second third metal layer 100 are stacked.

[0058] In one embodiment, the third metal layer 100 is any one of a molybdenum single-layer structure, a molybdenum / aluminum stacked structure, a molybdenum / copper stacked structure, a molybdenum-titanium / copper stacked structure, a molybdenum-titanium / copper / molybdenum-titanium stacked structure, a titanium / aluminum / titanium stacked structure, and a titanium / copper / titanium stacked structure.

[0059] In one embodiment, the planar layer 90 is made of a photoresist material, and the photoresist material is DL-1001-C photoresist.

[0060] In one embodiment, the second metal layer 60 is made of the same material as the first metal layer 20 .

[0061] In this embodiment, the second metal layer 60 and the first metal layer 20 are made of the same material, thereby reducing costs.

[0062] See also Figures 3A to 3F 、 Figure 4 , an embodiment of the present application provides a method for preparing an array substrate 1, comprising:

[0063] S1: providing a substrate 10;

[0064] S2: preparing the first metal layer 20 on the substrate 10, wherein the first metal layer 20 includes a source electrode 201 and a drain electrode 202;

[0065] S3: preparing an active layer 40 on a side of the first metal layer 20 away from the substrate 10;

[0066] S4: continuously depositing an insulating material and a metal material on a side of the active layer 40 away from the substrate 10, forming a second metal layer 60 by a yellow light process on the metal material, and completing the formation of the gate insulating layer 50 by a self-alignment process using the second metal layer 60, wherein a first undercut structure 120 and a second undercut structure 130 are formed on the first surface S1 and the second surface S2 of the gate insulating layer, respectively;

[0067] S5: Depositing a layer of transparent electrode material on the entire surface of the gate insulation layer 50 away from the substrate 10 to form a first part 701, a second part 702, and a third part 703 of the first transparent electrode layer 70, wherein the first part and the third part are disconnected at the first undercut structure, and the second part and the third part are disconnected at the second undercut structure, and the two ends of the first part 701 are respectively connected to the active layer 40 and the source 201, and the two ends of the second part 702 are respectively connected to the active layer 40 and the drain 202. The two ends of the first part 701 are respectively connected to the first overlapping surface S3 of the active layer 40 and the source 201, and the two ends of the second part 702 are respectively connected to the second overlapping surface S4 of the active layer and the drain 202.

[0068] Among them, see Figure 3A A first metal layer 20 is deposited on the substrate 10. The first metal layer 20 can be any one of Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, or Mo / Cu / ITO.

[0069] Among them, see Figure 3B ,exist Figure 3A On the basis of, a first buffer layer and an active layer 40 are sequentially deposited on the substrate 10, the first buffer layer can be a SiOx single-layer structure or a SiNx / SiOx stacked structure, and the preparation material of the active layer 40 is at least one of IGZO, IGZTO, and IGTO.

[0070] Among them, see Figure 3C ,exist Figure 3B On the basis of, a gate insulating layer and a layer of metal material are deposited in sequence, the layer of metal material is patterned to form a second metal layer 60, and the patterning of the gate insulating layer is completed by a self-alignment process of the second metal layer 60; further, during the patterning process of the gate insulating layer, an undercut structure 2 can be formed at both ends of the gate insulating layer 50 by etching or the like.

[0071] Among them, see Figure 3D ,exist Figure 3C On the basis of the substrate, a layer of transparent electrode material is deposited and patterned to form a first transparent electrode layer 70. The first portion 701 and the second portion 702 of the first transparent electrode layer 70 are used to overlap the active layer 40 and the first metal layer 20 to ensure conduction of the TFT device. The third portion 703 of the first transparent electrode layer 70 is disconnected at the undercut structure 2 of the gate insulating layer to prevent the second metal layer 60 from contacting the source 201, the drain 202, and the active layer 40 below through the first transparent electrode layer 70.

[0072] Among them, see Figure 3E ,exist Figure 3D On the basis of, a passivation layer 80 is deposited and a layer of photoresist material is coated on the passivation layer 80 to prepare a flat layer 90, and the passivation layer 80 film layer is any one of a SiOx single layer structure, an AlOx single layer structure, and a SiOx / SiNx stacked layer structure.

[0073] Among them, see Figure 3F ,exist Figure 3E On this basis, the third metal layer 100 and the second transparent electrode layer 110 are further prepared.

[0074] In one embodiment, the step of preparing the second metal layer 60 and the gate insulating layer 50 further includes: adopting a half-tone process and using the same photomask to prepare the second metal layer 60 and the gate insulating layer 50 .

[0075] In one embodiment, the step of forming the undercut structure 2 at both ends of the gate insulation layer 50 includes: first forming a sacrificial layer complementary to the undercut structure 2 of the gate insulation layer 50 , and obtaining the undercut structure 2 by removing the sacrificial layer.

[0076] In another embodiment, the step of forming the undercut structure 2 at both ends of the gate insulating layer 50 further includes: forming the undercut structure 2 by controlling an etching angle of a yellow light process.

[0077] The present application also proposes a display panel, a display module, and a display device. The display panel, the display module, and the display device all include the above-mentioned array substrate, which will not be described in detail here.

[0078] The array substrate provided in this embodiment includes a substrate, a first metal layer, an interlayer insulating layer, an active layer, a gate insulating layer, a second metal layer, a first transparent electrode layer, and a second transparent electrode layer. The first metal layer is arranged on the substrate, the first metal layer includes a source electrode and a drain electrode, the active layer is arranged on a side of the first metal layer away from the substrate, the gate insulating layer is arranged on a side of the active layer away from the substrate, the second metal layer is arranged on a side of the gate insulating layer away from the substrate, the first transparent electrode layer is arranged on a side of the second metal layer away from the substrate, and the second transparent electrode layer is arranged on a side of the first transparent electrode layer away from the substrate, wherein the first surface and the second surface of the gate insulating layer are respectively formed with a first undercut structure and a second undercut structure. The first transparent electrode layer includes a first part, a second part, and a third part, the first part and the third part are disconnected at the first undercut structure, the second part and the third part are disconnected at the second undercut structure, the two ends of the first part are respectively connected to the first overlapping surface of the active layer and the source electrode, and the two ends of the second part are respectively connected to the second overlapping surface of the active layer and the drain electrode; the first metal layer is arranged on the side of the active layer close to the substrate, the source electrode and the drain electrode are overlapped with the two ends of the active layer through the first transparent electrode layer. Since the first transparent electrode layer itself is a conductor, the active layer in the overlapping area does not need to undergo a conductorization process, thereby reducing costs and alleviating the technical problem of high cost caused by the need for partial conductorization of the active layer in the existing array substrate.

[0079] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0080] The above is a detailed introduction to the array substrate, display panel, and array substrate preparation method provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer, the first metal layer is arranged on one side of the substrate, and the first metal layer includes a source electrode and a drain electrode; an interlayer insulating layer, the interlayer insulating layer being arranged on a side of the first metal layer away from the substrate; an active layer, the active layer being arranged on a side of the interlayer insulating layer away from the first metal layer; a gate insulating layer, the gate insulating layer being disposed on a side of the active layer away from the substrate; a second metal layer, the second metal layer being disposed on a side of the gate insulating layer away from the substrate, the second metal layer comprising a gate; a first transparent electrode layer, the first transparent electrode layer being disposed on a side of the gate away from the substrate; In which, the first surface and the second surface of the gate insulation layer are respectively formed with a first undercut structure and a second undercut structure, the first transparent electrode layer includes a first part, a second part, and a third part, the first part and the third part are disconnected at the first undercut structure, the second part and the third part are disconnected at the second undercut structure, the two ends of the first part are respectively connected to the first overlapping surface of the active layer and the source electrode, and the two ends of the second part are respectively connected to the second overlapping surface of the active layer and the drain electrode.

2. The array substrate according to claim 1, wherein: The first surface of the gate insulating layer and the first overlapping surface of the active layer form the first undercut structure, and the second surface of the gate insulating layer and the second overlapping surface of the active layer form the second undercut structure.

3. The array substrate according to claim 1, wherein: The first surface of the gate insulating layer and the surface of the gate away from the first transparent electrode layer form the first undercut structure, and the second surface of the gate insulating layer and the surface of the gate away from the first transparent electrode layer form the second undercut structure.

4. The array substrate according to any one of claims 2 to 3, wherein: The projection of the gate on the substrate falls within the projection range of the gate insulating layer on the substrate, and the projection of the gate insulating layer on the substrate falls within the projection range of the active layer on the substrate.

5. The array substrate according to any one of claims 2 to 3, wherein: The projection of the source electrode or the drain electrode in the direction of the substrate covers the projection of the active layer on the substrate.

6. The array substrate according to claim 5, wherein: The array substrate also includes a passivation layer, a flat layer, and a second electrode layer. The passivation layer is arranged on the side of the first transparent electrode layer away from the substrate, the flat layer is arranged on the side of the passivation layer away from the substrate, and the second electrode layer is arranged on the side of the flat layer away from the substrate. The second electrode layer is connected to the first part or the second part through a via hole penetrating the passivation layer and the flat layer.

7. The array substrate according to claim 6, wherein: The second electrode layer includes a third metal layer and a second transparent electrode layer, and the third metal layer is directly connected to the first portion or the second portion.

8. The array substrate according to claim 7, wherein: The third metal layer is continuously disposed on a side of the second transparent electrode layer facing the substrate, and the third metal layer at least covers the inner wall and the bottom of the via hole.

9. The array substrate according to claim 8, wherein: The third metal layer is any one of a molybdenum single layer structure, a molybdenum / aluminum stacked structure, a molybdenum / copper stacked structure, a molybdenum-titanium / copper stacked structure, a molybdenum-titanium / copper / molybdenum-titanium stacked structure, a titanium / aluminum / titanium stacked structure, and a titanium / copper / titanium stacked structure.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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