Power supply module, switching power supply control circuit, chip and power supply system

Abstract

The application provides a power supply module, a switching power supply control circuit, a chip and a power supply system, comprising: a demagnetization detection unit for detecting a demagnetization time; a working state detection unit for judging a working state of a junction field effect transistor based on the demagnetization time; a reference selection unit for generating a reference voltage, wherein the reference voltage is a first voltage value when a source-drain voltage of the junction field effect transistor is less than a set value, and the reference voltage is a second voltage value when the source-drain voltage is greater than the set value; wherein the first voltage value is greater than the second voltage value; the junction field effect transistor has a drain connected to a DC bus voltage and a gate connected to ground; and a voltage stabilizing unit for generating a stable power supply voltage based on the reference voltage. The application can reduce the loss of the junction field effect transistor and improve the system efficiency; no additional pin is needed to sample the DC bus voltage, thereby reducing the cost and facilitating the miniaturization of the system; and for different output voltages, no sampling resistor needs to be adjusted, thereby reducing the design difficulty.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a power supply module, a switching power supply control circuit, a chip, and a power supply system. Background Technology

[0002] In some high-power-factor power systems, high-voltage power supply technology is used. For example... Figure 1 The diagram shows a typical high-power-factor AC / DC flyback power supply 1 employing high-voltage power supply technology. When the chip power supply voltage VDD is lower than the chip power supply reference voltage Vref, the JFET is turned on, and the DC bus voltage HV charges the capacitor Cvdd through the JFET, simultaneously supplying power to other modules in the chip (e.g., control module 11). When VDD is higher than Vref, the JFET is turned off, and the capacitor Cvdd supplies power to the chip. Therefore, the VDD voltage can be stabilized at Vref.

[0003] like Figure 2 As shown Figure 1 The waveform diagram of the main nodes in the high power factor AC / DC flyback power supply 1, due to the source-drain voltage V on the JFET. JFET_DS The voltage difference between HV and VDD, from Figure 2 As can be seen, when the HV voltage is high, there is a large loss (voltage * current) on the JFET, which will lead to a decrease in system efficiency, excessive JFET temperature, and affect chip life.

[0004] Therefore, how to improve the system efficiency of high power factor power supply systems and avoid affecting chip lifespan has become one of the problems that urgently need to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power supply module, a switching power supply control circuit, a chip, and a power supply system to solve the problems of system efficiency and short chip lifespan in the prior art for high power factor power supply systems.

[0007] To achieve the above and other related objectives, the present invention provides a power supply module for supplying power to a switching power supply control circuit, the power supply module comprising at least:

[0008] Demagnetization detection unit, operating status detection unit, reference selection unit, junction field-effect transistor and voltage regulation unit;

[0009] The demagnetization detection unit detects the demagnetization time of the switching power supply;

[0010] The working state detection unit is connected to the output terminal of the demagnetization detection unit, and judges the working state of the junction field effect transistor based on the demagnetization time. When the demagnetization time is less than a preset time, it is judged that the source-drain voltage of the junction field effect transistor is less than a set value. When the demagnetization time is greater than the preset time, it is judged that the source-drain voltage of the junction field effect transistor is greater than the set value.

[0011] The reference selection unit is connected to the output terminal of the working state detection unit, and generates a reference voltage. When the source-drain voltage of the junction field effect transistor is less than the set value, the reference voltage is a first voltage value. When the source-drain voltage of the junction field effect transistor is greater than the set value, the reference voltage is a second voltage value. The first voltage value is greater than the second voltage value.

[0012] The drain of the junction field effect transistor is connected to a DC bus voltage, and the gate is grounded.

[0013] The voltage stabilizing unit is connected to the source of the junction field effect transistor and the output terminal of the reference selection unit, and generates a stable power supply voltage based on the reference voltage.

[0014] Optionally, the voltage stabilizing unit includes a switch tube and a first comparator. The first end of the switch tube is connected to the source of the junction field effect transistor, and the second end serves as the output terminal of the voltage stabilizing unit. The input terminals of the first comparator are respectively connected to the output terminal of the voltage stabilizing unit and the output terminal of the reference selection unit, and the output terminal is connected to the control terminal of the switch tube.

[0015] More optionally, the voltage stabilizing unit further includes a diode. The anode of the diode is connected to the second end of the switch tube, and the cathode serves as the output terminal of the voltage stabilizing unit instead of the second end of the switch tube.

[0016] More optionally, the working state detection unit includes a current source, a first switch, a second switch, a first capacitor, a clock signal generating subunit, and a second comparator.

[0017] The output terminal of the current source is connected to the upper plate of the first capacitor via the first switch, and the lower plate of the first capacitor is grounded.

[0018] The control terminal of the first switch is connected to the output terminal of the demagnetization detection unit. The first switch is turned on during demagnetization, and is turned off after demagnetization is completed.

[0019] The clock signal generation subunit is connected to the output end of the demagnetization detection unit, and generates a first clock signal and a second clock signal between two demagnetizations, wherein the second clock signal lags behind the first clock signal, and the first clock signal and the second clock signal are non-overlapping;

[0020] The second switch is connected in parallel to the two ends of the first capacitor, and the control end is connected to the second clock signal, and the first capacitor is cleared based on the second clock signal;

[0021] The input ends of the second comparator are connected to the upper plate of the first capacitor and a reference voltage respectively, and the working state judgment signal of the junction field effect transistor is output.

[0022] More optionally, the non-inverting input end of the second comparator is connected to the reference voltage, and the inverting input end is connected to the upper plate of the first capacitor.

[0023] More optionally, the reference selection unit comprises a flip-flop, a third switch and a fourth switch; the data input end of the flip-flop is connected to the output end of the working state detection unit, the clock end is connected to the first clock signal, the non-inverting output end outputs a first selection signal, and the inverting output end outputs a second selection signal; one end of the third switch is connected to a reference voltage with a first voltage value, and the control end is connected to the first selection signal; one end of the fourth switch is connected to a reference voltage with a second voltage value, and the control end is connected to the second selection signal; the second ends of the third switch and the fourth switch are connected together and serve as the output end of the reference selection unit.

[0024] To achieve the above object and other related objects, the present application provides a switching power supply control circuit, which at least comprises:

[0025] a control module, a working voltage generation module and a power supply module;

[0026] The power supply module generates a power supply voltage based on a direct current bus voltage;

[0027] The working voltage generation module is connected to the output end of the power supply module, and generates a working voltage of the control module based on the power supply voltage;

[0028] The control module generates a driving control signal of a switching power supply to control the output voltage of the switching power supply.

[0029] Optionally, the control module comprises a constant voltage or constant current control unit, a logic control unit and a driving unit;

[0030] The constant voltage or constant current control unit generates a control signal based on the feedback signal of the output voltage;

[0031] The logic control unit is connected to the output end of the constant voltage or constant current control unit, and generates a driving signal based on the control signal;

[0032] The driving unit is connected to the output end of the logic control unit, and generates the driving control signal.

[0033] To achieve the above object and other related objects, the application provides a chip, which at least comprises the above-mentioned switching power supply control circuit.

[0034] To achieve the above object and other related objects, the application provides a power supply system, which at least comprises an input circuit, a switching power supply conversion circuit, a second capacitor and the above-mentioned switching power supply control circuit.

[0035] The input circuit converts an alternating current power supply into a direct current bus voltage.

[0036] The switching power supply control circuit generates a driving control signal of the switching power supply conversion circuit.

[0037] The switching power supply conversion circuit converts the direct current bus voltage into a preset output voltage based on the driving control signal.

[0038] The upper plate of the second capacitor is connected to the output end of a voltage stabilizing unit in the power supply module, and the lower plate is grounded.

[0039] Optionally, the switching power supply conversion circuit is a BUCK, BOOST or BUCK-BOOST topology structure.

[0040] As mentioned above, the power supply module, the switching power supply control circuit, the chip and the power supply system of the application have the following beneficial effects:

[0041] 1. The power supply module, the switching power supply control circuit, the chip and the power supply system of the application use demagnetization time to reflect the change of the direct current bus voltage, adjust the power supply voltage based on the demagnetization time, reduce the loss of junction field effect transistor and improve the system efficiency.

[0042] 2. The power supply module and the switching power supply control circuit of the application do not need to sample the direct current bus voltage, thus the chip does not need to set additional pins to sample the direct current bus voltage, which reduces the cost and is conducive to the miniaturization of the system.

[0043] 3. The power supply system of the application does not need to adjust the sampling resistance for different output voltages, which reduces the design difficulty. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 The structure schematic diagram of a high power factor AC / DC flyback power supply using high voltage power supply technology is shown.

[0045] Figure 2 Waveform diagram of main nodes in high power factor AC / DC flyback power supply shown as Figure 1

[0046] Figure 3 Structural diagram of high power factor AC / DC flyback power supply shown as improving system efficiency.

[0047] Figure 4 Waveform diagram of main nodes in high power factor AC / DC flyback power supply shown as Figure 3

[0048] Figure 5 Setting principle diagram shown as preset voltage.

[0049] Figure 6 Structural diagram of power supply module of the application.

[0050] Figure 7 Waveform diagram of main nodes in power supply module of the application.

[0051] Figure 8 Diagram shown as relationship between input current and DC bus voltage.

[0052] Figure 9 Structural diagram of switching power supply control circuit, chip and power supply system of the application.

[0053] Element number explanation

[0054] 1 high power factor AC / DC flyback power supply

[0055] 11 control module

[0056] 2 high power factor AC / DC flyback power supply

[0057] 21 control module

[0058] 22 comparator

[0059] 23 inverter

[0060] 24 operational amplifier

[0061] 25 working voltage generating module

[0062] 3 switching power supply control circuit

[0063] 31 power supply module

[0064] 311 demagnetization detection unit

[0065] 312 working state detection unit​​

[0066] 312a clock signal generating subunit

[0067] 312b second comparator

[0068] 313 reference selection unit

[0069] 313a flip-flop

[0070] 314 voltage stabilizing unit

[0071] 314a first comparator

[0072] 32 working voltage generating module

[0073] 33 control module

[0074] 331 constant voltage or constant current control unit

[0075] 332 logic control unit

[0076] 333 driving unit

[0077] 4 input circuit

[0078] 41 rectifying module

[0079] 5 switching power conversion circuit DETAILED DESCRIPTION

[0080] The present application is herein described, by way of example only, with reference to embodiments thereof. It is to be understood that variations and modifications will be apparent to those skilled in the art and that the scope of the present application encompasses all such obvious variations and modifications. The embodiments described herein are to be understood as illustrative only and are not intended to limit the scope of the present application in any way.

[0081] Reference will now be made to the drawings, wherein: Figures 3-9 It is to be understood that the above-mentioned arrangements are merely meant to be illustrative of the present application and that changes and modifications can be made thereto without departing from the scope of the present application. It is to be further understood that the above-mentioned arrangements are not meant to be restrictive of the present application and that changes and modifications can be made thereto without departing from the scope of the present application.

[0082] In order to reduce the loss on the junction field effect transistor (JFET), a direct current bus voltage (HV) is generally sampled to control the switching of the JFET. As shown in Figure 3As shown in the figure, the DC bus voltage HV is sampled by resistors R1 and R2 to obtain the sampled voltage Vin. The comparator 22 compares the sampled voltage Vin with the preset voltage Vin_ref (at this time, the preset voltage corresponding to the DC bus voltage HV is Vhv_ref), and outputs the control signal of the switch S2. The output signal of the comparator 22 is inverted by the inverter 23 to obtain the control signal of the switch S1. When the sampled voltage Vin is greater than the preset voltage Vin_ref (that is, the DC bus voltage HV > Vhv_ref), through the adjustment of the operational amplifier 24 and the switching transistor Q1, the power supply voltage VDD will be stabilized at the reference voltage Vref2. When the sampled voltage Vin is less than the preset voltage Vin_ref (that is, the DC bus voltage HV < Vhv_ref), through the adjustment of the operational amplifier 24 and the switching transistor Q1, the power supply voltage VDD will be stabilized at the reference voltage Vref1, where Vref1 > Vref2. The power supply voltage VDD generates the operating voltage of the control module 21 through the operating voltage generation module 25.

[0083] As Figure 4 shown, when the voltage V between the source and drain of the junction field effect transistor JFET is JFET_DS higher, the on-time of the junction field effect transistor JFET is short, and less charge is supplied to the power supply voltage VDD; when the voltage V between the source and drain of the junction field effect transistor JFET is JFET_DS lower, the on-time of the junction field effect transistor JFET is long, and more charge is supplied to the power supply voltage VDD. This reduces the loss of the junction field effect transistor JFET and improves the efficiency of the system.

[0084] However, this solution requires sampling the DC bus voltage HV externally, which requires additional components. At the same time, it also requires the chip to have additional pins to receive the sampled voltage signal, increasing the cost and being unfavorable for system miniaturization. In addition, this solution has certain limitations in the application of the BUCK topology circuit because the DC bus voltage HV in the BUCK topology circuit is not a sine wave but is clamped at the output voltage Vout by the output capacitor. As Figure 5 shown, when designing the system, the preset voltage Vhv_ref must be designed between the peak value HVmax of the DC bus voltage and the output voltage Vout. Therefore, for different output voltages, different sampling resistors need to be placed, increasing the difficulty of system design.

[0085] Based on the above reasons, the present invention provides a power supply module, a switching power supply control circuit, a chip and a power supply system, which do not require sampling the DC bus voltage HV, but judge the working state of the system through the demagnetization detection of the system, and then control the switching of the junction field effect transistor JFET. The specific solution is as follows.

[0086] Embodiment 1

[0087] As Figure 6 shown in the figure, the embodiment provides a power supply module 31 for powering the switching power supply control circuit, the power supply module 31 comprises:

[0088] a demagnetization detection unit 311, a working state detection unit 312, a reference selection unit 313, a junction field effect transistor JFET and a voltage stabilizing unit 314.

[0089] As Figure 6 shown, the demagnetization detection unit 311 detects the demagnetization time of the switching power supply.

[0090] Specifically, any circuit structure capable of realizing demagnetization detection is applicable to the present application, including but not limited to obtaining demagnetization information based on inductance current, which will not be described one by one. The demagnetization detection unit 311 outputs a demagnetization time detection signal Tdemag, as an example, the demagnetization time detection signal Tdemag is high during demagnetization, and the demagnetization time detection signal Tdemag is low after demagnetization ends, that is, the duration of high level is the demagnetization time.

[0091] As Figure 6 shown, the working state detection unit 312 is connected to the output end of the demagnetization detection unit 311, and judges the working state of the junction field effect transistor JFET based on the demagnetization time, judges that the source-drain voltage of the junction field effect transistor JFET is less than a set value when the demagnetization time is less than a preset time, and judges that the source-drain voltage of the junction field effect transistor JFET is greater than the set value when the demagnetization time is greater than the preset time.

[0092] Specifically, in the embodiment, the working state detection unit 312 comprises a current source I, a first switch SW1, a second switch SW2, a first capacitor C1, a clock signal generation subunit 312a and a second comparator 312b.

[0093] More specifically, the output end of the current source I is connected to the upper plate of the first capacitor C1 via the first switch SW1, and the lower plate of the first capacitor C1 is grounded. The current flowing through the current source I can be set as needed, which will not be described one by one. The control end of the first switch SW1 is connected to the output end of the demagnetization detection unit 311 (controlled by the demagnetization time detection signal Tdemag), the first switch SW1 is controlled to be turned on by a high level signal during demagnetization, and the current source I charges the first capacitor C1; the first switch SW1 is controlled to be turned off by a low level signal after demagnetization ends, and the current source I stops charging the first capacitor C1.

[0094] More specifically, the clock signal generating subunit 312a is connected to the output terminal of the demagnetization detection unit 311, generating a first clock signal CLK1 and a second clock signal CLK2 between two demagnetization operations, wherein the second clock signal CLK2 lags behind the first clock signal CLK1, and the first clock signal CLK1 and the second clock signal CLK2 do not overlap. Figure 7 As shown in the example, after the demagnetization time detection signal Tdemag goes low (demagnetization ends), the first clock signal CLK1 immediately goes high; after the first clock signal CLK1 goes low, the second clock signal CLK2 immediately goes high, and before the demagnetization time detection signal Tdemag goes high again, the second clock signal CLK2 goes low. In practical applications, the first clock signal and the second clock signal are valid between two demagnetization cycles, and the two clock signals do not overlap; this embodiment is not the limitation.

[0095] More specifically, the second switch SW2 is connected in parallel across the first capacitor C1, and its control terminal is connected to the second clock signal CLK2. Based on the second clock signal CLK2, the first capacitor C1 is cleared. After the first capacitor C1 is fully charged and the voltage on the first capacitor C1 is read, the second clock signal CLK2 becomes valid, the second switch SW2 is turned on, and the voltage on the first capacitor C1 is cleared.

[0096] More specifically, the input terminals of the second comparator 312b are respectively connected to the upper plate of the first capacitor C1 and the reference voltage Vdemag_ref, and output the operating state judgment signal D of the junction field-effect transistor (JFET). In this embodiment, the non-inverting input terminal of the second comparator 312b is connected to the reference voltage Vdemag_ref, and the inverting input terminal is connected to the upper plate of the first capacitor C1. In actual use, the relationship between the input signal of the second comparator and the polarity of the corresponding input terminal can be set as needed. This can be adjusted by setting an inverter, as long as the logic of the present invention can be realized.

[0097] It should be noted that any circuit structure capable of obtaining the working state judgment signal D of the junction field effect transistor JFET based on the demagnetization time is applicable to the present application, and is not limited to the present embodiment. In addition, logically, when the demagnetization time is less than the preset time, it is judged that the source-drain voltage of the junction field effect transistor JFET is less than the set value, when the demagnetization time is greater than the preset time, it is judged that the source-drain voltage of the junction field effect transistor JFET is greater than the set value, and when the demagnetization time is equal to the preset time, it is judged that the source-drain voltage of the junction field effect transistor JFET is equal to the set value. However, in actual application, the comparator can only output "0" or "1" to represent the greater or smaller state, and cannot represent the equal state; due to the hysteresis characteristic of the comparator, when the to-be-judged signal is equal to the reference signal, the output result of the comparator is determined according to the change trend of the to-be-judged signal. Taking the second comparator 312b of the present application as an example, in the initial stage of charging of the first capacitor C1, the voltage on the first capacitor C1 is less than the reference voltage Vdemag_ref, at this time, the second comparator 312b outputs high level; when the voltage on the first capacitor C1 increases to the reference voltage Vdemag_ref, the output signal of the second comparator 312b will not flip immediately, but will flip to low level when the voltage on the first capacitor C1 is slightly greater than the reference voltage Vdemag_ref. Similarly, when the voltage on the first capacitor C1 is greater than the reference voltage Vdemag_ref, the second comparator 312b outputs low level; when the voltage on the first capacitor C1 gradually decreases to the reference voltage Vdemag_ref, the output signal of the second comparator 312b will not flip immediately, but will flip to high level when the voltage on the first capacitor C1 is slightly less than the reference voltage Vdemag_ref. In the present embodiment, since the demagnetization time is calculated by charging the first capacitor C1, and the final calculated demagnetization time is judged and the judgment result is read (CLK1 is effective), the first capacitor C1 is discharged in the stage of not reading the judgment result (CLK1 is invalid), therefore, when the demagnetization time is equal to the preset time, the judgment result given by the second comparator 312b is high level, that is, the source-drain voltage of the junction field effect transistor JFET is less than the set value.

[0098] As Figure 6As shown, the reference selection unit 313 is connected to the output terminal of the working state detection unit 312, and generates a reference voltage, which is a first voltage value Vref1 when the source-drain voltage of the junction field effect transistor JFET is less than the set value, and a second voltage value Vref2 when the source-drain voltage of the junction field effect transistor is greater than the set value; wherein the first voltage value Vref1 is greater than the second voltage value Vref2.

[0099] Specifically, in the present embodiment, the reference selection unit 313 includes a flip-flop 313a, a third switch SW3 and a fourth switch SW4. The data input terminal D of the flip-flop 313a is connected to the output terminal of the working state detection unit 312, the clock terminal CLK is connected to the first clock signal CLK1, the non-inverted output terminal outputs a first selection signal, and the inverted output terminal outputs a second selection signal; as an example, the flip-flop 313a is a D flip-flop. One end of the third switch SW3 is connected to a reference voltage having the first voltage value Vref1, and the control terminal is connected to the first selection signal. One end of the fourth switch SW4 is connected to a reference voltage having the second voltage value Vref2, and the control terminal is connected to the second selection signal. The second ends of the third switch SW3 and the fourth switch SW4 are connected together and serve as the output terminal of the reference selection unit 313.

[0100] It should be noted that any circuit structure capable of providing a corresponding reference voltage based on the working state judgment signal D of the junction field effect transistor JFET is applicable to the present application, and is not limited to the present embodiment. In the present embodiment, based on the hysteresis characteristic of the comparator, in actual application, when the source-drain voltage of the junction field effect transistor is equal to the set value, the reference voltage is the first voltage value Vref1.

[0101] As shown in FIG. 3, the junction field effect transistor JFET is connected between the output terminal of the working state detection unit 312 and the reference selection unit 313. Figure 6 As shown, the drain of the junction field effect transistor JFET is connected to the DC bus voltage HV, and the gate is grounded.

[0102] As shown in FIG. 3, the junction field effect transistor JFET is connected between the output terminal of the working state detection unit 312 and the reference selection unit 313. Figure 6 As shown, the voltage stabilizing unit 314 is connected to the source of the junction field effect transistor JFET and the output terminal of the reference selection unit 313, and generates a stable power supply voltage VDD based on the reference voltage.

[0103] Specifically, in the embodiment, the voltage stabilizing unit 314 includes a switch tube Q1 and a first comparator 314a, and the power supply voltage VDD is stabilized at the reference voltage. The first end of the switch tube Q1 is connected to the source of the junction field effect transistor JFET, and the second end is used as the output end of the voltage stabilizing unit 314. The input ends of the first comparator 314a are respectively connected to the output end of the voltage stabilizing unit 314 and the output end of the reference selection unit 313, and the output end is connected to the control end of the switch tube Q1. As an example, the non-inverting input end of the first comparator 314a is connected to the output end of the reference selection unit 313, and the inverting input end is connected to the output end of the voltage stabilizing unit 314, so as to realize negative feedback. In actual use, the relationship between the input signals of the first comparator and the corresponding input ends can be set as needed, and the inverter can be adjusted to realize the logic of the present application.

[0104] It should be noted that, in the embodiment, the switch tube Q1 is implemented by an NMOS tube, at this time, the first end of the switch tube Q1 is the drain, the second end is the source, and the control end is the gate. In actual use, the corresponding relationship of the ports of the switch tube Q1 can be adjusted adaptively according to the needs, and will not be described here.

[0105] Specifically, as another implementation manner of the present application, the voltage stabilizing unit 314 further includes a diode D1, the anode of the diode D1 is connected to the second end of the switch tube Q1, and the cathode is used as the output end of the voltage stabilizing unit 314 instead of the second end of the switch tube Q1, so as to limit the current flow direction and avoid current backflow.

[0106] Generally, the input current of the high power factor switching power supply system follows the DC bus voltage. In the embodiment, taking an AC / DC flyback power supply working in the inductive current critical conduction mode as an example, as shown in FIG. 2, I Figure 8 L is the primary side current of the transformer, the primary side peak current follows the DC bus voltage, and is a sinusoidal envelope. According to:

[0107]

[0108] It can be obtained that:

[0109] wherein, L is the inductance of the primary side of the transformer, I L_pk is the primary side peak current of the transformer, N is the turns ratio of the primary side and the secondary side of the transformer, Vout is the output voltage of the switching power supply, and Tdemag is the demagnetization time of the transformer. Since L, N, and Vout in the system are fixed quantities, the demagnetization time Tdemag is also a sinusoidal envelope following the DC bus voltage, and the size of the DC bus voltage can be judged according to the length of the demagnetization time.​

[0110] As shown in Figure 6 and Figure 7 shown, when demagnetizing, the first switch SW1 is turned on, the second switch SW2 is turned off, and the current source I charges the first capacitor C1; after demagnetization ends, the first switch SW1 is turned off, and the voltage on the first capacitor C1 obtained at this time is compared with the reference voltage Vdemag_ref, and the comparison result D is given to the input end of the flip-flop 314a; then, the first clock signal CLK1 is sent out again, and the comparison result is transmitted to the output end Q of the flip-flop 314a and After the first clock signal CLK becomes low, the second clock signal CLK2 is sent out, the second switch SW2 is turned on, and the voltage on the first capacitor C1 is cleared. In the stage of short demagnetization time (as a judgment basis, the comparison result of the voltage on the first capacitor C1 with the reference voltage Vdemag_ref), the power supply voltage VDD is charged to Vref1; in the stage of long demagnetization time, the power supply voltage VDD is charged to Vref2 (Vref1>Vref2).

[0111] The power supply module of the present application reflects the change of the DC bus voltage by demagnetization time, and adjusts the power supply voltage based on the demagnetization time, so that the loss of the junction field effect transistor can be reduced, the system efficiency can be improved, and the cost can be reduced.

[0112] Embodiment two

[0113] As shown in Figure 9 , the present embodiment provides a switching power supply control circuit 3, which comprises:

[0114] A power supply module 31, a working voltage generation module 32, and a control module 33.

[0115] As shown in Figure 9 , the power supply module 31 generates a power supply voltage VDD based on a DC bus voltage HV.

[0116] Specifically, the circuit structure and working principle of the power supply module 31 are referred to in embodiment one, which will not be described here.

[0117] As shown in Figure 9 , the working voltage generation module 32 is connected to the output end of the power supply module 31, and generates the working voltage of the control module 33 based on the power supply voltage VDD.

[0118] Specifically, the working voltage generation module 32 converts the power supply voltage VDD into the working voltage required by the control module 33, and the working voltage is several, which is set according to the requirement, and will not be described here.

[0119] As shown in Figure 9 The control module 33 generates a driving control signal GATE of the switching power supply to control the output voltage Vout of the switching power supply.

[0120] Specifically, in the present embodiment, the control module 33 comprises a constant voltage or constant current control unit 331, a logic control unit 332 and a driving unit 333. The constant voltage or constant current control unit 331 generates a control signal based on the feedback signal CS of the output voltage; in the present example, the constant voltage or constant current control unit 331 is also connected to the output end of the demagnetization detection unit 311, and generates the control signal based on the feedback signal CS of the output voltage and the demagnetization time detection signal Tdemag. The logic control unit 332 is connected to the output end of the constant voltage or constant current control unit 331, and generates a driving signal based on the control signal. The driving unit 333 is connected to the output end of the logic control unit 332, and generates the driving control signal GATE.

[0121] Embodiment Three

[0122] As shown in Figure 9 The present embodiment provides a chip comprising a switching power supply control circuit 3. The circuit structure and working principle of the switching power supply control circuit 3 are not described here.

[0123] As shown in Figure 9 The chip has 4 pins, namely a DC bus voltage pin HV, a power supply voltage pin VDD, a driving control signal pin GATE and a feedback signal pin CS; the number of pins is reduced, and the cost is reduced.

[0124] Embodiment Four

[0125] As shown in Figure 9 The present embodiment provides a power supply system comprising a switching power supply control circuit 3, an input circuit 4, a switching power supply conversion circuit 5 and a second capacitor C2.

[0126] As shown in Figure 9 The input circuit 4 converts an alternating current power supply AC INPUT into a DC bus voltage HV.

[0127] Specifically, in the present embodiment, the input circuit 4 comprises a rectification module 41 and an input capacitor Cin. The rectification module 41 rectifies the alternating current power supply AC INPUT to obtain the DC bus voltage HV, and the input capacitor Cin is connected to the output end of the rectification module 41 to stabilize the DC bus voltage HV.

[0128] As shown in Figure 9As shown, the switching power supply control circuit 3 generates the driving control signal GATE of the switching power supply conversion circuit 5.

[0129] Specifically, the switching power supply control circuit 3 generates the power supply voltage VDD based on the DC bus voltage HV, and adjusts the power supply voltage VDD according to the demagnetization time to realize the high-voltage power supply technology; at the same time, the switching power supply control circuit 3 generates the driving control signal GATE of the switching power supply conversion circuit 5 based on the feedback signal CS of the output voltage (as another example, also based on the demagnetization time); for specific structure and principle, please refer to embodiment one and embodiment two, which will not be described here.

[0130] As shown, Figure 9 The switching power supply conversion circuit 5 converts the DC bus voltage HV into the preset output voltage Vout based on the driving control signal GATE.

[0131] Specifically, in the embodiment, the switching power supply conversion circuit 5 adopts a flyback converter, including a transformer T, a power switch tube Q2, a sampling resistor Rcs, a freewheeling diode D2, an output capacitor Cout and a load LOAD. One end of the primary winding of the transformer T is connected to the DC bus voltage HV, and the other end is grounded in turn via the power switch tube Q2 and the sampling resistor Rcs; one end of the secondary winding of the transformer T is connected to the anode of the freewheeling diode D2, and the other end is grounded. The cathode of the freewheeling diode D2 is grounded via the output capacitor Cout. The load LOAD is connected in parallel across the output capacitor Cout.

[0132] It should be noted that the switching power supply conversion circuit 5 includes but is not limited to BUCK, BOOST, BUCK-BOOST topology structure, which is not limited to the embodiment. Among them, BUCK, BOOST, BUCK-BOOST topology structure not only includes typical structure but also includes their derivative structure, which will not be described here.

[0133] The power supply system of the application does not need to adjust the sampling resistor for different output voltages, reducing the design difficulty.

[0134] The application provides a power supply module, a switching power supply control circuit, a chip and a power supply system, which comprise a demagnetization detection unit, a working state detection unit, a reference selection unit, a junction field effect transistor and a voltage stabilizing unit; the demagnetization detection unit detects the demagnetization time of the switching power supply; the working state detection unit is connected to the output end of the demagnetization detection unit, and judges the working state of the junction field effect transistor based on the demagnetization time; when the demagnetization time is less than the preset time, it is judged that the source-drain voltage of the junction field effect transistor is less than a set value; when the demagnetization time is greater than the preset time, it is judged that the source-drain voltage of the junction field effect transistor is greater than the set value; the reference selection unit is connected to the output end of the working state detection unit, and generates a reference voltage; when the source-drain voltage of the junction field effect transistor is less than the set value, the reference voltage is a first voltage value; when the source-drain voltage of the junction field effect transistor is greater than the set value, the reference voltage is a second voltage value; wherein the first voltage value is greater than the second voltage value; the drain of the junction field effect transistor is connected to a direct current bus voltage, and the gate is grounded; the voltage stabilizing unit is connected to the source of the junction field effect transistor and the output end of the reference selection unit, and generates a stable power supply voltage based on the reference voltage. The power supply module, the switching power supply control circuit, the chip and the power supply system can reduce the loss of the junction field effect transistor, improve the system efficiency, do not need to set an additional pin to sample the direct current bus voltage, reduce the cost, are beneficial to the miniaturization of the system, do not need to adjust the sampling resistor for different output voltages, and reduce the design difficulty. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.

[0135] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A power supply module for powering a switching power supply control circuit, characterized in that, The power supply module at least comprises: The demagnetization detection unit, the working state detection unit, the reference selection unit, the junction field effect transistor and the voltage stabilizing unit; The demagnetization detection unit detects the demagnetization time of the switching power supply; The working state detection unit is connected to the output end of the demagnetization detection unit, and judges the working state of the junction field effect transistor based on the demagnetization time; when the demagnetization time is less than a preset time, it is judged that the source-drain voltage of the junction field effect transistor is less than a set value; when the demagnetization time is greater than the preset time, it is judged that the source-drain voltage of the junction field effect transistor is greater than the set value; The reference selection unit is connected to the output end of the working state detection unit and generates a reference voltage; when the source-drain voltage of the junction field effect transistor is less than the set value, the reference voltage is a first voltage value; when the source-drain voltage of the junction field effect transistor is greater than the set value, the reference voltage is a second voltage value; wherein the first voltage value is greater than the second voltage value; The drain of the junction field effect transistor is connected to the DC bus voltage, and the gate is grounded. The voltage stabilizing unit is connected to the source of the junction field effect transistor and the output end of the reference selection unit, and generates a stable power supply voltage based on the reference voltage.

2. The power supply module of claim 1, wherein: The voltage stabilizing unit comprises a switch tube and a first comparator; the first end of the switch tube is connected to the source of the junction field effect transistor, and the second end serves as the output end of the voltage stabilizing unit; the input ends of the first comparator are respectively connected to the output end of the voltage stabilizing unit and the output end of the reference selection unit, and the output end is connected to the control end of the switch tube.

3. The power supply module of claim 2, wherein: The voltage stabilizing unit further comprises a diode, the anode of the diode is connected to the second end of the switch tube, and the cathode serves as the output end of the voltage stabilizing unit instead of the second end of the switch tube.

4. The power supply module according to any one of claims 1 to 3, characterized in that: The working state detection unit comprises a current source, a first switch, a second switch, a first capacitor, a clock signal generating subunit and a second comparator; The output end of the current source is connected to the upper plate of the first capacitor via the first switch, and the lower plate of the first capacitor is grounded. The control end of the first switch is connected to the output end of the demagnetization detection unit, and the first switch is turned on during demagnetization and turned off after demagnetization is completed. The clock signal generating subunit is connected to the output end of the demagnetization detection unit, and generates a first clock signal and a second clock signal between two demagnetizations, wherein the second clock signal lags behind the first clock signal, and the first clock signal and the second clock signal are non-overlapping. The second switch is connected in parallel across the first capacitor, and the control end is connected to the second clock signal, which clears the first capacitor based on the second clock signal. The input ends of the second comparator are respectively connected to the upper plate of the first capacitor and a reference voltage, and output the working state judgment signal of the junction field effect transistor.

5. The power module of claim 4, wherein: The non-inverting input end of the second comparator is connected to the reference voltage, and the inverting input end is connected to the upper plate of the first capacitor.

6. The power module of claim 4, wherein: The reference selection unit comprises a flip-flop, a third switch and a fourth switch; the data input end of the flip-flop is connected to the output end of the working state detection unit, the clock end is connected to the first clock signal, the positive phase output end outputs a first selection signal, and the inverting output end outputs a second selection signal; one end of the third switch is connected to a reference voltage with a first voltage value, and the control end is connected to the first selection signal; one end of the fourth switch is connected to a reference voltage with a second voltage value, and the control end is connected to the second selection signal; the second ends of the third switch and the fourth switch are connected together and serve as the output end of the reference selection unit.

7. A switching power supply control circuit, characterized by comprising: The switching power supply control circuit at least comprises: a control module, a working voltage generation module and the power supply module according to any one of claims 1-6; the power supply module generates a power supply voltage based on the DC bus voltage; the working voltage generation module is connected to the output end of the power supply module, generates the working voltage of the control module based on the power supply voltage; the control module generates a driving control signal of the switching power supply to control the output voltage of the switching power supply.

8. The switching power supply control circuit according to claim 7, characterized by: The control module comprises a constant voltage or constant current control unit, a logic control unit and a driving unit; the constant voltage or constant current control unit generates a control signal based on the feedback signal of the output voltage; the logic control unit is connected to the output end of the constant voltage or constant current control unit, generates a driving signal based on the control signal; the driving unit is connected to the output end of the logic control unit, and generates the driving control signal.

9. A chip, characterized by The chip at least comprises the switching power supply control circuit according to any one of claims 7-8.

10. A power supply system characterized by comprising: The power supply system at least comprises an input circuit, a switching power supply conversion circuit, a second capacitor and the switching power supply control circuit according to any one of claims 7-8; the input circuit converts an alternating current power supply into a DC bus voltage; the switching power supply control circuit generates a driving control signal of the switching power supply conversion circuit; the switching power supply conversion circuit converts the DC bus voltage into a preset output voltage based on the driving control signal; the upper plate of the second capacitor is connected to the output end of the voltage stabilizing unit in the power supply module, and the lower plate is grounded.

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