Display substrate and display panel

Abstract

The present application provides a display substrate and a display panel. The display substrate comprises: a substrate having a display area and a non-display area surrounding the display area, the substrate having multiple thin-film transistors therein, each having a source electrode, a drain electrode, and a gate electrode; a conductive layer located on the substrate, the conductive layer comprising multiple display conductive layers located within the display area, and a first bypass conductive layer located within the non-display area; wherein the first bypass conductive layer is insulated from the display conductive layer, electrically connected to the source electrode, and serves as a common electrode. By adding the first bypass conductive layer within the non-display area of ​​the plate, the present application can shorten the width of the VDD common electrode or VSS common electrode region, thereby further shortening the width of the non-display area of ​​the display substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays offer a wide range of potential applications, including self-luminescence, high brightness, wide viewing angles, high contrast, flexibility, and low energy consumption. Currently, the market is increasingly favoring narrow-border display panel designs, which significantly improve the overall performance and display quality of display devices. Consequently, these designs are becoming a market trend and a research hotspot for major manufacturers. Summary of the Invention

[0003] The present application provides a display substrate and a display panel, aiming to solve the technical problem of how to further shorten the width of the border area of ​​the display substrate.

[0004] In a first aspect, the present application provides a display substrate, comprising:

[0005] A substrate having a display area and a non-display area surrounding the display area, wherein the substrate has a plurality of thin film transistors, each of which has a source electrode, a drain electrode, and a gate electrode;

[0006] A conductive layer is located on the substrate and includes a plurality of display conductive layers located in the display area and a first bypass conductive layer located in the non-display area;

[0007] The first bypass conductive layer is insulated from the display conductive layer, the display conductive layer is electrically connected to the source electrode, and the first bypass conductive layer serves as a common electrode.

[0008] In some embodiments, the substrate has a first power common electrode corresponding to the non-display area;

[0009] The first bypass conductive layer is electrically connected to the first power common electrode.

[0010] In some embodiments, an orthographic projection of the first power common electrode on the substrate surface coincides with an orthographic projection of the first bypass conductive layer on the substrate surface.

[0011] In some embodiments, the first bypass conductive layer is arranged in a ring shape around the display area; or

[0012] The first bypass conductive layer is located on one side of the display area; or

[0013] The first bypass conductive layer is located on two opposite sides of the display area.

[0014] In some embodiments, the first power common electrode is arranged in a ring shape around the display area;

[0015] The second power common electrode is arranged in a ring shape around the display area.

[0016] In some embodiments, the substrate further includes a second power common electrode located in the non-display area;

[0017] The power-on layer further includes a second bypass conductive layer located in the non-display area, and the power-on layer further includes the second bypass conductive layer, and the second bypass conductive layer is insulated from the first bypass conductive layer;

[0018] The display conductive layer is insulated from the second bypass conductive layer, and the second bypass conductive layer is electrically connected to the second power common electrode.

[0019] In some embodiments, an orthographic projection of the second power common electrode on the substrate surface coincides with an orthographic projection of the second bypass conductive layer on the substrate surface.

[0020] In some embodiments, the second bypass conductive layer is arranged in a ring shape around the first bypass conductive layer; or

[0021] The second bypass conductive layer is located on one side of the display area; or

[0022] The second bypass conductive layer is located on two opposite sides of the display area.

[0023] In some embodiments, one of the first power common electrode and the second power common electrode is a VDD common electrode, and the other is a VSS common electrode.

[0024] In some embodiments, the substrate comprises:

[0025] substrate;

[0026] a first electrode layer, the first electrode layer being provided on the substrate;

[0027] a first buffer layer, the first buffer layer being disposed on the substrate and covering the first electrode layer;

[0028] a second electrode layer, the second electrode layer being disposed on the first buffer layer, the second electrode layer being opposite to the first electrode layer, the second electrode layer comprising a drain electrode, a source electrode, and a conductive channel, wherein the conductive channel is located between the drain electrode and the source electrode;

[0029] a first insulating layer, the first insulating layer being disposed on the conductive channel, and the gate being disposed on the first insulating layer;

[0030] a dielectric layer, the dielectric layer being disposed on the first buffer layer and covering the second electrode layer and the gate;

[0031] a third electrode layer, the third electrode layer including a first electrode, a second electrode, a first power common electrode, and a second power common electrode, wherein the first electrode is connected to the source electrode through the dielectric layer, and the second electrode is connected to the drain electrode through the dielectric layer;

[0032] a passivation layer, the passivation layer covering the third electrode layer;

[0033] The flat layer covers the passivation layer, the conductive layer is located on the flat layer, and the conductive layer is connected to the first electrode.

[0034] In some embodiments, the display substrate further includes a pixel defining layer, the pixel defining layer covering the planar layer;

[0035] The pixel defining layer has a pixel pit, and the display conductive layer is located in the pixel pit.

[0036] In a second aspect, the present application provides a display panel comprising the display substrate as described in the first aspect.

[0037] The present application adds a first bypass conductive layer in the non-display area of ​​the electrode plate and uses the first bypass conductive layer as a common electrode. That is, the drain electrodes of the thin film transistors in the display area can be electrically connected to the first bypass conductive layer, or the source electrodes of the thin film transistors in the display area can be electrically connected to the first bypass conductive layer, thereby replacing the original VDD common electrode or VSS common electrode, or reducing the width of the original VDD common electrode or VSS common electrode. That is to say, the first bypass conductive layer can be directly used as a common electrode, or the first bypass conductive layer can form another parallel path of the VDD common electrode or VSS common electrode. Common electrode, thereby shortening the width of the VDD common electrode or VSS common electrode area, thereby further shortening the width of the non-display area of ​​the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a planar schematic diagram of a display substrate provided in an embodiment of the present application;

[0040] Figure 2 Schematic diagram of a structure of a display substrate provided in an embodiment of the present application;

[0041] Figure 3 is another planar schematic diagram of a display substrate provided in an embodiment of the present application;

[0042] Figure 4 is another planar schematic diagram of a display substrate provided in an embodiment of the present application;

[0043] Figure 5 is another planar schematic diagram of a display substrate provided in an embodiment of the present application;

[0044] Figure 6 is another structural schematic diagram of a display substrate provided in an embodiment of the present application;

[0045] Figure 7 is another structural schematic diagram of a display substrate provided in an embodiment of the present application;

[0046] Figure 8 This is another structural schematic diagram of the display substrate provided in an embodiment of the present application.

[0047] Wherein, 10 is a substrate, 101 is a display area, 102 is a non-display area, and 103 is a thin film transistor;

[0048] 11 substrate, 12 first electrode layer, 121 first connecting electrode, 122 second connecting electrode, 123 third connecting electrode, 13 first buffer layer, 14 second electrode layer, 141 source electrode, 142 drain electrode, 143 conductive channel, 144 first insulating layer, 145 gate electrode, 146 fourth connecting electrode, 147 fifth connecting electrode, 15 dielectric layer, 16 third electrode layer, 161 first power common electrode, 162 second power common electrode, 163 first electrode, 164 second electrode, 165 sixth connecting electrode, 166 seventh connecting electrode, 17 passivation layer, 18 planarization layer;

[0049] 20 is a conductive layer, 21 is a display conductive layer, 22 is a first bypass conductive layer, and 23 is a second bypass conductive layer;

[0050] 30-pixel limiting layer, 31-pixel pit. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0052] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0053] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to make and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art will recognize that the invention can be practiced without these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0054] The embodiments of the present application provide a display substrate and a display panel, which are described in detail below.

[0055] First, see Figure 1 as well as Figure 2 , Figure 1 1 shows a planar schematic diagram of a display substrate in an embodiment of the present application, Figure 2 A schematic structural diagram of a display substrate in an embodiment of the present application is shown, wherein the display substrate includes:

[0056] The substrate 10 includes a display area 101 and a non-display area 102 surrounding the display area 101 . The substrate 10 includes a plurality of thin film transistors 103 . The thin film transistors 103 include a source electrode 141 , a drain electrode 142 , and a gate electrode 145 .

[0057] The conductive layer 20 is located on the substrate 10 and includes a plurality of display conductive layers 21 located in the display area 101 and a first bypass conductive layer 22 located in the non-display area 102 ;

[0058] The first bypass conductive layer 22 is insulated from the display conductive layer 21 , the display conductive layer 21 is electrically connected to the source electrode 141 , and the first bypass conductive layer 22 serves as a common electrode.

[0059] Specifically, the substrate 10 is used to provide a preparation basis for the conductive layer 20. For example, the conductive layer 20 is prepared on the flat layer 18 of the substrate 10, so as to form a conductive layer 20 pattern with a highly consistent process film thickness. Among them, the thin film transistor 103 controls whether the source electrode 141 and the drain electrode 142 are conductive by controlling the access voltage of its gate 145. Ultimately, the thin film transistor 103 is used to control whether the pixel light emitting diode is connected to the power supply. Exemplarily, the thin film transistor 103 can be an amorphous silicon thin film transistor 103, a low-temperature polycrystalline silicon thin film transistor 103, a high-temperature polycrystalline silicon thin film transistor 103, or an indium gallium zinc thin film transistor 103.

[0060] Generally, the substrate 10 is rectangular in shape, the display area 101 is a rectangular area located on the surface of the rectangular substrate 10, and the non-display area 102 is a square-shaped area surrounding the display area 101. It is understood that the shape of the substrate 10 and the display area 101 can also be other shapes, such as a circle, a regular hexagon, etc.

[0061] In some embodiments of the present application, the substrate 10 may further include a capacitor, and the capacitor and the thin film transistor 103 may form an xTxC light-emitting diode control circuit solution, for example, a 1T1C light-emitting diode control circuit solution, i.e., a light-emitting diode control circuit including one thin film transistor 103 and one capacitor; another example, a 7T2C light-emitting diode control circuit solution, i.e., a light-emitting diode control circuit including seven thin film transistors 103 and two capacitors; another example, a 3T1C light-emitting diode control circuit solution, i.e., a light-emitting diode control circuit including three thin film transistors 103 and one capacitor.

[0062] The power-carrying layer 20 is located on the substrate 10. On the one hand, it forms a display conductive layer 21 located in the display area 101. The display conductive layer 21 can serve as the cathode or anode of the OLED light-emitting diode to facilitate powering the light-emitting diode; on the other hand, it forms a first bypass conductive layer 22 located in the non-display area 102. The first bypass conductive layer 22 can be directly used as a common electrode, or directly used as a common electrode for an additional parallel path, thereby eliminating the original VDD common electrode or VSS common electrode, or reducing the width of the original VDD common electrode or VSS common electrode.

[0063] In an embodiment of the present application, the present application adds a first bypass conductive layer 22 in the non-display area 102 of the electrode plate, and uses the first bypass conductive layer 22 as a common electrode, that is, the drain electrodes of the thin film transistors 103 in the display area 101 can be electrically connected to the first bypass conductive layer 22, or the sources of the thin film transistors 103 in the display area 101 can be electrically connected to the first bypass conductive layer 22, thereby replacing the original VDD common electrode or VSS common electrode, or reducing the width of the original VDD common electrode or VSS common electrode, that is, the first bypass conductive layer 22 can be directly used as a common electrode, or the first bypass conductive layer 22 can form another parallel path of the VDD common electrode or VSS common electrode. Common electrode, thereby shortening the width of the VDD common electrode or VSS common electrode area, thereby further shortening the width of the non-display area of ​​the display substrate.

[0064] At the same time, because the first bypass conductive layer 22 and the underlying metal layer (e.g., the third electrode layer 16) are separated by an inorganic insulating layer, a thick passivation layer 17, and organic insulating layers such as the planarization layer 18, the coupling capacitance between the first bypass conductive layer 22 and the underlying metal layer is low, thereby substantially eliminating the risk of capacitive breakdown. Furthermore, the first bypass conductive layer 22 added to the non-display area 102 and the display conductive layer 21 in the display area 101 can be fabricated and formed in the same process, resulting in the first bypass conductive layer 22 and the display conductive layer 21 having the same properties (e.g., thickness, compression modulus, etc.), which helps ensure uniformity in the process film thickness and dimensions of the conductive layer 20 pattern.

[0065] In some embodiments of the present application, for example, the first bypass conductive layer 22 can form a common electrode used as another parallel path of the VDD common electrode or the VSS common electrode, see further. Figure 2 The substrate 10 has a first power common electrode 161 inside corresponding to the non-display area 102. The first bypass conductive layer 22 is electrically connected to the first power common electrode 161.

[0066] It should be noted that after the first bypass conductive layer 22 is electrically connected to the first power common electrode 161, the first bypass conductive layer 22 and the first power common electrode 161 form a parallel path, and current can flow through the first power common electrode 161 and the first bypass conductive layer 22 at the same time. Therefore, the width of the first power common electrode 161 can be reduced at this time, and the width of the non-display area 102 of the display substrate can be compressed without causing an increase in impedance.

[0067] In some embodiments of the present application, a via hole can be opened on the substrate 10 (for example, the flat layer 18 and the passivation layer 17 of the substrate 10), and the via hole extends from the non-display area 102 of the substrate 10 to the first power common electrode 161. When preparing the power-on layer 20, the first bypass conductive layer 22 extends into the via hole, thereby realizing electrical connection between the first bypass conductive layer 22 and the first power common electrode 161.

[0068] Further, in some embodiments of the present application, for example, for an embodiment in which the first bypass conductive layer 22 is electrically connected to the first power common electrode 161, please refer to Figure 2 The orthographic projection of the first power common electrode 161 on the surface of the substrate 10 coincides with the orthographic projection of the first bypass conductive layer 22 on the surface of the substrate 10. That is, the first power common electrode 161 and the first bypass conductive layer 22 coincide with each other in the vertical direction. This can avoid the first power common electrode 161 and the first bypass conductive layer 22 being located at different positions in the non-display area 102, thereby preventing the first power common electrode 161 and the first bypass conductive layer 22 from being located at different positions in the non-display area 102, thereby increasing the width of the non-display area 102 of the display substrate. This is beneficial for further compressing the width of the non-display area 102 of the display substrate.

[0069] In some embodiments of the present application, see Figure 1 , wherein the first bypass conductive layer 22 is arranged in a ring shape around the display area 101.

[0070] In some embodiments of the present application, see Figure 3 , Figure 3 Another schematic plan view of the display substrate in an embodiment of the present application is shown, wherein the first bypass conductive layer 22 is located on one side of the display area 101 .

[0071] In some embodiments of the present application, see Figure 4 , Figure 4 Another planar schematic diagram of the display substrate in an embodiment of the present application is shown, wherein the first bypass conductive layer 22 is located on two opposite sides of the display area 101, for example, the first bypass conductive layer 22 is located on the left and right sides of the display area 101; for another example, the first bypass conductive layer 22 is located on the upper and lower sides of the display area 101.

[0072] It is understandable that the first bypass conductive layer 22 may also have other arrangements. For example, the first bypass conductive layer 22 may be divided into multiple linear electrode traces and arranged on one side or two opposite sides of the display area 101 .

[0073] In some embodiments of this application, see Figure 5 as well as Figure 6 , Figure 5 Another schematic plan view of a display substrate in an embodiment of the present application is shown. Figure 6Another structural diagram of a display substrate in an embodiment of the present application is shown, wherein the substrate 10 further includes a second power common electrode 162 located in the non-display area 102;

[0074] The power-on layer 20 further includes a second bypass conductive layer 23 located in the non-display area 102 . The second bypass conductive layer 23 is insulated from the first bypass conductive layer 22 . The display conductive layer 21 is insulated from the second bypass conductive layer 23 . The second bypass conductive layer 23 is electrically connected to the second power common electrode 162 .

[0075] It should be noted that, since a second bypass conductive layer 23 electrically connected to the second power common electrode 162 is further provided, the second bypass conductive layer 23 forms a parallel path of the second power common electrode 162, and current can flow through the second power common electrode 162 and the second bypass conductive layer 23 at the same time. Therefore, while further realizing the compression of the width of the non-display area 102 of the display substrate, it will not cause the impedance of the second power common electrode 162 to increase.

[0076] In some embodiments of the present application, see Figure 7 , Figure 7 Another structural schematic diagram of the display substrate in an embodiment of the present application is shown. The first bypass conductive layer 22 and the second bypass conductive layer 23 can also be connected to the first power common electrode 161 at the same time, so that the first power common electrode 161 has two parallel paths at the same time, which is beneficial to further reduce the impedance of the first power common electrode 161.

[0077] It can be understood that the first bypass conductive layer 22 and the second bypass conductive layer 23 can also be connected to the second power common electrode 162 at the same time, so that the second power common electrode 162 has two parallel paths at the same time.

[0078] In some embodiments of the present application, a via hole can be opened on the substrate 10 (for example, the flat layer 18 and the passivation layer 17 of the substrate 10), and the via hole extends from the non-display area 102 of the substrate 10 to the second power common electrode 162. When preparing the power-on layer 20, the second bypass conductive layer 23 extends into the via hole, thereby realizing electrical connection between the second bypass conductive layer 23 and the second power common electrode 162.

[0079] In some embodiments of the present application, for example, for an embodiment in which the second bypass conductive layer 23 is electrically connected to the second power common electrode 162, please refer to Figure 6The orthographic projection of the second power common electrode 162 on the surface of the substrate 10 overlaps with the orthographic projection of the second bypass conductive layer 23 on the surface of the substrate 10. In other words, the second power common electrode 162 and the second bypass conductive layer 23 overlap in the vertical direction, which can avoid the phenomenon of increasing the width of the non-display area 102 of the display substrate when the second power common electrode 162 and the second bypass conductive layer 23 are located at different positions within the non-display area 102, thereby further reducing the width of the non-display area 102 of the display substrate.

[0080] In some embodiments of the present application, Figure 6 As shown, the second bypass conductive layer 23 is arranged in a ring shape around the first bypass conductive layer 22. In some embodiments of the present application, the second bypass conductive layer 23 is located on one side of the display area 101. In some embodiments of the present application, the second bypass conductive layer 23 is located on two opposite sides of the display area 101. It is understood that the second bypass conductive layer 23 can also have other arrangements, such as dividing the second bypass conductive layer 23 into multiple linear electrodes and arranging them on one side or two opposite sides of the display area 101.

[0081] In some embodiments of the present application, one of the first power common electrode 161 and the second power common electrode 162 is a VDD common electrode, and the other is a VSS common electrode. It is understandable that the first power common electrode 161 and the second power common electrode 162 can also be common electrode routings for other signals (such as display screen signals).

[0082] In some embodiments of the present application, the first power common electrode 161 is arranged in a ring shape around the display area 101. The second power common electrode 162 is arranged in a ring shape around the display area 101. It is understood that the first power common electrode 161 and the second power common electrode 162 can also be arranged in a linear shape on one side or on two opposite sides of the display area 101.

[0083] Further, in some embodiments of the present application, referring to the figure, the substrate 10 includes a substrate 11, a first electrode layer 12, a first buffer layer 13, a second electrode layer 14, a first insulating layer 144, a dielectric layer 15, a third electrode layer 16, a passivation layer 17 and a planar layer 18, the first electrode layer 12 is provided on the substrate 11; the first buffer layer 13 is provided on the substrate 11 and covers the first electrode layer 12; the second electrode layer 14 is provided on the first buffer layer 13, the second electrode layer 14 is opposite to the first electrode layer 12, and the second electrode layer 14 includes a drain electrode 142, a source electrode 141 and a conductive channel 143, and the conductive channel 143 is located between the drain electrode 142 and the source electrode 141 ; The first insulating layer 144 is arranged on the conductive channel 143, and the gate 145 is arranged on the first insulating layer 144; the dielectric layer 15 is arranged on the first buffer layer 13 and covers the second electrode layer 14 and the gate 145; the third electrode layer 16 includes a first electrode 163, a second electrode 164, a first power common electrode 161 and a second power common electrode 162, and the first electrode 163 passes through the dielectric layer 15 to connect to the source electrode 141, and the second electrode 164 passes through the dielectric layer 15 to connect to the drain electrode 142; the passivation layer 17 covers the third electrode layer 16; the flat layer 18 covers the passivation layer 17, and the power-on layer 20 is located on the flat layer 18, showing that the conductive layer 21 is connected to the first electrode 163.

[0084] It should be noted that the first electrode layer 12 and the first buffer layer 13 are opposite to the second electrode layer 14, the drain electrode 142 of the second electrode 164, the source electrode 141 and the conductive channel 143, the first insulating layer 144 and the gate 145 constitute the thin film transistor 103. When the conductive channel 143 is an N channel and the gate 145 is connected to the positive voltage, the conductive channel 143 causes electrons to gather in the N channel under the action of the gate 145 and the first electrode layer 12, thereby connecting the drain electrode 142 and the source electrode 141; conversely, when the gate 145 is connected to the negative voltage, the conductive channel 143 causes electrons to gather on the side adjacent to the first electrode layer 12 under the action of the gate 145 and the first electrode layer 12, thereby disconnecting the drain electrode 142 and the source electrode 141. In addition, the first buffer layer 13, the dielectric layer 15 and the passivation layer 17 can realize the insulation protection of the electrode layers they cover (such as the first electrode layer 12, the second electrode layer 14 and the third electrode layer 16), and the flat layer 18 can provide a flat preparation reference surface for the pixel defining layer 30 and the power-carrying layer 20, so as to facilitate the precise preparation of the pixel defining layer 30 and the power-carrying layer 20, and ensure the yield rate of the light-emitting diodes prepared in the pixel pits 31 of the pixel defining layer 30.

[0085] In some embodiments of the present application, for example, for an embodiment in which the substrate 10 further includes a capacitor, please refer to Figure 8 , Figure 8FIG2 shows another schematic diagram of the structure of a display substrate in an embodiment of the present application, in which the first electrode layer 12 includes a first connecting electrode 121, a second connecting electrode 122, and a third connecting electrode 123. The second electrode layer 14 also includes a fourth connecting electrode 146 and a fifth connecting electrode 147. The third electrode layer 16 also includes a sixth connecting electrode 165 and a seventh connecting electrode 166. The first connecting electrode 121 is electrically connected to the fourth connecting electrode 146, and the fourth connecting electrode 146 is electrically connected to the sixth connecting electrode 165. The drain electrode 142, the source electrode 141, and the conductive channel 143 are opposite to the second connecting electrode 122. The third connecting electrode 123 is opposite to the fifth connecting electrode 147. The seventh connecting electrode 166 is electrically connected to the third connecting electrode 123.

[0086] It should be noted that the first connection electrode 121 and the fourth connection electrode 146 are electrically connected to form a conductive circuit, while the drain electrode 142, the source electrode 141, and the conductive channel 143 are opposite the second connection electrode 122, so that the second connection electrode 122 and the gate 145 form a capacitor structure, thereby driving the movement of electrons in the conductive channel 143. At the same time, the third connection electrode 123 and the fifth connection electrode 147 form a capacitor, thereby forming a substrate 10 structure including a thin film field effect transistor and a capacitor.

[0087] It can be understood that the above-mentioned drawings only illustrate the arrangement of the connecting electrodes of the circuit scheme corresponding to the 1T1C light-emitting diode control circuit scheme. In fact, for light-emitting diode control circuit schemes with a larger number of thin-film transistors 103 and capacitors (such as 3T1C and 7T2C light-emitting diode circuit control schemes), the first electrode layer 12 and the second electrode layer 14 can also have a larger number of patterned connecting electrodes.

[0088] Further, in some embodiments of the present application, see Figure 7 or Figure 8 The display substrate also includes a pixel defining layer 30, which covers the flat layer 18. The pixel defining layer 30 has a pixel pit 31, and the display conductive layer 21 is located in the pixel pit 31, so as to facilitate the preparation of functional layers of the light-emitting diode such as the light-emitting layer, the electron transport layer and the electrode layer on the display conductive layer 21 in the pixel pit 31.

[0089] It is worth noting that the above content regarding the display substrate is intended to clearly illustrate the implementation verification process of the present application. In fact, those skilled in the art can also make equivalent modified designs based on the guidance of the present application. For example, a first bypass conductive layer 22 and / or a second bypass conductive layer 23 can be prepared between the passivation layer 17 and the flat layer 18 to further reduce the impedance of the first power common electrode 161 or the second power common electrode 162 and / or the width of the area occupied.

[0090] Furthermore, to better implement the display substrate in the embodiments of the present application, the present application also provides a display panel based on the display substrate. The display panel includes the display substrate of any of the above embodiments, and the display panel can be, for example, a liquid crystal display panel, an OLED display panel, or the like. Since the display panel in the embodiments of the present application includes the display substrate of the above embodiments, it has all the beneficial effects of the above display substrates, and therefore will not be further described here.

[0091] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0092] The basic concepts have been described above. It will be apparent to those skilled in the art that the detailed disclosure above is merely illustrative and does not limit the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application and remain within the spirit and scope of the exemplary embodiments of the present application.

[0093] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0094] Similarly, it should be noted that, in order to simplify the presentation of this application and thus facilitate understanding of one or more embodiments of the invention, the foregoing descriptions of the embodiments of this application sometimes combine multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the subject matter of this application requires more features than those recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single embodiment disclosed above.

[0095] In some embodiments, numbers are used to describe the quantity of components and attributes. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise stated, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the description and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the settings of such numerical values ​​are as accurate as possible within the feasible range.

[0096] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, and documents, cited in this application is hereby incorporated by reference in its entirety, except for any application history that is inconsistent with or conflicts with this application, and excluding any document (currently or subsequently appended to this application) that limits the broadest scope of the claims of this application. It should be noted that if the descriptions, definitions, and / or terminology used in the accompanying materials are inconsistent with or conflict with the content of this application, the descriptions, definitions, and / or terminology used in this application will control.

[0097] The above is a detailed introduction to a display substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display substrate, characterized in that: include: A substrate having a display area and a non-display area surrounding the display area, wherein a plurality of thin film transistors are provided in the substrate, and the thin film transistors have a source electrode, a drain electrode, and a gate electrode; A conductive layer, located on the substrate, comprising a plurality of display conductive layers located in the display area and a first bypass conductive layer located in the non-display area; Wherein, the first bypass conductive layer is insulated from the display conductive layer, the display conductive layer is electrically connected to the source electrode, and the first bypass conductive layer serves as a common electrode; Wherein, the substrate has a first power common electrode located in the non-display area; The first bypass conductive layer is electrically connected to the first power common electrode and the drain electrode; The first bypass conductive layer is provided on the same layer as the display conductive layer. The first bypass conductive layer and the underlying metal layer are at least separated by an inorganic insulating layer, a passivation layer and a flat layer. The underlying metal layer includes the first power common electrode.

2. The display substrate according to claim 1, wherein The orthographic projection of the first power common electrode on the surface of the substrate coincides with the orthographic projection of the first bypass conductive layer on the surface of the substrate.

3. The display substrate according to claim 2, wherein: The first bypass conductive layer is arranged in a ring shape around the display area; or The first bypass conductive layer is located on one side of the display area; or The first bypass conductive layer is located on two opposite sides of the display area.

4. The display substrate according to claim 1, wherein The substrate further comprises a second power supply common electrode located in the non-display area; The power-on layer further includes a second bypass conductive layer located in the non-display area, wherein the second bypass conductive layer is insulated from the first bypass conductive layer; The display conductive layer is insulated from the second bypass conductive layer, and the second bypass conductive layer is electrically connected to the second power common electrode.

5. The display substrate according to claim 4, wherein: The orthographic projection of the second power common electrode on the surface of the substrate coincides with the orthographic projection of the second bypass conductive layer on the surface of the substrate.

6. The display substrate according to claim 5, wherein: The second bypass conductive layer is arranged in a ring shape around the first bypass conductive layer; or The second bypass conductive layer is located on one side of the display area; or The second bypass conductive layer is located on two opposite sides of the display area.

7. The display substrate according to claim 4, wherein: The first power common electrode is arranged in a ring shape around the display area, and the second power common electrode is arranged in a ring shape around the display area.

8. The display substrate according to claim 4, wherein: The first power common electrode is a VDD common electrode, and the second power common electrode is a VSS common electrode.

9. The display substrate according to claim 1, wherein: The substrate comprises: substrate; a first electrode layer, wherein the first electrode layer is provided on the substrate; a first buffer layer, the first buffer layer being disposed on the substrate and covering the first electrode layer; a second electrode layer, the second electrode layer being disposed on the first buffer layer, the second electrode layer being opposite to the first electrode layer, the second electrode layer comprising the drain electrode, the source electrode, and a conductive channel, wherein the conductive channel is located between the drain electrode and the source electrode; a first insulating layer, wherein the first insulating layer is disposed on the conductive channel, and the gate is disposed on the first insulating layer; a dielectric layer, the dielectric layer being disposed on the first buffer layer and covering the second electrode layer and the gate; a third electrode layer, the third electrode layer including a first electrode, a second electrode, the first power common electrode, and a second power common electrode, wherein the first electrode passes through the dielectric layer to connect to the source electrode, and the second electrode passes through the dielectric layer to connect to the drain electrode; a passivation layer, wherein the passivation layer covers the third electrode layer; A planar layer covers the passivation layer, the conductive layer is located on the planar layer, and the display conductive layer is connected to the first electrode.

10. The display substrate according to claim 9, wherein The display substrate further includes a pixel defining layer, wherein the pixel defining layer covers the planar layer; The pixel defining layer has a pixel pit, and the display conductive layer is located in the pixel pit.

11. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 10.

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