Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel has a display area, and the display area includes at least one display sub-area. The display panel includes N scanning lines, at least part of each scanning line is arranged in one display sub-area, the N scanning lines extend along a first direction and are arranged side by side along a second direction, the first direction intersects the second direction, N is an integer greater than or equal to 1, and J sets of forward and reverse scanning pull-down circuits. Each set of forward and reverse scanning pull-down circuits includes N forward and reverse scanning pull-down modules, at least part of each forward and reverse scanning pull-down module is arranged in one display sub-area, J is an integer greater than or equal to 1, and in each set of forward and reverse scanning pull-down circuits, the output ends of the N forward and reverse scanning pull-down modules are electrically connected to the N scanning lines in one-to-one correspondence.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of display technology, people's demands for display product forms have also diversified. In order to provide users with a better display experience, ultra-high resolution is an important direction for the development of display panels. However, as the resolution of display panels continues to increase, the in-plane load of the display panel will undoubtedly increase as well, and excessive in-plane load will lead to display abnormalities.

[0003] Therefore, how to reduce display abnormalities caused by excessive in-plane load is a major bottleneck for existing displays. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and display device to improve the display abnormalities caused by excessive load on the display area of ​​the display panel and display device.

[0005] In a first aspect, this application provides a display panel having a display area, the display area including at least one display partition, the display panel comprising:

[0006] N scan lines, each of the N scan lines being at least partially disposed within one of the display partitions, the N scan lines extending along a first direction and arranged side-by-side along a second direction, the first direction intersecting the second direction, and N being an integer greater than or equal to 1; and

[0007] J groups of forward and reverse scan pull-down circuits, each group of forward and reverse scan pull-down circuits includes N forward and reverse scan pull-down modules, and at least a portion of each forward and reverse scan pull-down module is set in one of the display partitions, where J is an integer greater than or equal to 1;

[0008] In each of the forward and reverse scan pull-down circuits, the output terminals of the N forward and reverse scan pull-down modules are electrically connected to the N scan lines one-to-one.

[0009] Secondly, this application also provides a display device, which includes the aforementioned display panel.

[0010] Beneficial effects: Since at least a portion of each of the N scan lines is located in a display partition, and J sets of forward and reverse scan pull-down circuits correspond to one display partition, in each of the J sets of forward and reverse scan pull-down circuits, the output terminals of the N forward and reverse scan pull-down modules of each set are electrically connected one-to-one with the N scan lines in a display partition. Moreover, at least a portion of each forward and reverse scan pull-down module is located in a display partition. This ensures that regardless of whether the N scan lines of the display panel are scanned along the second direction or along the opposite direction, the falling edge of the scan signal transmitted by the N scan lines in a display partition can be quickly pulled down. This improves the problem of scan signal delay in the transmission of the N scan lines in a display partition, thereby improving display abnormality problems, reducing the risk of incorrect charging, increasing charging time, and facilitating high-frequency display of the display panel. Attached Figure Description

[0011] Figure 1 This is a plan view of a display device according to an embodiment of this application;

[0012] Figure 2 for Figure 1 A partially enlarged schematic diagram of the display panel shown;

[0013] Figure 3 for Figure 2 The image shows a simplified partial diagram of a display partition;

[0014] Figure 4 for Figure 2 A circuit diagram of the i-th forward and reverse scan pull-down module F(i) connected to the i-th scan line SL(i) at the output terminal;

[0015] Figure 5 for Figure 2 The image shows a magnified view of a display partition.

[0016] Figure 6 When the gate drive module outputs scan signals to multiple scan lines along the second direction x1, Figure 5 The following is the timing diagram of the i-th forward and reverse scan pull-down module F(i);

[0017] Figure 7 When the gate drive module outputs scan signals to multiple scan lines along the third direction x2, Figure 5 The following is the timing diagram of the i-th forward and reverse scan pull-down module F(i);

[0018] Figure 8 This is a partially enlarged schematic diagram of a display partition of a display device according to another embodiment of this application;

[0019] Figure 9This is a partially enlarged schematic diagram of a display partition of a display device according to another embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] Please see Figures 1 to 7 . Figure 1 This is a plan view of a display device according to an embodiment of this application. Figure 2 for Figure 1 A partially enlarged schematic diagram of the display panel shown. Figure 3 for Figure 2 The image shows a simplified partial diagram of a display partition. Figure 4 for Figure 2 A circuit diagram of the i-th forward and reverse scan pull-down module F(i) connected to the i-th scan line at the output terminal. Figure 5 for Figure 2 The image shows a magnified view of a display partition. Figure 6 When the gate drive module outputs scan signals to multiple scan lines along the second direction x1, Figure 5 The timing diagram of the i-th forward and reverse scan pull-down module F(i) is shown. Figure 7 When the gate drive module outputs scan signals to multiple scan lines along the third direction x2, Figure 5 The timing diagram of the i-th forward and reverse scan pull-down module F(i) is shown.

[0022] In this embodiment, the display device 100 is a liquid crystal display device. The display device 100 includes a display panel 10, a gate driving module 20, a source driving module 30, and a backlight module (not shown). The display panel 10 is located on the light-emitting side of the backlight module.

[0023] It is understood that the display device 100 can also be any one of an organic light-emitting diode (OLED) display device, a quantum dot display device, a micro LED display device, and a sub-millimeter LED display device. When the display device 100 is any one of an organic light-emitting diode (OLED) display device, a quantum dot display device, a micro LED display device, and a sub-millimeter LED display device, the display device 100 includes a display panel 10, a gate driving module 20, and a source driving module 30, but does not include a backlight module.

[0024] In this embodiment, the display panel 10 has a display area 10a and a non-display area 10b located on the periphery of the display area 10a.

[0025] In this embodiment, the display panel 10 includes multiple display pixels XP, multiple data lines DL, and multiple scan lines SL.

[0026] In this embodiment, a plurality of display pixels XP are used to display the image. The plurality of display pixels XP are located in the display area 10a of the display panel 10 and are arranged in an array along the second direction x1 and the first direction y, wherein the second direction x1 intersects the first direction y. Specifically, the second direction x1 is perpendicular to the first direction y, but is not limited thereto; the angle between the second direction x1 and the first direction y can also be an acute angle or an obtuse angle.

[0027] It should be noted that a row of display pixels XP formed by multiple display pixels XP arranged side by side along the first direction y is a row of display pixels XP. A row of display pixels XP formed by multiple display pixels XP arranged side by side along the second direction x1 is a column of display pixels XP.

[0028] In this embodiment, as Figure 5 As shown, when the display panel 10 is a liquid crystal display panel, the display pixel XP includes a pixel electrode P. Additionally, when the display device 100 is an organic light-emitting diode (OLED) display device, the display pixel XP includes an organic light-emitting layer. When the display device 100 is a quantum dot display device, the display pixel XP includes a quantum dot light-emitting layer. When the display device 100 is a micro-LED display device or a sub-millimeter LED display device, the display pixel XP includes an inorganic light-emitting diode.

[0029] In this embodiment, the display panel 10 further includes a plurality of redundant pixels DP, which are located in the non-display area 10b and disposed along the outer edge of the display area 10a. The redundant pixels DP are not used for display. The redundant pixels DP are used to ensure the process yield of the display pixel XP and the driving circuit of the display pixel XP, thereby ensuring that the display pixel XP can emit light normally. The design of the redundant pixels DP uses common techniques, which will not be elaborated here.

[0030] Specifically, the multiple redundant pixel DPs include two rows of redundant pixel DPs and two columns of redundant pixel DPs. The two rows of redundant pixel DPs are located on opposite sides of the display area 10a in the second direction x1, and each row of redundant pixel DPs includes multiple redundant pixel DPs arranged side by side along the first direction y. The two columns of redundant pixel DPs are located on opposite sides of the display area 10a in the first direction y, and each column of redundant pixel DPs includes multiple redundant pixel DPs arranged side by side along the second direction x1.

[0031] It is understandable that multiple redundant pixel DPs can include redundant pixel DPs with more than two rows and redundant pixel DPs with more than two columns.

[0032] In this embodiment, multiple data lines DL extend along a second direction x1 and are arranged along a first direction y. The first and last data lines DL arranged along the second direction are both located in the non-display area 10b and respectively on opposite sides of the display area 10a in the first direction y. The first and last data lines DL are each connected to a column of redundant pixels DP. At least a portion of each data line DL located between the first and last data lines DL is located in the display area 10a and is respectively connected to a column of display pixels XP.

[0033] In this embodiment, as Figure 2 and Figure 5 As shown, the multiple data lines DL include the first data line D(1) to the (M+2)th data line D(M+2) arranged sequentially along the first direction y. At least a portion of each of the first data lines D(1) to the (M+2)th data lines D(M+2) is located in the display area 10a, and M is greater than or equal to 5. The first data line D(1) to the (M+2)th data line D(M+2) includes the first data line D(1), the second data line D(2), the third data line D(3), the (M-1)th data line D(M-1), the Mth data line D(M), the (M+1)th data line D(M+1), and the (M+2)th data line D(M+2).

[0034] In this embodiment, a source driver module 30 is located on one side of the display area 10a in the second direction x1. The source driver module 30 is connected to multiple data lines DL and is used to transmit data signals to the multiple data lines DL.

[0035] In this embodiment, multiple scan lines SL extend along a first direction y and are arranged along a second direction x1. The first and last scan lines SL arranged along the second direction x1 are both located in the non-display area 10b and on opposite sides of the display area 10a in the second direction x1, respectively. Both the first and last scan lines arranged along the second direction x1 are connected to a row of redundant pixels DP. The scan lines SL located between the first and last scan lines are all located in the display area 10a and are all connected to a row of display pixels XP.

[0036] In this embodiment, as Figure 2As shown, the multiple scan lines SL include the 0th scan line SL(0) to the Nth scan line SL(N) arranged along the second direction x1. The 0th scan line SL(0) to the Nth scan line SL(N) include the 0th scan line SL(0), the 1st scan line SL(1), the 2nd scan line SL(2), the (i-1)th scan line SL(i-1), the 1st scan line SL(i), the (i+1)th scan line SL(i+1), the (N-2)th scan line SL(N-2), the (N-1)th scan line SL(N-1), the Nth scan line SL(N), and the (N+1)th scan line SL(N+1), where i is greater than or equal to 2 and less than or equal to N-1, and N is greater than or equal to 5. Among them, the 0th scan line SL(0) is located in the non-display area 10b and is the first scan line SL arranged along the second direction x1. At least a portion of the first scan line SL(1) to the (N+1)th scan line SL(N+1) are located in the display area 10a.

[0037] In this embodiment, the (i-1)th scan line SL(i-1) is used to transmit the (i-1)th level scan signal G(i-1), the ith scan line SL(i) is used to transmit the ith level scan signal G(i), the (i+1)th scan line SL(i+1) is used to transmit the (i+1)th level scan signal G(i+1), and other scan signal lines follow the same pattern, which will not be elaborated here.

[0038] In this embodiment, at least one gate driving module 20 is located on at least one side of the display area 10a in the first direction y. The at least one gate driving module 20 is connected to multiple scan lines SL, and is used to output scan signals to the multiple scan lines SL in a preset sequence. Specifically, two gate driving modules 20 are located on opposite sides of the display area 10a in the first direction y, and the opposite ends of each scan line SL are connected to two gate driving modules 20 respectively, meaning each scan line SL is driven by two gate driving modules 20.

[0039] Understandably, scan lines SL located in odd-numbered rows can be connected to one gate drive module 20, while scan lines SL located in even-numbered rows can be connected to another gate drive module 20.

[0040] In this embodiment, the display area 10a of the display panel 10 includes at least one display partition 10a1. A display partition 10a1 is provided with B×C display pixels XP, where B is the number of columns of the display pixels XP, C is the number of rows of the display pixels XP, and both B and C are integers greater than or equal to 2, and B is less than C.

[0041] Specifically, such as Figure 1As shown, the display area 10a includes multiple identical display partitions 10a1 arranged in an array along the second direction x1 and the first direction y. That is, the number of rows and columns of display pixels XP in each display area 10a is the same, but it is not limited to this. The multiple display partitions 10a1 can also be different from each other.

[0042] In this embodiment, a display partition 10a1 is used as an example for explanation, and other display partitions can be described in the same way. In a display partition, B is 40 and C is 42, that is, a display partition 10a1 includes 42 rows of display pixels XP and 40 columns of display pixels XP, but it is not limited to this.

[0043] In this embodiment, as Figure 2 As shown, N scan lines SL are provided in a display partition 10a1. The N scan lines SL extend along a first direction y and are arranged side by side along a second direction x1. At least a portion of each of the N scan lines SL is provided in a display partition 10a1 and connected to multiple display pixels XP.

[0044] It should be noted that if the display area 10a includes multiple display partitions 10a1 along the first direction y, since a scan line SL extends along the first direction y, a portion of the scan line SL will be located in the multiple display partitions 10a1 arranged side by side along the first direction y. Additionally, another portion of the scan line SL is located in the non-display area 10b and connected to the gate driving module 20.

[0045] In this embodiment, the display panel 10 also includes J sets of forward and reverse scanning pull-down circuits Z corresponding to each display partition 10a1, where J is an integer greater than or equal to 1. That is, the J sets of forward and reverse scanning pull-down circuits Z are set for one display partition 10a1 to pull down the falling edge of the scan signal transmitted by the N scan lines SL in one display partition 10a1.

[0046] In this embodiment, J is greater than or equal to 1 and less than or equal to 4. It should be noted that the larger J is, the faster the falling edge of the scan signal transmitted by the J-group forward and reverse scan pull-down circuits Z to the N scan lines SL of a display partition 10a1 will be pulled down. However, this will also result in too many circuits in the display area 10a in the display panel 10, thus reducing the aperture ratio of the display area 10a.

[0047] In order to describe the technical solution of this application, such as Figure 2 As shown, taking J equal to 2 as an example, that is, the two sets of positive and negative scanning pull-down circuits Z pull down the falling edge of the scanning signal transmitted by the N scanning lines SL in a display partition 10a1, but it is not limited to this, J can also be equal to 1, 3 or greater than 3.

[0048] In this embodiment, each set of forward and reverse scan pull-down circuits Z includes N forward and reverse scan pull-down modules F, and at least a portion of each forward and reverse scan pull-down module F is disposed in a display partition 10a1. In each set of forward and reverse scan pull-down circuits Z, the output terminals of the N forward and reverse scan pull-down modules F are electrically connected one-to-one with the N scan lines SL, so that when the gate driving module 20 sequentially outputs scan signals to multiple scan lines SL, whether along the second direction x1 or along the third direction x2 opposite to the second direction x1, the N forward and reverse scan pull-down modules F pull down one-to-one with the N scan lines SL of a display partition 10a, thereby improving the problem of scan signal transmission delay of the N scan lines SL of a display partition 10a1, thereby improving the display abnormality problem caused by scan signal delay, reducing the risk of incorrect charging, increasing charging time, and facilitating the display device to achieve high-frequency display.

[0049] It should be noted that at least one gate driving module 20 of the display device 100 has the function of scanning multiple scan lines SL along the second direction x1 and the third direction x2. At the same time, whether along the second direction x1 or the third direction x2, the J sets of forward and reverse scanning pull-down circuits Z can quickly pull down the falling edge of the scan signal transmitted by the N scan lines SL in a display partition 10a1, which can adapt to the situation where the installation direction of the display device 100 is uncertain.

[0050] In this embodiment, as Figure 2 As shown, the J-group forward and reverse scan pull-down circuits Z are arranged along the first direction y, that is, the J-group forward and reverse scan pull-down circuits Z are arranged along the extension direction of each scan line SL, so that the falling edge of the scan signal transmitted by each scan line SL is pulled down faster.

[0051] In this embodiment, each group of forward and reverse scan pull-down circuits Z includes K rows of forward and reverse scan pull-down modules P, and each row of forward and reverse scan pull-down modules P includes N / K forward and reverse scan pull-down modules F arranged along the second direction x1, where K is greater than or equal to 1 and less than or equal to N.

[0052] Specifically, the N / K forward and reverse scan drop-down modules F of each row of forward and reverse scan drop-down modules P are arranged side by side along the second direction x1. It can be understood that the N / K forward and reverse scan drop-down modules F of each row of forward and reverse scan drop-down modules P can also be staggered along the second direction x1.

[0053] In this embodiment, as Figure 4As shown, each forward and reverse scan pull-down module F includes a forward scan control unit Fb, a reverse scan control unit Fa, and a pull-down unit Fc. The control terminal of the pull-down unit Fc is connected to the output terminal of the forward scan control unit Fb and the output terminal of the reverse scan control unit Fa. The output terminal of the pull-down unit Fc is connected to a scan line SL, so that the pull-down unit Fc of each forward and reverse scan pull-down module F is controlled by the signal output by one of the forward scan control unit Fb and the reverse scan control unit Fa, and pulls down the falling edge of the scan signal transmitted by a scan line SL.

[0054] In this embodiment, the display panel 10 also includes J groups of signal lines TL corresponding to each display partition 10a1. The J groups of signal lines TL are configured one-to-one with the J groups of forward and reverse scan pull-down circuits Z, that is, each group of signal lines TL corresponds to a group of forward and reverse scan pull-down circuits Z. Each group of signal lines TL includes K groups of common signal lines CL. The K groups of common signal lines CL are configured one-to-one with K rows of forward and reverse scan pull-down modules P. The N / K forward and reverse scan pull-down modules F of each row of forward and reverse scan pull-down modules P are connected to a group of common signal lines CL, so that the N / K forward and reverse scan pull-down modules F of each row of forward and reverse scan pull-down modules P share a group of common signal lines CL, thereby reducing the wiring of the display area 10a and improving the aperture ratio of the display panel 10.

[0055] It should be noted that the J group signal lines TL set for each display partition 10a1 means that at least a portion of the J group signal lines TL is located in each display partition 10a1. The one-to-one setting of the J group signal lines TL and the J group forward and reverse scan pull-down circuits Z means that a group of signal lines TL and the corresponding group of forward and reverse scan pull-down circuits Z will be set in the same display partition 10a1.

[0056] In this embodiment, each group of shared signal lines CL includes an adjacent forward scan control signal line U2D, a reverse scan control signal line D2U, and a low-level signal line LL. The forward scan control signal line U2D, the reverse scan control signal line D2U, and the low-level signal line LL all extend along the second direction x1 and are arranged along the first direction y. Specifically, in each group of shared signal lines CL, the low-level signal line LL is located between the forward scan control signal line U2D and the reverse scan control signal line D2U.

[0057] In this embodiment, a reverse scan control signal line D2U is used to transmit the reverse scan control signal K1, and a forward scan control signal line U2D is used to transmit the forward scan control signal K2. The reverse scan control signal K1 and the forward scan control signal K2 are out of phase. The reverse scan control signal K1 and the forward scan control signal K2 are related to the scanning direction of the multiple scan lines SL, making the rapid pull-down of the falling edge of the scan signal transmitted by the multiple scan lines according to the scanning direction more stable and controllable.

[0058] Among them, the reverse scan control signal K1 and the forward scan control signal K2 can both be DC signals, but are not limited to this; the reverse scan control signal K1 and the forward scan control signal K2 can also both be AC ​​signals.

[0059] In this embodiment, a low-level signal line LL is used to transmit a low-level signal. The low-level signal can be a constant voltage low-potential signal or a pulse signal that includes a low-potential state.

[0060] In this embodiment, the second input terminals of the forward scan control units F(b) of the N / K forward and reverse scan pull-down modules F of each row of forward and reverse scan pull-down modules P are all connected to the same forward scan control signal line U2D, the second input terminals of the reverse scan control units Fa of the N / K forward and reverse scan pull-down modules F of each row of forward and reverse scan pull-down modules P are all connected to the same reverse scan control signal line D2U, and the input terminals of the pull-down units Fc of the N / K forward and reverse scan pull-down modules F of each row of forward and reverse scan pull-down modules P are all connected to the same low-level signal line LL.

[0061] Specifically, such as Figure 2 As shown, K=1, meaning each group of forward and reverse scan pull-down circuits Z includes a first row of forward and reverse scan pull-down modules P1, and the first row of forward and reverse scan pull-down modules P1 includes N forward and reverse scan pull-down modules F arranged along the second direction x1. The N forward and reverse scan pull-down modules F include the first forward and reverse scan pull-down module F(1) to the Nth forward and reverse scan pull-down module F(N). The N forward and reverse scan pull-down modules F of the first row of forward and reverse scan pull-down modules P1 are electrically connected one-to-one with the N scan lines SL of a display partition 10a1. The N forward and reverse scan pull-down modules F of the first row of forward and reverse scan pull-down modules P1 are arranged side by side along the second direction x1. In addition, when K=1, a group of signal lines TL includes a group of common signal lines CL. The first forward and reverse scan pull-down modules F(1) to the Nth forward and reverse scan pull-down modules F(N) of the first row of forward and reverse scan pull-down modules P1 are all connected to a group of common signal lines CL.

[0062] In this embodiment, combined with Figure 2 and Figure 4 In each row of forward and reverse scan pull-down modules P, the forward and reverse scan pull-down module F connected to the output terminal of the i-th scan line SL(i) is the i-th forward and reverse scan pull-down module F(i). The output terminal of the pull-down unit Fc(i) of the i-th forward and reverse scan pull-down module F(i) is connected to the i-th scan line SL(i), and the input terminal of the pull-down unit Fc(i) of the i-th forward and reverse scan pull-down module F(i) is connected to a low-level signal line LL. This allows the pull-down unit Fc(i) of the i-th forward and reverse scan pull-down module F(i) to respond to the signal output by the forward scan control unit Fb(i) or the reverse scan control unit Fa(i) to output the low-level signal transmitted by the low-level signal line LL to the i-th scan line SL(i) to pull down the falling edge of the scan signal transmitted by the i-th scan line SL(i).

[0063] The first input terminal of the forward scan control unit Fb(i) of the i-th forward and reverse scan pull-down module F(i) is connected to the (i+1)-th scan line S(i+1), and the second input terminal of the forward scan control unit Fb(i) of the i-th forward and reverse scan pull-down module F(i) is connected to a forward scan control signal line U2D, so that the forward scan control unit Fb(i) of the i-th forward and reverse scan pull-down module F(i) outputs a forward scan control signal K2 to the control terminal of the pull-down unit Fc(i) of the i-th forward and reverse scan pull-down module F(i) according to the scan signal transmitted by the (i+1)-th scan line S(i+1) and the control signal transmitted by the forward scan control signal line U2D.

[0064] The first input terminal of the reverse scan control unit Fa(i) of the i-th forward and reverse scan pull-down module F(i) is connected to the (i-1)-th scan line SL(i-1), and the second input terminal of the reverse scan control unit Fa(i) of the i-th forward and reverse scan pull-down module F(i) is connected to a reverse scan control signal line D2U, so that the reverse scan control unit Fa(i) of the i-th forward and reverse scan pull-down module F(i) outputs a reverse scan control signal K1 to the control terminal of the pull-down unit Fc(i) of the i-th forward and reverse scan pull-down module F(i) according to the scan signal transmitted by the (i-1)-th scan line SL(i-1) and the control signal transmitted by the reverse scan control signal line D2U.

[0065] Specifically, such as Figure 4 As shown, for the i-th forward / reverse scan pull-down module F(i) connected to the output terminal of the i-th scan line SL(i), the i-th forward / reverse scan pull-down module F(i) includes a forward scan control unit Fb(i), a reverse scan control unit Fa(i), and a pull-down unit Fc(i). The forward scan control unit Fb(i) includes the i-th forward scan control transistor Tb(i), the reverse scan control unit Fa(i) includes the i-th reverse scan control transistor Ta(i), and the pull-down unit Fc(i) includes the i-th pull-down transistor Tc(i).

[0066] In this configuration, one of the source and drain of the i-th forward scan control transistor Tb(i) is connected to the gate of the i-th pull-down transistor Tc(i), the other of the source and drain of the i-th forward scan control transistor Tb(i) is connected to a forward scan control signal line U2D, and the gate of the i-th forward scan control transistor Tb(i) is connected to the (i+1)-th scan line S(i+1).

[0067] One of the source and drain of the i-th reverse scan control transistor Ta(i) is also connected to the gate of the i-th pull-down transistor Tc(i), and the other of the source and drain of the i-th reverse scan control transistor Ta(i) is connected to the reverse scan control signal line D2U. The gate of the i-th reverse scan control transistor Ta(i) is connected to the (i-1)-th scan line SL(i-1).

[0068] One of the source and drain of the i-th pull-down transistor Tc(i) is connected to the i-th scan line SL(i), and the other of the source and drain of the i-th pull-down transistor Tc(i) is connected to the low-level signal line LL.

[0069] It should be noted that the i-th forward scan control transistor Tb(i), the i-th reverse scan control transistor Ta(i), and the i-th pull-down transistor Tc(i) are each independently selected from either an n-type thin-film transistor or a p-type thin-film transistor. The i-th forward scan control transistor Tb(i), the i-th reverse scan control transistor Ta(i), and the i-th pull-down transistor Tc(i) are each independently selected from either a metal-oxide-semiconductor thin-film transistor, a low-temperature polycrystalline silicon thin-film transistor, or an amorphous silicon thin-film transistor.

[0070] Specifically, in this embodiment, the i-th forward scan control transistor Tb(i), the i-th reverse scan control transistor Ta(i), and the i-th pull-down transistor Tc(i) are all n-type low-temperature polycrystalline silicon thin-film transistors.

[0071] In this embodiment, in each row of forward and reverse scan drop-down modules P, the forward scan control units Fb of N / K forward and reverse scan drop-down modules F are arranged side by side along the second direction x1, that is, the forward scan control units Fb of N / K forward and reverse scan drop-down modules F form a row of forward scan control units Fb; the reverse scan control units Fa of N / K forward and reverse scan drop-down modules F are arranged side by side along the second direction x1, that is, the reverse scan control units Fa of N / K forward and reverse scan drop-down modules F form a row of reverse scan control units Fa; and the drop-down units Fc of N / K forward and reverse scan drop-down modules F are arranged side by side along the second direction x1, that is, the drop-down units Fc of N / K forward and reverse scan drop-down modules F form a row of drop-down units Fc. In each row of forward and reverse scan drop-down modules P, in the first direction y, a row of drop-down units Fc is located between a row of forward scan control units Fb and a row of reverse scan control units Fa.

[0072] Specifically, such as Figure 3As shown, when K=1, in each row of forward and reverse scan pull-down modules P, the i-th forward scan control transistor Tb(i), the (i+1)-th forward scan control transistor Tb(i+1), and the (i+2)-th forward scan control transistor Tb(i+2) are arranged side by side along the second direction x1; the i-th reverse scan control transistor Ta(i), the (i+1)-th reverse scan control transistor Ta(i+1), and the (i+2)-th reverse scan control transistor Ta(i+2) are arranged side by side along the second direction x1; the i-th pull-down transistor Tc(i), the (i+1)-th pull-down transistor Tc(i+1), and the (i+2)-th pull-down transistor Tc(i+2) are arranged side by side along the second direction x1.

[0073] Please combine Figure 5 as well as Figure 6 When the gate driving module 20 sequentially outputs scanning signals to multiple scan lines SL along the second direction x1, after the (i-1)th level gate driving unit GOA(i-1) of the gate driving module 20 outputs a high-level (i-1)th level scan signal G(i-1) to the (i-1)th scan line SL(i-1), the (i)th level gate driving unit GOA(i) of the gate driving module 20 outputs a high-level (i)th level scan signal G(i) to the ith scan line SL(i), and then the (i+1)th level gate driving unit GOA(i+1) of the gate driving module 20 outputs a high-level (i+1)th level scan signal G(i+1) to the (i+1)th scan line SL(i+1). At this time, the forward scan control signal K2 is the first DC high potential signal VGH1, and the reverse scan control signal K1 is the first DC low potential signal VGL1. The low-level signal line LL transmits the constant voltage low-level signal VGL3.

[0074] When the (i+1)th scan line SL(i+1) receives the high-level (i+1)th scan signal G(i+1), the (i-1)th scan line SL(i-1) transmits the low-level (i-1)th scan signal G(i-1). The i-th reverse scan control transistor Ta(i) is turned off, the i-th forward scan control transistor Tb(i) is turned on, and the i-th pull-down transistor Tc(i) is turned on according to the first DC high potential signal VGH1 output by the turned-on i-th forward scan control transistor Tb(i). The low-level signal line LL transmits the second constant voltage low-level signal VGL2 and outputs it to the i-th scan line SL(i) to realize the rapid pull-down of the falling edge of the high-level (i)th scan signal G(i).

[0075] Please combine Figure 5 as well as Figure 7When the gate driving module 20 sequentially outputs scanning signals to multiple scan lines SL along a third direction x2 opposite to the second direction x1, after the (i+1)th level gate driving unit GOA(i+1) of the gate driving module 20 outputs a high-level (i+1)th level scan signal G(i+1) to the (i+1)th scan line SL(i+1), the (i)th level gate driving unit GOA(i) of the gate driving module 20 outputs a high-level (i)th level scan signal G(i) to the ith scan line SL(i), and then the (i-1)th level gate driving unit GOA(i-1) of the gate driving module 20 outputs a high-level (i-1)th level scan signal G(i-1) to the (i-1)th scan line SL(i-1). At this time, the forward scan control signal K2 is the second DC low-potential signal VGL2, and the reverse scan control signal K1 is the second DC high-potential signal VGH2. The low-level signal line LL transmits the constant voltage low-level signal VGL3.

[0076] When the (i-1)th scan line SL(i-1) outputs a high-level (i-1)th scan signal G(i-1), the (i+1)th scan line SL(i+1) outputs a low-level (i+1)th scan signal G(i+1). The i-th reverse scan control transistor Ta(i) turns on according to the high-level (i-1)th scan signal G(i-1), and the i-th forward scan control transistor Tb(i) turns off according to the low-level (i+1)th scan signal G(i+1). The i-th pull-down transistor Tc(i) turns on according to the second DC high-potential signal VGH2 output by the turned-on i-th reverse scan control transistor Ta(i). The constant voltage low-level signal VGL3 transmitted by the low-level signal line LL is output to the i-th scan line SL(i) to realize the rapid pull-down of the high-level (i)th scan signal G(i).

[0077] In this embodiment, as Figure 3 As shown, the display panel 10 also includes at least one redundant signal line DUL. At least a portion of the redundant signal line DUL is located in the display area 10a, and the redundant signal line DUL is floating, so that the redundant signal line DUL does not transmit signals. It should be noted that when the wiring distribution in the display area of ​​the display panel 10 is uneven, by adding at least one floating redundant signal line DUL, the wiring distribution of the display panel 10 can be made uniform, the aperture ratio distribution of the display device can be made uniform, and the problem of uneven display brightness of the display device 100 can be improved.

[0078] In this embodiment, as Figure 3 As shown, multiple redundant signal lines DUL extend along the second direction x1, and the multiple redundant signal lines DUL are regularly arranged in the display partition 10a1 so that the aperture ratio distribution of the display device 100 is uniform.

[0079] Specifically, in one display partition 10a1, multiple redundant signal lines DUL are spaced apart between one first-row forward / reverse scan pull-down module P1 and another first-row forward / reverse scan pull-down module P1. Multiple redundant signal lines DUL are also spaced apart on the side of one first-row forward / reverse scan pull-down module P1 away from the other first-row forward / reverse scan pull-down module P1, and multiple redundant signal lines DUL are also spaced apart on the side of the other first-row forward / reverse scan pull-down module P1 away from one first-row forward / reverse scan pull-down module P1. The redundant signal lines DUL in each of the multiple display partitions 10a1 are as follows: Figure 3 The arrangement is regular to ensure the uniformity of the aperture ratio of the display area 10a of the display device 100.

[0080] In this embodiment, multiple redundant signal lines DUL are arranged adjacent to the data line DL in a one-to-one manner, and the multiple redundant signal lines DUL and the data line DL are arranged on the same layer. It can be understood that the multiple redundant signal lines DUL and the data line DL can be located on different layers.

[0081] It should be noted that, Figure 3 The black dots in the diagram represent signal lines that transmit signals. These signal lines can be data lines (DL, etc.).

[0082] In this embodiment, at least one of the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D is located on the same layer as the redundant signal line DUL and is spaced apart. This is beneficial for using the existing redundant signal line DUL as the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D, thereby reducing the amount of additional metal wiring required and improving the problem of reduced aperture ratio of the display device 100.

[0083] Specifically, at least one of the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D has the same shape, material, and extension direction as the redundant signal line DUL, that is, the existing redundant signal line DUL is used as at least one of the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D.

[0084] It should be noted that when the display panel 10 includes redundant signal lines DUL, all or some of the redundant signal lines DUL on the display panel 10 can be used as the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D. Alternatively, when the display panel 10 does not include redundant signal lines DUL, they can be formed by adding additional traces to the display panel 10.

[0085] In this embodiment, the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D are respectively arranged one-to-one with three adjacent data lines DL and spaced apart, so that the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D are evenly distributed in the display area 10a, thereby improving the uniformity of the aperture ratio of the display area 10a of the display device 100.

[0086] In another embodiment, at least one of the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D is located on a different layer from the data line DL and overlaps with it, in order to improve the aperture ratio of the display panel 10. For example, at least one of the reverse scan control signal line D2U, the low-level signal line LL, and the forward scan control signal line U2D may be located on a different light-shielding metal layer than the data line DL and overlap with the data line DL.

[0087] Please see Figure 8 This is a partially enlarged schematic diagram of a display zone of a display device according to another embodiment of this application. The display device of this embodiment is similar to... Figure 1 The display devices shown are basically similar, and the similarities will not be repeated. The differences include: multiple scan lines SL include the (2i-4)th scan line SL(2i-4), the (2i-3)th scan line SL(2i-3), the (2i-2)th scan line SL(2i-2), the (2i-1)th scan line SL(2i-1), the 2ith scan line SL(2i), and the (2i+1)th scan line SL(2i+1); K=2, and each group of forward and reverse scan pull-down circuits Z includes a first row of forward and reverse scan pull-down modules P11 and a second row of forward and reverse scan pull-down modules P12 arranged along the first direction. The first row of forward and reverse scan pull-down modules P11 includes the first (2i-1) forward and reverse scan pull-down module F(2i-1) whose output terminal is connected to the (2i-1)th scan line SL(2i-1). The second row of forward and reverse scan pull-down modules P12 includes the second (2i) forward and reverse scan pull-down module F(2i) whose output terminal is connected to the 2ith scan line SL(2i). i is greater than or equal to 1 and less than or equal to N / 2, so that the N forward and reverse scan pull-down modules F of each group of forward and reverse scan pull-down circuits Z are arranged in two rows, so as to realize the rapid pull-down of the falling edge of the scan signal transmitted by the N scan lines, while improving the display unevenness caused by the concentration of lines.

[0088] Specifically, in each group of forward and reverse scan pull-down circuits Z, the first row of forward and reverse scan pull-down modules P11 and the second row of forward and reverse scan pull-down modules P12 are arranged at intervals along the first direction y. A redundant signal line DUL is provided between the first row of forward and reverse scan pull-down modules P11 and the second row of forward and reverse scan pull-down modules P12. Multiple redundant signal lines DUL are also provided at intervals on the side of the first row of forward and reverse scan pull-down modules P11 away from the second row of forward and reverse scan pull-down modules P12. Similarly, multiple redundant signal lines DUL are also provided at intervals on the side of the second row of forward and reverse scan pull-down modules P12 away from the first row of forward and reverse scan pull-down modules P11. For multiple groups of forward and reverse scan pull-down circuits Z, the arrangement of the redundant signal lines DUL is as follows: Figure 8 As shown.

[0089] The first row of forward and reverse scan pull-down modules P11 includes a (2i-1)th forward and reverse scan pull-down module F(2i-1) and a (2i-3)th forward and reverse scan pull-down module F(2i-3). The (2i-1)th forward and reverse scan pull-down module F(2i-1) includes a (2i-1)th forward scan control transistor Tb(2i-1), a (2i-1)th reverse scan control transistor Ta(2i-1), and a (2i-1)th pull-down transistor Tc(2i-1). The (2i-3)th forward and reverse scan pull-down module F(2i-3) includes a (2i-3)th forward scan control transistor Tb(2i-3), a (2i-3)th reverse scan control transistor Ta(2i-3), and a (2i-3)th pull-down transistor Tc(2i-3). The (2i-1)th forward scan control transistor Tb(2i-1) and the (2i-3)th forward scan control transistor Tb(2i-3) are arranged side by side along the second direction x1. The (2i-1)th reverse scan control transistor Ta(2i-1) and the (2i-3)th reverse scan control transistor Ta(2i-3) are arranged side by side along the second direction x1. The (2i-1)th pull-down transistor Tc(2i-1) and the (2i-3)th pull-down transistor Tc(2i-3) are arranged side by side along the second direction x1.

[0090] The second row of forward and reverse scan pull-down modules P12 includes a (2i) forward and reverse scan pull-down module F(2i) and a (2i-2) forward and reverse scan pull-down module F(2i-2). The (2i-2) forward and reverse scan pull-down module F(2i-2) includes a (2i-2) forward scan control transistor Tb(2i-2), a (2i-2) reverse scan control transistor Ta(2i-2), and a (2i-2) pull-down transistor Tc(2i-2). The (2i) forward and reverse scan pull-down module F(2i) includes a (2i) forward scan control transistor Tb(2i), a (2i) reverse scan control transistor Ta(2i), and a (2i) pull-down transistor Tc(2i). The (2i-2) forward scan control transistor Tb(2i-2) and the (2i) forward scan control transistor Tb(2i) are arranged side by side along the second direction x1. The (2i-2) reverse scan control transistor Ta(2i-2) and the (2i) reverse scan control transistor Ta(2i) are arranged side by side along the second direction x1. The (2i-2) pull-down transistor Tc(2i-2) and the (2i) pull-down transistor Tc(2i) are arranged side by side along the second direction x1.

[0091] Please see Figure 9 This is a partially enlarged schematic diagram of a display zone of a display device according to another embodiment of this application. The display device of this embodiment is similar to... Figure 1 The display devices shown are basically similar, and the similarities will not be repeated. The differences include that the multiple scan lines SL include the (3i-3)th scan line SL(3i-3), the (3i-2)th scan line SL(3i-2), the (3i-1)th scan line SL(3i-1), the (3i)th scan line SL(3i), the (3i+1)th scan line SL(3i+1), the (3i+2)th scan line SL(3i+2), the (3i+3)th scan line SL(3i+3), and the (3i+4)th scan line SL(3i+4); K=3, and each group of forward and reverse scan pull-down circuits Z includes a first row of forward and reverse scan pull-down modules P31, a second row of forward and reverse scan pull-down modules P32, and a third row of forward and reverse scan pull-down modules P33 arranged along the first direction y.

[0092] The first row of forward and reverse scan pull-down modules P31 includes a (3i-2)th forward and reverse scan pull-down module F(3i-2) whose output terminal is connected to the (3i-2)th scan line SL(3i-2), where i is greater than or equal to 1 and less than or equal to N / 3. The second row of forward and reverse scan pull-down modules P32 includes a (3i-1)th forward and reverse scan pull-down module F(3i-1) whose output terminal is connected to the (3i-1)th scan line SL(3i-1). The third row of forward and reverse scan pull-down modules P33 includes a (3i)th forward and reverse scan pull-down module F(3i) whose output terminal is connected to the 3ith scan line SL(3i), so that the N forward and reverse scan pull-down modules F of each group of forward and reverse scan pull-down circuits Z are arranged in three rows, which realizes the rapid pull-down of the falling edge of the scan signal transmitted by the N scan lines, and improves the display unevenness caused by the concentration of lines.

[0093] Specifically, in each group of forward and reverse scan pull-down circuits Z, the first row of forward and reverse scan pull-down modules P31, the second row of forward and reverse scan pull-down modules P32, and the third row of forward and reverse scan pull-down modules P33 are arranged along the first direction y, with the second row of forward and reverse scan pull-down modules P32 located between the first row of forward and reverse scan pull-down modules P31 and the third row of forward and reverse scan pull-down modules P33. A redundant signal line DUL is provided between the first row of forward and reverse scan pull-down modules P31 and the second row of forward and reverse scan pull-down modules P32, and a redundant signal line DUL is provided in the third row of forward and reverse scan pull-down modules P33 away from the second row of forward and reverse scan pull-down modules P32. When there are multiple groups of forward and reverse scan pull-down circuits Z, the correspondence between the redundant signal line DUL and each group of forward and reverse scan pull-down circuits Z is as follows: Figure 9 As shown.

[0094] The first row of forward and reverse scan pull-down modules P31 includes the (3i-2)th forward and reverse scan pull-down module F(3i-2) and the (3i+1)th forward and reverse scan pull-down module F(3i+1). The (3i-2)th forward and reverse scan pull-down module F(3i-2) includes the (3i-2)th forward scan control transistor Tb(3i-2), the (3i-2)th reverse scan control transistor Ta(3i-2), and the (3i-2)th pull-down transistor Tc(3i-2). The (3i+1)th forward and reverse scan pull-down module F(3i+1) includes the (3i+1)th forward scan control transistor Tb(3i+1), the (3i+1)th reverse scan control transistor Ta(3i+1), and the (3i+1)th pull-down transistor Tc(3i+1). The (3i-2)th forward scan control transistor Tb(3i-2) and the (3i+1)th forward scan control transistor Tb(3i+1) are arranged side by side along the second direction x1. The (3i-2)th reverse scan control transistor Ta(3i-2) and the (3i+1)th reverse scan control transistor Ta(3i+1) are arranged side by side along the second direction x1. The (3i-2)th pull-down transistor Tc(3i-2) and the (3i+1)th pull-down transistor Tc(3i+1) are arranged side by side along the second direction x1.

[0095] The second row of forward and reverse scan pull-down modules P32 includes a (3i-1) forward and reverse scan pull-down module F(3i-1) and a (3i+2) forward and reverse scan pull-down module F(3i+2). The (3i-1) forward and reverse scan pull-down module F(3i-1) includes a (3i-1) forward scan control transistor Tb(3i-1), a (3i-1) reverse scan control transistor Ta(3i-1), and a (3i-1) pull-down transistor Tc(3i-1). The (3i+2) forward and reverse scan pull-down module F(3i+2) includes a (3i+2) forward scan control transistor Tb(3i+2), a (3i+2) reverse scan control transistor Ta(3i+2), and a (3i+2) pull-down transistor Tc(3i+2). The (3i-1)th forward scan control transistor Tb(3i-1) and the (3i+2)th forward scan control transistor Tb(3i+2) are arranged side by side along the second direction x1. The (3i-1)th reverse scan control transistor Ta(3i-1) and the (3i+2)th reverse scan control transistor Ta(3i+2) are arranged side by side along the second direction x1. The (3i-1)th pull-down transistor Tc(3i-1) and the (3i+2)th pull-down transistor Tc(3i+2) are arranged side by side along the second direction x1.

[0096] The third row of forward and reverse scan pull-down modules P33 includes a (3i) forward and reverse scan pull-down module F(3i) and a (3i+3) forward and reverse scan pull-down module F(3i+3). The (3i) forward and reverse scan pull-down module F(3i) includes a (3i) forward scan control transistor Tb(3i), a (3i) reverse scan control transistor Ta(3i), and a (3i) pull-down transistor Tc(3i). The (3i+3) forward and reverse scan pull-down module F(3i+3) includes a (3i+3) forward scan control transistor Tb(3i+3), a (3i+3) reverse scan control transistor Ta(3i+3), and a (3i+3) pull-down transistor Tc(3i+3). The (3i) forward scan control transistor Tb(3i) and the (3i+3) forward scan control transistor Tb(3i+3) are arranged side by side along the second direction x1. The (3i) reverse scan control transistor Ta(3i) and the (3i+3) reverse scan control transistor Ta(3i+3) are arranged side by side along the second direction x1. The (3i) pull-down transistor Tc(3i) and the (3i+3) pull-down transistor Tc(3i+3) are arranged side by side along the second direction x1.

[0097] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized by, The display panel has a display area, the display area including at least one display partition, and the display panel includes: N scan lines, each of the N scan lines being at least partially disposed within one of the display partitions, the N scan lines extending along a first direction and arranged side-by-side along a second direction, the first direction intersecting the second direction, and N being an integer greater than or equal to 1; and J groups of forward and reverse scan pull-down circuits are set up corresponding to one of the display partitions. Each group of forward and reverse scan pull-down circuits includes N forward and reverse scan pull-down modules. At least a portion of each forward and reverse scan pull-down module is set in one of the display partitions. J is an integer greater than or equal to 1. In each of the forward and reverse scan pull-down circuits, the output terminals of the N forward and reverse scan pull-down modules are electrically connected to the N scan lines one-to-one. Each of the forward and reverse scan drop-down modules includes: A forward scan control unit includes a second input terminal and an output terminal; the second input terminal of the forward scan control unit is connected to a forward scan control signal line; A reverse scan control unit includes a second input terminal and an output terminal, wherein the second input terminal of the reverse scan control unit is connected to a reverse scan control signal line; and The pull-down unit includes a control terminal, an output terminal, and an input terminal; the control terminal of the pull-down unit is connected to the output terminal of the forward scan control unit and the output terminal of the reverse scan control unit, the output terminal of the pull-down unit is connected to a scan line, and the input terminal of the pull-down unit is connected to a low-level signal line. The display panel also includes at least one redundant signal line, which is disposed on the same layer as at least one of the forward scan control signal line, the reverse scan control signal line and the low-level signal line and is made of the same material.

2. The display panel of claim 1, wherein, The positive and negative sweep pull-down circuits described in Group J are arranged along the first direction.

3. The display panel of claim 1, wherein, Each group of forward and reverse scan pull-down circuits includes K rows of forward and reverse scan pull-down modules. Each row of forward and reverse scan pull-down modules includes N / K forward and reverse scan pull-down modules arranged along the second direction, where K is greater than or equal to 1 and less than or equal to N.

4. The display panel of claim 3, wherein, The output terminal of the pull-down unit of the forward and reverse scan pull-down module connected to the i-th scan line is connected to the i-th scan line. The first input terminal of the forward scan control unit of the forward and reverse scan pull-down module connected to the i-th scan line is connected to the (i+1)-th scan line. The first input terminal of the reverse scan control unit of the forward and reverse scan pull-down module connected to the i-th scan line is connected to the (i-1)-th scan line. The i is greater than or equal to 2 and less than or equal to N-1.

5. The display panel of claim 3 or 4, wherein, K=1。 6. The display panel of claim 3 or 4, wherein, K=2, each group of forward and reverse scan pull-down circuits includes a first row of forward and reverse scan pull-down modules and a second row of forward and reverse scan pull-down modules arranged along the first direction. The output terminal of the forward and reverse scan pull-down module in the first row is connected to the (2i-1)th scan line. The forward and reverse scan pull-down module in the second row includes a module whose output terminal is connected to the 2ith scan line, where i is greater than or equal to 1 and less than or equal to N / 2.

7. The display panel of claim 3 or 4, wherein, K=3, and each group of forward and reverse scan pull-down circuits includes a first row of forward and reverse scan pull-down modules, a second row of forward and reverse scan pull-down modules, and a third row of forward and reverse scan pull-down modules arranged along the first direction; The output terminal of the forward and reverse scan pull-down module in the first row of forward and reverse scan pull-down modules is connected to the (3i-2)th scan line, where i is greater than or equal to 1 and less than or equal to N / 3; The output terminal of the forward and reverse scan pull-down module in the second row is connected to the (3i-1)th scan line; The output terminal of the forward and reverse scan pull-down module in the third row is connected to the 3ith scan line.

8. The display panel of claim 3, wherein, The display panel also includes J groups of signal lines corresponding to each of the display zones. Each group of signal lines corresponds to a set of forward and reverse scan pull-down circuits. Each group of signal lines includes K groups of common signal lines. N / K forward and reverse scan pull-down modules in each row are connected to a set of common signal lines. Each group of shared signal lines includes one forward scan control signal line, one reverse scan control signal line, and one low-level signal line arranged adjacently. The forward scan control signal line, the reverse scan control signal line, and the low-level signal line all extend along the second direction and are arranged along the first direction. The second input terminal of the forward scan control unit of each row of N / K forward and reverse scan pull-down modules is connected to the same forward scan control signal line. The second input terminal of the reverse scan control unit of each row of N / K forward and reverse scan pull-down modules is connected to the same reverse scan control signal line. The input terminal of the pull-down unit of each row of N / K forward and reverse scan pull-down modules is connected to the same low-level signal line.

9. The display panel of claim 8, wherein, Also includes: Multiple data lines extend along the second direction and are arranged along the first direction; Among them, at least one redundant signal line extends along the second direction; The reverse scan control signal line, the low-level signal line, and the forward scan control signal line are respectively adjacent to the three adjacent data lines one-to-one and spaced apart.

10. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1-9.

Images