A three-dimensional capacitive cell structure, a three-dimensional capacitor and a three-dimensional integrated structure of a chip

Abstract

The present invention discloses a three-dimensional capacitor unit structure, a three-dimensional capacitor and a chip three-dimensional integrated structure, including a wafer; a misaligned hexagonal arrangement of three-tooth gear-shaped silicon pillar arrays are etched on the wafer, and silicon wall protrusions are formed on the silicon walls; a wafer insulating layer is grown on the surfaces of the silicon pillars, silicon walls and grooves; a three-dimensional capacitor layer is grown on the wafer insulating layer; a first distributed electrode and a second distributed electrode are provided at the top of each silicon pillar and at the top of the silicon wall protrusion; the first distributed electrode and the second distributed electrode are connected to a first planar metal redistribution layer and a second planar metal redistribution layer; the first planar metal redistribution layer and the second planar metal redistribution layer are connected to pads. By adopting three-tooth gear-shaped silicon pillars, the side wall area of the silicon pillars is increased without changing the period of the silicon pillar array, which is beneficial to further improving the capacitance density and still can ensure the uniformity of the groove gaps.

Description

Technical Field

[0001] The present invention belongs to the technical field of advanced electronic packaging, and in particular to a three-dimensional capacitor unit structure, a three-dimensional capacitor and a three-dimensional integrated structure of a chip thereof. Background Art

[0002] With the increase of integrated circuit chip frequency and switching speed, the frequency range of chip power noise is wider. While the multi-chip three-dimensional integration technology shortens the interconnection distance between chips and improves the integration density between chips, the power noise problem between integrated chips is becoming increasingly serious. The on-chip capacitors of the chip itself are small in value and cannot meet the low-frequency band filtering requirements. The traditional discrete capacitor method of surface-mounting around the chip is no longer applicable. How to provide large-capacitance, low-resistance, and low-inductance decoupling capacitors for three-dimensional integrated chips, suppress power noise, and provide a stable and pure power supply network for the chips in the three-dimensional integrated structure is an urgent problem to be solved.

[0003] Deep trenches are fabricated on a silicon substrate, which can increase the surface area of silicon and improve the capacitance density per unit area horizontally. Murata of Japan has introduced deep trench silicon capacitor products based on semiconductor MOS processes for DC decoupling and bypass filtering. There are also corresponding technologies in China. For example, the invention patent "Capacitance Structure and Its Forming Method" (application number 202010202321.5) applied by SMIC Manufacturing (Beijing) Co., Ltd., the invention patent "Internal Multilayer Electrode Connection Structure and Connection Method of Silicon Capacitor" (application number 201210165420.6) applied by Wuxi Nano Energy Technology Co., Ltd., the utility model patent "High-Capacity Silicon Capacitor with Groove Structure" (application number 201720825198.6) applied by Hongyan Microelectronics (Dalian) Co., Ltd., etc. These disclosed silicon-based capacitors continue the application scenarios of traditional discrete surface-mount capacitors and still adopt the lumped two-terminal lead-out form of traditional capacitors. This traditional lumped two-terminal capacitor lead-out form is suitable for wire-bonded chips with external pins distributed around the integrated circuit chip and can be surface-mounted around the chip. However, as high-end, high-speed, and high-capacity chips gradually adopt lead-out forms of narrow-pitch (less than 100 microns) micro-bump arrays, the number of micro-bumps for power and ground attributes can easily reach thousands or even tens of thousands. This lumped two-port capacitor obviously can no longer meet the requirements of high-frequency and low-parasitic decoupling capacitors for tens of millions of power-ground micro-bump pin pairs. In addition, these disclosed silicon-based capacitors are mainly based on the front-end process of silicon wafers. The silicon substrate mostly uses low-resistance silicon materials of n-type or p-type, and the electrodes mostly use doped polysilicon materials, with relatively high equipment requirements. In the middle-end wafer-level advanced packaging and integration process, a TSV (Through-Silicon-Via) silicon interposer substrate is introduced as a three-dimensional interconnection platform for chip integration with micro-bump arrays. The TSV silicon substrate usually needs to use high-resistance silicon with a resistivity of more than 1000 ohm·cm, and it is necessary to fabricate high-density capacitors compatible with the TSV process to meet the application needs of silicon-based chip integration. Summary of the Invention

[0004] To solve the problems existing in the prior art, the present invention provides a three-dimensional capacitor unit structure, a three-dimensional capacitor, and a three-dimensional integrated structure of a chip for solving the above problems.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A three-dimensional capacitor unit structure includes a wafer;

[0007] A staggered hexagonal arrangement of three-tooth gear-shaped silicon pillar arrays is etched on the wafer, and silicon wall protrusions are formed on the silicon walls;

[0008] A wafer insulating layer is grown on the surfaces of the silicon pillars, silicon walls, and grooves; a three-dimensional capacitor layer is grown on the wafer insulating layer;

[0009] At the top of each silicon pillar and at the top of the silicon wall protrusion, a first distributed electrode and a second distributed electrode are provided;

[0010] The first distributed electrode and the second distributed electrode are connected to a first planar metal redistribution layer and a second planar metal redistribution layer;

[0011] The first planar metal redistribution layer and the second planar metal redistribution layer are connected to the pads.

[0012] Preferably, it further includes TSV conductive vias, and the TSV conductive vias are connected to the first planar metal redistribution layer and the second planar metal redistribution layer, and further connected to the first distributed electrode and the second distributed electrode.

[0013] Preferably, the three-dimensional capacitor layer includes a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer and a filling layer;

[0014] On the wafer insulating layer, a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer are sequentially grown; a filling layer is formed in the surface groove of the third electrode layer.

[0015] Preferably, the first distributed electrode and the second distributed electrode are alternately distributed.

[0016] Preferably, the first planar metal redistribution layer is distributed in parallel strip shapes, and the first strip-shaped metal wiring and the second strip-shaped metal wiring with different polarities are arranged parallel to each other and staggered; the cutting direction of the second planar metal redistribution layer is perpendicular to the cutting direction of the strip-shaped metal wiring of the first planar metal redistribution layer.

[0017] Preferably, the diameter range of the silicon pillars is 3μm - 30μm; the ratio of the height to the diameter of the silicon pillars ranges from 3:1 to 20:1; the center distance between multiple silicon pillars is twice the diameter of the silicon pillars.

[0018] A discrete three-dimensional capacitor includes a three-dimensional capacitor unit structure as described in any one of the above;

[0019] The three-dimensional capacitor layer is integrated on one side of the wafer. The first distributed electrode and the second distributed electrode directly above the top of each silicon pillar and the silicon wall protrusion are respectively connected to the first planar metal redistribution layer and the second planar metal redistribution layer on the surface of this side of the wafer. The pads connected to the first planar metal redistribution layer and the second planar metal redistribution layer form a pad array. The power microbumps and ground microbumps on the pad array form a microbump array as the external pins of the discrete three-dimensional capacitor; the power microbumps and ground microbumps are alternately arranged, and one power microbump and one ground microbump can respectively correspond to multiple three-dimensional capacitor distributed electrodes.

[0020] A three-dimensional chip integration structure, including a discrete three-dimensional capacitor as described above;

[0021] The discrete three-dimensional capacitor is flip-chip bonded to one side surface of the packaging substrate through power microbumps and ground microbumps thereon to form a microbump array;

[0022] On the other side surface of the packaging substrate, a third chip is flip-chip bonded through microbumps to form a microbump array. The discrete three-dimensional capacitor is usually located directly below the third chip.

[0023] A three-dimensional chip integration structure, including a three-dimensional capacitor unit structure as described in any one of the above;

[0024] The three-dimensional capacitor unit structure is integrated on one side of the TSV silicon interposer substrate close to the chip. The first distributed electrode and the second distributed electrode directly above the tops of the respective silicon pillars and silicon wall protrusions are respectively connected to the first planar metal redistribution layer and the second planar metal redistribution layer on the upper surface of the TSV silicon interposer substrate;

[0025] The pad array formed by the pads serves as the external pins on the upper surface of each metal wiring layer of the TSV silicon interposer substrate, including the external pins connected to the chips assembled thereon; the chips are flip-chip bonded to the pads to form a pad array through microbumps, forming electrical connections with each metal wiring layer on the TSV silicon interposer substrate and the three-dimensional capacitor layer. Among them, the power microbumps connect the power pins of the chips and the second planar metal redistribution layer of the TSV silicon interposer substrate, the ground microbumps connect the ground pins of the chips and the first planar metal redistribution layer of the TSV silicon interposer substrate, and the third microbumps connect the other microbumps except for power and ground.

[0026] A three-dimensional chip integration structure, including a three-dimensional capacitor unit structure as described in any one of the above;

[0027] The three-dimensional capacitor layer is integrated on one side of the TSV silicon interposer substrate. The first distributed electrode and the second distributed electrode directly above the tops of the respective silicon pillars and silicon wall protrusions are respectively connected to the first planar metal redistribution layer and the second planar metal redistribution layer on this side surface of the TSV silicon interposer substrate;

[0028] A second chip is buried on the other side of the TSV silicon interposer substrate. The chip pads representing ground and power on the second chip are respectively connected to the second first planar metal redistribution layer and the second second planar metal redistribution layer on this side surface of the TSV silicon interposer substrate; the three-dimensional capacitor layer is electrically connected to the chip pads representing ground and power on the second chip through TSV conductive vias, and the first planar metal redistribution layer, the second first planar metal redistribution layer, the second planar metal redistribution layer, and the second second planar metal redistribution layer respectively located on both side surfaces of the TSV silicon interposer substrate.

[0029] Compared with the prior art, the present invention has the following beneficial technical effects:

[0030] The present invention provides a three-dimensional capacitor unit structure. By adopting a three-tooth gear-shaped silicon column, the side wall area of the silicon column is increased under the condition that the silicon column array period remains unchanged, which is conducive to further improving the capacitance density. In addition, the three-tooth gear-shaped silicon column can still ensure the uniformity of the groove gap, and the uniformity of the groove gap is the basic guarantee for the uniformity of the etching process, the capacitor electrode layer deposition process, and the capacitor dielectric layer deposition process. The three-tooth gear-shaped silicon column reduces the groove gap, increases the occupancy rate of the silicon material in the etching area unit, and alleviates the thermal stress problem in the subsequent groove filling process. The three-tooth gear-shaped silicon column still retains a complete central circular area, and reserves space for the subsequent setting of the capacitor electrode lead-out point at the top of the silicon column. The electrodes are led out at the top of each silicon column, which is conducive to reducing the parasitic resistance and parasitic inductance of the capacitor, so that the capacitor can have a faster electrical response and a higher operating frequency. From the perspective of structural mechanics, based on the stability of the equilateral triangle, the three-tooth gear-shaped silicon column structure is stronger than the toothless cylindrical structure, can support deeper grooves, and is less likely to tip over and bend in subsequent spin coating, cleaning, drying, film pressing and other processes.

[0031] The present invention provides a chip three-dimensional integrated structure, providing a spliced three-dimensional capacitor unit structure with high capacitance density, low parasitic inductance and low parasitic resistance; the connection between the chip power supply plane and the three-dimensional capacitor is achieved with the shortest distance and minimum parasitics, and large capacitance decoupling and filtering in a wide frequency band are provided to suppress power supply noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of the cross-section of the silicon pillars on the wafer after etching.

[0033] Figure 2 A schematic diagram of the surface of a three-dimensional capacitor unit after etching of a circular silicon pillar.

[0034] Figure 3 A schematic diagram of the surface of a three-dimensional capacitor unit after etching of a three-tooth gear-shaped silicon pillar.

[0035] Figure 4 Schematic diagram of the cross-sectional structure of a three-dimensional capacitor.

[0036] Figure 5a Example 1 of the distributed electrode planar position diagram of a three-dimensional capacitor having a three-tooth gear-shaped silicon pillar, which is a three-dimensional capacitor unit.

[0037] Figure 5b Example 2 of the distributed electrode planar position diagram of a three-dimensional capacitor having a three-tooth gear-shaped silicon column, which is a three-dimensional capacitor unit.

[0038] Figure 6Schematic cross-sectional view of a chip three-dimensional integration structure integrating three-dimensional capacitors.

[0039] Figure 7 Schematic cross-sectional view of another chip three-dimensional integration structure integrating three-dimensional capacitors.

[0040] Figure 8 Schematic cross-sectional view of a discrete three-dimensional capacitor structure.

[0041] Figure 9 An application embodiment of a discrete three-dimensional capacitor.

[0042] Figure 10 Schematic view of the structure of a three-dimensional capacitor unit after the first planar metal redistribution layer.

[0043] Figure 11 Schematic view of the structure of a three-dimensional capacitor unit after the second planar metal redistribution layer.

[0044] Figure 12 Schematic view of the structure inside a three-dimensional capacitor unit after the capacitor lead-out terminal.

[0045] Figure 13 Schematic view of an array capacitor formed by splicing 4 capacitor units.

[0046] In the attached drawings: 1 is a wafer; 1a is a silicon pillar; 1b is a silicon wall; 1c is a groove; 1ba is a silicon wall protrusion; 2 is a wafer insulating layer; 3 is a first electrode layer; 4 is a first dielectric layer; 5 is a second electrode layer; 6 is a second dielectric layer; 7 is a third electrode layer; 8 is a filling layer; 9 is an inter-electrode layer conductive via; 10 is a discrete three-dimensional capacitor; 11 is a first distributed electrode; 12 is a second distributed electrode; 13 is a TSV conductive via; 14 is a first planar metal redistribution layer; 15 is a second planar metal redistribution layer; 16 is a pad; 17a is a power micro-bump, 17b is a ground micro-bump, 17c is a third micro-bump, 18 is a solder ball; 19 is a three-dimensional capacitor layer, 19a is a first three-dimensional capacitor layer, 19b is a second three-dimensional capacitor layer; 20 is a chip pad; 21 is a first first planar metal redistribution layer; 21a is a metal wiring in the first first planar metal redistribution layer connecting the first distributed electrode; 21b is a metal wiring in the first first planar metal redistribution layer connecting the second distributed electrode; 22 is a first second planar metal redistribution layer; 22a is a metal wiring in the first second planar metal redistribution layer connecting the first distributed electrode; 22b is a metal wiring in the first second planar metal redistribution layer connecting the second distributed electrode; 23 is a capacitor lead-out terminal; 23a is a capacitor lead-out terminal connecting the first distributed electrode; 23b is a capacitor lead-out terminal connecting the second distributed electrode; 24 is a second first planar metal redistribution layer; 25 is a second second planar metal redistribution layer; 27 is a micro-bump; 100 is a TSV interposer substrate integrating a three-dimensional capacitor; 200 is a TSV interposer substrate integrating a chip and a three-dimensional capacitor; 300 is a packaging substrate; 101 is a first chip, 201 is a second chip, 301 is a third chip. Detailed implementation mode

[0047] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0048] The present invention provides a three-dimensional capacitor unit structure, including an array of misaligned hexagonal arranged three-tooth gear-shaped silicon pillars 1a, a silicon wall 1b with a silicon wall protrusion 1ba, a three-dimensional capacitor layer 19, a first distributed electrode 11 and a second distributed electrode 12 directly above the top of each silicon pillar 1a and silicon wall protrusion 1ba, a first planar metal redistribution layer 14 and a second planar metal redistribution layer 15 connecting the first distributed electrode 11 and the second distributed electrode 12, and a pad array composed of pads 16.

[0049] It further includes a TSV conductive via 13, and the TSV conductive via 13 connects the first planar metal redistribution layer 14 and the second planar metal redistribution layer 15, and further connects the first distributed electrode 11 and the second distributed electrode 12.

[0050] The three-dimensional capacitive layer 19 includes a first electrode layer 3, a first dielectric layer 4, a second electrode layer 5, a second dielectric layer 6, a third electrode layer 7, and a filling layer 8.

[0051] The dielectric layer materials of the first dielectric layer 4 and the second dielectric layer 6 can be inorganic dielectrics, including silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium oxide, but not limited thereto; the above dielectric layer materials can be dielectric materials or ferroelectric materials, including BT (BaTiO3), ST (SrTiO3), BS (BiScO3), PT (PbTiO3), PZ (PbZrO3), PZT (PbZr x Ti 1-x O3), BST (BaSr x Ti 1-x O3), etc., but not limited thereto; the above dielectric layer can be composed of a single material layer such as an inorganic dielectric or a ferroelectric material, or can be composed of two or more inorganic dielectric layers, or two or more ferroelectric material layers, or a composite dielectric layer with a "sandwich" structure composed of an inorganic dielectric layer - ferroelectric material layer - inorganic dielectric layer.

[0052] The materials of the first electrode layer 3, the second electrode layer 5, and the third electrode layer 7 are conductive materials, which can be metal materials or non-metal conductive materials such as TiN.

[0053] The material of the filling layer 8 can be an organic material, an inorganic material, or an inorganic-organic composite material.

[0054] The first distributed electrode 11 and the second distributed electrode 12 are alternately distributed; the capacitive units can be spliced into array capacitors with different areas and shapes according to requirements. The capacitive leads 23 of each capacitive unit in the spliced array capacitor are electrically insulated from each other, that is, each capacitive unit in the array capacitor is electrically insulated and independent of each other.

[0055] The first first-plane metal redistribution layer 21 is in the form of parallel strip-shaped metal wirings. The metal wiring 21a connecting the first distributed electrode in the first first-plane metal redistribution layer 21 and the metal wiring 21b connecting the second distributed electrode in the first first-plane metal redistribution layer are electrically insulated from each other and have different polarities. 21a and 21b are arranged alternately;

[0056] The metal wiring 22a connecting the first distributed electrode and the metal wiring 22b connecting the second distributed electrode in the first second-plane metal redistribution layer 22 are electrically insulated from each other and have different polarities. The splitting directions of 22a and 22b in the first second-plane metal redistribution layer 22 are perpendicular to the splitting directions of 21a and 21b in the first first-plane metal redistribution layer. 22a and 22b in the first second-plane metal redistribution layer 22 are respectively electrically connected to 21a and 21b in the first first-plane metal redistribution layer to respectively form electrical connections with the first distributed electrode 11 and the second distributed electrode 12.

[0057] The capacitance lead-out terminal 23a connecting the first distributed electrode and the capacitance lead-out terminal 23b connecting the second distributed electrode are electrically insulated from each other and have different polarities. By respectively electrically connecting 22a and 22b in the first second-plane metal redistribution layer 22 and 21a and 21b in the first first-plane metal redistribution layer, electrical connections with the first distributed electrode 11 and the second distributed electrode 12 are respectively formed.

[0058] Among them, the first three-dimensional capacitance layer 19a and the second three-dimensional capacitance layer 19b are integrated on one side (the upper surface) of the TSV silicon interposer substrate close to the first chip 101. The first distributed electrode 11 and the second distributed electrode 12 located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first-plane metal redistribution layer 14 (ground-plane metal layer) and the second-plane metal redistribution layer 15 (power-plane metal layer) on the upper surface of the TSV silicon interposer substrate. The pad array formed by the pads 16 serves as the external pins on the upper surface of each metal wiring layer (including but not limited to the first-plane metal redistribution layer 14 and the second-plane metal redistribution layer 15) of the TSV silicon interposer substrate, including the external pins connected to the first chip 101 assembled thereon; the first chip 101 is flip-chip bonded to the pad array formed by the pads 16 through the power microbumps 17a, the ground microbumps 17b, and the third microbumps 17c to form electrical connections with each metal wiring layer on the TSV silicon interposer substrate and with the first three-dimensional capacitance layer 19a and the second three-dimensional capacitance layer 19b. Among them, the power microbumps 17a connect the power pins of the first chip 101 and the second-plane metal redistribution layer 15 of the TSV silicon interposer substrate, the ground microbumps 17b connect the ground pins of the first chip 101 and the first-plane metal redistribution layer 14 of the TSV silicon interposer substrate, and the third microbumps 17c connect other microbumps except for power and ground. Further, electrical connections are formed between the power pins and the ground pins of the first chip 101 and the first distributed electrode 11 and the second distributed electrode 12 of the three-dimensional capacitance layer respectively, realizing the decoupling and filtering of the power network of the first chip 101 by the first three-dimensional capacitance layer 19a and the second three-dimensional capacitance layer 19b.

[0059] Among them, the three-dimensional capacitor layer 19 is integrated on one side of the TSV silicon interposer substrate. The first distributed electrode 11 and the second distributed electrode 12 located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first planar metal redistribution layer 14 and the second planar metal redistribution layer 15 on the surface of this side of the TSV silicon interposer substrate; the second chip 201 is embedded on the other side of the TSV silicon interposer substrate. The chip pads 20 representing ground and power supply on the second chip 201 are respectively connected to the second first planar metal redistribution layer 24 and the second second planar metal redistribution layer 25 on the surface of this side of the TSV silicon interposer substrate; the first distributed electrode 11 and the second distributed electrode 12 of the three-dimensional capacitor layer 19 pass through the TSV conductive vias 13, and the first planar metal redistribution layer 14, the second first planar metal redistribution layer 24 and the second planar metal redistribution layer 15, the second second planar metal redistribution layer 25 located on both surfaces of the TSV silicon interposer substrate respectively, to form an electrical connection with the chip pads 20 of the second chip 201 for ground and power supply, realizing the decoupling and filtering of the power network of the second chip 201 by the three-dimensional capacitor layer 19.

[0060] Among them, the third chip 301 is flip-chip bonded to a surface of the package substrate 300 through micro-bumps 27 to form a micro-bump array. The discrete three-dimensional capacitor 10 is flip-chip bonded to the other surface of the package substrate 300 through the power micro-bumps 17a and the ground micro-bumps 17b thereon to form a micro-bump array, realizing the electrical connection between the pins of the power property and the ground property of the third chip 301 and the first distributed electrode 11 and the second distributed electrode 12 of the discrete three-dimensional capacitor 10, and realizing the decoupling and filtering of the power network of the third chip 301 by the discrete three-dimensional capacitor 10. The discrete three-dimensional capacitor 10 is usually located at the central position directly below the third chip 301.

[0061] The described discrete three-dimensional capacitor 10 has a structure including that the three-dimensional capacitor layer 19 is integrated on one side of the wafer 1. The first distributed electrode 11 and the second distributed electrode located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first planar metal redistribution layer 14 (ground plane metal layer) and the second planar metal redistribution layer 15 (power supply plane metal layer) on the surface of this side of the wafer 1. The pads 16 connecting the above metal layers form a pad array, and the power micro-bumps 17a and the ground micro-bumps 17b thereon form a micro-bump array as the external pins of the discrete three-dimensional capacitor. The power micro-bumps 17a and the ground micro-bumps 17b are arranged alternately, and one power micro-bump 17a and one ground micro-bump 17b can respectively correspond to multiple three-dimensional capacitor distributed electrodes.

[0062] The three-dimensional capacitor unit structure of the present invention provides a spliceable three-dimensional capacitor unit structure with high capacitance density, low parasitic inductance, and low parasitic resistance; the present invention connects the chip power supply plane and the three-dimensional capacitor with the shortest distance and minimum parasitics, providing large-capacitance decoupling and filtering in a wide frequency band range and suppressing power supply noise.

[0063] Embodiment 1

[0064] As Figure 1 shown, the wafer 1 is preferably a conventional single-crystalline silicon substrate wafer, and there is no special requirement for its conductivity. It can be low-resistance silicon or high-resistance silicon.

[0065] When there are other structures on the silicon wafer 1, such as TSVs, transmission lines, etc., considering the high-frequency loss problems of TSVs and transmission lines, high-resistance silicon can be preferably used.

[0066] According to the formula of the capacitor , increasing the capacitor surface area can effectively increase the capacitance. As Figure 1 shown, a plurality of silicon pillars 1a are etched in a region on one surface of the wafer 1 to form a silicon pillar array. The etched part around the silicon pillars 1a forms grooves 1c, and silicon walls 1b are formed around the etched region. The side walls of the silicon pillars 1a and the silicon walls 1b are approximately perpendicular to the surface of the wafer 1. For the convenience of the subsequent growth and deposition of the thin film layer on the side walls, the silicon pillars 1a and the silicon walls 1b can also be smaller at the top and larger at the bottom, that is, the side walls are in an "eight" shape, but the deviation angle from the vertical is preferably controlled within 5 degrees.

[0067] As Figure 2 shown, the surface shape, height, and arrangement form of the silicon pillars 1a will all affect the surface area of the etched region. In the design of the etched region structure, it is necessary to increase the surface area ratio (the ratio of the actual three-dimensional surface area to the planar two-dimensional area) as much as possible under the condition allowed by the subsequent capacitor process.

[0068] As Figure 2 shown, a circle is the most conventional upper surface shape of the silicon pillars 1a. Compared with the square array arrangement, the staggered hexagonal arrangement has a larger surface area ratio. The silicon walls 1b are composed of the union of a "hui" character-shaped circular wall and the silicon pillars intersecting with it. For the silicon pillars intersecting with the "hui" character-shaped circular wall, the part protruding from the "hui" character-shaped circular wall forms silicon wall protrusions 1ba on the silicon walls 1b. The existence of the silicon wall protrusions 1ba can further increase the surface area ratio. Thereafter, since electrodes need to be led out from the top of the upper surface of each silicon pillar 1a and the silicon pillars corresponding to the silicon wall protrusions 1ba, and considering the strength of the silicon pillars 1a in the process, the diameter of the silicon pillars 1a is preferably in the range of 3um - 30 microns, the ratio of the height to the diameter of the silicon pillars 1a is preferably in the range of 3:1 - 20:1, and the center distance between the silicon pillars 1a is preferably close to 2 times the diameter of the silicon pillars 1a.

[0069] As Figure 3As shown in the figure, for the deep groove capacitor, the increased effective capacitance area is the side wall area of the silicon pillar 1a and the silicon wall 1b. Figure 2 The three-tooth round-top rectangular protrusions are introduced into the 15-minute, 35-minute and 55-minute positions of the circular silicon column 1a shown in the figure, respectively, to form a three-tooth gear-shaped silicon column 1a, and the silicon wall protrusion 1ba on the silicon wall 1b is also introduced with the same three-tooth round-top rectangular protrusion to form an attached silicon column 1a. Figure 3 A schematic diagram of the surface of an etched area unit is shown.

[0070] The three-tooth gear-shaped silicon column is an extension of the circular silicon column, which is the union of the circular silicon column and the dome-shaped rectangular protrusion. Compared with the circular silicon column, the three-tooth gear-shaped silicon column increases the side wall area of the silicon column while the silicon column array period remains unchanged, which is conducive to further improving the capacitance density. The three-tooth gear-shaped silicon column can still ensure the uniformity of the gap of the groove 1c. The uniformity of the gap of the groove 1c is the basic guarantee for the uniformity of the etching process, the deposition process of the capacitor electrode layer, and the deposition process of the capacitor dielectric layer.

[0071] The three-tooth gear-shaped silicon pillar reduces the gap of the groove 1c, increases the occupancy rate of the silicon material in the etching area unit, and alleviates the thermal stress problem in the subsequent groove filling process.

[0072] The three-tooth gear-shaped silicon column still retains a complete circular area in the center, reserving space for the subsequent setting of capacitor distributed electrodes at the top of the silicon column. Leading out the electrodes at the top of each silicon column is beneficial to reducing the parasitic resistance and parasitic inductance of the capacitor, allowing the capacitor to have a faster electrical response and a higher operating frequency.

[0073] And from the perspective of structural mechanics, based on the stability of the equilateral triangle, the three-tooth gear-shaped silicon column structure is stronger than the cylindrical structure, can support deeper grooves, and is less likely to tip over and bend during subsequent spin coating, cleaning, spin drying, and film pressing processes.

[0074] Example 2

[0075] like Figure 4 As shown, after the etching of the silicon pillar 1a on the wafer is completed, a wafer insulating layer 2 is grown on the surface of the silicon pillar 1a, the silicon wall 1b and the groove 1c. The preferred material of the wafer insulating layer 2 is SiO2. Then, a first electrode layer 3, a first dielectric layer 4, a second electrode layer 5, a second dielectric layer 6, and a third electrode layer 7 are grown in sequence on the wafer insulating layer 2.

[0076] The material of the electrode layer is a conductive material, which can be metal or non-metal, and the material of the dielectric layer can be an inorganic dielectric, including silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium oxide, but not limited thereto;

[0077] The dielectric layer material can be a ferroelectric material, including BT (BaTiO3), ST (SrTiO3), BS (BiScO3)PT (PbTiO3), PZ (PbZrO3), PZT (PbZr x Ti 1-x O3), BST (BaSr x Ti 1-x O3), etc., but not limited thereto;

[0078] The dielectric layer can be composed of a single material layer such as an inorganic dielectric or a ferroelectric material, or can be composed of two or more inorganic dielectric layers, or two or more ferroelectric material layers, or a dielectric layer with a "sandwich" structure composed of an inorganic dielectric layer - ferroelectric material layer - inorganic dielectric layer.

[0079] The present invention can be applied to the alternation of more electrode layers and dielectric layers. For the sake of simplicity, only the structure of the alternation of three electrode layers and two dielectric layers is described.

[0080] The filling layer 8 can be a non-conductive organic material. In this embodiment, the filling layer 8 is preferably prepared by a vacuum laminating method. After filling and growing the first electrode layer 3, the first dielectric layer 4, the second electrode layer 5, the second dielectric layer 6, and the third electrode layer 7, the remaining space of the groove 1c, the filling layer 8 also covers the surface of the third electrode layer 7 corresponding to the surface of the wafer 1, forming a passivation layer.

[0081] The edges of the first dielectric layer 4, the second electrode layer 5, the second dielectric layer 6, the third electrode layer 7, and the filling layer 8 sequentially wrap the underlying electrode layer and dielectric layer. That is to say, the edges of the first electrode layer 3, the first dielectric layer 4, the second electrode layer 5, the second dielectric layer 6, the third electrode layer 7, and the filling layer 8 expand outwards in sequence and are in contact with the wafer insulating layer 2 in sequence. This structure is beneficial to sharing the attack on the edge of the contact interface between the layer and the wafer insulating layer 2 in the subsequent process, reducing the process difficulty. On the other hand, it is also beneficial to increase the capacitance. The first electrode layer 3, the first dielectric layer 4, the second electrode layer 5, the second dielectric layer 6, the third electrode layer 7, and the filling layer 8 together constitute the three-dimensional capacitance layer 19.

[0082] The filling layer 8 is provided with electrode openings at the top of each silicon pillar 1a and at the top of the silicon wall protrusion 1ba, exposing the metal thereunder to form the first distributed electrode 11 and the second distributed electrode 12.

[0083] In this embodiment, the opening is preferably a circular opening, and the diameter of the opening is smaller than the diameter of the circular part at the center of the silicon pillar 1a.

[0084] To increase the capacitance density, the first electrode layer 3 and the third electrode layer 7 are electrically interconnected through the via holes 9 between electrode layers, which are also located at the top of each silicon pillar 1a and the top of the silicon wall protrusion 1ba. The via holes 9 between electrode layers are usually located directly below the distributed electrode openings on the filling layer 8. The via holes 9 between electrode layers electrically connect the first electrode layer 3 and the third electrode layer 7 to the first distributed electrode 11.

[0085] The second electrode layer 5 is exposed at the distributed electrode openings through the via holes 9 between electrode layers and is electrically connected to the second distributed electrode 12.

[0086] The first distributed electrode 11 and the second distributed electrode 12 are interconnected with the upper power plane P or ground plane G through a metal re - wiring process with the shortest possible distance, so as to have smaller parasitic resistance and parasitic inductance. In this way, when there is a transient charge demand at any point on the power plane P or ground plane G, the charge can be provided from the first distributed electrode 11 and the second distributed electrode 12 closest to that point at the fastest speed, suppressing the generation of instantaneous voltage fluctuations on the power plane P or ground plane G; when there is power noise at any point on the power plane P or ground plane G, the noise can also be bypassed and filtered out through the first distributed electrode 11 and the second distributed electrode 12 closest to that point at the fastest speed, suppressing the propagation of power noise.

[0087] Embodiment 3

[0088] As Figure 5a and Figure 5b shown, the first distributed electrode 11 and the second distributed electrode 12 are located directly above the top of each silicon pillar 1a and the silicon wall protrusion 1ba, and the first distributed electrode 11 and the second distributed electrode 12 are alternately distributed.

[0089] For the capacitance structure disclosed in the present invention, the first distributed electrode 11 and the second distributed electrode 12 actually have no positive and negative polarity distinction. For the sake of simplicity in description, Figure 4 and in Fig. 5( Figure 5a and Figure 5b ), the first distributed electrode 11 is connected to the power plane (P) and is labeled as "+", and the second distributed electrode 12 is connected to the ground plane (G) and is labeled as "-". Connecting them in the reverse way will not affect the effect of the present invention either.

[0090] The size of a capacitance unit can be adjusted according to actual application requirements by adjusting the size of the silicon pillar array. In use, multiple capacitance units can be spliced according to actual application requirements. The electrode layers within one capacitance unit are continuous, and the edges of the electrode layers are retracted compared to the unit edges. The electrode layers between adjacent capacitance units are disconnected and insulated, that is, the capacitance layers of each capacitance unit are relatively independent.

[0091] Example 4

[0092] As shown Figure 6 in the figure, the first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b are integrated on one side (upper surface) of the TSV silicon interposer substrate close to the first chip 101. The first distributed electrode 11 and the second distributed electrode 12 located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first planar metal redistribution layer 14 (ground plane metal layer) and the second planar metal redistribution layer 15 (power plane metal layer) on the upper surface of the TSV silicon interposer substrate. The pad array formed by the pads 16 serves as the external pins on the upper surface of each metal wiring layer (including but not limited to the first planar metal redistribution layer 14 and the second planar metal redistribution layer 15) of the TSV silicon interposer substrate, including the external pins connected to the first chip 101 assembled thereon. The first chip 101 is flip-chip bonded to the pad array formed by the pads 16 through the power micro-bumps 17a, ground micro-bumps 17b, and third micro-bumps 17c to form electrical connections with the metal wiring layers of each layer on the TSV silicon interposer substrate, as well as with the first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b. Among them, the power micro-bump 17a connects the power pin of the first chip 101 and the second planar metal redistribution layer 15 of the TSV silicon interposer substrate, the ground micro-bump 17b connects the ground pin of the first chip 101 and the first planar metal redistribution layer 14 of the TSV silicon interposer substrate, and the third micro-bump 17c connects other micro-bumps except for power and ground. The first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b are located directly below the power micro-bumps 17a and ground micro-bumps 17b of the first chip 101, and provide transient charge storage for the first chip 101 through the first planar metal redistribution layer 14, the second planar metal redistribution layer 15, and the pads 16 with the shortest path. One power micro-bump 17a and one ground micro-bump 17b can respectively correspond to multiple three-dimensional capacitor distributed electrodes. The electrode layers inside the first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b are not electrically connected, but the first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b can be electrically connected through the first planar metal redistribution layer 14 and the second planar metal redistribution layer 15.

[0093] The first chip 101 is flip-chip bonded to one side of the TSV interposer substrate 100 integrated with three-dimensional capacitors close to the first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b. The first three-dimensional capacitor layer 19a and the second three-dimensional capacitor layer 19b directly provide large-capacitance decoupling and filtering in a wide frequency band range for the power supply plane of the first chip 101 through the first planar metal redistribution layer 14 (ground plane metal layer), the second planar metal redistribution layer 15 (power plane metal layer), ground micro-bumps 17b, and power micro-bumps 17a. The solder balls 18 serve as external solder balls and provide external electrical connections for the entire integrated structure through the TSV conductive vias 13.

[0094] Example 5

[0095] As Figure 7 shown, the three-dimensional capacitor layer 19 is integrated on one side of the TSV silicon interposer substrate, and the first distributed electrode 11 and the second distributed electrode located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first planar metal redistribution layer 14 and the second planar metal redistribution layer 15 on the surface of this side of the TSV silicon interposer substrate; the second chip 201 is embedded on the other side of the TSV silicon interposer substrate, and the chip pads 20 representing ground and power supply on the second chip 201 are respectively connected to the second first planar metal redistribution layer 24 and the second second planar metal redistribution layer 25 on the surface of this side of the TSV silicon interposer substrate. The connection method is preferably metal re-wiring connection. Compared with wire bonding and bump flip-chip bonding, this connection method has a shorter connection distance, smaller parasitic parameters, and better DC and high-frequency performance. The three-dimensional capacitor layer 19 provides large-capacitance decoupling and filtering in a wide frequency band range for the power supply plane of the second chip 201 through the TSV conductive vias 13, and the first planar metal redistribution layer 14, the second first planar metal redistribution layer 24, the second planar metal redistribution layer 15, and the second second planar metal redistribution layer 25 located on both sides of the surface of the TSV silicon interposer substrate respectively.

[0096] The TSV interposer substrate 200 integrated with chips and three-dimensional capacitors can be used as a substrate to micro-assemble other functional chips, functional components, and components thereon, or can be micro-assembled as a new recreated chip onto other packaging substrates or printed circuit boards, or can also be used as a layer in a three-dimensional chip for subsequent three-dimensional stacking.

[0097] Example 6

[0098] An application example of a discrete three-dimensional capacitor. As Figure 8 shown, the three-dimensional capacitor structure disclosed in the present invention can also be not combined with TSV, but form an independent discrete three-dimensional capacitor 10. As Figure 8 shown, the three-dimensional capacitor layer 19 is integrated on one side of the wafer 1, and the first distributed electrode 11 and the second distributed electrode located directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba are respectively connected to the first planar metal redistribution layer 14 (ground plane metal layer) and the second planar metal redistribution layer 15 (power supply plane metal layer) on the surface of this side of the wafer 1. The pads 16 connecting the above metal layers form a pad array, and the power micro-bumps 17a and the ground micro-bumps 17b thereon form a micro-bump array as the external pins of the discrete three-dimensional capacitor. The power micro-bumps 17a and the ground micro-bumps 17b are arranged alternately, and one power micro-bump 17a and one ground micro-bump 17b can respectively correspond to multiple three-dimensional capacitor distributed electrodes.

[0099] Example 7

[0100] As shown Figure 9 in the figure, the third chip 301 is flip-chip bonded to a surface of the package substrate 300 through microbumps 27 to form a microbump array. The discrete three-dimensional capacitor 10 is flip-chip bonded to another surface of the package substrate 300 through power microbumps 17a and ground microbumps 17b thereon to form microbump arrays, realizing electrical connections between the power and ground pins of the third chip 301 and the first distributed electrode 11 and the second distributed electrode 12 of the discrete three-dimensional capacitor 10 respectively, and achieving decoupling and filtering of the power network of the third chip 301 by the discrete three-dimensional capacitor 10. Usually, the power and ground pins of the third chip 301 occupy a relatively large area in the central region of the chip. Therefore, the area of the discrete three-dimensional capacitor 10 is usually smaller than that of the third chip 301. The discrete three-dimensional capacitor 10 is usually located at the central position directly below the third chip 301 to provide large-capacitance decoupling and filtering in a wide frequency band range for the power supply plane of the third chip 301 with the shortest connection distance.

[0101] Embodiment 8

[0102] As shown Figure 10 in the figure, according to the polarity distribution of the first distributed electrode 11 and the second distributed electrode 12 directly above the tops of the respective silicon pillars 1a and the silicon wall protrusions 1ba, the first planar metal redistribution layer 21 is distributed in parallel strips. Among them, the strip metal wiring 21a connects the first distributed electrodes 11 with the polarity label of “+”, and the strip metal wiring 21b connects the second distributed electrodes 12 with the polarity label of “-”. The metal wiring 21a connecting the first distributed electrodes in the first planar metal redistribution layer and the metal wiring 21b connecting the second distributed electrodes in the first planar metal redistribution layer are arranged in parallel and staggered with each other, maintaining the characteristics of wide line width and narrow line pitch, which is beneficial to increasing capacitance, reducing parasitic inductance and parasitic resistance.

[0103] Embodiment 9

[0104] As shown Figure 11As shown, the first second-plane metal redistribution layer 22 is located above the first first-plane metal redistribution layer 21. Among them, the first second-plane metal redistribution layer 22 is approximately bisected into two parts: the metal wiring 22a in the first second-plane metal redistribution layer connecting the first distributed electrode and the metal wiring 22b in the first second-plane metal redistribution layer connecting the second distributed electrode. The cutting direction of the metal wiring 22a in the first second-plane metal redistribution layer connecting the first distributed electrode and the metal wiring 22b in the first second-plane metal redistribution layer connecting the second distributed electrode of the second-plane metal redistribution layer is perpendicular to the cutting direction of 21a of the first-plane metal redistribution layer and the metal wiring 21b in the first first-plane metal redistribution layer connecting the second distributed electrode, so as to further increase the capacitance, reduce the parasitic inductance and parasitic resistance. The metal wiring 22a in the first second-plane metal redistribution layer connecting the first distributed electrode and the metal wiring 22b in the first second-plane metal redistribution layer connecting the second distributed electrode of the second-plane metal redistribution layer are electrically connected to the metal wiring 21a in the first first-plane metal redistribution layer connecting the first distributed electrode and the metal wiring 21b in the first first-plane metal redistribution layer connecting the second distributed electrode of the first-plane metal redistribution layer through the conductive vias between the metal layers. For example, the metal wiring 22a in the first second-plane metal redistribution layer connecting the first distributed electrode of the second-plane metal redistribution layer is electrically connected to 21a of the first-plane metal redistribution layer, and then electrically connected to all the silicon pillars 1a and the first distributed electrodes 11 at the tops of the silicon wall protrusions 1ba; the metal wiring 22b in the first second-plane metal redistribution layer connecting the second distributed electrode of the second-plane metal redistribution layer is electrically connected to the metal wiring 21b in the first first-plane metal redistribution layer connecting the second distributed electrode of the first-plane metal redistribution layer, and then electrically connected to all the silicon pillars 1a and the second distributed electrodes 12 at the tops of the silicon wall protrusions 1ba.

[0105] Example 10

[0106] As Figure 12As shown, on the metal pattern connecting the metal wiring 22a connecting the first distributed electrode and the metal wiring 22b connecting the second distributed electrode in the first second-plane metal redistribution layer, the capacitance lead-out terminals 23a connecting the first distributed electrode and the capacitance lead-out terminals 23b connecting the second distributed electrode are respectively prepared; the capacitance lead-out terminals 23a connecting the first distributed electrode and the capacitance lead-out terminals 23b connecting the second distributed electrode are preferably located at the central positions of the metal wiring 22a connecting the first distributed electrode and the metal wiring 22b connecting the second distributed electrode in the first second-plane metal redistribution layer respectively. The capacitance lead-out terminals 23 are preferably circular. The capacitance lead-out terminals 23 can be a circular opening on the dielectric layer covering the metal pattern of the metal wiring 22a connecting the first distributed electrode and the metal wiring 22b connecting the second distributed electrode in the first second-plane metal redistribution layer, or can be a layer of circular metal additionally fabricated on the metal pattern of the metal wiring 22a connecting the first distributed electrode and the metal wiring 22b connecting the second distributed electrode in the first second-plane metal redistribution layer, or can also be bumps at the same positions added on the above two cases. The edge of the first second-plane metal redistribution layer 22 completely wraps the edge of the first first-plane metal redistribution layer 21, and the edge of the first second-plane metal redistribution layer 22 is smaller than the edge of this capacitance unit.

[0107] Embodiment 11

[0108] As Figure 13 shown, the above capacitance units can be spliced into array capacitors with different areas and shapes according to requirements. For example, the attached Figure 13 is a 2×2 capacitance array. Since the edge of the first second-plane metal redistribution layer 22 completely wraps the edge of the first first-plane metal redistribution layer 21 and the edge of the first second-plane metal redistribution layer 22 is smaller than the edge of this capacitance unit, the capacitance lead-out terminals 23 of each capacitance unit in the spliced array capacitor are electrically insulated and independent of each other. The defect of the inter-metal dielectric insulation layer leading to leakage is one of the main reasons for the failure of the capacitor. After the above capacitance lead-out terminals 23 are prepared, the leakage characteristics of each capacitance unit can be tested. For the capacitance units that do not meet the leakage requirements, the method of changing the capacitance lead-out terminals 23 (such as removing the bumps on the capacitance lead-out terminals 23, covering the capacitance lead-out terminals 23, etc.) can be used for removal, which does not affect the normal application of other capacitance units, thereby improving the yield of the array capacitor, reducing the process control requirements, and reducing the cost.

Claims

1. A three-dimensional capacitive cell structure, characterized in that, It includes a wafer (1); On the wafer (1), an array of staggered hexagonal arranged three-tooth gear-shaped silicon pillars (1a) is etched, and silicon wall protrusions (1ba) are formed on the silicon walls (1b); A wafer insulating layer (2) grows on the surfaces of the silicon pillars (1a), silicon walls (1b) and grooves (1c); a three-dimensional capacitor layer (19) grows on the wafer insulating layer (2); The three-dimensional capacitor layer (19) includes a first electrode layer (3), a first dielectric layer (4), a second electrode layer (5), a second dielectric layer (6), a third electrode layer (7) and a filling layer (8); The first electrode layer (3), the first dielectric layer (4), the second electrode layer (5), the second dielectric layer (6), and the third electrode layer (7) grow successively on the wafer insulating layer (2); a filling layer (8) is formed in a groove on the surface of the third electrode layer (7); At the tops of a part of the silicon pillars (1a) and at the tops of a part of the silicon wall protrusions (1ba), a first distributed electrode (11) is provided, and at the tops of the remaining silicon pillars (1a) and at the tops of the remaining silicon wall protrusions (1ba), a second distributed electrode (12) is provided; The first distributed electrode (11) and the second distributed electrode (12) are respectively connected to a first planar metal redistribution layer (14) and a second planar metal redistribution layer (15); the first planar metal redistribution layer (14) and the second planar metal redistribution layer (15) are respectively connected to pads (16); the first distributed electrode (11) is electrically connected to the first electrode layer (3) and the third electrode layer (7) through an inter-electrode conductive via (9), while the second distributed electrode (12) is electrically connected to the second electrode layer (5).

2. The three-dimensional capacitive cell structure according to claim 1, characterized in that It further includes TSV conductive vias (13), a part of the TSV conductive vias (13) is connected to the first planar metal redistribution layer (14), and the remaining part of the TSV conductive vias (13) is connected to the second planar metal redistribution layer (15), and then are respectively connected to the first distributed electrode (11) and the second distributed electrode (12).

3. A three-dimensional capacitive cell structure according to claim 1, characterized in that, The first distributed electrode (11) and the second distributed electrode (12) are alternately distributed.

4. A three-dimensional capacitive cell structure according to claim 1, characterized in that, The first planar metal redistribution layer (14) is distributed in parallel strip shapes, and the first strip-shaped metal wiring (21a) and the second strip-shaped metal wiring (21b) with different polarities are arranged parallel to each other and staggered; The cutting direction of the second planar metal redistribution layer (15) is perpendicular to the cutting direction of the strip-shaped metal wiring of the first planar metal redistribution layer.

5. A three-dimensional capacitive cell structure according to claim 1, characterized in that, The diameter range of the silicon pillars (1a) is 3μm - 30μm; the ratio of the height to the diameter of the silicon pillars (1a) ranges from 3:1 to 20:1; the center distance between multiple silicon pillars (1a) is twice the diameter of the silicon pillars (1a).

6. A discrete three-dimensional capacitor, characterized in that, It includes a three-dimensional capacitor unit structure according to any one of claims 1 to 5; The three-dimensional capacitor layer (19) is integrated on one side of the wafer (1). The first distributed electrode (11) and the second distributed electrode directly above the top of each silicon pillar (1a) and the silicon wall protrusion (1ba) are respectively connected to the first planar metal redistribution layer (14) and the second planar metal redistribution layer (15) on the surface of this side of the wafer (1). The pads (16) connected to the first planar metal redistribution layer (14) and the second planar metal redistribution layer (15) form a pad array. The power microbumps (17a) and the ground microbumps (17b) on the pad array form a microbump array as the external pins of the discrete three-dimensional capacitor. The power microbumps (17a) and the ground microbumps (17b) are arranged alternately. One said power microbump (17a) corresponds to multiple distributed electrodes of the three-dimensional capacitor, and one said ground microbump (17b) corresponds to multiple distributed electrodes of the three-dimensional capacitor.

7. A three-dimensional integrated structure of a chip, characterized in that Comprising a discrete three-dimensional capacitor as described in claim 6; The discrete three-dimensional capacitor (10) is flip-chip bonded to one surface of the package substrate (300) through the power microbumps (17a) and the ground microbumps (17b) thereon to form a microbump array. On the other surface of the package substrate (300), a third chip (301) is flip-chip bonded through microbumps (27) to form a microbump array. The discrete three-dimensional capacitor (10) is located directly below the third chip (301).

8. A three-dimensional integrated structure of a chip, characterized in that Comprising a three-dimensional capacitor unit structure as described in any one of claims 1 to 5; The three-dimensional capacitor unit structure is integrated on one side of the TSV silicon interposer substrate close to the chip (101). The first distributed electrode (11) and the second distributed electrode (12) directly above the top of each silicon pillar (1a) and the silicon wall protrusion (1ba) are respectively connected to the first planar metal redistribution layer (14) and the second planar metal redistribution layer (15) on the upper surface of the TSV silicon interposer substrate. The pad array formed by the pads (16) serves as the external pins of each metal wiring layer on the upper surface of the TSV silicon interposer substrate, including the external pins connected to the chip (101) assembled thereon. The chip (101) is flip-chip bonded to the pad array formed by the pads (16) to form electrical connections with each metal wiring layer on the TSV silicon interposer substrate and the three-dimensional capacitor layer (19). Among them, the power microbumps (17a) are connected to the power pins of the chip (101) and the second planar metal redistribution layer (15) of the TSV silicon interposer substrate, the ground microbumps (17b) are connected to the ground pins of the chip (101) and the first planar metal redistribution layer (14) of the TSV silicon interposer substrate, and the third microbumps (17c) are connected to the other microbumps except the power microbumps (17a) and the ground microbumps (17b).

9. A three-dimensional integrated structure of a chip, characterized in that, Comprising a three-dimensional capacitor unit structure as described in any one of claims 1 to 5; The three-dimensional capacitor layer (19) is integrated on one side of the TSV silicon interposer substrate. The first distributed electrode (11) and the second distributed electrode (12) directly above the tops of the respective silicon pillars (1a) and the silicon wall protrusions (1ba) are respectively connected to the first planar metal redistribution layer (14) and the second planar metal redistribution layer (15) on the surface of this side of the TSV silicon interposer substrate; A second chip (201) is buried on the other side of the TSV silicon interposer substrate. The chip pads (20) representing ground and power supply on the second chip (201) are respectively connected to the second first planar metal redistribution layer (24) and the second second planar metal redistribution layer (25) on the surface of this side of the TSV silicon interposer substrate; The three-dimensional capacitor layer (19) is electrically connected to the chip pads (20) representing ground and power supply of the second chip (201) through the TSV conductive vias (13), and the first planar metal redistribution layer (14), the second first planar metal redistribution layer (24), the second planar metal redistribution layer (15), and the second second planar metal redistribution layer (25) located on both surfaces of the TSV silicon interposer substrate respectively.

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