MOSFET device with integrated heterojunction diode and preparation method thereof

Abstract

The present invention relates to a MOSFET device with integrated heterojunction diode and a preparation method thereof. The device comprises a substrate layer, an epitaxial layer and a current spreading layer which are sequentially arranged from bottom to top; and also comprises a convex structure, which is located at the middle of the upper end of the current spreading layer and comprises a raised portion and a base which are arranged from bottom to top, wherein the raised portion is arranged as a p-shield layer; the base comprises a first single crystal silicon and a second single crystal silicon, wherein the first single crystal silicon is symmetrically arranged on both sides of the p-shield layer in a width direction and contacts the current spreading layer; the second single crystal silicon is located at the top of the convex structure, and an oxide layer is arranged between the first single crystal silicon and the second single crystal silicon; a P-type base region, a P-type region, a P-type well region and an N-type source region are further arranged on the current spreading layer; the present invention integrates a heterojunction diode at a corner of a trench gate, improves the characteristics of a parasitic body diode, reduces switching loss, and increases switching rate, while keeping the static characteristics of the device unaffected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOSFET device with an integrated heterojunction diode and a preparation method thereof. Background Art

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a commonly used semiconductor device that is used to control the flow of current in electronic circuits to achieve amplification, switching and current modulation functions; the third-generation semiconductor silicon carbide has broken through the limitations of silicon-based devices with its wide bandgap, high critical breakdown electric field and high saturation drift rate, and is widely used in power electronic systems.

[0003] SiC MOSFET has the problem of bipolar degradation during use due to its wider bandgap. When the parasitic body diode is used as a freewheeling diode, it is subjected to high current and the bipolar degradation effect is more serious, which increases the on-resistance of the device, increases dynamic loss, and reduces reliability. In the prior art, an anti-parallel Schottky diode is used as a freewheeling diode, but this introduces additional inductance and capacitance into the circuit. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the technical difficulty in the prior art that the parasitic body diode of the MOSFET device is severely affected by the bipolar degradation effect when used as a freewheeling diode, and to provide a MOSFET device with an integrated heterojunction diode and a preparation method, in which the heterojunction diode is integrated at the corner of the trench gate, the characteristics of the parasitic body diode are improved, and the switching loss is reduced.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a MOSFET device with an integrated heterojunction diode, which comprises:

[0006] A substrate layer, wherein the substrate layer is set to a first conductivity type;

[0007] an epitaxial layer, the epitaxial layer being located above the substrate layer and being set to a first conductivity type;

[0008] a current spreading layer, the current spreading layer being located above the epitaxial layer;

[0009] A convex structure, the convex structure is located in the middle of the upper end of the current spreading layer, and includes a protrusion and a base arranged from bottom to top, the base is arranged as a groove, and the protrusion is arranged as a p-shield layer; the base includes a first single crystal silicon and a second single crystal silicon, the first single crystal silicon is symmetrically arranged on both sides of the p-shield layer in the width direction, and is in contact with the current spreading layer; the second single crystal silicon is located on the top of the convex structure, and an oxide layer is arranged between the first single crystal silicon and the second single crystal silicon;

[0010] A P-type base region, the P-type base region is symmetrically arranged on both sides of the upper end of the current spreading layer;

[0011] A P-type region, wherein the P-type region is symmetrically arranged on both sides of the current spreading layer, and the P-type region is located at the bottom of the P-type base region;

[0012] A P-type well region, the P-type well region is located between the P-type base region and the convex structure, and is symmetrically arranged on both sides of the base of the convex structure;

[0013] An N-type source region is located above the P-type well region, and the N-type source region and the P-type well region are isolated from one side of the convex structure by the oxide layer.

[0014] In one embodiment of the present invention, the oxide layer includes a first gate oxide layer and a second gate oxide layer, the first gate oxide layer is located on both side walls of the groove of the convex structure, the second gate oxide layer is located above the p-shield layer to isolate the first single crystal silicon, and the second gate oxide layer is also located above the first single crystal silicon to isolate the second single crystal silicon from the first single crystal silicon.

[0015] In one embodiment of the present invention, the width of the p-shield layer is 1 μm to 3 μm, and the thickness of the p-shield layer is 4 μm to 8 μm.

[0016] In one embodiment of the present invention, two ends of the bottom of the p-shield layer are in arc shape, and one end of the bottom of the first single crystal silicon away from the oxide layer is in arc shape.

[0017] In one embodiment of the present invention, the implantation dose of the P-type base region is 5×10 14 cm 2 ~1.5×10 15 cm 2 The implantation dose of the P-type well region is 5×10 13 cm 2 ~6×10 14 cm 2 The implantation dose of the N-type source region is 5×10 14cm 2 ~1.5×10 15 cm 2 The implantation dose of the P-type region is 5×10 15 cm 2 ~1.5×10 16 cm 2 .

[0018] In one embodiment of the present invention, a drain metal is further included, wherein the drain metal contacts a surface of the substrate layer facing away from the epitaxial layer and is electrically coupled to the substrate layer, and the substrate layer is configured as a silicon carbide substrate.

[0019] In a second aspect, the present invention further provides a method for preparing a MOSFET device with an integrated heterojunction diode, which is used to prepare the MOSFET device with an integrated heterojunction diode described in any of the above embodiments, and the preparation method comprises the following steps:

[0020] Step S1, growing the epitaxial layer on the surface of the substrate layer by an epitaxial process, etching away a portion of the epitaxial layer and filling the current spreading layer;

[0021] Step S2, injecting P-type semiconductor impurities into the current spreading layer through photolithography and ion implantation to form the P-type base region; injecting P-type semiconductor impurities into one end of the P-type base region to form the P-type well region; and injecting N-type semiconductor impurities into the P-type well region to form the N-type source region;

[0022] Step S3, etching the current spreading layer to obtain two first trenches by a trench etching process; backfilling the first single crystal silicon at the bottom of the first trenches, and obtaining a third gate oxide layer by a thermal oxidation process on the top of the first single crystal silicon;

[0023] Step S4, injecting P-type semiconductor impurities into the current spreading layer between the two first trenches to form the p-shield layer;

[0024] Step S5, wet-etching the third gate oxide layer to retain the area located on the sidewall of the first trench to obtain a first gate oxide layer; and etching the spacing area between the two first trenches in the width direction by a trench etching process to connect the two first trenches;

[0025] Step S6, growing a second gate oxide layer by a thermal oxidation process;

[0026] Step S7, backfilling the second single crystal silicon above the second gate oxide layer;

[0027] Step S8, implanting P-type semiconductor impurities into the bottom of the P-type base region by an ion implantation process to obtain the P-type region.

[0028] In one embodiment of the present invention, the depth of the first grooves is set to be 1.7 μm to 3.8 μm.

[0029] In one embodiment of the present invention, the thickness of the first single crystal silicon is 1 μm to 2 μm, and the first gate oxide layer is located between the first trench sidewall and the second single crystal silicon, and has a thickness of 0.7 μm to 1.8 μm.

[0030] In one embodiment of the present invention, the thickness of the second gate oxide layer is 1.5 μm to 2.5 μm.

[0031] The above technical solution of the present invention has the following advantages compared with the prior art:

[0032] The MOSFET device with integrated heterojunction diode and the preparation method described in the present invention integrate heterojunction diodes at the corners of the trench gate, improve the characteristics of the parasitic body diode, reduce switching losses, and increase the switching rate, while keeping the static characteristics of the device unaffected; at the same time, by depositing a thicker gate oxide layer, gate oxide breakdown caused by electric field concentration at the bottom and corners of the trench gate is avoided. When the device is in a reverse bias state, the depletion region formed between the P-type base regions can reduce the electric field strength between the gate oxide layer and the Si heterojunction, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0034] Figure 1 This is a schematic diagram of the structure after step S2 in the second embodiment of the present invention is completed;

[0035] Figure 2 is a schematic diagram of the structure after the first groove is obtained in step S3 in the second embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the structure after step S3 in the second embodiment of the present invention is completed;

[0037] Figure 4 This is a schematic diagram of the structure after step S4 in the second embodiment of the present invention is completed;

[0038] Figure 5 This is a schematic diagram of the structure after step S5 in the second embodiment of the present invention is completed;

[0039] Figure 6 This is a schematic diagram of the structure after step S6 in the second embodiment of the present invention is completed;

[0040] Figure 7This is a schematic diagram of the structure after step S7 in the second embodiment of the present invention is completed;

[0041] Figure 8 It is a schematic diagram of the structure of a MOSFET device with an integrated heterojunction diode obtained after step S8 in the second embodiment of the present invention is completed.

[0042] Explanation of the reference numerals in the specification: 1. substrate layer; 2. epitaxial layer; 21. current dispersion layer; 3. P-type base region; 4. P-type well region; 5. N-type source region; 6. first trench; 7. first single crystal silicon; 8. p-shield layer; 9. second single crystal silicon; 10. P-type region; 11. first gate oxide layer; 12. second gate oxide layer; 13. third gate oxide layer. DETAILED DESCRIPTION

[0043] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0044] Embodiment 1

[0045] When existing MOSFET devices switch from the on state to the off state, or from the off state to the on state, the charge redistribution between the gate and the channel generates current, so there is energy loss in the switching process. Excessive energy loss will affect the service life of the device; in addition, the channel resistance is related to the on state of the MOSFET device. A higher on-resistance will cause more voltage drop, which in turn affects the switching rate of the device and reduces the corresponding rate of the device.

[0046] Accordingly, refer to Figure 8 As shown, Embodiment 1 of the present invention provides a MOSFET device with an integrated heterojunction diode. Compared with the existing MOSFET device, the present invention integrates a heterojunction diode at the corner of the trench gate to improve the characteristics of the parasitic body diode, reduce switching losses, and increase the switching rate, while keeping the static characteristics of the device unaffected.

[0047] Specifically, refer to Figure 8 As shown, the MOSFET device with integrated heterojunction diode of the present invention includes a drain metal, a substrate layer 1, an epitaxial layer 2 and a current spreading layer 21 from bottom to top, and the current spreading layer 21 is integrated with a convex structure for forming a heterojunction diode and an ion implantation area; the substrate layer 1 is set to a first conductivity type, the epitaxial layer 2 is located above the substrate layer 1 and is set to the first conductivity type, the drain metal contacts the surface of the substrate layer 1 on one side away from the epitaxial layer 2, and is electrically coupled to the substrate layer 1. In some embodiments, the substrate layer 1 is set to a silicon carbide substrate.

[0048] Specifically, refer to Figure 8 As shown, the convex structure is located in the middle of the upper end of the current dispersion layer 21, and includes a protrusion and a base arranged from bottom to top, the base is arranged as a groove, and the protrusion is arranged as a p-shield layer 8; the base includes a first single crystal silicon 7 (filled with short horizontal lines) and a second single crystal silicon 9 (filled with short horizontal lines), the first single crystal silicon 7 is located on both sides of the p-shield layer 8 in the width direction, and is in contact with the current dispersion layer 21; the second single crystal silicon 9 is located at the top of the convex structure, and an oxide layer (grid line filling) is arranged between the first single crystal silicon 7 and the second single crystal silicon 9 for isolation.

[0049] Furthermore, the two ends of the bottom of the p-shield layer 8 are arc-shaped, the width of the p-shield layer 8 is 1μm to 3μm, and the thickness of the p-shield layer 8 is 4μm to 8μm; in the first embodiment of the present invention, the p-shield layer 8 is arranged at the bottom corner of the trench gate as a P-type shielding area of ​​silicon carbide, and a Si-SiC heterojunction diode is integrated. Due to the difference in energy bands, only electrons are transported between diodes as carriers, and there is no storage and extraction of holes during the switching process of the MOSFET device, thereby improving the characteristics of the body diode, reducing losses, and increasing the switching rate.

[0050] Specifically, refer to Figure 8 As shown, the ion implantation region includes a P-type base region 3 (point filling), a P-type region 10, a P-type well region 4 (right oblique line filling) and an N-type source region 5 (left oblique line filling); the P-type base region 3 is symmetrically arranged on both sides of the upper end of the current dispersion layer 21, the P-type region 10 is symmetrically arranged on both sides of the current dispersion layer 21, and the P-type region 10 is located at the bottom of the P-type base region 3; the P-type well region 4 is located between the P-type base region 3 and the convex structure, and is symmetrically arranged on both sides of the base of the convex structure; the N-type source region 5 is located above the P-type well region 4, the N-type source region 5 is located between the P-type base region 3 and the convex structure, and is symmetrically arranged on both sides of the base of the convex structure, and the N-type source region 5 and the P-type well region 4 are isolated by the oxide layer on the side close to the convex structure.

[0051] Furthermore, the oxide layer includes a first gate oxide layer 11 and a second gate oxide layer 12, the first gate oxide layer 11 is located on both side walls of the groove of the convex structure, the second gate oxide layer 12 is located above the p-shield layer 8 to isolate the first single crystal silicon 7 on both sides, and the second gate oxide layer 12 is also located above the first single crystal silicon 7 to isolate the second single crystal silicon 9 and the first single crystal silicon 7.

[0052] Further, in some embodiments, the sum of the thicknesses of the P-type well region 4 and the N-type source region 5 is greater than the thickness of the second single crystal silicon 9, and the sum of the thicknesses of the P-type well region 4 and the N-type source region 5 is less than the thickness of the first gate oxide layer 11. It should be noted that the thickness of the first gate oxide layer 11 is set to the distance from the top of the first single crystal silicon 7 to the top of the device, that is, the extension length of the first gate oxide layer 11 in the depth direction of the trench; the bottom of the P-type well region 4 is located between the bottom of the second single crystal silicon 9 and the top of the first single crystal silicon 7 in the thickness direction.

[0053] Furthermore, in some embodiments, the thickness of the P-type base region 3 is greater than the depth of the trench, and the width of the P-type region 10 is greater than the width of the P-type base region 3. The end of the bottom of the P-type region 10 away from the device side is in an arc shape.

[0054] Furthermore, the implantation dose of the P-type base region 3 is 5×10 14 cm 2 ~1.5×10 15 cm 2 The implantation dose of the P-type well region 4 is 5×10 13 cm 2 ~6×10 14 cm 2 The implantation dose of the N-type source region 5 is 5×10 14 cm 2 ~1.5×10 15 cm 2 The implantation dose of the P-type region 10 is 5×10 15 cm 2 ~1.5×10 16 cm 2 .

[0055] Embodiment 2

[0056] Reference Figures 1 to 8 As shown, the second embodiment of the present invention further provides a method for preparing a MOSFET device with an integrated heterojunction diode, which is used to prepare the MOSFET device with an integrated heterojunction diode described in the first embodiment above, and the preparation method comprises the following steps:

[0057] Step S1, growing the epitaxial layer 2 on the surface of the substrate layer 1 by an epitaxial process, etching away a portion of the epitaxial layer 2 and filling the current spreading layer 21, wherein the doping concentration of the current spreading layer 21 is different from that of the epitaxial layer 2;

[0058] Step S2, refer to Figure 1As shown, P-type semiconductor impurities are implanted into the current spreading layer 21 by photolithography and ion implantation to form the P-type base region 3; P-type semiconductor impurities are implanted into one end of the P-type base region 3 to form the P-type well region 4; and N-type semiconductor impurities are implanted into the P-type well region 4 to form the N-type source region 5;

[0059] Step S3, refer to Figure 2 and Figure 3 As shown, two first trenches 6 are etched in the current spreading layer 21 by a trench etching process; the first single crystal silicon 7 is backfilled at the bottom of the first trench 6, and a third gate oxide layer 13 is formed on the top of the first single crystal silicon 7 by a thermal oxidation process;

[0060] The first groove 6 is located in the middle of the current spreading layer 21, the two first grooves 6 are symmetrically arranged and extend in parallel, and there is a certain gap between the two first grooves 6; in some embodiments, the depth of the first grooves 6 is set to 1.7 μm to 3.8 μm;

[0061] Further, the width of the first single crystal silicon 7 is consistent with the width of the first groove 6, the thickness of the first single crystal silicon 7 is 1 μm to 2 μm, and the thickness of the first single crystal silicon 7 in the first grooves 6 on both sides is the same;

[0062] Further, the width of the third gate oxide layer 13 is the same as the width of the first trench 6 and the first single crystal silicon 7; the sum of the thickness of the third gate oxide layer 13 and the thickness of the first single crystal silicon 7 is consistent with the depth of the first trench 6, and the thickness of the third gate oxide layer 13 is 0.7 μm to 1.8 μm;

[0063] Step S4, refer to Figure 4 As shown, P-type semiconductor impurities are injected into the current spreading layer 21 between the two first trenches 6 to form the p-shield layer 8;

[0064] Step S5, refer to Figure 5 As shown, the third gate oxide layer 13 is wet-etched to retain the area located on the side wall of the first trench 6 to obtain the first gate oxide layer 11; at the same time, the spacing area between the two first trenches 6 in the width direction is etched by a trench etching process to connect the two first trenches 6;

[0065] When etching the third gate oxide layer 13, one side thereof close to the spacing region in the width direction is removed, so the first gate oxide layer 11 has the same thickness as the third gate oxide layer 13, and the thickness of the first gate oxide layer 11 is 0.7 μm to 1.8 μm; the first gate oxide layer 11 is located between the sidewall of the first trench 6 and the second single crystal silicon 9 for isolation;

[0066] Step S6, refer to Figure 6 As shown, the second gate oxide layer 12 is grown by a thermal oxidation process;

[0067] The second gate oxide layer 12 is grown in the area between the first trenches 6 etched in step S5, and in the area of ​​the first trench 6 outside the first single crystal silicon 7 and the first gate oxide layer 11, and the thickness of the second gate oxide layer 12 is 1.5 μm to 2.5 μm;

[0068] Furthermore, depositing a thicker gate oxide layer can avoid gate oxide breakdown due to electric field concentration at the bottom and corners of the trench gate; when the MOSFET device of the present invention is in a reverse bias state, the depletion region formed between the P-type base regions 3 can reduce the electric field strength between the gate oxide layer and the Si heterojunction, thereby improving device reliability;

[0069] Step S7, refer to Figure 7 As shown, the second single crystal silicon 9 is backfilled on the second gate oxide layer 12 as a gate;

[0070] Step S8, refer to Figure 8 As shown, P-type semiconductor impurities are implanted at the bottom of the P-type base region 3 by an ion implantation process to obtain the P-type region 10 .

[0071] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A MOSFET device with an integrated heterojunction diode, characterized in that: include, A substrate layer, wherein the substrate layer is set to a first conductivity type and the substrate layer is set to a silicon carbide substrate; an epitaxial layer, the epitaxial layer being located above the substrate layer and being set to be of a first conductivity type, and the material of the epitaxial layer being set to be silicon carbide; A current spreading layer, the current spreading layer is located above the epitaxial layer, and the material of the current spreading layer is set to be silicon carbide; A convex structure, the convex structure is located in the middle of the upper end of the current spreading layer, and comprises a convex portion and a base portion arranged from bottom to top, the base portion is arranged as a groove, and the convex portion is arranged as a p-shield layer; The base includes a first single crystal silicon and a second single crystal silicon, wherein the first single crystal silicon is symmetrically arranged on both sides of the p-shield layer in the width direction and is in contact with the current spreading layer to integrate a Si-SiC heterojunction diode; the second single crystal silicon is located on the top of the convex structure, and an oxide layer is arranged between the first single crystal silicon and the second single crystal silicon; A P-type base region, the P-type base region is symmetrically arranged on both sides of the upper end of the current spreading layer; A P-type region, wherein the P-type region is symmetrically arranged on both sides of the current spreading layer, and the P-type region is located at the bottom of the P-type base region; A P-type well region, the P-type well region is located between the P-type base region and the convex structure, and is symmetrically arranged on both sides of the base of the convex structure; An N-type source region, the N-type source region is located above the P-type well region, and the N-type source region and the P-type well region are isolated from one side of the convex structure by the oxide layer; The device also includes a drain metal, wherein the drain metal contacts a surface of the substrate layer that is away from the epitaxial layer and is electrically coupled to the substrate layer.

2. The MOSFET device with integrated heterojunction diode according to claim 1, characterized in that: The oxide layer includes a first gate oxide layer and a second gate oxide layer, the first gate oxide layer is located on both side walls of the groove of the convex structure, the second gate oxide layer is located above the p-shield layer to isolate the first single crystal silicon, and the second gate oxide layer is also located above the first single crystal silicon to isolate the second single crystal silicon from the first single crystal silicon.

3. The MOSFET device with integrated heterojunction diode according to claim 1, characterized in that: The width of the p-shield layer is 1 μm to 3 μm, and the thickness of the p-shield layer is 4 μm to 8 μm.

4. The MOSFET device with integrated heterojunction diode according to claim 3, characterized in that: Both ends of the bottom of the p-shield layer are in arc shape, and one end of the bottom of the first single crystal silicon away from the oxide layer is in arc shape.

5. The MOSFET device with integrated heterojunction diode according to claim 1, characterized in that: The implantation dose of the P-type base region is 5×10 14 cm 2 ~1.5×10 15 cm 2 ; The implantation dose of the P-type well region is 5×10 13 cm 2 ~6×10 14 cm 2 The implantation dose of the N-type source region is 5×10 14 cm 2 ~1.5×10 15 cm 2 ; The implantation dose of the P-type region is 5×10 15 cm 2 ~1.5×10 16 cm 2 .

6. A method for preparing a MOSFET device with an integrated heterojunction diode, for preparing a MOSFET device with an integrated heterojunction diode as claimed in any one of claims 1 to 5, characterized in that: The preparation method comprises the following steps: Step S1, growing the epitaxial layer on the surface of the substrate layer by an epitaxial process, etching away a portion of the epitaxial layer and filling the current spreading layer; Step S2, injecting P-type semiconductor impurities into the current spreading layer through photolithography and ion implantation to form the P-type base region; injecting P-type semiconductor impurities into one end of the P-type base region to form the P-type well region; and injecting N-type semiconductor impurities into the P-type well region to form the N-type source region; Step S3, etching the current spreading layer to obtain two first trenches by a trench etching process; backfilling the first single crystal silicon at the bottom of the first trenches, and obtaining a third gate oxide layer by a thermal oxidation process on the top of the first single crystal silicon; Step S4, injecting P-type semiconductor impurities into the current spreading layer between the two first trenches to form the p-shield layer; Step S5, wet-etching the third gate oxide layer to retain the area located on the sidewall of the first trench to obtain a first gate oxide layer; and etching the spacing area between the two first trenches in the width direction by a trench etching process to connect the two first trenches; Step S6, growing a second gate oxide layer by a thermal oxidation process; Step S7, backfilling the second single crystal silicon above the second gate oxide layer; Step S8, implanting P-type semiconductor impurities into the bottom of the P-type base region by an ion implantation process to obtain the P-type region.

7. The method for preparing a MOSFET device with an integrated heterojunction diode according to claim 6, characterized in that: The depth of the first grooves is set to be 1.7 μm to 3.8 μm.

8. The method for preparing a MOSFET device with an integrated heterojunction diode according to claim 7, characterized in that: The thickness of the first single crystal silicon is 1 μm to 2 μm, and the first gate oxide layer is located between the first trench sidewall and the second single crystal silicon, and has a thickness of 0.7 μm to 1.8 μm.

9. The method for preparing a MOSFET device with an integrated heterojunction diode according to claim 6, characterized in that: The thickness of the second gate oxide layer is 1.5 μm to 2.5 μm.

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