Data management device

Abstract

This application discloses a data management device, belonging to the field of pipeline inspection technology. This device is applied in a magnetic flux leakage composite detector. One end of the first electrical connector is electrically connected to a data processing board, and the other end is used to electrically connect to a control device. A second electrical connector is soldered onto a probe interface board, which is electrically connected to the data processing board. The data processing board integrates FPGA circuitry and isolation circuitry. The isolation circuitry isolates interference from other data transmissions from affecting the second data transmission. The FPGA circuitry decodes commands issued by the control device or encodes data sent to the control device. Therefore, this device reduces the occurrence of bit errors by isolating interference and encoding / decoding, thereby improving the accuracy of massive data transmission.

Description

Technical Field

[0001] This application relates to the field of pipeline inspection technology. In particular, it relates to a data management device. Background Technology

[0002] The quality of pipeline circumferential welds is crucial for ensuring pipeline safety; therefore, regular or irregular quality inspections are necessary. Currently, magnetic flux leakage detectors are primarily used to inspect the quality of pipeline circumferential welds.

[0003] In related technologies, the magnetic flux leakage composite detector includes: a data management device, a control device, and multiple probes. These multiple probes are mainly used to collect data from the pipeline to be inspected, and then send the collected data to the data management device. The data management device includes a transmission circuit, which is used to transmit data to the control device. The control device is used to store the data, so that relevant personnel can inspect the quality of the pipeline circumferential weld based on the data.

[0004] As the number of probes increases and the sampling interval decreases, the amount of data that needs to be transmitted becomes larger and larger. The sampling interval represents the interval between the current acquisition position and the previous acquisition position. Since the data acquired by the probe is directly transmitted through the transmission circuit in related technologies, the amount of data is large and is easily affected by the transmission of other data, which can cause bit errors during transmission, resulting in low accuracy of data transmission. Summary of the Invention

[0005] This application provides a data management device that can improve the accuracy of data transmission. The specific technical solution is as follows:

[0006] This application provides a data management device for use in a magnetic flux leakage composite detector. The device includes: a probe interface board, a first electrical connector, a second electrical connector, and a data processing board.

[0007] One end of the first electrical connector is electrically connected to the data processing board, and the other end is used for electrical connection to the control device;

[0008] The second electrical connector is soldered to the probe interface board, which is electrically connected to the data processing board; wherein, the data processing board integrates a programmable gate array (FPGA) circuit and an isolation circuit.

[0009] The second electrical connector includes a plurality of first connection core sockets for electrical connection with a plurality of probes;

[0010] The first electrical connector is used to receive a first data acquisition command sent by the control device and send the first data acquisition command to the FPGA circuit; the FPGA circuit is used to decode the first data acquisition command and send the decoded first data acquisition command to the multiple probes based on the transmission protocol between the multiple probes; the multiple probes are used to acquire first data based on the decoded first data acquisition command, wherein the first data is data obtained by performing magnetic flux leakage detection on the pipeline to be tested.

[0011] The FPGA circuit is further configured to receive first data sent by the plurality of probes, convert the first data to obtain second data, and send the second data to the first electrical connector; the first electrical connector is further configured to receive the second data and send the second data to the control device, and the control device is configured to decode the second data and store the decoded second data.

[0012] The isolation circuit includes multiple isolation chips for isolating the second data from other data.

[0013] In one possible implementation, the FPGA circuit includes: a management module, a first data transmission module, a data processing module, and a second data transmission module;

[0014] The second data transmission module is used to decode the first data acquisition instruction and send the decoded first data acquisition instruction to the management module;

[0015] The management module is used to receive the decoded first data acquisition instruction and send the decoded first data acquisition instruction to the first data transmission module;

[0016] The first data transmission module is configured to receive the decoded first data acquisition instruction and send a start instruction to the plurality of probes; when a first response message is received from the plurality of probes, the first data acquisition instruction is sent to the plurality of probes, wherein the first response message is used to indicate that the plurality of probes have received the start instruction;

[0017] The first data transmission module is further configured to receive first data sent by the plurality of probes, and when receiving a notification message sent by the plurality of probes, to send a second response message to the plurality of probes and to send the first data to the data processing module; the notification message is used to indicate that data acquisition at the current acquisition location is complete, and the second response message is used to indicate that data reception at the current acquisition location is complete;

[0018] The data processing module is used to convert the data format of the first data based on a preset data format, add data tags corresponding to the preset data format to the converted data to obtain the third data, and send the third data to the second data transmission module.

[0019] The second data transmission module is used to encode the third data to obtain the second data, and then send the second data to the control device through the first electrical connector.

[0020] In another possible implementation, the data processing board also integrates: a program embedding circuit;

[0021] The program-fixing circuit is used to store the logic code of the FPGA circuit;

[0022] The FPGA circuit is used to load the logic code upon power-up; based on the logic code, it sends the first data acquisition command to the plurality of probes and performs conversion processing on the first data to obtain the second data.

[0023] In another possible implementation, the FPGA circuit further includes an update module;

[0024] The second data transmission module is further configured to decode the update command sent by the control device and send the decoded update command to the management module;

[0025] The management module is also used to receive the decoded update instruction and send the decoded update instruction to the update module, wherein the decoded update instruction carries the updated logic code;

[0026] The update module is used to write the updated logic code into the program solidification circuit;

[0027] The program-fixing circuit is used to store the updated logic code and load the updated logic code when the FPGA circuit is powered on again.

[0028] In another possible implementation, the data processing board also integrates a differential circuit.

[0029] The differential circuit is used to receive a first data acquisition command sent by the first electrical connector, convert the first data acquisition command into a differential form of a data acquisition command to obtain a second data acquisition command, and send the second data acquisition command to the second data transmission module.

[0030] The second data transmission module is further configured to decode the second data acquisition instruction and send the decoded second data acquisition instruction to the management module. The management module is configured to send the decoded second data acquisition instruction to the first data transmission module.

[0031] The differential circuit is also used to receive the second data sent by the second data transmission module, convert the second data into differential data to obtain the fourth data, and send the fourth data to the control device.

[0032] In another possible implementation, the data processing board also integrates a power management circuit.

[0033] The power management circuit is used to provide multiple voltages to power the multiple probes and the multiple circuits on the data processing board.

[0034] The control module is also used to control the state of the power management circuit, the state indicating whether the power management circuit is in a working state or an idle state.

[0035] In another possible implementation, the device further includes: a housing, a base, and a cover plate;

[0036] The first electrical connector is disposed at one end of the housing, and the probe interface board, the first electrical connector, the second electrical connector and the data processing board are all disposed on the housing;

[0037] The cover plate is fixed to the housing by a connector, and the housing is connected to the base.

[0038] In another possible implementation, the gap between the assembly and the housing is filled with epoxy resin, and the assembly consists of the second electrical connector, the probe interface board, and the data processing board.

[0039] In another possible implementation, multiple safety devices are provided at the connection points between the plurality of first connecting core sockets and the plurality of probes, with one safety device corresponding to each connection point;

[0040] The fuse device is used to cut off the current when the current value flowing through the connection is greater than a preset current value, thus forming an open circuit; and to restore the circuit when the power is off.

[0041] In another possible implementation, the second electrical connector further includes: a connector base;

[0042] The gaps between the plurality of first connector core sockets and the connector base are sealed with plastic.

[0043] The beneficial effects of the technical solutions provided in this application are:

[0044] This application provides a data management device, which includes a data processing board integrating an FPGA circuit and an isolation circuit. The isolation circuit isolates interference from other data transmissions on the second data transmission. The FPGA circuit decodes instructions issued by a control device or encodes data sent to the control device. Therefore, this device reduces bit errors by isolating interference and performing encoding / decoding, thereby improving the accuracy of massive data transmission. Attached Figure Description

[0045] Figure 1 This is a top view of a data management device provided in an embodiment of this application;

[0046] Figure 2 This is a side view of a data management device provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of a probe interface board provided in an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of a data processing board provided in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of an FPGA circuit provided in an embodiment of this application.

[0050] The reference numerals in the attached figures represent:

[0051] 1-Probe interface board, 2-First electrical connector, 3-Second electrical connector, 4-Data processing board

[0052] 5-House, 6-Base, 7-Cover plate, 8-Epoxy resin adhesive, 9-Connector, 10-Counterhead screw

[0053] 11-Connector pad, 12-Double row double plastic pin header pad, 13-Power / ground pad, 14-Power pad.

[0054] 15-Debugging interface, 16-Bracket positioning hole, 21-First connecting core socket, 22-Fuse device.

[0055] 31-Second connection core socket, 41-FPGA circuit, 42-Isolation circuit, 43-Programming circuit.

[0056] 44 - Differential circuit, 45 - Power management circuit, 411 - Management module, 412 - First data transmission module

[0057] 413 - Data processing module, 414 - Second data transmission module, 415 - Update module, 421 - Isolation chip, 441 - Differential signal line. Detailed Implementation

[0058] To make the technical solution and advantages of this application clearer, the embodiments of this application will be described in further detail below.

[0059] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0060] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data and instructions involved in this application were obtained under full authorization.

[0061] This application provides a data management device applied in a magnetic flux leakage composite detector. See [link to relevant documentation]. Figures 1 to 4 The device includes: a probe interface board 1, a first electrical connector 2, a second electrical connector 3, and a data processing board 4;

[0062] One end of the first electrical connector 2 is electrically connected to the data processing board 4, and the other end is used to electrically connect to the control device;

[0063] The second electrical connector 3 is soldered onto the probe interface board 1, and the probe interface board 1 is electrically connected to the data processing board 4; wherein, the data processing board 4 integrates FPGA (Field Programmable Gate Array) circuit and isolation circuit 42;

[0064] The second electrical connector 3 includes a plurality of first connection core sockets 21, which are used for electrical connection with a plurality of probes;

[0065] The first electrical connector 2 is used to receive the first data acquisition command sent by the control device and send the first data acquisition command to the FPGA circuit 41; the FPGA circuit 41 is used to decode the first data acquisition command and send the decoded first data acquisition command to the multiple probes based on the transmission protocol between the multiple probes; the multiple probes are used to acquire first data based on the decoded first data acquisition command, and the first data is the data obtained by performing magnetic flux leakage detection on the pipeline to be tested.

[0066] The FPGA circuit 41 is also used to receive first data sent by multiple probes, convert the first data to obtain second data, and send the second data to the first electrical connector 2; the first electrical connector 2 is also used to receive the second data and send the second data to the control device, and the control device is used to decode the second data and store the decoded second data.

[0067] The isolation circuit 42 includes multiple isolation chips 421 for isolating the second data from other data.

[0068] In this implementation, the first electrical connector 2 can be electrically connected to the data processing board 4 via a cable, and to the control device via multiple second connector sockets 31 and a plug, with the plug being inserted into the second connector sockets 31. These multiple second connector sockets 31 can be functionally divided into a power supply group, a communication group, and an update group. The second connector sockets 31 in the power supply group are used to supply power to the data processing board 4; the second connector sockets 31 in the communication group are used for data communication between the control device and the data processing board 4; and the second connector sockets 31 in the update group are used to transmit update instructions to the data processing board 4, which are used to update the logic code of the FPGA circuit 41.

[0069] The plurality of second connecting core sockets 31 can be sealed using a glass sintering process to ensure the stability of the electrical connection under high-voltage conditions. Furthermore, the number of the plurality of second connecting core sockets 31 can be set and changed as needed; for example, the number of second connecting core sockets 31 can be 22, meaning the first electrical connector 2 includes 22 second connecting core sockets 31. Additionally, the shape of the first electrical connector 2 can be set and changed as needed; for example, the first electrical connector 2 can be circular, see [reference needed]. Figure 2 .

[0070] The isolation circuit 42 includes multiple isolation chips 421 for isolating the second data from other data. For each isolation chip 421, the isolation chip 421 can isolate the second data from other data through optocoupler isolation or other isolation methods to prevent damage to the FPGA circuit 41 due to factors such as static electricity or overvoltage, and ensure that the FPGA circuit 41 can operate stably and normally.

[0071] It should be noted that the data is transmitted in the form of electrical signals. Therefore, the function of the multiple isolation chips 421 is to isolate the electrical signals corresponding to the second data from the electrical signals corresponding to other data. Furthermore, this data management device is used in a magnetic flux leakage composite detector, which is an ultra-high-definition magnetic flux leakage composite detector.

[0072] This application provides a data management device, which includes a data processing board 4. The data processing board 4 integrates an FPGA circuit 41 and an isolation circuit 42. The isolation circuit 42 isolates interference from other data transmissions on the second data transmission. The FPGA circuit 41 decodes instructions issued by the control device or encodes data sent to the control device. Therefore, this device reduces bit errors by isolating interference and encoding / decoding, thereby improving the accuracy of massive data transmission.

[0073] In this embodiment of the application, in addition to the probe interface board 1, the first electrical connector 2, the second electrical connector 3, and the data processing board 4, the device also includes: a housing 5, a base 6, and a cover plate 7;

[0074] The first electrical connector 2 is disposed at one end of the housing 5, and the probe interface board 1, the first electrical connector 2, the second electrical connector 3 and the data processing board 4 are all disposed on the housing 5;

[0075] The cover plate 7 is fixed to the housing 5 by the connector 9, and the housing 5 is connected to the base 6.

[0076] In this implementation method, please refer to [link / reference]. Figure 2 The first electrical connector 2 is disposed on the end face of the housing 5. The cover plate 7 is fixed to the housing 5 by a connector 9. The connector 9 can be configured and modified as needed. For example, the connector 9 can be an internal hex screw or a screw of other shapes. In addition, the connection method between the housing 5 and the base 6 can also be configured and modified as needed. For example, the housing 5 and the base 6 can be fixedly connected by countersunk screws 10.

[0077] In this implementation, the second electrical connector 3 is soldered onto the probe interface board 1. The probe interface board 1 and the data processing board 4 are connected via a double-row, double-plastic pin header. The second electrical connector 3, the probe interface board 1, and the data processing board 4 form an assembly. This assembly is fixed to the base 6 by a bracket. Then, epoxy resin 8 is used to fill the gap between the assembly and the housing 5. Filling the gap between the assembly and the housing 5 with epoxy resin 8 ensures the normal operation of the data management device under high-voltage conditions. See also... Figure 1 The second electrical connector 3 is located on the connector pad 11, and the double-row double-plastic pin header is located on the double-row double-plastic pin header pad 12.

[0078] In this embodiment, the second electrical connector 3 includes a connector base and a plurality of first connector core sockets 21. The gap between the plurality of first connector core sockets 21 and the connector base is sealed with plastic, which ensures that no epoxy resin 8 returns from the annulus when the epoxy resin 8 is potted.

[0079] The number of the second electrical connector 3 can be one or more. For example, the number of the second electrical connector 3 can be two. See also... Figure 1 For each second electrical connector 3, the number of first connection core sockets 21 included in the second electrical connector 3 can also be set and changed as needed. For example, if the number of first connection core sockets 21 is 80, multiple probes can be inserted into these 80 first connection core sockets 21, so that multiple probes can transmit data to the FPGA circuit 41 through the second electrical connector 3, and multiple probes can also receive instructions transmitted from the FPGA circuit 41. If the number of first connection core sockets 21 is 80, these 80 first connection core sockets 21 can be connected to 10 probes, with each probe occupying 8 first connection core sockets 21.

[0080] In this embodiment, the data management device can be protected by a self-resetting fuse 22. See also... Figure 3 Multiple safety devices 22 are provided at the connection points between the multiple first connection core sockets 21 and the multiple probes, with one safety device 22 corresponding to one connection point;

[0081] The fuse 22 is used to cut off the current when the current value flowing through the connection is greater than a preset current value, thus forming an open circuit; and to restore the circuit when the power is off.

[0082] In this implementation, the probe interface board 1 adopts an overcurrent protection design, mainly to realize the electrical connection between the probe and the data processing board 4. The preset current value can be set and changed as needed. For example, the preset current value is 100mA, that is, when the current flowing through the connection is greater than 100mA, an open circuit is formed. When the power is off, the circuit is automatically restored. This ensures that even if the probe is electrically damaged, it will not affect the normal operation of the data management device.

[0083] The safety device 22 can be configured and modified as needed, and no specific limitation is made in this embodiment.

[0084] In this embodiment, the FPGA circuit 41 is the control core of the data management device, responsible for parsing instructions, controlling the power supply and shutdown of the probe, implementing the probe transmission protocol, and implementing the encoding and decoding protocol, thereby ensuring that the data can be accurately acquired and transmitted at high speed and reliably. The FPGA circuit 41 will be described in detail below.

[0085] See Figure 5 The FPGA circuit 41 includes: a management module 411, a first data transmission module 412, a data processing module 413, and a second data transmission module 414.

[0086] The second data transmission module 414 is used to decode the first data acquisition command and send the decoded first data acquisition command to the management module 411.

[0087] Management module 411 is used to receive the decoded first data acquisition command and send the decoded first data acquisition command to first data transmission module 412;

[0088] The first data transmission module 412 is used to receive the decoded first data acquisition command and send a start command to multiple probes; when it receives the first response message returned by multiple probes, it sends the decoded first data acquisition command to multiple probes, and the first response message is used to indicate that multiple probes have received the start command;

[0089] The first data transmission module 412 is also used to receive first data sent by multiple probes, and when it receives notification messages sent by multiple probes, it sends second response messages to multiple probes and sends first data to the data processing module 413; the notification messages are used to indicate that data acquisition at the current acquisition location is complete, and the second response messages are used to indicate that data transmission at the current acquisition location is complete;

[0090] Data processing module 413 is used to convert the data format of the first data based on a preset data format, add data tags corresponding to the preset data format to the converted data to obtain the third data, and send the third data to the second data transmission module 414.

[0091] The second data transmission module 414 is used to encode the third data to obtain the second data, and then send the second data to the control device through the first electrical connector 2.

[0092] In this implementation, the second data transmission module 414 is mainly used to encode the data and send the encoded data to the control device; or to decode the instructions issued by the control device and send the decoded instructions to the management module 411.

[0093] The management module 411 is mainly used to parse the decoded instructions and control the status of other modules, indicating whether they are powered on or off. The decoded instructions mainly include data acquisition instructions and update instructions. The data acquisition instructions control the probe to acquire data, and the update instructions update the logic code. In this implementation, after receiving the decoded first data acquisition instruction, the management module 411 parses it and sends the parsed first data acquisition instruction to the first data transmission module 412.

[0094] The first data transmission module 412 is mainly used to send instructions to multiple probes or receive data collected by multiple probes based on the transmission protocol between them. This transmission protocol can be a custom SPI protocol, implemented through a handshake. For example, when the first data transmission module 412 receives the parsed first data acquisition instruction sent by the management module 411, it first sends a start instruction "5C" to the multiple probes. Upon receiving the first response message "5A" from the multiple probes, it sends the parsed first data acquisition instruction "AA" to the multiple probes, instructing them to collect data and prepare to receive data. When it receives the notification message "5E" from the multiple probes, it indicates that data acquisition at the current acquisition location is complete. Then, it sends a second response message "EE" to the multiple probes, indicating that data reception at the current acquisition location is complete, and then sends the received first data to the data processing module 413.

[0095] If the second electrical connector 3 includes 80 first connecting core sockets 21, and these 80 first connecting core sockets 21 are connected to 10 probes, and the number of second electrical connectors 3 is 2, then the number of probes is 20, that is, the magnetic flux leakage composite detector collects data through 20 probes.

[0096] The data processing module 413 is mainly used to convert the received data according to a predefined data format, add data tags corresponding to the data format, and then send the data to the second data transmission module 414. Correspondingly, the data processing module 413 converts the data format of the first data based on a preset data format, adds data tags corresponding to the preset data format to the converted data, obtains the third data, and sends the third data to the second data transmission module 414.

[0097] In one possible implementation, the second data transmission module 414 encodes the third data to obtain the second data, and then sends the second data to the control device through the first electrical connector 2. The encoding / decoding protocol can be the HEC protocol or other protocols.

[0098] In another possible implementation, the second data transmission module 414 encodes the third data, obtains the second data, performs differential conversion on the second data via differential circuit 44, and then sends the differentially converted data to the control device. Accordingly, see [link to relevant documentation]. Figure 4 The data processing board 4 also integrates: differential circuit 44;

[0099] The differential circuit 44 is used to receive the second data sent by the second data transmission module 414, convert the second data into differential data to obtain the fourth data, and send the fourth data to the control device.

[0100] In this implementation, the differential circuit 44 is electrically connected to the second data transmission module 414. The second data transmission module 414 sends second data to the differential circuit 44. Then, the differential circuit 44 converts the second data into fourth data in differential form and sends the fourth data to the first electrical connector 2 through the differential signal line 441. The first electrical connector 2 then forwards the fourth data to the control device.

[0101] In this embodiment, the differential circuit 44, in addition to performing differential conversion on data, can also perform differential conversion on commands issued by the control device. Accordingly, the differential circuit 44 is used to receive a first data acquisition command sent by the first electrical connector 2, convert the first data acquisition command into a differential form of a data acquisition command to obtain a second data acquisition command, and send the second data acquisition command to the second data transmission module 414.

[0102] The second data transmission module 414 is also used to decode the second data acquisition command and send the decoded second data acquisition command to the management module 411. The management module 411 is used to send the decoded second data acquisition command to the first data transmission module 412. The first data transmission module 412 controls multiple probes to acquire data based on the decoded second data acquisition command.

[0103] In this embodiment, encoding and decoding based on a codec protocol can improve the accuracy of data transmission. Furthermore, converting data or instructions into differential form using the differential circuit 44 enhances both signal driving capability and anti-interference capability, ensuring reliability and accuracy of data transmission even at a transmission speed of 100Mb / s and a line length exceeding 10m. The differential circuit 44 can be an LVDS (Low Voltage Differential Signaling) circuit.

[0104] In the embodiments of this application, see also Figure 4 The data processing board 4 also integrates a program hardening circuit 43 and a power management circuit 45. Next, we will introduce the program hardening circuit 43.

[0105] The program-fixing circuit 43 is used to store the logic code of the FPGA circuit 41;

[0106] FPGA circuit 41 is used to load the logic code when powered on; based on the logic code, it sends a first data acquisition command to multiple probes and performs conversion processing on the first data to obtain second data.

[0107] In this implementation, the FPGA circuit 41 loads the logic code in the program-fixed circuit 43 to receive instructions or process data.

[0108] In this embodiment, the logic code in the program-fixed circuit 43 can also be updated to achieve an upgrade. Correspondingly, the FPGA circuit 41 also includes an update module 415;

[0109] The second data transmission module 414 is also used to decode the update command sent by the control device and send the decoded update command to the management module 411.

[0110] The management module 411 is also used to receive the decoded update instruction and send the decoded update instruction to the update module 415. The decoded update instruction carries the updated logic code.

[0111] The update module 415 is used to write the updated logic code into the program solidification circuit 43;

[0112] The program persistence circuit 43 is used to store the updated logic code, and the updated logic code is loaded when the FPGA circuit 41 is powered on again.

[0113] In this implementation, the updated logic code is written into the NorFlash chip of the program solidification circuit 43 by the update module 415. In this way, when the FPGA circuit 41 is powered on again, the updated logic code can be loaded and the updated logic code can be used to receive instructions or process data.

[0114] Next, we will introduce the power management circuit 45.

[0115] The power management circuit 45 is used to provide multiple voltages to power multiple probes and multiple circuits on the data processing board 4.

[0116] The control module is also used to control the state of the power management circuit 45, which indicates whether the power management circuit 45 is in a working state or an idle state.

[0117] In this implementation, the power management circuit 45 is mainly used to convert the power required by multiple circuits on the data processing board 4. The power management circuit 45 provides multiple voltages, including 1V, 1.8V, and 3.3V. The 3.3V is used to power the probe. The power supply is controlled by the management module 411. That is, when the management module 411 controls the power management circuit 45 to be in the working state, the power management circuit 45 powers the probe, or when the management module 411 controls the power management circuit 45 to be in the idle state, the probe is powered off. The 1V and 1.8V are used to power multiple circuits such as the FPGA circuit 41, the differential circuit 44, the program embedding circuit 43, and the isolation circuit 42.

[0118] See also Figure 4 The data processing board 4 is also provided with a bracket positioning hole 16, a power ground pad 13, a power pad 14, and a debugging interface 15. The bracket fixes the assembly and the base 6 by passing through the bracket positioning hole 16. The power ground pad 13 is used to connect the ground wire. The power pad 14 is used to connect to the second connection core socket 31 of the power supply group in the first electrical connector 2 to supply power to the data processing board 4. The debugging interface 15 is used to debug the FPGA circuit 41 and the program solidification circuit 43 when the leakage magnetic composite detector is in an idle state.

[0119] It should be noted that in related technologies, after the probe collects data, it sends the data to a data management device. This data management device, in addition to the transmission circuit, includes an analog-to-digital converter (ADC). The ADC performs analog-to-digital conversion on the data before sending the converted data to the transmission circuit, which then transmits the converted data. When the amount of data to be converted is large, the method in related technologies results in high power consumption for the data management device. In this application, however, after the probe collects data, it can perform analog-to-digital conversion itself to obtain the first data, which is then directly sent to the FPGA circuit 41. Therefore, the data management device provided in this application does not require analog-to-digital conversion, thus significantly reducing power consumption.

[0120] Furthermore, in related technologies, analog-to-digital converters occupy a large amount of space, resulting in low integration of the data processing board 4. In this application, however, multiple circuits such as FPGA circuit 41, differential circuit 44, isolation circuit 42, program embedding circuit 43, and power management circuit 45 can be integrated on the data processing board 4, and there is no need to integrate the analog-to-digital converter on the data processing board 4. Therefore, the data processing board 4 provided by this application has a high degree of integration.

[0121] Furthermore, in related technologies, the number of probes is relatively small, and the sampling interval is relatively large, generally 2-3 mm. In this application, the number of probes is increased to 20, and the sampling interval is reduced to 1 mm. Therefore, the amount of data will increase exponentially. Under these circumstances, the data management device provided in this application can not only achieve high-speed data acquisition, but also achieve accurate transmission of massive amounts of data, ensuring the accuracy and stability of the transmission.

[0122] In summary, the data management device provided in this application has high integration, low power consumption, and can achieve high-speed acquisition and high-speed zero-error transmission over long cables, ensuring the accuracy and stability of data acquisition and transmission for the magnetic flux leakage detector.

[0123] The above description is only for the purpose of enabling those skilled in the art to understand the technical solution of this application, and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data management apparatus characterized by comprising: The device, which is used in a magnetic flux leakage composite detector, includes: a probe interface board (1), a first electrical connector (2), a second electrical connector (3), and a data processing board (4). One end of the first electrical connector (2) is electrically connected to the data processing board (4), and the other end is used to be electrically connected to the control device; The second electrical connector (3) is soldered onto the probe interface board (1), and the probe interface board (1) is electrically connected to the data processing board (4); wherein, the data processing board (4) integrates a programmable gate array (FPGA) circuit (41), an isolation circuit (42), and a differential circuit (44); the FPGA circuit (41) includes: a management module (411), a first data transmission module (412), and a second data transmission module (414). The second electrical connector (3) includes a plurality of first connection core sockets (21) for electrical connection with a plurality of probes; The first electrical connector (2) is used to receive the first data acquisition command sent by the control device and send the first data acquisition command to the FPGA circuit (41); the FPGA circuit (41) is used to decode the first data acquisition command and send the decoded first data acquisition command to the multiple probes based on the transmission protocol between the multiple probes; the multiple probes are used to acquire first data based on the decoded first data acquisition command, and the first data is the data obtained by performing magnetic flux leakage detection on the pipeline to be tested; The FPGA circuit (41) is also used to receive first data sent by the plurality of probes, convert the first data to obtain second data, and send the second data to the first electrical connector (2); the first electrical connector (2) is also used to receive the second data and send the second data to the control device, and the control device is used to decode the second data and store the decoded second data; The isolation circuit (42) includes multiple isolation chips (421) for isolating the second data from other data; The differential circuit (44) is used to receive the first data acquisition instruction sent by the first electrical connector (2), convert the first data acquisition instruction into a differential form of data acquisition instruction to obtain a second data acquisition instruction, and send the second data acquisition instruction to the second data transmission module (414). The second data transmission module (414) is used to decode the second data acquisition instruction and send the decoded second data acquisition instruction to the management module (411); the management module (411) is used to send the decoded second data acquisition instruction to the first data transmission module (412); The differential circuit (44) is also used to receive the second data sent by the second data transmission module (414), convert the second data into differential data to obtain the fourth data, and send the fourth data to the control device.

2. The data management device according to claim 1, characterized in that, The FPGA circuit (41) further includes: a data processing module (413). The second data transmission module (414) is used to decode the first data acquisition instruction and send the decoded first data acquisition instruction to the management module (411); The management module (411) is used to receive the decoded first data acquisition instruction and send the decoded first data acquisition instruction to the first data transmission module (412); The first data transmission module (412) is used to receive the decoded first data acquisition instruction and send a start instruction to the plurality of probes; when a first response message is received from the plurality of probes, the decoded first data acquisition instruction is sent to the plurality of probes, wherein the first response message is used to indicate that the plurality of probes have received the start instruction; The first data transmission module (412) is also used to receive first data sent by the plurality of probes, and when receiving a notification message sent by the plurality of probes, to send a second response message to the plurality of probes and to send the first data to the data processing module (413); the notification message is used to indicate that the data acquisition at the current acquisition location is complete, and the second response message is used to indicate that the data reception at the current acquisition location is complete; The data processing module (413) is used to convert the data format of the first data based on a preset data format, add data tags corresponding to the preset data format to the converted data to obtain the third data, and send the third data to the second data transmission module (414). The second data transmission module (414) is used to encode the third data to obtain the second data, and send the second data to the control device through the first electrical connector (2).

3. The data management device according to claim 2, characterized in that, The data processing board (4) also integrates: a program solidification circuit (43); The program-fixing circuit (43) is used to store the logic code of the FPGA circuit (41); The FPGA circuit (41) is used to load the logic code when powered on; Based on the logic code, the first data acquisition command is sent to the plurality of probes, and the first data is converted and processed to obtain the second data.

4. The data management device according to claim 3, characterized in that, The FPGA circuit (41) further includes: an update module (415); The second data transmission module (414) is also used to decode the update command sent by the control device and send the decoded update command to the management module (411); The management module (411) is also used to receive the decoded update instruction and send the decoded update instruction to the update module (415), wherein the decoded update instruction carries the updated logic code; The update module (415) is used to write the updated logic code into the program solidification circuit (43); The program solidification circuit (43) is used to store the updated logic code and load the updated logic code when the FPGA circuit (41) is powered on again.

5. The data management device according to claim 2, characterized in that, The data processing board (4) also integrates a power management circuit (45). The power management circuit (45) is used to provide multiple voltages to power the multiple probes and the multiple circuits on the data processing board (4); The control device is also used to control the state of the power management circuit (45), the state being used to indicate whether the power management circuit (45) is in a working state or an idle state.

6. The data management device according to claim 1, characterized in that, The device also includes: a housing (5), a base (6), and a cover plate (7); The first electrical connector (2) is disposed at one end of the housing (5), and the probe interface board (1), the first electrical connector (2), the second electrical connector (3) and the data processing board (4) are all disposed on the housing (5); The cover plate (7) is fixed to the housing (5) by a connector (9), and the housing (5) is connected to the base (6).

7. The data management device according to claim 6, characterized in that, The gap between the assembly and the housing (5) is filled with epoxy resin glue (8). The assembly consists of the second electrical connector (3), the probe interface board (1) and the data processing board (4).

8. The data management device according to claim 1, characterized in that, Multiple safety devices (22) are provided at the connection points between the multiple first connection core sockets (21) and the multiple probes, with one safety device (22) corresponding to one connection point. The fuse (22) is used to cut off the current when the current value flowing through the connection is greater than a preset current value, thus forming an open circuit; and to restore the circuit when the power is off.

9. The data management device according to claim 1, characterized in that, The second electrical connector (3) further includes: a connector base; The gaps between the plurality of first connecting core sockets (21) and the connecting base are sealed with plastic.

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