Dynamic voltage and frequency scaling method, apparatus, device, medium, and processor system

Abstract

The application provides a dynamic voltage frequency adjustment method, device, equipment, medium and processor system, wherein the method comprises the following steps: acquiring performance information of a processor system, wherein the performance information comprises a workload, a temperature and power consumption; determining a frequency adjustment period and an adjustment level according to the performance information; and adjusting the voltage / frequency level of the processor system by one or more levels according to the adjustment level in the frequency adjustment period. By determining different frequency adjustment periods and adjustment levels according to the performance parameters of the processor system, the system power consumption can be controlled, the system performance can be improved, the stability of the system can be ensured, no additional device needs to be added to the processor system, the software implementation mode can be adopted, and the cost and complexity of hardware design are saved.

Description

Technical Field

[0001] This application relates to the field of circuits, and more specifically, to a dynamic voltage frequency regulation method, apparatus, medium, and processor system. Background Technology

[0002] Dynamic voltage and frequency scaling (DVFS) is an important technique for adjusting the performance and power consumption of chips such as central processing unit (CPU) chips and graphics processing unit (GPU) chips. DVFS adjusts processor performance and dynamic and static power consumption by changing the processor's frequency and voltage.

[0003] In the existing technology, the specific implementation of DVFS also requires corresponding hardware circuit support, which makes it relatively complex to implement. Summary of the Invention

[0004] The purpose of this application is to provide a dynamic voltage frequency adjustment method, device, medium, and processor system to reduce the difficulty of implementing voltage frequency adjustment, improve processor system performance, and ensure processor system stability.

[0005] The first aspect of this application provides a dynamic voltage and frequency adjustment method, the method comprising: acquiring performance information of a processor system, the performance information including: workload, temperature, and power consumption; determining a frequency adjustment period and adjustment level based on the performance information; and adjusting the voltage / frequency level of the processor system by one or more levels based on the adjustment level within the frequency adjustment period.

[0006] The aforementioned dynamic voltage and frequency adjustment method determines different frequency adjustment cycles and adjustment levels based on the processor system's performance parameters. This allows the processor system to employ targeted adjustment strategies under different performance states, controlling system power consumption, improving system performance, and ensuring system stability. Ultimately, this results in excellent performance and stability for the processor system. Furthermore, it can be implemented without adding any components to the processor system, allowing for software implementation and saving on hardware design costs and complexity.

[0007] In an optional embodiment, the step of adjusting the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency modulation cycle includes: determining a target voltage / frequency level based on the current frequency voltage level and the adjustment level; determining a target frequency and a target voltage based on the target frequency voltage level; adjusting the frequency of the processor system to the target frequency; and adjusting the voltage of the processor system to the target voltage.

[0008] In the above embodiments, the processor system receives performance information, then makes a decision based on the received performance information, determines the target voltage / frequency level of the processor system, and adjusts the voltage and frequency according to the target voltage / frequency level, thereby adjusting the voltage and frequency of the system to an ideal state.

[0009] In an optional embodiment, adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: determining an adjustment mode, the adjustment mode including frequency up-adjustment and frequency down-adjustment; when the adjustment mode is frequency up-adjustment, first adjusting the voltage of the processor system to the target voltage, and then adjusting the frequency of the processor system to the target frequency; when the adjustment mode is frequency down-adjustment, first adjusting the frequency of the processor system to the target frequency, and then adjusting the voltage of the processor system to the target voltage.

[0010] In the above embodiments, the order of voltage regulation and frequency regulation is adjusted according to different adjustment modes, thereby ensuring the stability of the processor system voltage during adjustment and improving the system stability.

[0011] In an optional embodiment, adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: disabling the memory refresh mechanism of the processor system; and starting frequency adjustment after waiting for the last piece of data on the memory link of the processor system to be transmitted.

[0012] In the above embodiments, during frequency adjustment, the voltage requirement during frequency adjustment is reduced by shutting down the traffic on the memory link to avoid clock skew caused by voltage regulation, thereby saving power consumption and improving performance.

[0013] In an optional embodiment, determining the frequency modulation cycle and adjustment level based on the performance information includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if the workload is greater than or equal to a load threshold, and the temperature margin is less than a first threshold and the power consumption margin is less than a second threshold, the frequency modulation cycle is determined to be a first cycle, and the adjustment level is determined to be a first adjustment level; if the workload is greater than or equal to the load threshold, and the temperature margin is greater than or equal to the first threshold and the power consumption margin is greater than or equal to the second threshold, the frequency modulation cycle is determined to be a second cycle, and the adjustment level is determined to be a second adjustment level, wherein the first cycle is less than the second cycle, and the number of adjustment levels of the first adjustment level is greater than the number of adjustment levels of the second multi-level adjustment.

[0014] In the above embodiments, different frequency modulation cycles and adjustment levels are determined based on temperature margin and power consumption margin, enabling the system to adopt targeted adjustment strategies for different performance states, making it more adaptable. Compared with the method of adjusting voltage / frequency levels step by step, this can improve system performance, ensure system stability, and avoid excessive power consumption.

[0015] In an optional embodiment, the method further includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if the workload is greater than a load threshold, and the temperature margin is greater than a third threshold and the power consumption margin is greater than a fourth threshold, then the current voltage / frequency level of the processor system is maintained.

[0016] In the above embodiments, when it is determined that both the temperature margin and the power consumption margin are in a state of no margin, the current voltage / frequency level in the processor system is maintained to avoid adjustment, thereby ensuring the stability of system operation and improving system stability.

[0017] In an optional embodiment, the method further includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if both the temperature margin and the power consumption margin are negative margins, determining the adjustment mode as frequency reduction adjustment; and / or, if the workload is less than a load threshold, determining the adjustment mode as frequency reduction adjustment; when the adjustment mode is frequency reduction adjustment, determining the target frequency and target voltage of the processor system; adjusting the frequency of the processor system to the target frequency, and adjusting the voltage of the processor system to the target voltage.

[0018] In the above embodiments, timely frequency reduction adjustment under low workload can reduce system power consumption, and timely frequency reduction adjustment when both temperature margin and power margin are negative can ensure system stability. Moreover, the frequency reduction mode directly determines the target frequency for adjustment, which can speed up the response speed, further reduce power consumption and ensure stability.

[0019] A second aspect of this application provides a dynamic voltage and frequency adjustment device, the device comprising: a decision module, configured to acquire performance information of a processor system, the performance information including: workload, temperature, and power consumption; and configured to determine the frequency adjustment period and adjustment level based on the performance information;

[0020] The adjustment module is used to adjust the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency adjustment cycle.

[0021] A third aspect of this application provides a processor system, comprising: a computing unit, a power management unit, a clock source, a memory controller, and a memory; the power management unit is configured to provide voltage to the computing unit; the clock source is configured to provide a clock signal to the computing unit; the memory controller is configured to search for and read instructions from the memory; the memory is configured to store the instructions; and the computing unit is configured to execute the dynamic voltage frequency adjustment method as described in any one of the first aspects.

[0022] The fourth aspect of this application provides an electronic device, characterized in that the electronic device includes a processor system as described in the third aspect.

[0023] The fifth aspect of this application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer program instructions, which, when read and executed by a computer, perform the dynamic voltage frequency adjustment method as described in any one of the first aspects. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic block diagram of a processor system provided in an embodiment of this application;

[0026] Figure 2 A flowchart of a dynamic voltage frequency adjustment method provided in an embodiment of this application;

[0027] Figure 3 This is a schematic block diagram of a dynamic voltage and frequency adjustment device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0029] With the development of semiconductor process technology and the further increase in on-chip resource density, power consumption has become increasingly serious, becoming a bottleneck restricting the further development of chip processing performance. Dynamic Voltage Frequency Scaling (DVFS), Clock Gating (CG), and Power Gating (PG) are important means to regulate performance and power consumption. Among them, DVFS technology regulates processor performance and dynamic and static power consumption by changing the processor's frequency and voltage.

[0030] DVFS can adjust voltage / frequency (V / F) levels at fixed intervals and in progressive steps based on factors such as workload, power quality, and processor temperature, thereby enabling switching between different voltage / frequency levels to regulate performance and power consumption. Performance adjustment is achieved by changing the processor's clock frequency. Dynamic power consumption adjustment is achieved by changing the processor's clock frequency and operating voltage. Static power consumption adjustment is achieved by changing the processor's supply voltage.

[0031] In existing technologies, DVFS solutions are typically hardware-based, requiring dedicated hardware circuitry within the chip to implement the DVFS function. Basic circuit modules needed to implement DVFS include: an Activity Info (load prediction) unit, a clock generation unit, a clock adjustment unit, and a power adjustment unit. Furthermore, specific implementation schemes for DVFS also require corresponding hardware circuitry support, making implementation quite complex. Moreover, since voltage regulation can lead to large clock skew, existing technologies generally address this by increasing the supply voltage or employing clock pre-compensation circuits, which further limits DVFS performance and increases design complexity.

[0032] In addition, the existing DVFS adjusts one V / F (voltage / frequency) level in each frequency modulation cycle to achieve step-by-step adjustment of voltage / frequency levels. This adjustment method has a slow frequency response and is not flexible enough in terms of temperature and power consumption control.

[0033] Based on this, this application proposes a dynamic voltage and frequency adjustment method, apparatus, device, medium, and processor system. Different frequency adjustment cycles and adjustment levels are determined according to the performance parameters of the processor system, thereby enabling the processor system to adopt targeted adjustment strategies under different performance states. Compared with the existing method of adjusting voltage / frequency levels step by step, the method of this application can control system power consumption, improve system performance, and ensure system stability, enabling the processor system to achieve excellent results in both performance and stability.

[0034] The aforementioned dynamic voltage and frequency adjustment method is applied to a processor system, which refers to a processing device that is integrated into a single integrated circuit or chip and systematically performs operations in a preset order under the control of computer instructions.

[0035] This application Figure 1 A processor system 100 is shown. Figure 1 This is a schematic block diagram of a processor system provided in an embodiment of this application. The processor system includes a computing unit 110, a power management unit (PMU) 120, a clock source 130, a memory controller 140, and a memory 150.

[0036] The computing unit 110 can be designed as an integrated circuit implemented with multiple transistors. The computing unit 110 can be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or an image signal processor (ISP), etc.

[0037] In some embodiments, the computing unit 110 may include a computing block 111 and a cache 112. In some embodiments, the computing block 111 is a processor core (e.g., a logic block including an arithmetic logic unit (ALU), an execution unit (EU), a scheduler, registers, etc.). In some embodiments, the computing block 111 includes an accelerator for artificial intelligence (AI) processing. For example, the computing block 111 includes multiple multiplier arrays coupled to perform multiplication of large numbers. In some embodiments, the computing block 111 includes a processor core of a microprocessor or graphics processing unit. In some embodiments, the computing block 111 is the core logic of a field-programmable gate array (FPGA). In some embodiments, the computing block 111 is the core logic of a digital signal processor (DSP).

[0038] The computing block 111 included in the computing unit 110 can process instructions according to the clock signal CLK and the power supply voltage VDD. The performance of the computing block 111 can depend on the clock signal CLK and the power supply voltage VDD. As the amplitude of the power supply voltage VDD increases and the frequency of the clock signal CLK increases, the performance of the computing unit can be improved and the power consumption of the computing unit can increase.

[0039] In some embodiments, cache 112 includes one or more lower-level caches. Cache 112 may include any suitable memory, such as dynamic random access memory (DRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive RAM (ReRAM), static RAM (SRAM), etc. Cache 112 stores data required by computation block 111 when executing instructions.

[0040] The power management unit 120 can generate a power supply voltage VDD and can adjust the level of the power supply voltage VDD based on a voltage control signal CTRL_VDD. For example, the power management unit 120 may include a switching regulator that generates the power supply voltage VDD based on the control signal CTRL_VDD. In some embodiments, the power management unit 120 may also be referred to as a power management integrated circuit (PMIC).

[0041] Clock source 130 generates a clock signal CLK, and the frequency of the clock signal CLK can be adjusted based on the clock control signal CTRL_CLK. For example, clock source 130 may include an oscillator that generates the clock signal CLK based on the clock control signal CTRL_CLK. In some embodiments, clock management unit 130 may also be referred to as a clock generator and clock generation circuit. In some embodiments, clock source 130 may be a clock generation device including a phase-locked loop (PLL), a delay phase-locked loop (DLL), and a crystal modifier. In some embodiments, the operating clock signal may also be supplied to another device, such as memory controller 140.

[0042] The computing unit 110 sends a request to the memory controller 140 to locate data from the memory 150. The memory controller 140 then issues one or more commands (e.g., a read command) to locate the data in the memory 150. The memory 150 can be any suitable memory, such as dynamic random access memory (DRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive RAM (ReRAM), static RAM (SRAM), etc. Once the data is located in the memory 150, it is transferred to the computing unit 110 or cache 112.

[0043] The memory 150 stores the above-mentioned dynamic voltage frequency adjustment method. The computing unit 110 reads part or all of the data of the above-mentioned dynamic voltage frequency adjustment method from the memory controller 140 and executes it. Based on the performance parameters of the processor system, it determines different frequency adjustment cycles and adjustment levels, so that the processor system adopts targeted adjustment strategies under different performance states.

[0044] Some or all of the components of the processor system 100 may be on a single die (e.g., a system-on-a-chip), on a single package having multiple dies, or on multiple dies in multiple packages. A system-on-a-chip refers to a processing device that integrates various functional blocks (e.g., central processing unit (CPU), memory, interface units, digital signal processing units, analog signal processing units, etc.) into a single or several semiconductor integrated circuits (ICs) to implement an electronic system (such as a computer system). For example, a SoC may include various functions such as processor functions, multimedia functions, graphics functions, interface functions, and security functions.

[0045] The processor system 100 can correspond to various types of data processing devices, such as laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, portable multimedia players (PMPs), personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable computers, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, or e-books.

[0046] like Figure 2 As shown, Figure 2 This is a flowchart illustrating a dynamic voltage frequency regulation method provided in an embodiment of this application. The method includes steps 210 to 230:

[0047] Step 210: Obtain the performance information of the processor system, including: workload, temperature, and power consumption.

[0048] Obtain performance information of the processor system, including at least workload, temperature, and power consumption.

[0049] The workload of a processor system refers to the utilization rate of computing units 110 within the processor system 100 per unit time. In some embodiments, this can be represented by the number of clock cycles in a non-idle state on each computing block 111 of the computing unit 110. That is, in each statistical cycle, the number of clock cycles in a non-idle state of the computing block within that statistical cycle is counted, and the utilization rate of the computing block within that statistical cycle is obtained by dividing the number of clock cycles in a non-idle state by the total number of clock cycles in that statistical cycle. The utilization rate of the computing unit can be represented by the average utilization rate of the computing blocks. In some embodiments, the workload can be the ratio of the current load value to the maximum load value, and the load value can be calculated by multiplying the ratio of working time to unit time by the current operating frequency. For example, if the current operating frequency is 1MHz, the unit time is 0.1 milliseconds, and the idle time is 0.01 milliseconds, then the load on the CPU 110 can be calculated as "9000000". In some embodiments, the workload can be the activity information of the Activity Monitor. This application embodiment does not limit the method of obtaining the workload.

[0050] The temperature of the processor system 100 refers to the current temperature of the entire processor system 100 or the current temperature of the computing unit 110 within the processor system. In some embodiments, this temperature can be obtained through a temperature sensor located within the processor system. For example, the computing unit 110 can periodically obtain the currently measured temperature data from the temperature sensor as its temperature. In some embodiments, better implementation results can be achieved when the temperature in the performance information is the current temperature of the computing unit within the processor system.

[0051] The power consumption of a processor system refers to the overall power of the processor system 100 or the current power of the computing unit 110 within the processor system. For example, the current current and voltage of the processor system 100 can be measured to calculate the current power of the processor system. In some embodiments, better implementation results can be achieved when the power consumption in the performance information is the current power consumption of the computing unit 110 within the processor system. The power consumption of the computing unit 110 can be calculated based on the total power of its included computing blocks 111. The power of a computing block can be calculated based on the voltage, frequency, etc., of the computing block. This application does not limit the calculation method of the computing block power.

[0052] In some embodiments, temperature and power consumption information can be obtained from the PVT module.

[0053] Step 220: Determine the frequency modulation period and adjustment level based on the performance information.

[0054] The corresponding frequency adjustment cycle and adjustment level are determined based on the current performance information of the processor system, so that the processor system can simultaneously meet the requirements of performance and stability.

[0055] In this application, multiple voltage / frequency (V / F) levels are pre-set for the computing unit 110. The voltage / frequency level of the computing unit can be calculated from the voltage required by all computing blocks 111 included in the computing unit 110 and the total frequency of all computing blocks. To ensure the stable operation of the computing blocks, multiple voltage / frequency levels are set for the computing blocks, for example, 1.3GHz / 1.7V, indicating that the computing block needs a 1.7V power supply when running at a frequency of 1.3GHz. By setting the voltage / frequency levels, a balance can be achieved between the performance and power consumption of the computing block. In some embodiments, the multiple voltage / frequency levels of the computing unit can be recorded in a table to generate a voltage / frequency level lookup table (V / F lookup table), which can be stored in the memory 150.

[0056] Frequency modulation level refers to the number of levels at which the voltage / frequency level of the computing unit within the processor system needs to be adjusted. For example, a frequency modulation level of one means that the current voltage / frequency level of the computing unit within the processor system will be adjusted down or down one level.

[0057] The frequency modulation cycle refers to the unit of time for adjusting the computing units within the processor system according to the frequency modulation level.

[0058] For example, the operating status of the computing unit within the processor system is determined based on performance information. When the operating status indicates that the computing unit is under high load, the frequency adjustment period is determined to be long and the adjustment level is determined to be low. When the operating status indicates that the computing unit is under low load, the frequency adjustment period is determined to be short and the adjustment level is determined to be high.

[0059] In other words, when performance information indicates that the processor system is operating under high load, the frequency adjustment period is set to a long period, such as 50ms, and the adjustment level is set to a low level, such as level one or two, to ensure the stability of the processor system. When performance information indicates that the processor system is operating under low load, the frequency adjustment period is set to a short period, such as 10ms, and the adjustment level is set to a high level, such as level three, to ensure that the processor system can adjust quickly to meet load requirements.

[0060] In some embodiments of this application, determining the frequency modulation cycle and adjustment level based on the performance information includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if the workload is greater than or equal to a load threshold, and the temperature margin is less than a first threshold and the power consumption margin is less than a second threshold, the frequency modulation cycle is determined to be a first cycle, and the adjustment level is determined to be a first adjustment level; if the workload is greater than or equal to the load threshold, and the temperature margin is greater than or equal to the first threshold and the power consumption margin is greater than or equal to the second threshold, the frequency modulation cycle is determined to be a second cycle, and the adjustment level is determined to be a second adjustment level, wherein the first cycle is less than the second cycle, and the adjustment level of the first adjustment level is greater than the adjustment level of the second adjustment level.

[0061] Temperature margin and power margin are determined based on the temperature and power consumption information in the performance data. In existing technologies, to ensure the security of the processor system, power consumption walls and temperature walls are usually set for the system or module. The power consumption wall refers to the maximum power consumption of the system or module during operation, and the temperature wall refers to the maximum temperature at which the system or module operates.

[0062] The power consumption limit and temperature limit should correspond to the acquired performance information. For example, when some or all components of processor system 100 can be built on a single die to form a system-on-a-chip, the acquired performance information is the overall performance information of the processor system. In this case, the power consumption limit and temperature limit should be the overall power consumption limit and temperature limit of the processor system. Similarly, when some or all components of processor system 100 are located on multiple dies in multiple packages, the acquired performance information is the performance information of the computing unit. In this case, the power consumption limit and temperature limit should be the power consumption limit and temperature limit set for the computing unit.

[0063] Temperature margin refers to the ratio between the current temperature and the preset temperature limit. For example, if the current temperature of the calculation unit in the performance information is 60°C and the temperature limit of the calculation unit is 100°C, then the temperature margin is 60%. In some embodiments, temperature margin is expressed as the distance between the current temperature and the temperature limit. For example, if the current temperature of the calculation unit in the performance information is 50°C and the temperature limit of the calculation unit is 80°C, then the temperature margin is 30°C.

[0064] Power margin refers to the ratio between the current power consumption and the preset power limit. For example, if the current power consumption of the computing unit is 60W and the temperature limit of the computing unit is 100W in the performance information, then the power margin is 60%. In some embodiments, power margin is expressed as the distance between the current power consumption and the power limit. For example, if the current power consumption of the computing unit is 50W and the power limit of the computing unit is 80W in the performance information, then the power margin is 30W.

[0065] Make decisions based on the workload, temperature margin, and power consumption margin in the performance information:

[0066] If the workload in the performance information is greater than or equal to the preset load threshold, it indicates that the processor system load prediction is large. For example, if the utilization rate of the computing unit is ≥50%, it indicates that the system load prediction is large. At this time, the temperature margin and power margin are judged. If the current temperature is less than the preset first threshold (e.g., temperature margin <50%) and the current power consumption is less than the preset second threshold (e.g., power margin <65%), it indicates that the temperature margin and power margin are large. At this time, the frequency adjustment period can be determined as the first period (e.g., 10ms) and the adjustment level can be determined as the first adjustment level (e.g., level three adjustment).

[0067] If the workload in the performance information is greater than or equal to a preset load threshold, it indicates that the processor system load prediction is large. For example, if the utilization rate of the computing unit is ≥50%, it indicates that the system load prediction is large. In this case, the temperature margin and power margin are judged. If the current temperature is greater than or equal to a preset first threshold (e.g., temperature margin ≥50%), and the current power consumption is less than a preset second threshold (e.g., power margin ≥65% of the power limit), it indicates that the temperature margin and power margin are small. In this case, the frequency adjustment period can be determined as the second period (e.g., 50ms), and the adjustment level can be determined as the second adjustment level (e.g., two-level adjustment). In some embodiments, to achieve better adjustment effects, it is necessary to distinguish between the range with small power margin and the range with power margin close to the critical value. Therefore, the case of small temperature margin and power margin should be that the temperature margin falls within a specified range (e.g., temperature margin >= 50% and <= 90%), and the power margin falls within a specified range (e.g., >= 65% of the power limit and <= 80%).

[0068] Specifically, the length of the first cycle needs to be shorter than the second cycle, and the number of adjustment stages of the first adjustment level is greater than the number of stages of the second adjustment level. When the system has a larger temperature margin and power consumption margin, the system frequency can be quickly adjusted using a short cycle and a large number of stages, thereby enabling the system to process tasks in a timely manner and improving system performance. Conversely, when the system has a smaller temperature margin and power consumption margin, the system frequency needs to be adjusted using a long cycle and a small number of stages, which can improve system performance, ensure system stability, and avoid excessive power consumption.

[0069] Multiple optimal frequency modulation (FM) cycles can be pre-analyzed using frequency and performance test results, such as SHMOO plots. When determining the FM cycle, these optimal cycles can be selected. For example, two optimal FM cycles can be identified: 10ms and 50ms. If a longer FM cycle is required, 50ms can be selected.

[0070] In the above embodiments, different frequency modulation cycles and adjustment levels are determined based on temperature margin and power consumption margin, enabling the system to adopt targeted adjustment strategies for different performance states, making it more adaptable. Compared with the method of adjusting voltage / frequency levels step by step, this can improve system performance, ensure system stability, and avoid excessive power consumption.

[0071] In some embodiments of this application, the method further includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if the workload is greater than a load threshold, and the temperature margin is greater than a third threshold and the power consumption margin is greater than a fourth threshold, then the current voltage / frequency level of the processor system is maintained.

[0072] In addition to determining the frequency modulation cycle for one or more levels of adjustment, this application also includes other adjustment strategies, such as determining whether to maintain the current voltage / frequency level based on performance information.

[0073] After obtaining the performance information, the temperature margin and power consumption margin are determined based on the temperature and power consumption in the performance information. The temperature margin refers to the ratio of the temperature to the preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to the preset power consumption limit.

[0074] Make decisions based on the workload, temperature margin, and power consumption margin in the performance information:

[0075] If the workload in the performance information is large, such as the utilization rate of the computing unit being ≥50%, it indicates that the system load prediction is large. At this time, the temperature margin and power margin are judged. If the temperature margin in the performance information is found to be greater than the third threshold (e.g., temperature margin >90%), and the power margin is found to be greater than the fourth threshold (e.g., power margin >80%), it means that the processor system has no temperature margin and power margin. In this case, the current voltage / frequency level of the computing unit in the processor system is maintained.

[0076] In the above embodiments, when it is determined that both the temperature margin and the power consumption margin are in a state of no margin, the current voltage / frequency level in the processor system is maintained to avoid adjustment, thereby ensuring the stability of system operation and improving system stability.

[0077] In some embodiments of this application, the method further includes: determining a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if both the temperature margin and the power consumption margin are negative margins, determining the adjustment mode as frequency reduction adjustment; and / or, if the workload is less than a load threshold, determining the adjustment mode as frequency reduction adjustment; when the adjustment mode is frequency reduction adjustment, determining the target frequency and target voltage of the processor system; adjusting the frequency of the processor system to the target frequency, and adjusting the voltage of the processor system to the target voltage.

[0078] In addition to determining the frequency modulation cycle for one or more levels of adjustment, this application also includes other adjustment strategies, such as determining whether to downclock and the downclocking strategy based on performance information:

[0079] After obtaining the performance information, the temperature margin and power consumption margin are determined based on the temperature and power consumption in the performance information. The temperature margin refers to the ratio of the temperature to the preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to the preset power consumption limit.

[0080] Make decisions based on the workload, temperature margin, and power consumption margin in the performance information:

[0081] The system assesses the workload status. If the workload is less than a preset load threshold, such as a computing unit utilization rate of <50%, it indicates that the system predicts a very low or idle load. In this case, frequency reduction is required to save energy, and the appropriate adjustment mode is determined to be frequency reduction. Frequency reduction can control the computing unit to operate at a lower or even the lowest voltage / frequency level, and clock gating (CG) can be used to further reduce static power consumption. Clock gating is a technique used to reduce the power consumption of digital circuits. By controlling the transmission of clock signals, clock gating can turn on or off the operation of specific circuit areas, thereby saving power when not needed. CG is disabled when there is a task to perform.

[0082] If both the temperature margin and power consumption margin are determined to be negative (e.g., temperature margin ≥ 100%, power consumption margin ≥ 95%, indicating a negative margin), then the system needs to reduce its frequency promptly to lower the temperature, maintain stability, and avoid malfunctions. In this case, the adjustment mode is determined to be frequency reduction.

[0083] After determining that the adjustment mode is frequency reduction adjustment, the target frequency to which the computing unit will be adjusted and the corresponding target voltage can be determined. Then, the frequency of the computing unit in the processor system is adjusted to the target frequency, and the input voltage of the computing unit in the processor system is adjusted to the target voltage. For example, after determining that both the temperature margin and the power consumption margin are negative margins, the target frequency is set to 50% of the maximum frequency allowed by the system, and frequency reduction adjustment is performed to ensure the stability of the system.

[0084] The aforementioned frequency reduction adjustment, performed promptly under low workload conditions, lowers system power consumption. Furthermore, this frequency reduction adjustment directly targets the desired frequency, enabling rapid adjustment and further reducing power consumption. Additionally, timely frequency reduction adjustment, performed when both temperature and power margins are negative, ensures system stability. This frequency reduction adjustment, also directly targeting the desired frequency, rapidly lowers the temperature, further guaranteeing system stability.

[0085] In the above embodiments, timely frequency reduction adjustment under low workload can reduce system power consumption, and timely frequency reduction adjustment when both temperature margin and power margin are negative can ensure system stability. Moreover, the frequency reduction mode directly determines the target frequency for adjustment, which can speed up the response speed, further reduce power consumption and ensure stability.

[0086] In some embodiments of this application, the processor system executes a decision-making process to determine the voltage / frequency level the system should be at in the next moment, and issues voltage adjustment commands and frequency adjustment commands based on the decision results. The decision content includes:

[0087] Monitor workload information. If the system is detected to have a large amount of data transmission and computing demands, such as a computing unit utilization rate >= 50%, then the system will take action.

[0088] The system monitors the current power and temperature margins. If the current temperature margin is <50% and the power margin is <65%, it indicates that the current power and temperature margins are large. In this case, a large-amplitude frequency adjustment is performed, using the smallest possible frequency adjustment period, and the clock gating state is exited. Large-amplitude frequency adjustment and a small frequency adjustment period can accelerate the frequency response, thereby improving system performance. If the current power margin is >= 65% and <= 80% and the temperature margin is >= 50% and <= 90%, it indicates that the power and temperature margins are small. In this case, a small-amplitude frequency adjustment is performed, using a large frequency adjustment period, and the clock gating state is exited. Small-amplitude frequency adjustment and a large frequency adjustment period can improve system performance. If the current temperature margin is >90% and the power margin is >80%, it indicates that there are no current temperature and power margins. Based on the defined temperature and power limits, the current frequency state is maintained, and the clock gating state is exited. If the current temperature and power margins are negative, frequency reduction is performed, and the clock gating state is exited.

[0089] If there is no large demand for data transmission and computation, such as workload information indicating that the computing unit utilization rate is <50%, then the current frequency state is maintained and the clock gating state is entered.

[0090] Step 230: During the frequency adjustment cycle, the voltage / frequency level of the processor system is adjusted by one or more levels according to the adjustment level.

[0091] After determining the frequency modulation period and adjustment level under the current performance information, within the frequency modulation period, the current voltage / frequency level of the computing unit is adjusted up or down by the aforementioned adjustment level. For example, if the adjustment level is level three and the current level is level six, such as 1.3GHz / 1.7V, then the level of the computing unit is directly adjusted down to level three, such as 1.0GHz / 1.1V.

[0092] The aforementioned dynamic voltage and frequency adjustment method determines different frequency adjustment cycles and adjustment levels based on the performance parameters of the processor system, thereby enabling the processor system to adopt targeted adjustment strategies under different performance states. Compared with the step-by-step adjustment method in the prior art, the method of this application can control system power consumption, improve system performance, and ensure system stability, enabling the processor system to achieve excellent results in both performance and stability.

[0093] Furthermore, the aforementioned dynamic voltage and frequency adjustment method can be implemented without adding any components to the processor system, and can be implemented in software, thus saving some of the cost and complexity of hardware design.

[0094] In some embodiments of this application, the step of adjusting the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency modulation cycle includes: determining a target voltage / frequency level based on the current frequency voltage level and the adjustment level; determining a target frequency and a target voltage based on the target frequency voltage level; adjusting the frequency of the processor system to the target frequency; and adjusting the voltage of the processor system to the target voltage.

[0095] After determining the frequency modulation cycle and adjustment level under the current performance information, the voltage / frequency level lookup table can be read. Based on the current voltage / frequency level of the calculation unit, the adjustment level can be searched downwards or downwards to obtain the target voltage / frequency level of the calculation unit. After determining the target voltage / frequency level, the voltage and frequency of the target voltage / frequency level are found in the voltage / frequency level lookup table to obtain the target frequency and target voltage.

[0096] After obtaining the target frequency, the processor system adjusts the frequency of the computing unit to the target frequency or a near-target frequency. For example, it adjusts the frequency of the clock signal CLK based on the clock control signal CTRL_CLK, thereby adjusting the frequency of the clock signal input to the computing unit, and thus changing the frequency of the computing unit to the target frequency. In some embodiments of this application, a phase-locked loop (PLL) provides the clock requirement for the system, which provides the initial frequency to the processor system after passing through a clock generator.

[0097] After obtaining the target voltage, the processor system adjusts the voltage of the computing unit to match the input voltage. For example, a voltage control signal CTRL_VDD is output to the power management unit 120. The power management unit can output a power supply voltage VDD with an adjustment range based on the voltage control signal CTRL_VDD. In some embodiments, after determining the target frequency, the voltage regulation module can be instructed to find its required operating voltage according to a voltage / frequency lookup table (V / F lookup table), and then send its voltage requirement to the power module (DC-DC Converter) on the hardware board, which will then output the corresponding voltage.

[0098] In the above embodiments, the processor system receives performance information, then makes a decision based on the received performance information, determines the target voltage / frequency level of the processor system, and adjusts the voltage and frequency according to the target voltage / frequency level, thereby adjusting the voltage and frequency of the system to an ideal state.

[0099] In some embodiments of this application, adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: determining an adjustment mode, wherein the adjustment mode includes frequency up-adjustment and frequency down-adjustment; when the adjustment mode is frequency up-adjustment, first adjusting the voltage of the processor system to the target voltage, and then adjusting the frequency of the processor system to the target frequency; when the adjustment mode is frequency down-adjustment, first adjusting the frequency of the processor system to the target frequency, and then adjusting the voltage of the processor system to the target voltage.

[0100] When instructing voltage regulation, the regulation mode needs to be determined. For example, before the calculation unit 110 instructs the power management unit 120 to perform voltage regulation, the calculation unit 110 needs to determine the current regulation mode. Regulation modes include frequency upregulation and frequency downregulation. Frequency upregulation means that the calculation unit increases its own frequency relative to the current frequency, while frequency downregulation means that the calculation unit decreases its own frequency relative to the current frequency.

[0101] When the adjustment mode is frequency upscaling, the input voltage to the calculation unit needs to be adjusted first based on the target voltage, and then the frequency of the calculation unit can be adjusted based on the target frequency. For example, the calculation unit can also issue frequency adjustment commands and voltage adjustment commands simultaneously. After issuing the voltage adjustment command, a 300µs delay is required to wait for the power supply to stabilize before proceeding to the next step, such as frequency adjustment. In some embodiments, the calculation unit can issue a voltage adjustment command first, and after issuing the voltage adjustment command, a 300µs delay is required to wait for the power supply to stabilize before issuing the frequency adjustment command.

[0102] When the adjustment mode is frequency reduction adjustment, the frequency of the calculation unit needs to be adjusted according to the target frequency first, and then the voltage of the calculation unit needs to be adjusted.

[0103] Because the communication bus used by the power management unit has a slow communication speed, there is a delay from command issuance to voltage stabilization. For example, when the unit management unit uses PMBus, there is a delay of about 300µs, as measured in actual tests at a PMBus communication speed of 100k / s. That is, when increasing the frequency, the voltage is adjusted first, then the frequency. When decreasing the frequency, the frequency is adjusted first, then the voltage.

[0104] In the above embodiments, the order of voltage regulation and frequency regulation is adjusted according to different adjustment modes, thereby ensuring the stability of the processor system voltage during adjustment and improving the system stability.

[0105] Because the workload of the processor system itself can cause voltage instability (voltage overshoot and undershoot), if a voltage regulation instruction is executed to periodically adjust the voltage, the combination of these two factors will cause system clock instability (frequency overshoot and undershoot), resulting in clock skew.

[0106] In some embodiments of this application, adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: disabling the memory refresh mechanism of the processor system; and starting frequency adjustment after waiting for the last piece of data on the memory link of the processor system to be transmitted.

[0107] Upon receiving the frequency adjustment command, the processor system will disable the memory refresh mechanism, which is a mechanism used by the processor system to read data from memory such as memory 150 for processing.

[0108] After disabling the memory refresh mechanism, data transfer on the memory link does not immediately pause. The memory link refers to the path of data from memory to the computation block that processes the data, including cache, stack, etc. It requires waiting for a small amount of data to be transferred on the memory link.

[0109] After the last piece of data on the processor system's memory link is transmitted, the processor system begins frequency adjustment and waits for the clock to stabilize, such as waiting for the PLL to relock (stabilize).

[0110] Once the clock stabilizes, the memory refresh mechanism is activated, at which point the frequency adjustment instruction is considered to have been executed within the frequency adjustment cycle.

[0111] In the above embodiments, during frequency adjustment, the voltage requirement during frequency adjustment is reduced by shutting down the traffic on the memory link to avoid clock skew caused by voltage regulation, thereby saving power consumption and improving performance.

[0112] like Figure 3 The above, Figure 3 This is a schematic block diagram of a dynamic voltage frequency adjustment device 300 provided in an embodiment of this application. The device includes:

[0113] Decision module 310 is used to acquire performance information of the processor system, including workload, temperature, and power consumption; and to determine the frequency adjustment cycle and adjustment level based on the performance information.

[0114] The adjustment module 320 is used to adjust the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency adjustment cycle.

[0115] In some embodiments of this application, the adjustment module includes:

[0116] The determination module is used to determine the target voltage / frequency level based on the current frequency voltage level and the adjustment level;

[0117] The query module is used to determine the target frequency and target voltage based on the target frequency voltage level;

[0118] A frequency and voltage adjustment module is used to adjust the frequency of the processor system to the target frequency and the voltage of the processor system to the target voltage.

[0119] In some embodiments of this application, the frequency and voltage adjustment module includes a voltage adjustment submodule, which is used to determine an adjustment mode, including frequency up-adjustment and frequency down-adjustment. When the adjustment mode is frequency up-adjustment, the voltage of the processor system is first adjusted to the target voltage, and then the frequency of the processor system is adjusted to the target frequency. When the adjustment mode is frequency down-adjustment, the frequency of the processor system is first adjusted to the target frequency, and then the voltage of the processor system is adjusted to the target voltage.

[0120] In some embodiments of this application, the frequency and voltage adjustment module includes a shutdown submodule, which is used to disable the memory refresh mechanism of the processor system; and to start frequency adjustment after the last piece of data on the memory link of the processor system has been transmitted.

[0121] In some embodiments of this application, the determining module is specifically used to determine a temperature margin and a power margin based on the temperature and the power consumption. The temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit. If the workload is greater than or equal to a load threshold, and the temperature margin is less than a first threshold and the power consumption margin is less than a second threshold, the frequency modulation period is determined to be a first period, and the adjustment level is determined to be a first adjustment level. If the workload is greater than or equal to the load threshold, and the temperature margin is greater than or equal to the first threshold and the power consumption margin is greater than or equal to the second threshold, the frequency modulation period is determined to be a second period, and the adjustment level is determined to be a second adjustment level. The first period is less than the second period, and the number of adjustment levels of the first adjustment level is greater than the number of adjustment levels of the second multi-level adjustment.

[0122] In some embodiments of this application, the device further includes a holding module, which is used to determine a temperature margin and a power margin based on the temperature and the power consumption. The temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit.

[0123] If the workload exceeds the load threshold, and the temperature margin exceeds the third threshold and the power consumption margin exceeds the fourth threshold, then the current voltage / frequency level of the processor system is maintained.

[0124] In some embodiments of this application, the device further includes an adjustment module, which is configured to determine a temperature margin and a power margin based on the temperature and the power consumption, wherein the temperature margin refers to the ratio of the temperature to a preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to a preset power consumption limit; if both the temperature margin and the power consumption margin are negative margins, the adjustment mode is determined to be frequency reduction adjustment; and / or, if the workload is less than a load threshold, the adjustment mode is determined to be frequency reduction adjustment; when the adjustment mode is frequency reduction adjustment, the target frequency and target voltage of the processor system are determined; the frequency of the processor system is adjusted to the target frequency, and the voltage of the processor system is adjusted to the target voltage.

[0125] This application provides an electronic device, which includes the processor system described in any of the above embodiments.

[0126] This application provides a computer-readable storage medium storing computer program instructions. When the computer program instructions are read and executed by a computer, the dynamic voltage frequency adjustment method described in any of the above embodiments is performed.

[0127] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0128] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0130] It should be noted that if the function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0131] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0132] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A dynamic voltage frequency regulation method, characterized in that, The method includes: Obtain performance information of the processor system, including workload, temperature, and power consumption; The frequency modulation period and adjustment level are determined based on the performance information. During the frequency adjustment cycle, the voltage / frequency level of the processor system is adjusted by one or more levels according to the adjustment level.

2. The method according to claim 1, characterized in that, The step of adjusting the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency modulation cycle includes: The target voltage / frequency level is determined based on the current voltage / frequency level and the aforementioned adjustment level; The target frequency and target voltage are determined based on the target voltage / frequency level. Adjust the frequency of the processor system to the target frequency and adjust the voltage of the processor system to the target voltage.

3. The method according to claim 2, characterized in that, The step of adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: Determine the adjustment mode, which includes frequency up adjustment and frequency down adjustment; When the adjustment mode is frequency up adjustment, the voltage of the processor system is first adjusted to the target voltage, and then the frequency of the processor system is adjusted to the target frequency. When the adjustment mode is frequency reduction adjustment, the frequency of the processor system is first adjusted to the target frequency, and then the voltage of the processor system is adjusted to the target voltage.

4. The method according to claim 2, characterized in that, The step of adjusting the frequency of the processor system to the target frequency and adjusting the voltage of the processor system to the target voltage includes: Disable the memory refresh mechanism of the processor system; Frequency adjustment begins after the last piece of data on the processor system's memory link has been transmitted.

5. The method according to claim 1, characterized in that, Determining the frequency modulation period and adjustment level based on the performance information includes: The temperature margin and power consumption margin are determined based on the temperature and the power consumption. The temperature margin refers to the ratio of the temperature to the preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to the preset power consumption limit. If the workload is greater than or equal to the load threshold, and the temperature margin is less than the first threshold and the power consumption margin is less than the second threshold, the frequency modulation cycle is determined to be the first cycle, and the adjustment level is determined to be the first adjustment level. If the workload is greater than or equal to the load threshold, and the temperature margin is greater than or equal to the first threshold and the power consumption margin is greater than or equal to the second threshold, the frequency modulation period is determined to be the second period, the adjustment level is determined to be the second adjustment level, the first period is less than the second period, and the adjustment level of the first adjustment level is greater than the adjustment level of the second adjustment level.

6. The method according to claim 1, characterized in that, The method further includes: The temperature margin and power consumption margin are determined based on the temperature and the power consumption. The temperature margin refers to the ratio of the temperature to the preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to the preset power consumption limit. If the workload exceeds the load threshold, and the temperature margin exceeds the third threshold and the power consumption margin exceeds the fourth threshold, then the current voltage and frequency level of the processor system is maintained.

7. The method according to claim 1, characterized in that, The method further includes: The temperature margin and power consumption margin are determined based on the temperature and the power consumption. The temperature margin refers to the ratio of the temperature to the preset temperature limit, and the power consumption margin refers to the ratio of the power consumption to the preset power consumption limit. If both the temperature margin and the power consumption margin are negative margins, the adjustment mode is determined to be frequency reduction adjustment; And / or, if the workload is less than the load threshold, the adjustment mode is determined to be frequency reduction adjustment; When the adjustment mode is frequency reduction adjustment, determine the target frequency and target voltage of the processor system; Adjust the frequency of the processor system to the target frequency and adjust the voltage of the processor system to the target voltage.

8. A dynamic voltage frequency adjustment device, characterized in that, The device includes: A decision module is used to acquire performance information of the processor system, including workload, temperature, and power consumption; and to determine the frequency adjustment cycle and adjustment level based on the performance information. The adjustment module is used to adjust the voltage / frequency level of the processor system by one or more levels according to the adjustment level during the frequency adjustment cycle.

9. A processor system, characterized in that, include: Computing unit, power management unit, clock source, memory controller, and memory; The power management unit is used to provide voltage to the computing unit; The clock source is used to provide a clock signal to the computing unit; The storage controller is used to search for and read instructions from the memory; The memory is used to store the instructions; The computing unit is used to execute the instructions to implement the dynamic voltage frequency adjustment method as described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes the processor system as described in claim 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when read and executed by a computer, perform the dynamic voltage frequency adjustment method as described in any one of claims 1-7.

Images