Wafer hybrid bonding method and grinding apparatus

Abstract

A wafer hybrid bonding method and grinding device, the method comprising: performing first grinding processing on an initial edge region from the first surface to the second surface direction to form a first wafer structure, the first wafer structure comprising a functional region and an edge region surrounding the functional region, the edge region having a first grinding opening, the side wall of the first grinding opening having an obtuse angle with the first surface; forming a first conductive structure in a first dielectric layer, the surface of the first dielectric layer exposing the surface of the first conductive structure; providing a second wafer structure, the second wafer structure comprising a second dielectric layer and a second conductive structure in the second dielectric layer, the surface of the second dielectric layer exposing the surface of the second conductive structure; performing bonding processing on the first wafer structure and the second wafer structure, so that the second dielectric layer is bonded to the first dielectric layer, and the first conductive structure is bonded to the second conductive structure, thereby improving the uniformity of the first conductive structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer hybrid bonding method and grinding apparatus. Background Technology

[0002] As the development of very large-scale integrated circuits (VLSI) approaches its physical limits, three-dimensional integrated circuits, with their advantages in physical size and cost, represent an effective way to extend Moore's Law and solve advanced packaging problems. Wafer bonding is a technology that uses external energy to bond atoms at the wafer interface together through van der Waals forces, molecular forces, and even atomic forces.

[0003] Hybrid bonding is a commonly used wafer bonding method widely applied in the 3D chip industry, such as in the bonding of CMOS image sensors, Dynamic Random Access Memory (DRAM), and logic devices. Hybrid bonding technology can simultaneously bond two wafers together to achieve internal interconnections of thousands of chips, significantly improving chip performance and reducing costs.

[0004] However, existing wafer hybrid bonding technology needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a wafer hybrid bonding method and grinding apparatus to improve the performance of the formed hybrid bonding structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a wafer hybrid bonding method, comprising: providing an initial first wafer structure, the initial first wafer structure including a functional region and an initial edge region surrounding the functional region, the initial first wafer structure including a first wafer and a first dielectric layer located on the first wafer, the first wafer having a first face and a second face opposite to each other, the first dielectric layer being located on the first face; performing a first grinding process on the initial edge region from the first face toward the second face to form a first wafer structure, the first wafer structure including a functional region and an edge region surrounding the functional region, the edge region having a first grinding opening, the sidewall of the first grinding opening forming an obtuse angle with the first face; forming a first conductive structure within the first dielectric layer, the surface of the first dielectric layer exposing the surface of the first conductive structure; providing a second wafer structure, the second wafer structure including a second dielectric layer and a second conductive structure located within the second dielectric layer, the surface of the second dielectric layer exposing the surface of the second conductive structure; performing a bonding process on the first wafer structure and the second wafer structure, such that the second dielectric layer is bonded to the first dielectric layer, and the first conductive structure is bonded to the second conductive structure.

[0007] Optionally, the first wafer has a first metal layer, and the first surface exposes the surface of the first metal layer; the method of forming the first conductive structure includes: forming a first opening in a first dielectric layer, the first opening exposing the surface of the first metal layer; forming a seed material layer in the first opening, a first grinding opening and the surface of the functional region; forming a conductive material layer on the seed material layer; planarizing the conductive material layer until the top surface of the functional region is exposed, thereby forming the first conductive structure with the conductive material layer and the seed material layer.

[0008] Optionally, the thickness of the seed crystal material layer ranges from 700 angstroms to 1500 angstroms.

[0009] Optionally, the seed crystal material layer can be formed using a physical vapor deposition process.

[0010] Optionally, the method for forming the conductive material layer includes: providing an electroplating machine; placing a cathode probe of the electroplating machine on the sidewall of the edge region and placing the surface of the seed material layer in an electrolyte; and passing a direct current between the cathode probe and the anode of the electroplating machine to form the conductive material layer.

[0011] Optionally, the first opening includes a first groove and a first through hole located below and communicating with the first groove.

[0012] Optionally, before forming the first opening and after forming the first grinding hole, a third dielectric layer is formed on the first dielectric layer, and the first opening is also located within the third dielectric layer; the method of forming the first opening includes: etching the third dielectric layer and the first dielectric layer, forming a first trench in the third dielectric layer, and forming a first through hole in the first dielectric layer.

[0013] Optionally, after the bonding process, the process may include: thinning the first wafer from the second surface.

[0014] Optionally, after the bonding process and before the thinning process, the process further includes: performing a second grinding process on the edge area from the second surface toward the first surface, forming a second grinding opening with the first grinding opening, wherein the angle between the sidewall of the second grinding opening and the first surface ranges from 88 degrees to 92 degrees.

[0015] Optionally, the depth of the first grinding kerf ranges from 32 micrometers to 153 micrometers.

[0016] Optionally, the angle between the sidewall of the first grinding port and the first surface is greater than 160 degrees.

[0017] Optionally, the second wafer structure further includes: a second wafer having a functional surface, a second metal layer inside the second wafer, and the functional surface exposing the second metal layer, a second dielectric layer located on the functional surface, and a second conductive structure located on the second metal layer.

[0018] Optionally, the second wafer structure further includes a barrier layer located on the second dielectric layer, the second conductive structure being located within the barrier layer, and the barrier layer exposing the surface of the second conductive structure.

[0019] Optionally, the first grinding process includes: providing a grinding apparatus, the grinding apparatus including an annular grinding section, the grinding section being rotatable along the central axis of the annulus, the grinding section having a first cutting surface and a second cutting surface relative to each other along the central axis, the first cutting surface being perpendicular to the central axis, the second cutting surface being inclined relative to the central axis, the thickness of the grinding section decreasing from the inner diameter to the outer diameter of the annulus, the first cutting surface and the second cutting surface forming a cutting edge at the outer diameter of the annulus; and using the grinding apparatus to grind the initial edge area.

[0020] Accordingly, the present invention also provides a grinding apparatus for wafer hybrid bonding. The grinding apparatus includes an annular grinding section that can rotate along the central axis of the annulus. The grinding section has a first cutting surface and a second cutting surface along the central axis. The first cutting surface is perpendicular to the central axis, and the second cutting surface is inclined relative to the central axis. The thickness of the grinding section decreases from the inner diameter to the outer diameter of the annulus. The first cutting surface and the second cutting surface form a cutting edge at the outer diameter of the annulus.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the wafer hybrid bonding method provided by the present invention, the initial edge region is subjected to a first grinding process from the first surface to the second surface to form a first wafer structure. The first wafer structure includes a functional region and an edge region surrounding the functional region. The edge region has a first grinding port. The sidewall of the first grinding port forms an obtuse angle with the first surface. Since the sidewall of the first grinding port is inclined, it is beneficial to deposit the seed material layer on the sidewall of the first grinding port during the formation of the first conductive structure, thereby improving the thickness and uniformity of the seed material layer on the sidewall of the first grinding port. This reduces the difficulty of the current flowing from the edge region to the surface of the functional region during the electroplating process of forming the first conductive structure, and improves the uniformity of the first conductive structure.

[0023] Furthermore, after the bonding process and before the thinning process, the process includes: performing a second grinding process on the edge region from the second surface towards the first surface, forming a second grinding opening with the first grinding opening. The angle between the sidewall of the second grinding opening and the first surface ranges from 88 degrees to 92 degrees, which helps to reduce edge chipping problems during the thinning process after the bonding of the first wafer structure and the second wafer structure. In addition, to reduce edge chipping problems, this technical solution uses two grinding processes. Compared with grinding only after the bonding process and before the thinning process, the former requires less material of the first conductive structure to be ground in the second grinding process, which helps to reduce the difficulty of the process. Attached Figure Description

[0024] Figures 1 to 6 This is a schematic diagram of the steps in a wafer hybrid bonding method;

[0025] Figures 7 to 17 This is a schematic diagram of the structure of each step of the hybrid bonding method according to an embodiment of the present invention;

[0026] Figures 18 to 20 This is a schematic diagram of the structure of the wafer hybrid bonding grinding apparatus according to an embodiment of the present invention. Detailed Implementation

[0027] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0028] As mentioned in the background section, the performance of hybrid bonding structures formed using existing hybrid bonding technologies urgently needs improvement. This paper will now illustrate and analyze a wafer hybrid bonding method.

[0029] Figures 1 to 6 This is a schematic diagram of the steps in a wafer hybrid bonding method.

[0030] Please refer to Figure 1 An initial first wafer structure is provided, the initial first wafer structure includes an initial functional region I' and an initial edge region II' surrounding the initial functional region I', the initial first wafer structure includes a first wafer 100 and a first dielectric layer 102 located on the first wafer 100, the first wafer 100 has a first surface 100a and a second surface 100b opposite to each other, the first wafer 100 has a first metal layer 101, and the first surface 100a exposes the first metal layer 101.

[0031] Please refer to Figure 2 Grinding is performed on the initial edge region II' from the first surface 100a toward the second surface 100b to form edge region II and grinding port 103 located on edge region II.

[0032] Please refer to Figure 3 After grinding, a second dielectric layer 104 is formed on the surface of the first dielectric layer 102 to form a first wafer structure. The first wafer structure includes a functional region I and an edge region II. The initial functional region I' and the second dielectric layer 104 located on the initial functional region I' are the functional region I. A trench (not shown in the figure) and a via (not shown in the figure) located below the trench and communicating with the trench are formed in the functional region I. The trench is located in the second dielectric layer 104, and the via is located in the first dielectric layer 102, exposing the first metal layer 101. A first conductive material layer 105 is formed in the trench and the via.

[0033] Please refer to Figure 4The first conductive material layer 105 is planarized until the surface of the second dielectric layer 104 is exposed, and a first conductive structure 106 is formed in the trench and via.

[0034] Please refer to Figure 5 A second wafer 200 is provided, the second wafer 200 having a functional surface 200a, a second metal layer 201 within the second wafer 200, and the functional surface 200a exposing the second metal layer 201; a third dielectric layer 202 and a barrier layer 203 located on the surface of the functional surface 200a are formed, the barrier layer 203 and the third dielectric layer 202 having a second conductive structure 204, the second conductive structure 204 also being located on the surface of the second metal layer 201.

[0035] Please continue to refer to this. Figure 5 After grinding, the barrier layer 203 is oriented toward the second dielectric layer 104, and the first conductive structure 165 is oriented toward the second conductive structure 204, and the first wafer 100 and the second wafer 200 are bonded together.

[0036] Please refer to Figure 6 After the bonding process, the first wafer 100 is thinned from the second side 100b.

[0037] In the above-described method for forming wafer hybrid bonding, the width of the grinding aperture 103 is 3 mm and the depth is 150 μm. The grinding process gives functional region I a sidewall A adjacent to edge region II. Sidewall A is perpendicular to edge region II, and the height of sidewall A is the depth of the grinding aperture 103. The thinning process includes mechanical grinding and a mechanical-chemical polishing process following mechanical grinding. The purpose of the grinding process is to reduce the bonding structure of the formed first wafer 100 and second wafer 200, as the bonding ability at the edges is poor, resulting in edge chipping during the thinning process.

[0038] The method for forming the first conductive material layer includes: forming a seed layer (not shown in the figure) on the surface of functional region I, trenches, and vias; and forming a metal material layer (not shown in the figure) on the surface of the seed layer. The seed layer is formed using a physical vapor deposition (PVD) process. Due to the directionality of PVD deposition, the seed layer on the sidewall A surface is relatively thin. The metal material layer is formed using an electroplating process, and the material of the metal material layer is copper. In existing electroplating equipment, the cathode probe needs to be connected at a position 1.3 mm to 1.4 mm away from the wafer edge. Therefore, in this embodiment, the cathode probe T needs to be connected to the surface of edge region II (e.g., ...). Figure 3As shown in the figure. During the formation of the metal material layer, when the current flows through the cathode probe T to the surface of the first dielectric layer 102, it needs to pass through the seed crystal layer on the surface of the sidewall A. However, since the seed crystal layer on the surface of the sidewall A is relatively thin and the height of the sidewall A is relatively large, the seed crystal layer on the surface of the sidewall A has a significant impact on the current, which leads to the phenomenon that the copper material in the through holes and trenches in some areas cannot be filled.

[0039] To reduce the phenomenon of incomplete copper filling in vias and trenches, the following possible improvement methods are adopted: 1) Increase the thickness of the seed material layer to enhance the conductivity of sidewall A, thereby improving the filling of the metal material layer during the electroplating process. However, increasing the seed material layer may cause the vias and trenches on the functional area to be filled prematurely, thus preventing the filling of the metal material layer; 2) Increase the electroplating process time. This will lead to an increase in the thickness of the copper material on the surface of functional area I, making the subsequent mechanical and chemical polishing process more difficult, and it cannot completely solve the problem of incomplete copper filling in some areas; 3) Reduce the depth of the grinding hole 103, thereby reducing the height of sidewall A and reducing the path of current through sidewall A during the electroplating process. However, the subsequent wafer thinning process will cause stress to be transmitted to the wafer edge, increasing the risk of wafer edge breakage; 4) Change the electroplating equipment and move the position of the cathode probe to functional area I. This method requires custom-made equipment from the equipment manufacturer, which is costly and has poor feasibility.

[0040] To address the aforementioned problems, this invention provides a wafer hybrid bonding method and grinding apparatus. A first grinding process is performed on an initial edge region from a first surface towards a second surface to form a first wafer structure. The first wafer structure includes a functional region and an edge region surrounding the functional region. The edge region has a first grinding port. The sidewall of the first grinding port forms an obtuse angle with the first surface. Because the sidewall of the first grinding port is inclined, it facilitates the deposition of a seed material layer on the sidewall of the first grinding port during the formation of the first conductive structure, improving the thickness and uniformity of the seed material layer on the sidewall of the first grinding port. This reduces the difficulty of current flowing from the edge region to the surface of the functional region during the electroplating process of forming the first conductive structure, thereby improving the uniformity of the first conductive structure.

[0041] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 7 to 17 This is a schematic diagram of the structure of each step of the hybrid bonding method according to an embodiment of the present invention.

[0043] Please refer to Figure 7An initial first wafer structure is provided, the initial first wafer structure includes a functional region A and an initial edge region B' surrounding the functional region A. The initial first wafer structure includes a first wafer 300 and a first dielectric layer 301 located on the first wafer 300. The first wafer has opposing first surfaces 300a and second surfaces 300b, and the first dielectric layer 301 is located on the first surface 300a.

[0044] In this embodiment, the first wafer has a first metal layer 302, and the first surface 300a exposes the surface of the first metal layer 302.

[0045] In this embodiment, the first wafer includes a substrate (not shown in the figure); a device layer (not shown in the figure) located on the substrate; and a metal interconnect layer located on the device layer. The metal interconnect layer is electrically connected to the device layer, and the metal interconnect layer includes a first metal layer 302.

[0046] In this embodiment, a first etch stop layer (not shown in the figure) is also provided between the first dielectric layer 301 and the first wafer.

[0047] In this embodiment, the material of the first dielectric layer 301 includes silicon oxide; the material of the first etch stop layer includes silicon nitride.

[0048] Please refer to Figures 8 to 9 , Figure 8 This is a schematic diagram of the first grinding process. Figure 9 This is a schematic diagram of the first wafer structure formed after the first grinding process. The initial edge region B' is subjected to the first grinding process from the first surface 300a to the second surface 300b to form the first wafer structure. The first wafer structure includes a functional region A and an edge region B surrounding the functional region A. The edge region B has a first grinding port 303. The sidewall of the first grinding port 303 forms an obtuse angle α with the first surface 300a.

[0049] The purpose of the first grinding process is to improve the thickness and uniformity of the subsequent seed crystal material layer.

[0050] In this embodiment, the depth h of the first grinding aperture 303 ranges from 32 micrometers to 153 micrometers. In other embodiments, the depth h can be adjusted according to different product process requirements.

[0051] In this embodiment, the angle α between the sidewall of the first grinding port 303 and the first surface 300a is greater than 160 degrees.

[0052] In this embodiment, please refer to the method of the first grinding process. Figures 18 to 20 And continue to refer to Figure 8 .

[0053] Figures 18 to 20 This is a schematic diagram of the structure of the wafer hybrid bonding grinding apparatus according to an embodiment of the present invention.

[0054] Please refer to Figures 18 to 20 , Figure 18 It is a front view. Figure 19 It is a side view. Figure 20 This is a side projection view, showing a grinding apparatus. The grinding apparatus includes an annular grinding section 50, which can rotate along the central axis XX' of the annulus. The grinding section 50 has a first cutting surface 501a and a second cutting surface 501b along the central axis XX'. The first cutting surface 501a is perpendicular to the central axis XX', and the second cutting surface 501b is inclined relative to the central axis XX'. The thickness of the grinding section 50 decreases from the inner diameter to the outer diameter of the annulus. The first cutting surface 501a and the second cutting surface 501b form a cutting edge 502 at the outer diameter of the annulus.

[0055] In this embodiment, the grinding part 50 is a hollow grinding wheel.

[0056] Please continue to refer to this. Figure 8 The initial edge region B' was ground using a grinding device.

[0057] Specifically, in the first grinding process, the grinding part 50 and the cutting edge 502 are placed above the edge region B'. The grinding part 50 rotates along the annular central axis XX', and the first conductive structure rotates along the central axis YY' of the functional region A. The edge region B' is ground in a way that moves from the first surface 300a toward the second surface 300b and from the edge region B' toward the functional region A.

[0058] After the first grinding process, a first conductive structure is formed within the first dielectric layer 301, and the surface of the first conductive structure is exposed on the surface of the first dielectric layer 301. For the method of forming the first conductive structure in this embodiment, please refer to [reference needed]. Figures 10 to 13 .

[0059] Please refer to Figure 10 A first opening 304 is formed in the first dielectric layer 301, and the first opening 304 exposes the surface of the first metal layer 302.

[0060] In this embodiment, before the first opening 304 is formed and after the first grinding opening 303 is formed, a third medium layer 305 is also formed on the first medium layer 301, and the first opening 304 is also located in the third medium layer 305.

[0061] In this embodiment, a third etch stop layer (not shown in the figure) is also provided between the third dielectric layer 305 and the first dielectric layer 301.

[0062] In this embodiment, the material of the third dielectric layer 305 is silicon oxide; the material of the third etch stop layer is silicon nitride.

[0063] In this embodiment, the first opening 304 includes a first groove 304a and a first through hole 304b located below the first groove 304a and communicating with the first groove 304a.

[0064] In this embodiment, the method for forming the first opening 304 includes: etching the third dielectric layer 305 and the first dielectric layer 301, forming a first trench 304a in the third dielectric layer 305, and forming a first through hole 304b in the first dielectric layer 301.

[0065] Please refer to Figure 11 A seed crystal material layer 306 is formed in the first opening 304, the first grinding opening 303 and the surface of functional area A.

[0066] In the above embodiment, the angle α between the sidewall of the first grinding port 303 and the first surface 300a is obtuse, that is, the sidewall of the first grinding port 303 is inclined. Therefore, during the formation of the first conductive structure, it is beneficial to deposit the seed crystal material layer 306 on the sidewall of the first grinding port 303, improve the thickness and uniformity of the seed crystal material layer 306 on the sidewall of the first grinding port 303, and thus reduce the difficulty of the current flowing from the edge region B to the surface of the functional region A during the electroplating process of forming the first conductive structure, and improve the uniformity of the first conductive structure.

[0067] In this embodiment, the thickness of the seed crystal material layer 306 ranges from 700 angstroms to 1500 angstroms. In other embodiments, the thickness of the seed crystal material layer 306 can be adjusted according to actual electrical performance parameters (such as resistance values) requirements.

[0068] In this embodiment, the formation process of the seed crystal material layer 306 includes physical vapor deposition.

[0069] Please refer to Figure 12 A conductive material layer 307 is formed on the seed crystal material layer 306.

[0070] In this embodiment, the method for forming the conductive material layer 307 includes: providing an electroplating machine; placing the cathode probe of the electroplating machine on the sidewall of the edge region B, and placing the surface of the seed crystal material layer 306 in the electrolyte; and passing a direct current between the cathode probe and the anode of the electroplating machine to form the conductive material layer 307.

[0071] Please refer to Figure 13 The conductive material layer 307 is planarized until the top surface of the functional region A is exposed, forming a first conductive structure 308 with the conductive material layer 307 and the seed crystal material layer 306.

[0072] Please refer to Figure 14A second wafer structure is provided, the second wafer structure including a second dielectric layer 402 and a second conductive structure 404 located within the second dielectric layer 402, the surface of the second dielectric layer 402 exposing the surface of the second conductive structure 404.

[0073] In this embodiment, the second wafer structure further includes: a second wafer 400, the second wafer having a functional surface 400a, the second wafer 400 having a second metal layer 401, and the functional surface 400a exposing the second metal layer 401, the second dielectric layer 402 being located on the functional surface 400a, and the second conductive structure 404 being located on the second metal layer 401.

[0074] In this embodiment, a second etch stop layer (not shown in the figure) is also provided between the second dielectric layer 402 and the second wafer 400.

[0075] In this embodiment, the material of the second dielectric layer 402 is silicon oxide; the material of the second etch stop layer is silicon nitride.

[0076] In this embodiment, the second wafer structure further includes a barrier layer 405 located on the second dielectric layer 402, and the second conductive structure 404 is also located within the barrier layer 405, with the barrier layer 405 exposing the surface of the second conductive structure 404.

[0077] In this embodiment, the material of the barrier layer 405 is silicon nitride.

[0078] Please refer to Figure 15 The first wafer structure and the second wafer structure are bonded together so that the second dielectric layer 402 is bonded to the third dielectric layer 305, and the first conductive structure 308 is bonded to the second conductive structure 404.

[0079] Specifically, the first wafer structure and the second wafer structure are bonded together, so that the barrier layer 405 is bonded to the first dielectric layer 305, and the first conductive structure 308 is bonded to the second conductive structure 404.

[0080] At the bonding surface, the dimension of the first conductive structure 308 in the direction along the bonding surface is smaller than the dimension of the second conductive structure 404 in the direction along the bonding surface, and the material of the barrier layer 405 is silicon nitride, which is used to reduce the diffusion of metal ions in the conductive structure into the opposite wafer.

[0081] Subsequently, after the bonding process, the process also includes: thinning the first wafer 300 from the second side 300b.

[0082] In this embodiment, after the bonding process and before the thinning process, please also refer to... Figure 16 .

[0083] Please refer to Figure 16From the second surface 300b toward the first surface 300a, the edge region B is subjected to a second grinding process, forming a second grinding port 309 with the first grinding port 303. The angle β between the sidewall of the second grinding port 309 and the first surface 300a ranges from 88 degrees to 92 degrees.

[0084] The sidewall of the second grinding port 309 is perpendicular or nearly perpendicular to the first surface 300a, which helps to reduce edge chipping during the thinning process after the bonding of the first wafer structure and the second wafer structure. In addition, to reduce edge chipping, this technical solution uses two grinding processes. Compared with grinding only after the bonding process and before the thinning process, the former requires less material of the first conductive structure 308 to be ground in the second grinding process, which helps to reduce the difficulty of the process.

[0085] Please refer to Figure 17 Following the bonding process, the process also includes thinning the first wafer 300 from the second surface 300b.

[0086] The thinning process includes mechanical and chemical polishing.

[0087] Accordingly, embodiments of the present invention also provide a grinding apparatus for wafer hybrid bonding; please refer to [link / reference needed]. Figures 18 to 20 The grinding device includes an annular grinding section 50, which can rotate along the central axis XX' of the annulus. The grinding section 50 has a first cutting surface 501a and a second cutting surface 501b along the central axis XX'. The first cutting surface 501a is perpendicular to the central axis XX', and the second cutting surface 501b is inclined relative to the central axis XX'. The thickness of the grinding section 50 decreases from the inner diameter to the outer diameter of the annulus. The first cutting surface 501a and the second cutting surface 501b form a cutting edge 502 at the outer diameter of the annulus.

[0088] When using the grinding equipment, please continue to refer to the following: Figure 8 In the first grinding process, the grinding part 50 and the cutting edge 502 are placed above the edge region B'. The grinding part 50 rotates along the annular central axis XX', and the first conductive structure rotates along the central axis YY' of the functional region A. The edge region B' is ground in the direction from the first surface 300a to the second surface 300b and from the edge region B' to the functional region A.

[0089] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wafer hybrid bonding method, characterized in that, include: An initial first wafer structure is provided, the initial first wafer structure including a functional region and an initial edge region surrounding the functional region, the initial first wafer structure including a first wafer and a first dielectric layer located on the first wafer, the first wafer having opposing first and second surfaces, the first dielectric layer being located on the first surface; The initial edge region is subjected to a first grinding process from the first surface toward the second surface to form a first wafer structure. The first wafer structure includes the functional region and an edge region surrounding the functional region. The edge region has a first grinding hole, and the sidewall of the first grinding hole forms an obtuse angle with the first surface. A first conductive structure is formed within the first dielectric layer, and the surface of the first dielectric layer exposes the surface of the first conductive structure. A second wafer structure is provided, the second wafer structure including a second dielectric layer and a second conductive structure located within the second dielectric layer, the surface of the second dielectric layer exposing the surface of the second conductive structure; The first wafer structure and the second wafer structure are bonded together, such that the second dielectric layer is bonded to the first dielectric layer, and the first conductive structure is bonded to the second conductive structure.

2. The wafer hybrid bonding method as described in claim 1, characterized in that, The first wafer has a first metal layer, and the first surface exposes the surface of the first metal layer; The method for forming the first conductive structure includes: forming a first opening in the first dielectric layer, the first opening exposing the surface of the first metal layer; forming a seed material layer in the first opening, the first grinding hole and the surface of the functional region; forming a conductive material layer on the seed material layer; planarizing the conductive material layer until the top surface of the functional region is exposed, thereby forming the first conductive structure with the conductive material layer and the seed material layer.

3. The wafer hybrid bonding method as described in claim 2, characterized in that, The thickness of the seed crystal material layer ranges from 700 angstroms to 1500 angstroms.

4. The wafer hybrid bonding method as described in claim 2, characterized in that, The formation process of the seed crystal material layer includes physical vapor deposition.

5. The wafer hybrid bonding method as described in claim 2, characterized in that, The method for forming the conductive material layer includes: providing an electroplating machine; placing a cathode probe of the electroplating machine on the sidewall of the edge region and placing the surface of the seed crystal material layer in an electrolyte; and passing a direct current between the cathode probe and the anode of the electroplating machine to form the conductive material layer.

6. The wafer hybrid bonding method as described in claim 2, characterized in that, The first opening includes a first groove and a first through hole located below and communicating with the first groove.

7. The wafer hybrid bonding method as described in claim 6, characterized in that, Before the first opening is formed and after the first grinding hole is formed, a third medium layer is also formed on the first medium layer, and the first opening is also located within the third medium layer; The method for forming the first opening includes: etching the third dielectric layer and the first dielectric layer, forming the first trench in the third dielectric layer, and forming the first through hole in the first dielectric layer.

8. The wafer hybrid bonding method as described in claim 1, characterized in that, Following the bonding process, the process further includes: thinning the first wafer from the second surface.

9. The wafer hybrid bonding method as described in claim 8, characterized in that, After the bonding process and before the thinning process, the process further includes: performing a second grinding process on the edge region from the second surface toward the first surface, forming a second grinding opening with the first grinding opening, wherein the angle between the sidewall of the second grinding opening and the first surface ranges from 88 degrees to 92 degrees.

10. The wafer hybrid bonding method as described in claim 1, characterized in that, The depth of the first grinding hole ranges from 32 micrometers to 153 micrometers.

11. The wafer hybrid bonding method as described in claim 1, characterized in that, The angle between the sidewall of the first grinding hole and the first surface is greater than 160 degrees.

12. The wafer hybrid bonding method as described in claim 1, characterized in that, The second wafer structure further includes: a second wafer having a functional surface, a second metal layer therein, and the functional surface exposing the second metal layer, a second dielectric layer located on the functional surface, and a second conductive structure located on the second metal layer.

13. The wafer hybrid bonding method as described in claim 12, characterized in that, The second wafer structure further includes a barrier layer located on the second dielectric layer, the second conductive structure being located within the barrier layer, and the barrier layer exposing the surface of the second conductive structure.

14. The wafer hybrid bonding method as described in claim 1, characterized in that, The first grinding process includes: providing a grinding apparatus, the grinding apparatus including an annular grinding section, the grinding section being rotatable along the central axis of the annulus, the grinding section having a first cutting surface and a second cutting surface opposite to each other along the central axis, the first cutting surface being perpendicular to the central axis, the second cutting surface being inclined relative to the central axis, the thickness of the grinding section decreasing from the inner diameter to the outer diameter of the annulus, the first cutting surface and the second cutting surface forming a cutting edge at the outer diameter of the annulus; and using the grinding apparatus to grind the initial edge region.

15. A grinding apparatus for wafer hybrid bonding, characterized in that, The grinding device includes an annular grinding section that can rotate along the central axis of the annulus. The grinding section has a first cutting surface and a second cutting surface along the central axis. The first cutting surface is perpendicular to the central axis, and the second cutting surface is inclined relative to the central axis. The thickness of the grinding section decreases from the inner diameter to the outer diameter of the annulus. The first cutting surface and the second cutting surface form a cutting edge at the outer diameter of the annulus.

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