Digital calibration method, device and analog-to-digital converter in high-precision successive approximation SAR ADC

Abstract

The present invention provides a digital calibration method, device and analog-to-digital converter in a high-precision successive approximation SARADC, by introducing a calibration process in a segmented capacitor array of a lower plate sampling type SARADC, using all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, and sequentially performing actual weight evaluation on the capacitors to be evaluated in order from low to high, and during analog-to-digital conversion, using the actual weight of each segmented capacitor to perform compensation calibration on each segmented capacitor. The present invention can eliminate the influence of capacitor device mismatch caused by random mismatch of semiconductor process on SARADC performance, improve the accuracy of successive approximation SARADC, and thus broaden the applicable scope of SARADC.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a digital calibration method and device in a high-precision successive approximation SAR ADC, and an analog-to-digital converter. Background Art

[0002] At present, my country's semiconductor integrated circuit industry is developing rapidly. In order to meet application needs, various types of chips are being researched and developed. ADC chips, as a bridge to convert analog signals into digital signals in the real world, are increasingly widely used in modern integrated circuit design. In the ADC classification, it is mainly divided into Nyquist ADC and non-Nyquist (oversampling) ADC. Nyquist ADC mainly includes successive approximation SAR ADC, flash ADC and pipeline ADC. Non-Nyquist (oversampling) ADC mainly includes common Δ∑ ADC. Among them, the successive approximation SAR ADC has many advantages such as low power consumption, small area, simple structure, easy to understand, and does not occupy too much power consumption and area in multi-channel applications, so it has become a research hotspot in this field in recent years.

[0003] Among the many indicators of ADC chips, accuracy and linearity are usually the main factors that limit the application scope of ADC chips.

[0004] In semiconductor technology, random mismatch of devices is inevitable. Different from the systematic mismatch of devices, its impact can be solved or reduced by optimizing the layout, such as using common centroids. Random mismatch of devices is mainly caused by uneven bottom etching and uneven oxide layer thickness during semiconductor manufacturing. Based on the above unfavorable factors, SARADCs above 12 bits generally need to be calibrated to improve their accuracy. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a digital calibration method and device in a high-precision successive approximation SAR ADC and an analog-to-digital converter, so as to solve the above-mentioned problems of the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a digital calibration method in a high-precision successive approximation SAR ADC, which is applied to a SAR ADC with 14-bit precision. The method adopts a capacitor array with a segmented structure, and the capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment. The method includes: using all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, and sequentially performing actual weight evaluation on each segmented capacitor to be evaluated in order from low to high; during analog-to-digital conversion, using the actual weight of each segmented capacitor to perform compensation calibration on each segmented capacitor.

[0007] In one embodiment of the present invention, the capacitor array further includes: a bridging capacitor and a compensation capacitor; and the lower board of each segmented capacitor is connected to a power supply or a ground via a one-or-two switch.

[0008] In one embodiment of the present invention, the 14-bit precision SARADC also includes: a comparator, a control switch and a digital logic circuit; wherein the comparator has a negative input terminal connected to the upper plate of the capacitor of the capacitor array, a positive input terminal connected to the common mode voltage, and an output terminal connected to the input terminal of the digital logic circuit; the control switch has two ends connected to the upper plate of the capacitor of the capacitor array and the common mode voltage respectively; the digital logic circuit has an output terminal connected to the lower plate of the capacitor of the capacitor array.

[0009] In one embodiment of the present invention, an actual weight evaluation is performed on each segmented capacitor that needs to be evaluated by executing a sampling control operation; wherein the sampling control operation includes: closing the control switch so that the upper plate of the capacitor of the capacitor array is connected to the common mode voltage; wherein all low-order segmented capacitors of the segmented capacitor that currently needs to be evaluated are connected to the power supply through a two-choice switch, and the segmented capacitor that currently needs to be evaluated and all its high-order segmented capacitors are grounded through a two-choice switch; disconnecting the control switch, and connecting the segmented capacitor that currently needs to be evaluated to the power supply through a two-choice switch; the comparator compares the voltage values ​​of its positive input terminal and negative input terminal, and outputs the comparison result to the digital logic circuit; the digital logic circuit loops back the control instruction to the lower plate of the capacitor based on the comparison result of the comparator, and sequentially controls all low-order segmented capacitors of the segmented capacitor that currently needs to be evaluated to switch the two-choice switch, so that the voltage of the upper plate of the capacitor of the capacitor array approaches the common mode voltage one by one, so as to obtain the actual weight of the segmented capacitor that currently needs to be evaluated.

[0010] In an embodiment of the present invention, all segmented capacitors have at least one redundant capacitor configured according to requirements, and the segmented capacitors other than the redundant capacitors satisfy a binary weight relationship.

[0011] In one embodiment of the present invention, the number of segmented capacitor bits in the MSB segment is not less than the number of capacitor bits in the LSB segment.

[0012] In one embodiment of the present invention, the actual weight of the segmented capacitance obtained by evaluation is stored in a RAM, so that during the digital-to-analog conversion, compensation calibration is performed using the actual weight of each segmented capacitance stored in the RAM.

[0013] In one embodiment of the present invention, a compensation module for operation compensation is set in a SARADC with 14-bit precision before analog-to-digital conversion; the compensation module is set between the lower plate of the capacitor of the capacitor array and the digital logic circuit, so that during the analog-to-digital conversion, based on the actual weight of each bit segmented capacitor, the control signal of the received digital logic circuit is compensated to obtain a compensation control signal, and the compensation control signal is fed back to the lower plate of the capacitor of the capacitor array for calibration compensation.

[0014] In one embodiment of the present invention, a SAR ADC with 14-bit precision is applied, which adopts a capacitor array with a segmented structure, and the capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment, and the method includes: an actual weight evaluation module, which is used to use all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, and perform actual weight evaluation on each segmented capacitor to be evaluated in sequence from low to high; a compensation calibration module, which is connected to the actual weight evaluation module and is used to perform compensation calibration on each segmented capacitor using the actual weight of each segmented capacitor during analog-to-digital conversion.

[0015] To achieve the above-mentioned purpose and other related purposes, the present invention provides a high-precision successive approximation analog-to-digital converter, comprising: a capacitor array with a segmented structure, the capacitor array comprising: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment; wherein the high-precision successive approximation analog-to-digital converter performs digital calibration in the following manner: utilizing all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, and sequentially performing actual weight evaluation on each segmented capacitor to be evaluated in order from low to high; and during analog-to-digital conversion, utilizing the actual weight of each segmented capacitor to perform compensation calibration on each segmented capacitor.

[0016] As described above, the present invention is a digital calibration method, device and analog-to-digital converter in a high-precision successive approximation SARADC, which has the following beneficial effects: the present invention introduces a calibration process in the segmented capacitor array of the lower plate sampling type SARADC, utilizes all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, and sequentially performs actual weight evaluation on each segmented capacitor to be evaluated in order from low to high, and during the analog-to-digital conversion, utilizes the actual weight of each segmented capacitor to perform compensation calibration on each segmented capacitor. The present invention can eliminate the influence of capacitor device mismatch caused by random mismatch of semiconductor process on the performance of SARADC, improve the accuracy of successive approximation SARADC, and thus broaden the applicable scope of SARADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of a digital calibration method in a high-precision successive approximation SAR ADC according to an embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram of the structure of a SAR ADC with 14-bit precision in one embodiment of the present invention.

[0019] Figure 3 Shown is a diagram showing the connection relationship between the upper and lower plates of a SAR ADC with 14-bit precision in one embodiment of the present invention.

[0020] Figure 4 Shown is a diagram showing the connection relationship between the upper and lower plates of a SAR ADC with 14-bit precision in one embodiment of the present invention.

[0021] Figure 5 It is a schematic diagram of the structure of a SAR ADC with 14-bit precision in one embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram showing compensation calibration of a SAR ADC with 14-bit precision in one embodiment of the present invention.

[0023] Figure 7 Shown is a simulation result diagram of the performance indicators without calibration in one embodiment of the present invention.

[0024] Figure 8 A diagram showing simulation results of performance indicators for calibration in one embodiment of the present invention.

[0025] Fig. 9 It is a structural schematic diagram of a digital calibration device in a high-precision successive approximation SAR ADC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0028] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0029] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0030] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0031] The invention discloses a digital calibration method in a high-precision successive approximation SAR ADC. The calibration process is introduced into the segmented capacitor array of the lower plate sampling type SAR ADC. All low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array are used to perform actual weight evaluation on each segmented capacitor to be evaluated in order from low to high. During analog-to-digital conversion, the actual weight of each segmented capacitor is used to perform compensation calibration on each segmented capacitor. The invention can eliminate the influence of capacitor device mismatch caused by random mismatch of semiconductor process on the performance of SAR ADC, improve the accuracy of successive approximation SAR ADC, and thus broaden the applicable scope of SAR ADC.

[0032] At the same time, in order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution in the embodiment of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the invention.

[0033] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0034] <1> SARADC (SAR type ADC, successive approximation analog-to-digital converter) is a Nyquist type converter. The conversion object is the sampled value of the analog signal at the sampling moment or the previous few moments, and the result is output immediately. The SARADC used in the present invention is a high-precision successive approximation analog-to-digital converter of the bottom plate sampling type.

[0035] <2> MSB (Most Significant Bit);

[0036] <3> LSB (Least Significant Bit);

[0037] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0038] like Figure 1 A schematic flow chart showing a digital calibration method in a high-precision successive approximation SAR ADC according to an embodiment of the present invention is shown.

[0039] In the SAR ADC with 14-bit precision, in the DAC structure, the capacitor array DAC has better temperature characteristics and linearity than the resistor array DAC, so the capacitor array DAC structure is adopted; in order to achieve 14-bit precision, if the traditional binary structure is adopted, the ratio of the highest-bit capacitor to the lowest-bit capacitor will be greatly different, and the larger total capacitance value means a larger area and higher power consumption. Therefore, the present invention adopts a capacitor array with a segmented structure, and divides the capacitor array into two segments, respectively called the LSB segment and the MSB segment, and sets a plurality of segmented capacitors in the LSB segment and the MSB segment from low to high.

[0040] The method comprises:

[0041] Step S11: using all low-order segmented capacitors of each segmented capacitor to be evaluated in the capacitor array, perform actual weight evaluation on each segmented capacitor to be evaluated in order from low to high.

[0042] In order to better describe the implementation of the digital calibration method in a high-precision successive approximation SAR ADC, the specific structure of the 14-bit precision SAR ADC used in the present invention is first described in conjunction with the following drawings and embodiments.

[0043] In one embodiment, if Figure 2 , 14-bit precision SARADC includes:

[0044] The capacitor array of the segmented structure includes: a plurality of segmented capacitors C0-C15, a bridge capacitor Cb and a compensation capacitor Cc arranged in sequence from low to high in the LSB segment and the MSB segment; the capacitor lower plates of each segmented capacitor C0-C15 are connected to the power supply or the ground through a one-to-two switch;

[0045] It should be noted that Figure 2Taking a 14-bit SAR ADC composed of 16-bit capacitors as an example, the LSB segment consists of three-bit capacitors, labeled C0, C1 and C2, and the MSB segment capacitors consist of thirteen-bit capacitors, labeled C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14 and C15 in sequence; preferably, because the parasitic capacitance of the upper plate to the ground in the LSB segment directly affects the linearity of the ADC, the LSB is not suitable for using a larger number of bits, so the number of segmented capacitors in the MSB segment is not less than the number of capacitors in the LSB segment.

[0046] A comparator 101, whose negative input terminal is connected to the upper plate of the capacitor of the capacitor array, whose positive input terminal is connected to the common mode voltage VCM, and whose output terminal is connected to the input terminal of the digital logic circuit 102; the comparator 101 is used to compare the voltage values ​​of its positive input terminal and negative input terminal, and output the comparison result to the digital logic circuit 102;

[0047] The control switch S1 has two ends connected to the upper plate of the capacitor of the capacitor array and the common mode voltage VCM respectively; specifically, when the control switch S1 is closed, the upper plate of the capacitor is connected to the common mode voltage VCM; when the control switch S1 is opened, the upper plate of the capacitor is disconnected from the common mode voltage VCM;

[0048] The digital logic circuit 102 has an output terminal connected to the capacitor bottom plate of the capacitor array. The digital logic circuit 102 has an initial output control signal, and then feeds back a control signal to the capacitor bottom plate based on the comparison result of the comparator 101 to switch the corresponding segment capacitor between two switches.

[0049] In a preferred embodiment, all segmented capacitors have at least one redundant bit capacitor set according to requirements, and the segmented capacitors other than the redundant bit satisfy a binary weight relationship;

[0050] like Figure 2 , the 14-bit SARADC is composed of 16-bit capacitors because two redundant bits are inserted in the middle for use in capacitor array mismatch calibration. If the lowest bit C0 has a unit capacitance Cu, in order to satisfy the binary ratio, the capacitances of C1 and C2 in the LSB segment are 2*Cu and 4*Cu respectively, the capacitance of the compensation capacitor Cc is 7*Cu, the capacitance of the bridge capacitor Cb is 2*Cu, and the capacitances of the high-order MSB segment C3~C15 are Cu, 2*Cu, 2*Cu (redundant bit), 4*Cu, 8*Cu, 16*Cu, 32Cu, 32Cu (redundant bit), 64Cu, 128Cu, 256Cu, 512Cu and 1024Cu respectively. Among them, the capacitances corresponding to C4 and C9 are redundant bits inserted in the CDAC capacitor array, and the weights corresponding to C0~C15 are:

[0051] Table 1: Capacitance and ideal weight relationship

[0052]

[0053] Among them, C4 and C9 are inserted redundant capacitors. Except C4 and C9, the remaining capacitors C0 to C15 satisfy the binary weight relationship.

[0054] As shown in Table 1, the weights of the capacitors of the sub-capacitor arrays C0 to C5 are 1, 2, 4, 8, 16, and 16, respectively. The weights of C4 and C5 are the same, both of which are 16. C4 is an inserted redundant bit. Only by inserting reasonable redundant bits can a certain design space be left to ensure that the low-order sub-capacitor array can reasonably evaluate the actual weight of the segmented capacitor C6.

[0055] The invention uses a method of using low-order capacitors to calibrate high-order capacitors to find out their true weights to ultimately achieve calibration of the capacitor array. Because as the binary relationship of the capacitor array increases, the capacitance value becomes larger and larger, and the corresponding capacitor mismatch value also becomes larger and larger. Compared with the low-order capacitors, the high-order capacitors have a more significant impact on the ADC linearity. Assuming that the impact of the low-order capacitor mismatch on the ADC linearity is controlled at a lower level, then using low-order capacitors to calibrate high-order capacitors to find out their true weights is feasible. In addition, the method of using low-order capacitors to calibrate high-order capacitors also saves the area waste caused by the traditional calibration method that requires an additional calibration capacitor array to calibrate the main capacitor array.

[0056] In order to better describe step S11, the implementation principle of using low-order capacitance to calibrate high-order capacitance to find out its true weight is first explained.

[0057] like Figure 2 If C0~C5 are capacitors that do not need to be calibrated separately, use C0~C5 to calibrate their high positions. First, use the C0~C5 sub-capacitor array to evaluate the actual weight of capacitor C6. After obtaining the weight of C6, use the C0~C6 sub-capacitor array to evaluate the actual weight of capacitor C7. After obtaining the weight of C7, use the C0~C7 sub-capacitor array to evaluate the actual weight of capacitor C8. And so on, until finally using the C0~C14 sub-capacitor array to evaluate the actual weight of capacitor C15.

[0058] When the real capacitance of C6 capacitor is evaluated by using C0~C5 sub-capacitor array, in the sampling phase, S1 is closed, the upper plate of the capacitor is connected to the common mode voltage VCM, the lower plates of C6 and capacitors higher than C6 (here C6~C15) are grounded, and the lower plates of capacitors lower than C6 are connected to the power supply through a two-choice switch, which is represented by VREFP. In this way, the total charge of the upper plate of the capacitor of the capacitor array is:

[0059]

[0060] At the sampling moment, the switch S1 connecting the upper plate of the capacitor to VCM is first disconnected, and then the lower plate of the C6 capacitor is switched from ground to VREFP through a two-choice switch. The C0-C5 capacitors are still connected to VREFP. At the moment when the control switch S1 is disconnected, the charge on the upper plate is conserved. Assuming that the voltage on the upper plate of the capacitor is VX at this time, the total charge on the upper plate of the capacitor can be described as:

[0061]

[0062] From the conservation of charge on the upper plate, we know that Q1 = Q2. Simplifying, the voltage VX on the upper plate of the capacitor is:

[0063]

[0064] in,

[0065]

[0066] It can be seen that a voltage component is superimposed on the upper plate of the capacitor on the basis of the common mode voltage VCM:

[0067]

[0068] The value of the voltage component depends on the real weight of the capacitor C6 to be evaluated, so the real weight of C6 can be obtained.

[0069] Therefore, all low-order segmented capacitors of the segmented capacitors that need to be evaluated in the capacitor array can be used to perform actual weight evaluation on the segmented capacitors that need to be evaluated in order from low to high.

[0070] In one embodiment, based on the above principle, the present invention performs actual weight evaluation on each segmented capacitor that needs to be evaluated by executing a sampling control operation; and after the actual weight evaluation of one segmented capacitor is completed, the actual weight evaluation is performed on the next segmented capacitor, until the actual weight evaluation of the highest segmented capacitor is completed, and the process ends.

[0071] The sampling control operation is described by evaluating the actual weight of the capacitor C6, including:

[0072] like Figure 3 , close the control switch S1 so that the upper plate of the capacitor of the capacitor array is connected to the common mode voltage VCM; wherein, all the low-order segment capacitors C0-C5 of the segment capacitor C6 currently to be evaluated are connected to the power supply through the two-choice switch, and the segment capacitor C6 currently to be evaluated and all its high-order segment capacitors C7-C15 are grounded through the two-choice switch;

[0073] like Figure 4, disconnect the control switch S1, and connect the segment capacitor C6 currently to be evaluated to the power supply through the one-or-the-other switch;

[0074] The comparator 101 compares the voltage values ​​at its positive input terminal and negative input terminal, and outputs the comparison result to the digital logic circuit 102;

[0075] The digital logic circuit 102 loops back the control instruction to the lower plate of the capacitor based on the comparison result of the comparator 101, and sequentially controls all the low-order segmented capacitors C0-C5 to switch between two-to-one switches, so that the voltage of the upper plate of the capacitor array gradually approaches the common mode voltage VCM, so as to obtain the actual weight of the segmented capacitor C6 that needs to be evaluated currently.

[0076] Specifically, the digital logic circuit 102 initially outputs Dcal<5:0>=100000 and is sequentially connected to the lower plates of capacitors C5 to C0. The comparator outputs a comparison result through the voltage values ​​at the positive and negative terminals of the comparator. The digital logic circuit determines the highest bit Dcal of Dcal<5:0> based on the comparison result. <5> =1 is to keep or set to zero; if the comparison result is positive, Dcal <5> The high bit is kept as 1. Then the second high bit Dcal of Dcal<5:0> is <4> Set high, that is, Dcal<5:0> outputs 11 0000; if the comparison result is negative, Dcal <5> The high bit is set from 1 to 0, and then the second high bit Dcal of Dcal<5:0> is set to <4> Set high, that is, Dcal<5:0> outputs 010000; this cycle is repeated, and all low-order segmented capacitors C0-C5 are controlled to switch between two-choice switches in turn, so that the voltage of the upper plate of the capacitor array approaches the VCM voltage one by one until the conversion is completed. After such logic, the real weight of the C6 capacitor is evaluated through the C0~C5 sub-capacitor array.

[0077] At this point, the actual weight of C6 is obtained according to the method described above. When evaluating the actual weight of C7 capacitor, the capacitor array C0~C6 with lower bits than C7 is used for evaluation; the real weight of C6 has been obtained by the above method, and the initial output of the digital logic circuit Dcal<6:0>=100 0000 is connected to the lower plates of C6~C0 capacitors in turn. Through the voltage values ​​of the positive and negative terminals of the comparator, the comparator outputs the comparison result, and the digital logic circuit determines the highest bit Dcal of Dcal<6:0> according to the comparison result. <6> =1 is to keep or set to zero. If the comparison result is positive, Dcal <6> The high bit is kept as 1. Then the second high bit Dcal of Dcal<6:0> is set <5> Set high, that is, Dcal<6:0> outputs 110 0000. If the comparison result is negative, Dcal <6> The high bit is set from 1 to 0, and then the second high bit Dcal of Dcal<6:0> is set to <5> Set high, that is, Dcal<6:0> outputs 010 0000, and this cycle is repeated, so that the voltage of the upper plate of the capacitor array gradually approaches the VCM voltage until the conversion is completed. After such logic, the real weight of the C7 capacitor is evaluated through the C0~C6 sub-capacitor array.

[0078] The same method can be used to gradually evaluate the actual weights of the high-level capacitors C8 to C15.

[0079] Because C0~C5 are at a lower position, the impact caused by their process mismatch is relatively small. Therefore, it is feasible to use C0~C5 capacitors to sequentially evaluate the remaining high-position capacitors in the capacitor array. Compared with the traditional method that requires an additional calibration capacitor array to calibrate the main capacitor array, it can save a considerable part of the layout area. First, use C0~C5 to evaluate the actual weight of the C6 capacitor. After obtaining the actual weight of the C6 capacitor, the C6 capacitor and the C0~C5 capacitors are formed into a new sub-capacitor array, and the new sub-capacitor array composed of C0~C6 is used to evaluate the actual weight of the C7 capacitor (that is, the actual weight of the C6 capacitor and the weight of the C0~C5 capacitor are used to evaluate the actual weight of the C7 capacitor). After obtaining the actual weight of the C7 capacitor, the C7 capacitor and C0~C6 are used to form a new sub-capacitor array, and the new sub-capacitor array composed of C0~C7 is used to evaluate the actual weight of the C8 capacitor (that is, the actual weight of the C7 capacitor, the actual weight of the C6 capacitor and the capacitance weight of C0~C5 are used to evaluate the weight of the C8 capacitor). The actual capacitance weight search process of the remaining higher-position capacitors C9~C15 is similar. It can be seen that this method of weight estimation is simple and intuitive, with very little hardware overhead, and only requires some digital circuits to control the input switches of the capacitors.

[0080] Step S12: During analog-to-digital conversion, compensation calibration is performed on each segment capacitor using the actual weight of each segment capacitor.

[0081] In one embodiment, the actual weight of the segment capacitance obtained by evaluation is stored in a RAM, so that during the digital-to-analog conversion, compensation calibration is performed using the actual weight of each segment capacitance stored in the RAM.

[0082] For example, after the actual weight evaluation of capacitors C6 to C15 is completed, they are stored in RAM. During the actual conversion of the ADC, when the corresponding bits are converted, the values ​​obtained in the weight evaluation process need to be integrated into the actual conversion process of the ADC using a certain calculation method, so that it can compensate and calibrate the mismatch of the capacitor array, thereby improving the accuracy of the SAR ADC.

[0083] In one embodiment, if Figure 5 Before performing analog-to-digital conversion, a compensation module 103 for operation compensation is set in the SARADC with 14-bit precision; the compensation module 103 is set between the lower plate of the capacitor of the capacitor array and the digital logic circuit 102, so that during the analog-to-digital conversion, based on the actual weight of each bit segmented capacitor, the control signal of the received digital logic circuit is compensated to obtain a compensation control signal, and the compensation control signal is fed back to the lower plate of the capacitor of the capacitor array for calibration compensation.

[0084] Specifically, since the successive approximation SAR ADC in the present invention performs sampling in a manner that the lower plate samples, in the sampling phase, the upper plate of the capacitor array is connected to the common mode level VCM through a switch, and the lower plate of the capacitor is connected to the input signal. At the sampling moment, the upper plate of the capacitor is first disconnected from the common mode level. At the moment of disconnection, the upper plate of the capacitor becomes a high resistance point. Therefore, the charge on the upper plate of the capacitor array is conserved. After a short delay is achieved through a non-overlapping clock, the lower plate of the capacitor is disconnected from the input signal. In this way, the linearity of the sampling process can be improved.

[0085] Next, the digital logic circuit 102 outputs a digital signal D<15:0>=1000 0000 0000 0000 to the lower plate of the entire capacitor array. Ideally, because of charge conservation, a change in the voltage of the lower plate of the capacitor array will cause a change in the voltage of the upper plate of the capacitor array, and the amount of change is directly related to the ideal capacitor weight.

[0086] If there is mismatch in the capacitor array, the compensation module 103 needs to compensate the digital signal D<15:0>, and after compensation, the digital signal D<15:0> is X<15:0>, and then X<15:0> is connected to the lower plate of the capacitor array.

[0087] If the actual weight of the highest capacitor in the capacitor array is lower than its ideal weight by one weight, the digital logic circuit 102 outputs D<15:0>=1000 0000 0000 0000, and the compensation module 103 performs calculation compensation based on the actual weight of the capacitor, and X<15:0> outputs 1000 0000 0000 0001 to the lower plate of the capacitor array. Figure 6 In this way, the voltage change generated by the upper plate of the capacitor is consistent with the voltage change value generated under ideal conditions, achieving the purpose of compensation.

[0088] If the actual weight of the highest-order capacitor in the capacitor array is one weight higher than its ideal weight, the digital logic circuit 102 outputs D<15:0>=1000 0000 0000 0000. After the compensation module 103 performs calculation compensation based on the actual weight of the capacitor, X<15:0> outputs 0000 0000 0000 0001 to the lower plate of the capacitor array. In this way, the voltage change generated by the upper plate of the capacitor is consistent with the voltage change value generated under ideal conditions, thereby achieving the purpose of compensation.

[0089] If the actual weight of the highest capacitor in the capacitor array is equal to its ideal weight, the digital logic circuit 102 outputs D<15:0>=1000 0000 0000 0000. After the compensation module 103 performs calculation compensation based on the actual weight of the capacitor, X<15:0>=D<15:0>=1000 0000 0000 0000 to the lower plate of the capacitor array. In this way, the voltage change generated by the upper plate of the capacitor is consistent with the voltage change value generated under ideal conditions, thereby achieving the purpose of compensation.

[0090] After the digital calibration method of the high-precision successive approximation SAR ADC of the present invention is used for simulation operation, the performance indicators after calibration are as follows: Figure 7 as well as Figure 8As shown, under the premise of capacitor mismatch, a capacitor mismatch of +5‰ is introduced in the highest capacitor, and a capacitor mismatch of -5‰ is introduced in the remaining bits, and no calibration is performed. The simulation results show that the SINAD is 49db, the ENOB is 7.85bit, and the SFDR is 52.3db; similarly, under the premise of capacitor mismatch, a capacitor mismatch of +5‰ is introduced in the highest capacitor, and a capacitor mismatch of -5‰ is introduced in the remaining bits. After calibration, the simulation results show that the SINAD reaches 84.83db, the ENOB reaches 13.8bit, and the SFDR reaches 102.75db. Compared with the results with mismatch but no calibration, it is obvious that the SINAD is improved from 49db to 84.83db, the ENOB is improved from 7.85bit to 13.8bit, and the SFDR is improved from 52.3db to 102.75db. It can be seen that through the present invention, the key indicator performance of ADC is significantly improved. That is, by introducing the digital calibration algorithm and integrating it into the actual conversion process of the ADC, the capacitor mismatch can be calibrated, which can significantly improve the key performance indicators of SAR ADC, such as SINAD, ENOB and SFDR.

[0091] Therefore, the present invention utilizes the characteristic that the low-order capacitor mismatch has little effect on the performance of SARADC, making it possible to use low-order capacitors to evaluate the actual weight of high-order capacitors. By using a segmented capacitor array, the capacitance value can be reduced, thereby reducing the layout area and power consumption, etc. Two binary redundancies are inserted on the basis of the binary capacitor array, so that the sum of the low-order capacitors is always greater than the capacitor to be calibrated, ensuring that the actual weight of the capacitor to be calibrated can be evaluated by the low-order capacitor. Through this process, the actual weight of each capacitor in the entire capacitor array can be gradually evaluated, and the evaluated actual weight of the capacitor is stored in the RAM. During the analog-to-digital conversion of the actual ADC, the actual weight of the capacitor is taken out when each bit is converted, and it is compensated to the ADC conversion device, thereby achieving the purpose of calibration. It can be seen that this method of weight estimation is simple and intuitive, with very little hardware overhead, and only some digital circuits are needed to control the input switch of the capacitor. This method can improve the conversion accuracy, linearity and other key performance indicators of SARADC. And then expand the applicable scope of ADC chips and enhance the competitiveness of chip module products.

[0092] Similar to the principle of the above embodiment, the present invention provides a digital calibration device in a high-precision successive approximation SAR ADC.

[0093] The following provides specific embodiments in conjunction with the accompanying drawings:

[0094] like Fig. 9 A structural schematic diagram of a digital calibration device in a high-precision successive approximation SAR ADC according to an embodiment of the present invention is shown.

[0095] A SAR ADC for 14-bit precision is applied, which adopts a capacitor array with a segmented structure, and the capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment; and the device can be implemented by a state machine, and the device includes:

[0096] The actual weight evaluation module 1 is used to use all the low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array to perform actual weight evaluation on each segmented capacitor that needs to be evaluated in order from low to high;

[0097] The compensation calibration module 2 is connected to the actual weight evaluation module 1 and is used to perform compensation calibration on each segment capacitor using the actual weight of each segment capacitor during analog-to-digital conversion.

[0098] Since the implementation principle of the digital calibration device in the high-precision successive approximation SAR ADC has been described in the above embodiments, it will not be repeated here.

[0099] In one embodiment, the capacitor array further includes: a bridging capacitor and a compensation capacitor; and the lower board of each segmented capacitor is connected to a power supply or a ground via a one-or-two switch.

[0100] In one embodiment, the 14-bit precision SAR ADC also includes: a comparator, a control switch and a digital logic circuit; wherein the comparator has a negative input terminal connected to the upper plate of the capacitor of the capacitor array, a positive input terminal connected to the common mode voltage, and an output terminal connected to the input terminal of the digital logic circuit; the control switch has two ends respectively connected to the upper plate of the capacitor of the capacitor array and the common mode voltage; the digital logic circuit has an output terminal connected to the lower plate of the capacitor of the capacitor array.

[0101] In one embodiment, the actual weight evaluation is performed on each segmented capacitor to be evaluated by executing a sampling control operation; wherein the sampling control operation includes: closing the control switch so that the upper plate of the capacitor of the capacitor array is connected to the common mode voltage; wherein all the low-order segmented capacitors of the segmented capacitor currently to be evaluated are connected to the power supply through a two-choice switch, and the segmented capacitor currently to be evaluated and all its high-order segmented capacitors are grounded through a two-choice switch; disconnecting the control switch, and connecting the segmented capacitor currently to be evaluated to the power supply through a two-choice switch; the comparator compares the voltage values ​​of its positive input terminal and negative input terminal, and outputs the comparison result to the digital logic circuit; the digital logic circuit loops back the control instruction to the lower plate of the capacitor based on the comparison result of the comparator, and sequentially controls all the low-order segmented capacitors of the segmented capacitor currently to switch the two-choice switch, so that the voltage of the upper plate of the capacitor of the capacitor array approaches the common mode voltage one by one, so as to obtain the actual weight of the segmented capacitor currently to be evaluated.

[0102] In one embodiment, all segment capacitors have at least one redundant capacitor configured according to requirements, and the segment capacitors other than the redundant capacitors satisfy a binary weight relationship.

[0103] In one embodiment, the number of segmented capacitor bits in the MSB segment is not less than the number of capacitor bits in the LSB segment.

[0104] In one embodiment, the actual weight of the segment capacitance obtained by evaluation is stored in a RAM, so that during the digital-to-analog conversion, compensation calibration is performed using the actual weight of each segment capacitance stored in the RAM.

[0105] In one embodiment, a compensation module for operation compensation is set in a SARADC with 14-bit precision before analog-to-digital conversion; the compensation module is set between the lower plate of the capacitor of the capacitor array and the digital logic circuit, so that during the analog-to-digital conversion, based on the actual weight of each bit segmented capacitor, the control signal of the received digital logic circuit is compensated to obtain a compensation control signal, and the compensation control signal is fed back to the lower plate of the capacitor of the capacitor array for calibration compensation.

[0106] like Figure 2 , showing a schematic structural diagram of a high-precision successive approximation analog-to-digital converter in an embodiment of the present invention.

[0107] The high-precision successive approximation analog-to-digital converter is the SARADC with 14-bit precision in the above embodiment, which adopts a capacitor array with a segmented structure, and the capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment;

[0108] Among them, the method of digital calibration of the high-precision successive approximation analog-to-digital converter includes: using all low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array, and evaluating the actual weight of each segmented capacitor that needs to be evaluated in order from low to high; during the analog-to-digital conversion, using the actual weight of each segmented capacitor to compensate and calibrate each segmented capacitor.

[0109] Since the implementation principle of the high-precision successive approximation analog-to-digital converter has been described in the aforementioned embodiment, it will not be repeated here.

[0110] In summary, the digital calibration method, device and analog-to-digital converter in the high-precision successive approximation SAR ADC of the present invention introduce a calibration process in the segmented capacitor array of the lower plate sampling type SAR ADC, and use all the low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array to perform actual weight evaluation on each segmented capacitor that needs to be evaluated in order from low to high, and during the analog-to-digital conversion, use the actual weight of each segmented capacitor to compensate and calibrate each segmented capacitor. The present invention can eliminate the influence of the mismatch of capacitor devices caused by random mismatch of semiconductor processes on the performance of SAR ADC, improve the accuracy of the successive approximation SAR ADC, and thus broaden the applicable scope of SAR ADC. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A digital calibration method in a high-precision successive approximation SAR ADC, characterized in that: A SAR ADC with 14-bit precision is applied, which uses a capacitor array with a segmented structure. The capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment. The method includes: Using all low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array, actual weight evaluation is performed on each segmented capacitor that needs to be evaluated in order from low to high; During analog-to-digital conversion, the actual weight of each segment capacitor is used to perform compensation calibration on each segment capacitor; Among them, the SARADC with 14-bit precision is composed of 16-bit segmented capacitors, the LSB segment is composed of three-bit segmented capacitors, and the MSB segment capacitors are composed of thirteen-bit segmented capacitors; the MSB segment includes two redundant bit capacitors, so that the segmented capacitors except the redundant bit capacitors satisfy the binary weight relationship, so that the sum of the low-bit capacitors is always greater than the capacitor to be calibrated, ensuring that the actual weight of the capacitor to be calibrated can be evaluated using the low-bit capacitors; the number of segmented capacitor bits in the MSB segment is not less than the number of capacitor bits in the LSB segment; The capacitor array further includes: a bridging capacitor and a compensation capacitor; and the lower board of each segmented capacitor is connected to a power supply or a ground via a one-or-two switch.

2. The digital calibration method in the high-precision successive approximation SAR ADC according to claim 1, characterized in that: The 14-bit precision SARADC also includes: a comparator, a control switch and a digital logic circuit; Wherein, the comparator has a negative input terminal connected to the upper plate of the capacitor of the capacitor array, a positive input terminal connected to the common mode voltage, and an output terminal connected to the input terminal of the digital logic circuit; The control switch has two ends connected to the upper plate of the capacitor of the capacitor array and the common mode voltage respectively; The output end of the digital logic circuit is connected to the lower plate of the capacitor of the capacitor array.

3. The digital calibration method in the high-precision successive approximation SAR ADC according to claim 2, characterized in that: Performing actual weight evaluation on each segment capacitance that needs to be evaluated by performing a sampling control operation; Wherein, the sampling control operation includes: The control switch is closed so that the upper plate of the capacitor of the capacitor array is connected to the common mode voltage; wherein all the low-order segment capacitors of the segment capacitor currently to be evaluated are connected to the power supply through the two-choice switch, and the segment capacitor currently to be evaluated and all its high-order segment capacitors are grounded through the two-choice switch; Disconnect the control switch, and connect the segmented capacitor that currently needs to be evaluated to the power supply through the one-to-one switch; The comparator compares the voltage values ​​of its positive input terminal and negative input terminal, and outputs the comparison result to the digital logic circuit; The digital logic circuit loops back control instructions to the lower plate of the capacitor based on the comparison result of the comparator, and sequentially controls all low-order segmented capacitors of the segmented capacitor that currently needs to be evaluated to switch between two-to-one switches, so that the voltage of the upper plate of the capacitor of the capacitor array gradually approaches the common mode voltage, so as to obtain the actual weight of the segmented capacitor that currently needs to be evaluated.

4. The digital calibration method in the high-precision successive approximation SAR ADC according to claim 1, characterized in that: The actual weight of the segment capacitance obtained by evaluation is stored in the RAM, so that during the digital-to-analog conversion, compensation calibration is performed using the actual weight of each segment capacitance stored in the RAM.

5. The digital calibration method in the high-precision successive approximation SAR ADC according to claim 3, characterized in that: Before performing analog-to-digital conversion, a compensation module for operation compensation is set in the 14-bit precision SARADC; The compensation module is arranged between the lower plate of the capacitor of the capacitor array and the digital logic circuit, so as to compensate the control signal of the received digital logic circuit based on the actual weight of each bit segmented capacitor during analog-to-digital conversion to obtain a compensation control signal, and feed the compensation control signal back to the lower plate of the capacitor of the capacitor array for calibration compensation.

6. A digital calibration device in a high-precision successive approximation SAR ADC, characterized in that: The device is applied to a SAR ADC with 14-bit precision, which adopts a capacitor array with a segmented structure. The capacitor array includes: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment. The device includes: An actual weight evaluation module is used to use all low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array to perform actual weight evaluation on each segmented capacitor that needs to be evaluated in order from low to high; A compensation calibration module, connected to the actual weight evaluation module, for performing compensation calibration on each segment capacitor using the actual weight of each segment capacitor during analog-to-digital conversion; Among them, the SARADC with 14-bit precision is composed of 16-bit segmented capacitors, the LSB segment is composed of three-bit segmented capacitors, and the MSB segment capacitors are composed of thirteen-bit segmented capacitors; the MSB segment includes two redundant bit capacitors, so that the segmented capacitors except the redundant bit capacitors satisfy the binary weight relationship, so that the sum of the low-bit capacitors is always greater than the capacitor to be calibrated, ensuring that the actual weight of the capacitor to be calibrated can be evaluated using the low-bit capacitors; the number of segmented capacitor bits in the MSB segment is not less than the number of capacitor bits in the LSB segment; The capacitor array further includes: a bridging capacitor and a compensation capacitor; and the lower board of each segmented capacitor is connected to a power supply or a ground via a one-or-two switch.

7. A high-precision successive approximation analog-to-digital converter, characterized in that: include: A capacitor array with a segmented structure, the capacitor array comprises: a plurality of segmented capacitors arranged in sequence from low to high in the LSB segment and the MSB segment; the capacitor array further comprises: a bridging capacitor and a compensation capacitor; and the lower board of each segmented capacitor is connected to a power supply or a ground through a one-or-two switch; The high-precision successive approximation analog-to-digital converter adopts a SARADC with a 14-bit precision, and is composed of 16-bit segmented capacitors, wherein the LSB segment is composed of three-bit segmented capacitors, and the MSB segment capacitors are composed of thirteen-bit segmented capacitors; the MSB segment includes two redundant bit capacitors, so that the segmented capacitors other than the redundant bit capacitors satisfy a binary weight relationship, so that the sum of the low-bit capacitors is always greater than the capacitor to be calibrated, ensuring that the actual weight of the capacitor to be calibrated can be evaluated using the low-bit capacitors; the number of segmented capacitor bits in the MSB segment is not less than the number of capacitor bits in the LSB segment; The high-precision successive approximation analog-to-digital converter uses all low-order segmented capacitors of each segmented capacitor that needs to be evaluated in the capacitor array, and performs actual weight evaluation on each segmented capacitor that needs to be evaluated in order from low to high. During analog-to-digital conversion, each segment capacitor is compensated and calibrated using the actual weight of each segment capacitor.

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