Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductor, and is used for solving the technical problem that the isolation side wall is easy to be damaged. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of bit lines which are arranged at intervals along a first direction on the substrate, wherein the width of the top of each bit line is greater than the width of the bottom of the bit line; forming an initial isolation side wall which covers each bit line, respectively, wherein the initial isolation side wall comprises a first initial isolation layer, a second isolation layer and a third initial isolation layer which are arranged in layers, the first initial isolation layer covers the bit line, the second isolation layer is located between the first initial isolation layer and the third initial isolation layer, and the top surface of the second isolation layer is flush with the first step surface; and removing the initial isolation side wall on the substrate between adjacent bit lines, wherein the remaining initial isolation side wall constitutes an isolation side wall. The present disclosure is used for preventing the formation of a gap in the isolation side wall, and improves the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM typically consists of multiple repeating storage cells, each containing a transistor and a capacitor. The transistor's gate is connected to the word line, its drain to the bit line, and its source to the capacitor structure. Voltage signals on the word line control the transistor's on / off state, allowing data to be read from or written to the capacitor structure via the bit line. To isolate adjacent bit lines, each bit line is encased in insulating sidewalls.

[0003] Dynamic random access memory also includes capacitive contact structures located between adjacent bit lines. One end of the capacitive contact structure is connected to the source or drain of the transistor, and the other end of the capacitive contact structure is connected to a capacitor to realize the electrical connection between the capacitor and the source or drain.

[0004] However, the isolation sidewalls are easily damaged during the formation of the capacitor contact structure, which reduces the yield of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method, which can avoid damage to the isolation sidewalls and improve the yield of the semiconductor structure.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0007] Provide a base;

[0008] A plurality of bit lines are formed on the substrate at intervals along a first direction, wherein the width of the top of each bit line is greater than the width of the bottom of the bit line;

[0009] An initial isolation sidewall is formed covering each of the bit lines. The initial isolation sidewall includes a first initial isolation layer, a second isolation layer and a third initial isolation layer stacked together. The first initial isolation layer covers the bit lines. The second isolation layer is located between the first initial isolation layer and the third initial isolation layer, and the top surface of the second isolation layer is lower than the top surface of the first initial isolation layer.

[0010] The initial isolation sidewalls on the substrate located between adjacent bit lines are removed, and the retained initial isolation sidewalls constitute the isolation sidewalls.

[0011] In some embodiments, the step of forming a plurality of bit lines spaced apart along a first direction on the substrate includes:

[0012] A plurality of initial bit lines are formed on the substrate at intervals along a first direction, each initial bit line comprising an initial bit line conductive layer and a bit line insulating layer stacked together; the width of the initial bit line conductive layer is equal to the width of the bit line insulating layer.

[0013] Along the first direction, a portion of the initial bit line conductive layer is removed, leaving the remaining initial bit line conductive layer to form a bit line conductive layer, and a first step surface is formed between the bit line conductive layer and the bit line insulating layer.

[0014] In some embodiments, the initial bit line conductive layer includes an initial contact layer, an initial barrier layer, and an initial conductive layer stacked sequentially; the step of removing a portion of the width of the initial bit line conductive layer along a first direction includes:

[0015] A first etching process is used to remove a portion of the width of the initial conductive layer and the initial barrier layer along a first direction to form a stacked intermediate conductive layer and an intermediate barrier layer.

[0016] A second etching process is used to remove a portion of the width of the intermediate conductive layer, the intermediate barrier layer, and the initial contact layer along the first direction to form a bit line.

[0017] In some embodiments, the first etching process and the second etching process are the same.

[0018] In some embodiments, the first etching process includes dry etching; the etching gas in the first etching process includes chlorine and carbon tetrafluoride, and the ratio of chlorine to carbon tetrafluoride is 1:2 to 1:4.

[0019] In some embodiments, the volumetric flow rate of chlorine is 25 sccm to 35 sccm, and the volumetric flow rate of carbon tetrafluoride is 90 sccm to 110 sccm.

[0020] In some embodiments, the etching time of the first etching process is 10s to 30s; the bias voltage of the first etching process is 0V.

[0021] In some embodiments, the second etching process includes dry etching; the etching gas in the second etching process includes chlorine and nitrogen trifluoride, and the ratio of chlorine to nitrogen trifluoride is 3:1 to 1:1.

[0022] In some embodiments, the volumetric flow rate of chlorine is 15 sccm to 25 sccm, and the volumetric flow rate of nitrogen trifluoride is 5 sccm to 15 sccm.

[0023] In some embodiments, the etching time of the second etching process is 10s to 20s; the bias voltage of the first etching process is 0V.

[0024] In some embodiments, the step of forming an initial isolation sidewall covering each of the bit lines includes:

[0025] A first initial isolation layer is formed, which wraps around the bit lines and covers a substrate located between adjacent bit lines; wherein the first initial isolation layer forms a second step surface at the first step surface;

[0026] A second initial isolation layer is formed, which covers the first initial isolation layer;

[0027] The second initial isolation layer with a portion of its thickness is removed, as well as the second initial isolation layer located between adjacent bit lines, leaving the second initial isolation layer to form the second isolation layer, the top surface of the second isolation layer being lower than the top surface of the first initial isolation layer;

[0028] A third initial isolation layer is formed, which covers the second isolation layer and the first initial isolation layer.

[0029] In some embodiments, the step of removing a portion of the thickness of the second initial insulating layer includes:

[0030] A third etching process is used to remove the second initial isolation layer located above the second step surface and the second initial isolation layer located between adjacent bit lines, so that the top surface of the formed second isolation layer is flush with the second step surface.

[0031] In some embodiments, the third etching process includes dry etching, and the etching gas in the third etching process includes carbon tetrafluoride;

[0032] The volumetric flow rate of the carbon tetrafluoride is 100 sccm to 300 sccm; the bias voltage of the third etching process is 10V to 100V.

[0033] A second aspect of this disclosure provides a semiconductor structure, comprising: the semiconductor structure being fabricated by the method for fabricating the semiconductor structure described in the first aspect. The semiconductor structure includes:

[0034] Base;

[0035] Multiple bit lines are spaced apart along a first direction, and the width of the top of each bit line is greater than the width of the bottom of the bit line, so that the bit line has a first stepped surface;

[0036] An isolation sidewall covers each of the bit lines; wherein the isolation sidewall includes a first isolation layer, a second isolation layer and a third isolation layer, the first isolation layer covers the bit lines, the second isolation layer is located between the first isolation layer and the third isolation layer, and the top surface of the second isolation layer is lower than the top surface of the first isolation layer.

[0037] In some embodiments, the top surface of the second isolation layer is lower than the first step surface, and the longitudinal section is a cross section perpendicular to the substrate, wherein the longitudinal section shape of the second isolation layer is an inverted L-shape.

[0038] In the semiconductor structure fabrication method and fabrication method provided in this disclosure, by making the top surface of the second isolation layer lower than the top surfaces of the first initial isolation layer and the third initial isolation layer, the top surface of the second isolation layer is not exposed. When the initial isolation sidewalls located between adjacent bit lines and on the substrate are subsequently removed, the second isolation layer located on the sidewalls of the bit lines will not be etched, thereby preventing the formation of voids in the isolation sidewalls and improving the yield of the semiconductor structure.

[0039] Furthermore, when removing the initial isolation sidewalls on the substrate located between adjacent bit lines, the top of the wider bit line can protect the initial isolation sidewalls located at the bottom of the narrower bit line without the need for an additional sacrificial layer. This also prevents damage to the initial isolation sidewalls located on and below the first step surface, thus improving the yield of the semiconductor structure.

[0040] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1A schematic diagram of a semiconductor structure with capacitive contact holes provided for related technologies;

[0043] Figure 2 A schematic diagram of a semiconductor structure with conductive materials provided for related technologies;

[0044] Figure 3 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0045] Figure 4 This is a schematic diagram of the formation of initial bit lines in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0046] Figure 5 A schematic diagram illustrating the formation of intermediate bit lines in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0047] Figure 6 This is a schematic diagram of bit line formation in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0048] Figure 7 This is a schematic diagram of the formation of a first initial isolation layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0049] Figure 8 This is a schematic diagram of the formation of a second initial isolation layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0050] Figure 9 This is a schematic diagram of the formation of the second isolation layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0051] Figure 10 A schematic diagram illustrating the formation of initial isolation sidewalls in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0052] Figure 11 A schematic diagram illustrating the formation of initial isolation sidewalls in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0053] Figure 12 This is a schematic diagram of the formation of a capacitor contact structure in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0054] Figure label:

[0055] 1: Substrate; 2: Bit line; 3: Void; 4: Capacitor contact hole; 5: Conductive material;

[0056] 10: Base;

[0057] 20: Initial bit line; 21: Initial bit line conductive layer; 211: Initial contact layer; 212: Initial barrier layer; 213: Initial conductive layer; 214: Intermediate barrier layer; 215: Intermediate conductive layer; 22: Bit line insulating layer;

[0058] 30: Intermediate bit line; 40: Bit line; 41: Bit line conductive layer; 411: Contact layer; 412: Barrier layer; 413: Conductive layer;

[0059] 50: Initial isolation sidewall; 51: First initial isolation layer; 52: Second initial isolation layer; 53: Third initial isolation layer;

[0060] 60: Isolation sidewall; 61: First isolation layer; 62: Second isolation layer; 63: Third isolation layer;

[0061] 70: First step surface; 80: Second step surface; 90: Capacitor contact structure. Detailed Implementation

[0062] The semiconductor structure in related technologies suffers from low yield. The inventors have discovered that the reason for this problem lies in the following (see attached document). Figure 1 and attached Figure 2 The isolation sidewall typically consists of a stacked silicon nitride layer, a silicon oxide layer, and a silicon nitride layer, referred to as a NON structure. When the isolation sidewall located between adjacent bit lines 2 and on the substrate 1 is removed to form capacitor contact holes 4, the silicon oxide layer is easily removed, resulting in gaps 3 in the isolation sidewall. During subsequent capacitor contact construction, the conductive material 5 of the capacitor contact structure is deposited into the gaps 3. This reduces the isolation function of the isolation sidewall and increases the parasitic capacitance formed between the bit lines 2 and the conductive material present in the isolation sidewall, thus reducing the yield of the semiconductor structure.

[0063] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. By making the top surface of the second isolation layer lower than the top surfaces of the first and third initial isolation layers, the top surface of the second isolation layer is not exposed. When the initial isolation sidewalls located between adjacent bit lines and on the substrate are subsequently removed, the second isolation layer located on the sidewalls of the bit lines will not be etched, thus preventing the formation of voids within the isolation sidewalls and improving the yield of the semiconductor structure.

[0064] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0065] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0066] like Figure 3 As shown in the embodiments of this disclosure, a method for fabricating a semiconductor structure includes the following steps:

[0067] Step S100: Provide a substrate.

[0068] Please refer to the attached document. Figure 4 The substrate 10 is used to support the semiconductor device disposed thereon. The substrate 10 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0069] It should be noted that the substrate 10 has multiple active regions, and shallow trench isolation (STI) structures can be set between these active regions to separate them and ensure that each active region is independent of the others. For example, shallow trenches are formed in the substrate using a patterning process, and insulating material is filled into the shallow trenches, thereby defining multiple active regions separated by the shallow trench isolation structures on the substrate. The patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process. The insulating material can include silicon oxide, but is not limited to this.

[0070] Step S200: A plurality of bit lines are formed on the substrate at intervals along a first direction, wherein the width of the top of each bit line is greater than the width of the bottom of the bit line.

[0071] For example, please refer to the appendix. Figure 4 A plurality of initial bit lines 20 are formed on a substrate 10 at intervals along a first direction. Each initial bit line 20 includes an initial bit line conductive layer 21 and a bit line insulating layer 22 stacked sequentially. In the first direction, the width of the bit line insulating layer 22 is equal to the width of the initial bit line conductive layer 21. The first direction can be an adjacent... Figure 4 The X direction in the equation.

[0072] In one possible implementation, the individual film layers for forming the initial bit line 20 can be deposited on a substrate first. Then, portions of the individual film layers are removed using a patterning process to form the initial bit line 20. The width of the initial bit line 20 is substantially equal from top to bottom, resulting in a rectangular cross-sectional shape. This simplifies the patterning process and facilitates the fabrication of the initial bit line 20.

[0073] The initial bit line conductive layer 21 can be a stacked structure. For example, the initial bit line conductive layer 21 includes an initial contact layer 211, an initial barrier layer 212, and an initial conductive layer 213 stacked sequentially. A portion of the initial contact layer 211 can be disposed within the substrate 10 to facilitate electrical connection of the active region of the substrate 10. The material of the initial contact layer 211 includes polysilicon, but is not limited to it.

[0074] It should be noted that, for the sake of convenience in describing the structure of the initial bit line 20, the appendix... Figure 4 The semiconductor structure has been simplified, and only the initial contact layer 211 located on the substrate 10 is shown.

[0075] An initial barrier layer 212 is disposed on the initial contact layer 211. The initial barrier layer 212 has both conductive and barrier properties. For example, the initial barrier layer 212 can prevent the metallic conductive material in the initial conductive layer 213 from diffusing into the initial contact layer 211 and the substrate 10, ensuring insulation between the initial bit line 20 and the subsequent capacitor contact structure. The material of the initial barrier layer includes titanium nitride, but is not limited to this.

[0076] An initial conductive layer 213 is disposed on the initial barrier layer 212. The material of the initial conductive layer 213 includes tungsten, which has strong conductivity and can improve the conductivity of the initial bit line 20.

[0077] After the initial bit lines are formed, please refer to the appendix. Figure 5 and attached Figure 6 Along the first direction, a portion of the width of the initial bit line conductive layer 21 is removed, and the remaining initial bit line conductive layer 21 constitutes the bit line conductive layer 41, and a first step surface 70 is formed between the bit line conductive layer 41 and the bit line insulating layer 22.

[0078] In this embodiment, a portion of the initial bit line conductive layer 21 can be removed using an etching process, resulting in a bit line 40 that is wider at the top and narrower at the bottom. This configuration allows a second isolation layer to be formed within the area enclosed by the first step surface 70 and the bit line conductive layer 41, preventing the top surface of the second isolation layer from being flush with the top surface of the bit line 40. When removing the initial isolation sidewalls located between adjacent bit lines 40 and on the substrate 10, the second isolation layer on the sidewalls of the bit lines 40 will not be etched, thus preventing the formation of voids within the isolation sidewalls and improving the yield of the semiconductor structure.

[0079] The etching process can be a single etching or multiple etching processes. A single etching process can refer to one etching step, in which the initial bit line conductive layer 21 is etched to a preset width using a single etching process. Multiple etching processes can refer to multi-step etching or step-by-step etching, in which the initial bit line conductive layer 21 is etched to a preset width using at least two etching processes, wherein the types and / or process parameters of the at least two etching processes are the same or different.

[0080] In one possible example, the initial bit line conductive layer 21 is etched directly to its initial width in a single etching process. This setup simplifies the etching process, requiring no additional steps or adjustments to process parameters.

[0081] In some other possible examples, the initial bit line conductive layer 21 is etched to the initial width through two etching processes. This setting can ensure that the initial conductive layer is etched to the initial width more accurately, thereby reducing or avoiding over-etching of the initial conductive layer.

[0082] For example, please refer to the appendix. Figure 5 The first etching process is used to remove a portion of the width of the initial conductive layer 213 and the initial barrier layer 212 along the first direction to form a stacked intermediate conductive layer 215 and an intermediate barrier layer 214. For ease of description of the bit line formation process, the structure in this step may be referred to as the intermediate bit line 30.

[0083] In this embodiment, the intermediate bit line 30 formed by the first etching process has a shape that is equal in width at the top and bottom and narrow in the middle. That is, the width of the intermediate conductive layer 215 is smaller than the width of the bit line insulating layer 22 and also smaller than the width of the initial contact layer 211.

[0084] Please refer to the appendix afterward. Figure 6A second etching process is used to remove a portion of the width of the intermediate conductive layer 215, intermediate barrier layer 214, and initial contact layer 211 along the first direction. The remaining intermediate conductive layer 215 forms the conductive layer 413, the remaining intermediate barrier layer 214 forms the barrier layer 412, and the remaining initial contact layer 211 forms the contact layer 411. Thus, the contact layer 411, barrier layer 412, conductive layer 413, and bit line insulating layer 22, located in the same vertical direction and stacked, form a bit line 40. The width of the bit line conductive layer 41 in the bit line 40 is smaller than the width of the bit line insulating layer 22, and the width of the bit line conductive layer 41 is 2nm-10nm. This configuration allows the formation of the first step surface 70 in the bit line 40 while preventing excessive reduction of the width of the initial bit line conductive layer, thus ensuring the conductivity of the bit line 40.

[0085] In this step, the widths of the intermediate conductive layer 215 and the intermediate barrier layer 214 removed are equal and smaller than the width of the initial contact layer 211 removed. This arrangement allows for convenient adjustment of the parameters in the first and second etching processes based on the different materials of each film layer in the initial bit line conductive layer 21. This enables precise control of the width of each film layer removed in the initial bit line conductive layer 21, minimizing or avoiding over-etching of the initial bit line conductive layer 21, improving the yield of the bit line 40, and consequently improving the yield of the semiconductor structure.

[0086] In this example, the first etching process and the second etching process can be the same or different.

[0087] In one possible implementation, the first etching process and the second etching process can both be either dry etching or wet etching. This configuration simplifies the etching process of the initial bit line conductive layer 21.

[0088] For example, the first etching process and the second etching process are both dry etching processes, and the process parameters of the first etching process and the second etching process are different. In this way, the width of each film layer removed in the initial bit line conductive layer 21 can be reasonably adjusted.

[0089] Specifically, the etching gas in the first etching process may include a combination of chlorine (Cl2) and carbon tetrafluoride (CF4). The ratio of chlorine (Cl2) to carbon tetrafluoride (CF4) is 1:2 to 1:4. This configuration allows for control over the etching selectivity of each layer in the initial bit line conductive layer 21. For example, if the etching selectivity of the first etching process for the initial conductive layer 213 and the initial barrier layer 212 is equal to 1, the difference in the width of the etched initial conductive layer 213 and the initial barrier layer 212 can be minimized to the greatest extent possible. Simultaneously, if the etching selectivity of the first etching process for the initial conductive layer 213 and the initial contact layer 211 is greater than 1, then when simultaneously removing a portion of the width of the initial conductive layer 213 and the initial barrier layer 212, the initial contact layer 211 is not etched, thus forming an intermediate bit line 30 that is equal in width at the top and bottom and narrow in the middle.

[0090] The volumetric flow rate of chlorine (Cl2) in the first etching process is 25 sccm to 35 sccm, and the volumetric flow rate of carbon tetrafluoride (CF4) is 90 sccm to 110 sccm; preferably, the volumetric flow rate of chlorine (Cl2) is 30 sccm, and the volumetric flow rate of carbon tetrafluoride (CF4) is 100 sccm. The etching time of the first etching process is 10 s to 30 s, preferably 20 s. This setting ensures that the formed intermediate bit line 30 has a shape that is equal in width at the top and bottom and narrow in the middle.

[0091] The bias voltage of the first etching process is 0V. With this setting, the etching gas can remove only a portion of the width of the initial conductive layer 213 and the initial barrier layer 212 along the first direction, reducing or even avoiding damage to the substrate 10 or the alignment line insulating layer 22 in the vertical direction, thereby improving the yield of the semiconductor structure.

[0092] The etching gas in the second etching process may include chlorine (Cl2) and nitrogen trifluoride (NF3), with a ratio of chlorine (Cl2) to nitrogen trifluoride (NF3) of 3:1 to 1:1. This configuration allows for control over the etching selectivity of the etching gas towards the intermediate conductive layer 215, the intermediate barrier layer 214, and the initial contact layer 211. This ensures that the width of the initial contact layer 211 etched is greater than the widths of the intermediate conductive layer 215 and the intermediate barrier layer 214, resulting in a bit line 40 with a wider width at the top and a narrower width at the bottom. For example, if the etching selectivity ratio of the second etching process towards the intermediate conductive layer 215 and the intermediate barrier layer 214 is equal to 1, the difference in the etched widths of the intermediate conductive layer 215 and the intermediate barrier layer 214 can be minimized to the greatest extent possible. At the same time, the etching selectivity ratio of the second etching process for the intermediate conductive layer 215 and the initial contact layer 211 is less than 1, so that the width of the initial contact layer 211 etched is greater than the width of the intermediate conductive layer 215 and the intermediate barrier layer 214 etched, and within a certain period of time, the remaining widths of the intermediate conductive layer 215, the intermediate barrier layer 214 and the initial contact layer 211 are consistent.

[0093] The volumetric flow rate of chlorine (Cl2) in the second etching process is 15 sccm to 25 sccm, and the volumetric flow rate of nitrogen trifluoride (NF3) is 5 sccm to 15 sccm. Preferably, the volumetric flow rate of chlorine (Cl2) is 20 sccm, and the volumetric flow rate of nitrogen trifluoride (NF3) is 10 sccm. The etching time of the second etching process is 10 s to 20 s, preferably 15 s. This setting ensures that the width of the formed bit line 40 is wider at the top and narrower at the bottom.

[0094] The bias voltage of the second etching process is 0V. With this setting, the etching gas of the second etching process can remove only a portion of the width of the intermediate conductive layer 215, intermediate barrier layer 214 and initial contact layer 211 along the first direction, without damaging the substrate 10 or the alignment line insulating layer 22 in the vertical direction, thus improving the yield of the semiconductor structure.

[0095] It should be noted that the first etching process and the second etching process can also be different. For example, the first etching process is dry etching, and the second etching process is wet etching; or, the first etching process is wet etching, and the second etching process is dry etching. This configuration allows for the utilization of the better consistency of dry etching, improving pattern accuracy; it also allows for the utilization of the better etching selectivity of wet etching, avoiding damage to the exposed substrate 10 and bit line insulating layer 22 during the etching of the initial bit line conductive layer 21. That is, less damage to the substrate 10 and bit line insulating layer 22 is caused, reducing damage to semiconductor devices (e.g., word lines) within the substrate 10, thereby ensuring the performance of the semiconductor structure; furthermore, reduced damage to the bit line insulating layer 22 improves the insulation performance between the bit lines and subsequent formation of other semiconductor devices (e.g., capacitor contact structures), improving the yield of the semiconductor structure.

[0096] Step S300: Form an initial isolation sidewall covering each bit line. The initial isolation sidewall includes a first initial isolation layer, a second isolation layer and a third isolation layer stacked together. The first initial isolation layer covers the bit line. The second isolation layer is located between the first initial isolation layer and the third initial isolation layer. The top surface of the second isolation layer is lower than the top surface of the first initial isolation layer.

[0097] In one example, the top surface of the second isolation layer 62 may be located between the top surface of the first initial isolation layer 51 and the first step surface 70. In another example, the top surface of the second isolation layer 62 may be flush with the first step surface 70. In yet another example, the top surface of the second isolation layer 62 is lower than the first step surface 70, that is, the top surface of the second isolation layer 62 is located between the first step surface 70 and the substrate 10.

[0098] For example, please refer to the appendix. Figure 7 An atomic layer deposition process is used to form a first initial isolation layer 51, which wraps around the bit line 40 and covers the substrate 10 located between adjacent bit lines 40; wherein, the first initial isolation layer 51 forms a second step surface 80 at the first step surface 70. The material of the first initial isolation layer 51 is the same as that of the bit line insulating layer 22, both of which include silicon nitride.

[0099] Next, please refer to the appendix. Figure 8 A second initial isolation layer 52 is formed using an atomic layer deposition process. The second initial isolation layer 52 covers the first initial isolation layer 51, that is, the second initial isolation layer 52 conformally covers the first initial isolation layer 51. The material of the second initial isolation layer 52 includes silicon oxide.

[0100] Next, please refer to the appendix. Figure 9The second initial isolation layer 52 with a portion of its thickness is removed, as well as the second initial isolation layer 52 located between adjacent bit lines 40, and the remaining second initial isolation layer 52 constitutes the second isolation layer 62.

[0101] For example, the second initial isolation layer 52 located above the second step surface 80 and the second initial isolation layer 52 located between adjacent bit lines 40 can be removed so that the top surface of the second isolation layer 62 is lower than the first step surface, for example, the top surface of the second isolation layer 62 is flush with the second step surface 80. With this configuration, the second isolation layer can be completely shielded by the first initial isolation layer 51 and the bit line insulation layer 22 located thereon, after which the first initial isolation layer 51 and the third initial isolation layer 53 located on the substrate 10 between adjacent bit lines 40 (see Appendix). Figure 10 When the first initial isolation layer 51 and the second isolation layer 62 are combined, the second isolation layer 62 will not be damaged. In this embodiment, the total thickness of the first initial isolation layer 51 and the second isolation layer 62 is 1 to 5 nm. This facilitates the fabrication of the second isolation layer 62 while maintaining the second step surface 80 and avoiding damage to the second isolation layer 62 by subsequent processes.

[0102] In some possible examples, a third etching process is used to remove the second initial isolation layer 52 located above the second step surface 80, and the second initial isolation layer 521 located between adjacent bit lines 40. That is, the third etching process is used to remove the second initial isolation layer 52 on the first initial isolation layer 51 corresponding to the bit line insulating layer 22.

[0103] The third etching process includes dry etching, and the etching gas used in the third etching process is carbon tetrafluoride (CF4). The volumetric flow rate of carbon tetrafluoride (CF4) is 100 sccm to 300 sccm. The etching selectivity of carbon tetrafluoride (CF4) for the second initial isolation layer 52 is greater than that for the first initial isolation layer 51. This setting allows only a portion of the second initial isolation layer 52 to be etched away, reducing or avoiding damage to the first initial isolation layer 51 and ensuring the insulation performance of the isolation sidewall.

[0104] The bias voltage of the third etching process is 10V to 100V. This setting ensures that the etching gas can be introduced in a direction perpendicular to the substrate 10, thereby weakening the etching of the second initial isolation layer 52 located on the sidewall of the bit line conductive layer 41, so that the formed second isolation layer 62 forms an inverted L-shape.

[0105] Furthermore, the bit line 40 has an inverted convex shape with a larger top and a smaller bottom. The wider bit line insulating layer 22 can protect the first initial isolation layer 51 and the second isolation layer 62 located on the narrower bit line conductive layer 41 without the need for an additional sacrificial layer. This avoids lateral etching of the first initial isolation layer 51 and the second isolation layer 62 and also ensures that the first initial isolation layer 51 and the second isolation layer 62 located on the bit line conductive layer 41 will not be damaged when the initial isolation sidewalls 50 located on the substrate between adjacent bit lines 40 are subsequently removed, thereby improving the yield of the semiconductor structure.

[0106] Please refer to the attached document. Figure 10 A third initial isolation layer 53 is formed using an atomic layer deposition process, which covers the second isolation layer 62 and the first initial isolation layer 51. The material of the third initial isolation layer 53 includes silicon nitride.

[0107] It should be noted that the initial isolation sidewall in this embodiment is not limited to the above-mentioned NON structure, and other materials with low dielectric constants can also be used.

[0108] Step S400: Remove the initial isolation sidewalls on the substrate located between adjacent bit lines, and the retained initial isolation sidewalls constitute the isolation sidewalls.

[0109] Please refer to the attached document. Figure 11 The first initial isolation layer 51 and the third initial isolation layer 53 located on the substrate between adjacent bit lines 40 are removed by dry etching or wet etching. The remaining first initial isolation layer 51 constitutes the first isolation layer 61, and the remaining third initial isolation layer 53 constitutes the third isolation layer 63.

[0110] In other words, the isolation sidewall 60 includes a first isolation layer 61, a second isolation layer 62, and a third isolation layer 63 stacked together. The first isolation layer 61 covers the position line 40, and the second isolation layer 62 is located between the first isolation layer 61 and the third isolation layer 63, with the top surface of the second isolation layer 62 being lower than the top surface of the first isolation layer 61. For example, the top surface of the second isolation layer 62 is lower than the first step surface 70.

[0111] In this embodiment, when removing the first initial isolation layer and the third initial isolation layer located on the substrate between adjacent bit lines, the wider bit line insulating layer can protect the first initial isolation layer and the second isolation layer located on the narrower bit line conductive layer without the need for an additional sacrificial layer. This also ensures that the first initial isolation layer and the second isolation layer located on the bit line conductive layer will not be damaged when the initial isolation sidewalls located on the substrate between adjacent bit lines are subsequently removed, thereby improving the yield of the semiconductor structure.

[0112] Please refer to the attached document. Figure 12After forming the isolation sidewall 60, the method for fabricating the semiconductor structure further includes: forming a plurality of capacitor contact structures 90, wherein the plurality of capacitor contact structures 90 are arranged in a one-to-one correspondence with the bit lines 40, and each capacitor contact structure 90 is located between adjacent bit lines 40 and is insulated from the bit lines 40.

[0113] This disclosure also provides a semiconductor structure, which is prepared by the preparation method described in the above embodiments.

[0114] Please continue to refer to the appendix. Figure 12 The semiconductor structure includes a substrate 10, a plurality of bit lines 40, and a plurality of isolation sidewalls 60. The bit lines 40 are spaced apart on the substrate 10 along a first direction and are electrically connected to an active region in the substrate 10. The top width of each bit line 40 is greater than the bottom width, such that the bit line 40 has a first stepped surface 70. Exemplarily, each bit line 40 includes a stacked bit line conductive layer 41 and a bit line insulating layer 22, the width of which is greater than the width of the bit line conductive layer 41, such that a first stepped surface 70 is formed between the bit line insulating layer 22 and the bit line conductive layer 41.

[0115] Multiple isolation sidewalls 60 are configured in a one-to-one correspondence with multiple position lines 40, with one isolation sidewall 60 covering one position line 40. Each isolation sidewall 60 includes a first isolation layer 61, a second isolation layer 62, and a third isolation layer 63. The first isolation layer 61 covers the position line 40, and the second isolation layer 62 is located between the first isolation layer 61 and the third isolation layer 63, with the top surface of the second isolation layer 62 lower than the top surface of the first isolation layer 61. For example, the top surface of the second isolation layer 62 is lower than the first step surface 70; that is, with a section perpendicular to the base 10 as the longitudinal section, the longitudinal section of the second isolation layer 62 is formed as an inverted L-shape.

[0116] Thus, the second isolation layer 62 is surrounded by the first isolation layer 61 and the third isolation layer 63, making the isolation sidewall 60 a dense structure. When the capacitor contact structure 90 is formed subsequently, even if the top structure of the bit line 40 is ground, the second isolation layer 62 will not be exposed, preventing the second isolation layer 62 from being removed by the etching solution. The conductive material of the capacitor contact structure 90 will not be deposited into the isolation sidewall 60. In this way, the isolation function of the isolation sidewall 60 can be guaranteed, and the formation of parasitic capacitance between the bit line 40 and the isolation sidewall 60 can be avoided, thereby improving the yield of the semiconductor structure.

[0117] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0118] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0119] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide a base; A plurality of bit lines are formed on the substrate at intervals along a first direction, wherein the width of the top of each bit line is greater than the width of the bottom of the bit line; An initial isolation sidewall is formed covering each of the bit lines. The initial isolation sidewall includes a first initial isolation layer, a second isolation layer and a third initial isolation layer stacked together. The first initial isolation layer covers the bit lines. The second isolation layer is located between the first initial isolation layer and the third initial isolation layer, and the top surface of the second isolation layer is lower than the top surface of the first initial isolation layer. Remove the initial isolation sidewalls on the substrate located between adjacent bit lines, and retain the initial isolation sidewalls to form isolation sidewalls; The step of forming a plurality of bit lines spaced apart along a first direction on the substrate includes: A plurality of initial bit lines are formed on the substrate at intervals along a first direction, each initial bit line comprising an initial bit line conductive layer and a bit line insulating layer stacked together; the width of the initial bit line conductive layer is equal to the width of the bit line insulating layer. Along the first direction, a portion of the width of the initial bit line conductive layer is removed, and the remaining initial bit line conductive layer constitutes the bit line conductive layer. A first step surface is formed between the bit line conductive layer and the bit line insulating layer. The initial bit line conductive layer includes an initial contact layer, an initial barrier layer and an initial conductive layer stacked sequentially. The step of removing a portion of the initial bit line conductive layer along the first direction includes: A first etching process is used to remove a portion of the width of the initial conductive layer and the initial barrier layer along a first direction to form a stacked intermediate conductive layer and an intermediate barrier layer. A second etching process is used to remove a portion of the width of the intermediate conductive layer, the intermediate barrier layer, and the initial contact layer along the first direction to form a bit line; The second etching process includes dry etching; the etching gas in the second etching process includes chlorine and nitrogen trifluoride, and the ratio of chlorine to nitrogen trifluoride is 3:1 to 1:

1.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first etching process and the second etching process are the same.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first etching process includes dry etching; the etching gas in the first etching process includes chlorine and carbon tetrafluoride, and the ratio of chlorine to carbon tetrafluoride is 1:2 to 1:

4.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The volumetric flow rate of the chlorine gas is 25 sccm to 35 sccm, and the volumetric flow rate of the carbon tetrafluoride gas is 90 sccm to 110 sccm.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The etching time of the first etching process is 10s to 30s; the bias voltage of the first etching process is 0V.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The volumetric flow rate of the chlorine gas is 15 sccm to 25 sccm, and the volumetric flow rate of the nitrogen trifluoride is 5 sccm to 15 sccm.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching time for the second etching process is 10s to 20s; the bias voltage for the first etching process is 0V.

8. The method for preparing a semiconductor structure according to any one of claims 1-7, characterized in that, The steps of forming an initial isolation sidewall covering each of the bit lines include: A first initial isolation layer is formed, which wraps around the bit lines and covers a substrate located between adjacent bit lines; wherein the first initial isolation layer forms a second step surface at the first step surface; A second initial isolation layer is formed, which covers the first initial isolation layer; The second initial isolation layer with a portion of its thickness is removed, as well as the second initial isolation layer located between adjacent bit lines, leaving the second initial isolation layer to form the second isolation layer, the top surface of the second isolation layer being lower than the top surface of the first initial isolation layer; A third initial isolation layer is formed, which covers the second isolation layer and the first initial isolation layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The step of removing a portion of the thickness of the second initial isolation layer includes: A third etching process is used to remove the second initial isolation layer located above the second step surface and the second initial isolation layer located between adjacent bit lines, so that the top surface of the formed second isolation layer is flush with the second step surface.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The third etching process includes dry etching, and the etching gas in the third etching process includes carbon tetrafluoride. The volumetric flow rate of the carbon tetrafluoride is 100 sccm to 300 sccm; the bias voltage of the third etching process is 10V to 100V.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1-10, and the semiconductor structure comprises: Base; Multiple bit lines are spaced apart along a first direction, and the width of the top of each bit line is greater than the width of the bottom of the bit line, so that the bit line has a first stepped surface; An isolation sidewall covers each of the bit lines; wherein the isolation sidewall includes a first isolation layer, a second isolation layer and a third isolation layer, the first isolation layer covers the bit lines, the second isolation layer is located between the first isolation layer and the third isolation layer, and the top surface of the second isolation layer is lower than the top surface of the first isolation layer.

12. The semiconductor structure according to claim 11, characterized in that, The top surface of the second isolation layer is lower than the first step surface, and the longitudinal section is perpendicular to the base. The longitudinal section shape of the second isolation layer is an inverted L-shape.

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