Method and device for recovering and allocating index data in hash table

Abstract

The present application provides a method and device for recovering and allocating index data in a hash table, the method comprising: allocating a RAM target address space for a target hash table in the current RAM; allocating a DDR target address space for a target hash table in the DDR; allocating each index data to be recovered in the target hash table to the DDR target address space; reading a preset number of the index data from the DDR target address space and writing them to the RAM target address space; based on the index recovery instruction received from the user input, reading the first RAM address pointer in the index parameter table corresponding to the user; based on the first RAM address pointer in the index parameter table, writing the target index data pre-read from the RAM target address space to the RAM target address space; and adding 1 to the value of the first RAM address pointer to obtain a second RAM address pointer. The present application can effectively improve the efficiency of DPU data storage and reduce the data storage pressure of DPU.

Description

Technical Field

[0001] The present application relates to the field of data storage, and in particular to a method and device for recovering and allocating index data in a hash table. Background Art

[0002] The hash algorithm maps a binary value of any length to a shorter fixed-length binary value, which is called a hash value. A hash value is a unique and extremely compact numerical representation of a piece of data. If you hash a plain text and change even one letter of the paragraph, subsequent hashes will produce different values. The significance of the hash algorithm is that it provides a method for quickly accessing data. It uses an algorithm to establish a correspondence between key values ​​and real values. Each real value can only have one key value, but a key value can correspond to multiple real values, so that data can be quickly accessed in conditions such as arrays. In the hash table of DOE (Database Offload Engine), the key (key value) is hashed to obtain the hashcode (real value), and the hashcode is divided and then the remainder is obtained to obtain the hash value, which also corresponds to the offset address of the key value in the hash table. The hashcode is the only one that will not be repeated, but the hash value will definitely be repeated. Different key values ​​cannot be stored at the same address. This is called a hash conflict.

[0003] When the existing technology resolves hash conflicts, the DPU performs data storage inefficiently and places great storage pressure. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a method and device for recovering and allocating index data in a hash table to eliminate or improve one or more defects existing in the prior art.

[0005] A first aspect of the present application provides a method for recovering and allocating index data in a hash table, the method comprising:

[0006] Allocate RAM target address space for the target hash table in the current RAM; allocate DDR target address space for the target hash table in DDR;

[0007] Allocating each index data to be recovered in the target hash table to the DDR target address space; reading a preset number of the index data from the DDR target address space and writing them to the RAM target address space;

[0008] Based on the received index recovery instruction input by the user, read the first RAM address pointer in the index parameter table corresponding to the user;

[0009] The target index data pre-read from the RAM target address space is written into the RAM target address space based on the first RAM address pointer in the index parameter table; and the value of the first RAM address pointer is increased by 1 to obtain a second RAM address pointer.

[0010] In some embodiments of the present application, after adding 1 to the value of the first RAM address pointer parameter to obtain the second RAM address pointer, the method further includes:

[0011] Determining whether the number of remaining index data in the RAM target address space is greater than the preset first index data number based on the second RAM address pointer;

[0012] If yes, based on the second RAM address pointer, read the first preset number of index data in the RAM target address space and write them into the DDR target address space; add the value of the first preset number to the value of the first DDR address pointer in the index parameter table, and return the updated first DDR address pointer to the index parameter table; subtract the value of the first preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table;

[0013] If not, return the second RAM address pointer to the index parameter table.

[0014] In some embodiments of the present application, it also includes:

[0015] Based on the received index application instruction input by the user, read the third RAM address pointer in the index parameter table corresponding to the user;

[0016] The index data in the RAM target address space is read based on the third RAM address pointer; and the value of the third RAM address pointer is reduced by 1 to obtain a fourth RAM address pointer.

[0017] In some embodiments of the present application, after the step of subtracting 1 from the value of the third RAM address pointer to obtain the fourth RAM address pointer, the method further includes:

[0018] Determining whether the number of remaining index data in the RAM target address space is less than a preset second index data number based on the fourth RAM address pointer;

[0019] If yes, based on the second DDR address pointer in the index parameter table, read the second preset number of index data in the DDR target address space and write them into the RAM target address space; subtract the value of the second preset number from the value of the second DDR address pointer, and return the updated second DDR address pointer to the index parameter table; add the value of the second preset number to the fourth RAM address pointer, and return the updated fourth RAM address pointer to the index parameter table;

[0020] If not, return the fourth RAM address pointer to the index parameter table.

[0021] In some embodiments of the present application, it also includes:

[0022] If a hash conflict occurs when inserting target index data into the target hash master table, the target index data is written to the RAM target address space.

[0023] In some embodiments of the present application, if the number of remaining index data in the RAM target address space is less than a preset third number of index data, based on the second DDR address pointer, the third preset number of index data in the DDR target address space is read and written into the RAM target address space.

[0024] In some embodiments of the present application, if the number of remaining index data in the RAM target address space is greater than a preset fourth index data number, based on the second RAM address pointer, the fourth preset number of index data in the RAM target address space is read and written into the DDR target address space.

[0025] A second aspect of the present application provides an index data recovery and allocation device in a hash table, the device comprising:

[0026] An address space allocation module is used to allocate a RAM target address space for a target hash table in the current RAM; and allocate a DDR target address space for the target hash table in the DDR;

[0027] An index data migration module, used to allocate each index data to be recovered in the target hash table to the DDR target address space; read a preset number of the index data from the DDR target address space and write them to the RAM target address space;

[0028] A parameter retrieving module, configured to read a first RAM address pointer in the index parameter table corresponding to the user based on an index recovery instruction received from the user;

[0029] The index writing module is used to write the target index data pre-read from the RAM target address space into the RAM target address space based on the first RAM address pointer in the index parameter table; and add 1 to the value of the first RAM address pointer to obtain a second RAM address pointer.

[0030] In some embodiments of the present application, it also includes:

[0031] An index determination module, configured to determine whether the number of remaining index data in the target address space is greater than a preset first index data number based on the second RAM address pointer;

[0032] an index recovery module, configured to, if yes, read a first preset number of index data in the RAM target address space based on the first DDR address pointer in the index parameter table and write the index data into the DDR target address space; add the value of the first DDR address pointer to the value of the second preset number, and return the updated first DDR address pointer to the index parameter table; subtract the value of the second preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table;

[0033] The parameter returning module is used for returning the second RAM address pointer to the index parameter table if no.

[0034] The third aspect of the present application provides a DPU, which is provided with a database offload engine, and the database offload engine is used to execute the index data recovery and allocation method in the hash table described in the first aspect.

[0035] The present application provides a method and device for recovering and allocating index data in a hash table, the method comprising: allocating a RAM target address space for a target hash table in the current RAM; allocating a DDR target address space for a target hash table in the DDR; allocating each index data to be recovered in the target hash table to the DDR target address space; reading a preset number of the index data from the DDR target address space and writing them to the RAM target address space; based on the index recovery instruction received from the user input, reading the first RAM address pointer in the index parameter table corresponding to the user; based on the first RAM address pointer in the index parameter table, writing the target index data pre-read from the RAM target address space to the RAM target address space; and adding 1 to the value of the first RAM address pointer to obtain a second RAM address pointer. The present application can effectively improve the efficiency of DPU data storage and reduce the data storage pressure of DPU.

[0036] Additional advantages, purposes, and features of the present application will be partially described in the following description, and will become partially apparent to those skilled in the art after studying the following, or may be learned from the practice of the present application. The purposes and other advantages of the present application can be achieved and obtained by the structures specifically pointed out in the specification and the drawings.

[0037] Those skilled in the art will understand that the purposes and advantages that can be achieved by the present application are not limited to the above specific description, and the above and other purposes that can be achieved by the present application will be more clearly understood based on the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present application, constitute a part of the present application, and do not constitute a limitation of the present application. The components in the drawings are not drawn to scale, but are only for the purpose of illustrating the principles of the present application. In order to facilitate the illustration and description of some parts of the present application, the corresponding parts in the drawings may be enlarged, that is, they may become larger relative to other components in the exemplary device actually manufactured according to the present application. In the drawings:

[0039] Figure 1 It is a flowchart of a method for recovering and allocating index data in a hash table in one embodiment of the present application.

[0040] Figure 2 It is a structural diagram of an index data recovery and allocation device in a hash table in another embodiment of the present application.

[0041] Figure 3 Schematic diagram of the process of reading index data in a RAM table in one embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the implementation modes and the accompanying drawings. Here, the illustrative implementation modes and descriptions of the present application are used to explain the present application, but are not intended to limit the present application.

[0043] It should also be noted here that in order to avoid obscuring the present application due to unnecessary details, only the structures and / or processing steps closely related to the scheme according to the present application are shown in the accompanying drawings, while other details that are not very relevant to the present application are omitted.

[0044] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0045] It should also be noted that, unless otherwise specified, the term “connection” herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0046] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0047] The details are described in detail through the following examples.

[0048] The present application embodiment provides a method for recovering and allocating index data in a hash table that can be executed by an index data recovery and allocation device or a DOE (Database Offload Engine) in a hash table, see Figure 1 The index data recovery and allocation method in the hash table specifically includes the following contents:

[0049] Step 110: Allocate a RAM target address space for the target hash table in the current RAM; and allocate a DDR target address space for the target hash table in the DDR.

[0050] Step 120: Allocate each index data to be recovered in the target hash table to the DDR target address space; read a preset number of the index data from the DDR target address space and write them to the RAM target address space.

[0051] Step 130: Based on the received index recovery instruction input by the user, read the first RAM address pointer in the index parameter table corresponding to the user.

[0052] Step 140: Based on the first RAM address pointer in the index parameter table, write the target index data pre-read from the RAM target address space into the RAM target address space; and add 1 to the value of the first RAM address pointer to obtain a second RAM address pointer.

[0053] Specifically, DOE allocates RAM target address space for the target hash table in the current RAM; allocates DDR target address space for the target hash table in DDR. Then, each index data to be recovered in the target hash table is allocated to the DDR target address space; a preset number (64) of the index data is read from the DDR target address space and written to the RAM target address space. Next, based on the index recovery instruction received from the user, the first RAM address pointer (i.e., ram_point in Table 1) in the index parameter table corresponding to the user is read. Finally, based on the first RAM address pointer in the index parameter table, the target index data pre-read from the RAM target address space is written to the RAM target address space; and the value of the first RAM address pointer is added by 1 to obtain the second RAM address pointer, thereby effectively improving the efficiency of DPU data storage and reducing the data storage pressure of DPU.

[0054] Among them, RAM (Random Access Memory) means random access memory; DDR (Double Data Rate Synchronous Dynamic Random Access Memory) means double data rate synchronous dynamic random access memory; RAM target address space and DDR target address space can both contain 256 addresses; the index parameter table is shown in Table 1:

[0055] Table 1

[0056] Parameters Bit width Detailed Description ddr_addr 32 Index the starting address of DDR memory ddr_point 32 Address pointer for reading and writing DDR index data ram_addr 16 Index to the starting address of the on-chip RAM ram_point 16 Address pointer for reading and writing RAM index data

[0057] In addition, the method for solving hash conflicts in this application is the chain address method, which is to organize objects with the same hash value into a linked list and place them in the slot corresponding to the hash value. All nodes in the linked list except the head node are stored in the hash table sub-table space, and the corresponding offset address is randomly assigned. The target hash table refers to the hash table sub-table in this method.

[0058] In order to further improve the efficiency of data storage by the DPU, after step 140, the following steps are further included:

[0059] Step 150: determining whether the number of remaining index data in the RAM target address space is greater than the preset first index data number based on the second RAM address pointer; if so, executing step 151; if not, executing step 152;

[0060] Step 151: If yes, then based on the second RAM address pointer, read the first preset number of index data in the RAM target address space and write them into the DDR target address space; add the value of the first DDR address pointer (i.e., ddr_point in Table 1) in the index parameter table to the value of the first preset number, and return the updated first DDR address pointer to the index parameter table; subtract the value of the first preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table;

[0061] Step 152: If not, return the second RAM address pointer to the index parameter table.

[0062] Specifically, DOE determines whether the number of remaining index data in the RAM target address space is more than the preset first index data number (3 / 4 of the total number of addresses in the RAM target address space) based on the second RAM address pointer; if so, based on the second RAM address pointer, read the first preset number (64) of index data in the RAM target address space and write them into the DDR target address space; add the value of the first preset number to the value of the first DDR address pointer in the index parameter table, and return the updated first DDR address pointer to the index parameter table; subtract the value of the first preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table; if not, return the second RAM address pointer to the index parameter table, thereby further improving the efficiency of DPU in data storage.

[0063] In order to effectively obtain index data, the index data recovery and allocation method in the aforementioned hash table also includes:

[0064] Step 160: Based on the received index application instruction input by the user, read the third RAM address pointer in the index parameter table corresponding to the user;

[0065] Step 170: Read the index data in the RAM target address space based on the third RAM address pointer; and subtract 1 from the value of the third RAM address pointer to obtain a fourth RAM address pointer.

[0066] Specifically, see Figure 3 Based on the index application instruction received from the user, the DPU reads the third RAM address pointer in the index parameter table corresponding to the user; then reads the index data in the RAM target address space based on the third RAM address pointer; and subtracts 1 from the value of the third RAM address pointer to obtain the fourth RAM address pointer, thereby effectively obtaining the index data.

[0067] In order to further effectively obtain index data, after step 170, the following steps are further included:

[0068] Step 180: Based on the fourth RAM address pointer, determine whether the number of remaining index data in the RAM target address space is less than the preset second index data number; if so, execute step 181; if not, execute step 182.

[0069] Step 181: If yes, based on the second DDR address pointer in the index parameter table, read the second preset number of index data in the DDR target address space and write them into the RAM target address space; subtract the value of the second preset number from the value of the second DDR address pointer, and return the updated second DDR address pointer to the index parameter table; add the value of the second preset number to the fourth RAM address pointer, and return the updated fourth RAM address pointer to the index parameter table.

[0070] Step 182: If not, return the fourth RAM address pointer to the index parameter table.

[0071] Specifically, DOE determines whether the number of remaining index data in the RAM target address space is less than the preset second index data number (1 / 4 of the total number of addresses in the RAM target address space) based on the fourth RAM address pointer; if so, based on the second DDR address pointer in the index parameter table, read the second preset number (64) of index data in the DDR target address space and write them into the RAM target address space; subtract the value of the second preset number from the value of the second DDR address pointer, and return the updated second DDR address pointer to the index parameter table; add the value of the second preset number to the fourth RAM address pointer, and return the updated fourth RAM address pointer to the index parameter table. If not, return the fourth RAM address pointer to the index parameter table, so that the index data can be further effectively obtained.

[0072] In order to effectively improve the storage efficiency of index data when hash conflicts occur, the index data recovery and allocation method in the aforementioned hash table also includes:

[0073] If a hash conflict occurs when inserting target index data into the target hash master table, the target index data is written to the RAM target address space.

[0074] Specifically, when a hash conflict occurs when inserting instruction data into the target hash master table, the hash engine module in DOE writes the instruction data into the RAM target address space, thereby effectively improving the storage efficiency of index data during hash conflicts.

[0075] In order to improve DPU performance, if the number of remaining index data in the RAM target address space is less than a preset third number of index data, based on the second DDR address pointer, the third preset number of index data in the DDR target address space is read and written into the RAM target address space.

[0076] Specifically, if the number of remaining index data in the RAM target address space is less than the preset third index data number (optionally 32), the DPU reads the third preset number (optionally 64) of index data in the DDR target address space based on the second DDR address pointer and writes it to the RAM target address space, thereby effectively improving the DPU performance.

[0077] In order to further improve DPU performance, if the number of remaining index data in the RAM target address space is more than the preset fourth index data number, based on the second RAM address pointer, the fourth preset number of index data in the RAM target address space is read and written into the DDR target address space.

[0078] Specifically, if the number of remaining index data in the RAM target address space is more than the preset fourth index data number (which can be 224), then based on the second RAM address pointer, the fourth preset number (which can be 64) of index data in the RAM target address space is read and written into the DDR target address space, thereby further effectively improving the DPU performance.

[0079] From the software level, the present application also provides a device for recovering and allocating index data in a hash table for executing all or part of the method for recovering and allocating index data in a hash table, see Figure 2 The index data recovery and allocation device in the hash table specifically includes the following contents:

[0080] The address space allocation module 10 is used to allocate a RAM target address space for the target hash table in the current RAM; and allocate a DDR target address space for the target hash table in the DDR.

[0081] The index data migration module 20 is used to allocate each index data to be recovered in the target hash table to the DDR target address space; read a preset number of the index data from the DDR target address space and write them to the RAM target address space.

[0082] The parameter retrieving module 30 is used to read the first RAM address pointer in the index parameter table corresponding to the user based on the index recovery instruction received from the user.

[0083] The index writing module 40 is used to write the target index data pre-read from the RAM target address space into the RAM target address space based on the first RAM address pointer in the index parameter table; and add 1 to the value of the first RAM address pointer to obtain a second RAM address pointer.

[0084] In some embodiments of the present application, the index data recovery and allocation device in the aforementioned hash table further includes:

[0085] An index determination module is used to determine whether the number of remaining index data in the target address space is greater than a preset first index data number based on the second RAM address pointer.

[0086] An index recovery module is used to, if yes, read a first preset number of index data in the RAM target address space and write them into the DDR target address space based on the first DDR address pointer in the index parameter table; add the value of the first DDR address pointer to the value of the second preset number, and return the updated first DDR address pointer to the index parameter table; subtract the value of the second preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table.

[0087] The parameter returning module is used for returning the second RAM address pointer to the index parameter table if no.

[0088] The embodiment of the index data recovery and allocation device in the hash table provided in the present application can be specifically used to execute the processing flow of the embodiment of the index data recovery and allocation method in the hash table in the above-mentioned embodiment. Its functions will not be repeated here, and reference can be made to the detailed description of the embodiment of the index data recovery and allocation method in the hash table mentioned above.

[0089] The embodiment of the present application also provides a DPU, which is provided with a database offload engine (DOE), and the database offload engine is used to execute the index data recovery and allocation method in the aforementioned hash table.

[0090] The present application provides an index data recovery and allocation device in a hash table, and the method executed by the device includes: allocating a RAM target address space for a target hash table in the current RAM; allocating a DDR target address space for a target hash table in the DDR; allocating each index data to be recovered in the target hash table to the DDR target address space; reading a preset number of the index data from the DDR target address space and writing them to the RAM target address space; based on the index recovery instruction received from the user input, reading the first RAM address pointer in the index parameter table corresponding to the user; based on the first RAM address pointer in the index parameter table, writing the target index data pre-read from the RAM target address space to the RAM target address space; and adding 1 to the value of the first RAM address pointer to obtain a second RAM address pointer. The present application can effectively improve the efficiency of DPU in data storage and reduce the data storage pressure of DPU.

[0091] It should be understood by those skilled in the art that the exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is specifically performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0092] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0093] In the present application, features described and / or illustrated for one embodiment may be used in the same manner or in a similar manner in one or more other embodiments, and / or combined with features of other embodiments or replace features of other embodiments.

[0094] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for recovering and allocating index data in a hash table, characterized in that: include: Allocate RAM target address space for the target hash table in the current RAM; Allocate DDR target address space for the target hash table in DDR; Allocating each index data to be recovered in the target hash table to the DDR target address space; Reading a preset amount of the index data from the DDR target address space and writing the index data to the RAM target address space; Based on the received index recovery instruction input by the user, read the first RAM address pointer in the index parameter table corresponding to the user; writing the target index data pre-read from the RAM target address space into the RAM target address space based on the first RAM address pointer in the index parameter table; And add 1 to the value of the first RAM address pointer to obtain a second RAM address pointer; After adding 1 to the value of the first RAM address pointer parameter to obtain the second RAM address pointer, the method further includes: Determining whether the number of remaining index data in the RAM target address space is greater than the preset first index data number based on the second RAM address pointer; If yes, based on the second RAM address pointer, read the first preset number of index data in the RAM target address space and write them into the DDR target address space; add the value of the first preset number to the value of the first DDR address pointer in the index parameter table, and return the updated first DDR address pointer to the index parameter table; subtract the value of the first preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table; If not, return the second RAM address pointer to the index parameter table.

2. The index data recovery and allocation method in a hash table according to claim 1, characterized in that: Also includes: Based on the received index application instruction input by the user, read the third RAM address pointer in the index parameter table corresponding to the user; Reading index data in the RAM target address space based on the third RAM address pointer; And the value of the third RAM address pointer is reduced by 1 to obtain a fourth RAM address pointer.

3. The index data recovery and allocation method in a hash table according to claim 2, characterized in that: After the value of the third RAM address pointer is reduced by 1 to obtain the fourth RAM address pointer, the method further includes: Determining whether the number of remaining index data in the RAM target address space is less than a preset second index data number based on the fourth RAM address pointer; If yes, based on the second DDR address pointer in the index parameter table, read the second preset number of index data in the DDR target address space and write them into the RAM target address space; subtract the value of the second preset number from the value of the second DDR address pointer, and return the updated second DDR address pointer to the index parameter table; add the value of the second preset number to the fourth RAM address pointer, and return the updated fourth RAM address pointer to the index parameter table; If not, return the fourth RAM address pointer to the index parameter table.

4. The index data recovery and allocation method in a hash table according to claim 1, characterized in that: Also includes: If a hash conflict occurs when inserting target index data into the target hash master table, the target index data is written to the RAM target address space.

5. The index data recovery and allocation method in a hash table according to claim 3, characterized in that: If the number of remaining index data in the RAM target address space is less than a preset third number of index data, based on the second DDR address pointer, a third preset number of index data in the DDR target address space is read and written into the RAM target address space.

6. The index data recovery and allocation method in a hash table according to claim 1, characterized in that: If the remaining index data in the RAM target address space is greater than a fourth preset index data number, based on the second RAM address pointer, a fourth preset number of index data in the RAM target address space is read and written into the DDR target address space.

7. An index data recovery and allocation device in a hash table, characterized in that: include: An address space allocation module, for allocating a RAM target address space for a target hash table in the current RAM; Allocate DDR target address space for the target hash table in DDR; An index data migration module, used for allocating each index data to be recovered in the target hash table to the DDR target address space; Reading a preset amount of the index data from the DDR target address space and writing the index data to the RAM target address space; A parameter retrieving module, configured to read a first RAM address pointer in the index parameter table corresponding to the user based on the index recovery instruction received from the user; An index writing module, configured to write target index data pre-read from the RAM target address space into the RAM target address space based on a first RAM address pointer in the index parameter table; And add 1 to the value of the first RAM address pointer to obtain a second RAM address pointer; The index data recovery and allocation device in the hash table also includes: An index determination module, configured to determine whether the number of remaining index data in the target address space is greater than a preset first index data number based on the second RAM address pointer; an index recovery module, configured to, if yes, read a first preset number of index data in the RAM target address space based on the first DDR address pointer in the index parameter table and write the index data into the DDR target address space; add the value of the first preset number to the value of the first DDR address pointer, and return the updated first DDR address pointer to the index parameter table; subtract the value of the first preset number from the second RAM address pointer, and return the updated second RAM address pointer to the index parameter table; The parameter returning module is used for returning the second RAM address pointer to the index parameter table if no.

8. A DPU, provided with a database offloading engine, characterized in that: The database unloading engine is used to execute the index data recovery and allocation method in the hash table described in any one of claims 1-6.

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