Low latency bridge supporting out-of-order execution

Abstract

This document describes systems and techniques for low latency bridges that support out-of-order execution. The described systems and techniques can facilitate out-of-order execution of a memory controller for in-order transaction requests. When it receives a transaction response associated with an in-order transaction request, the bridge can send a first transaction response without storing it in a re-order buffer. Similarly, the bridge can determine whether a next transaction response is available for sending to a corresponding client. The bridge only introduces latency to a larger system (e.g., SoC) when a secondary response (e.g., non-first) of an in-order transaction response is first received. In this way, the memory controller can handle transaction requests from one or more clients with minimal latency introduced by the bridge and a smaller re-order buffer.

Description

Technical Field

[0001] This application relates to methods and apparatus for using low-latency bridges to support out-of-order execution. Background Technology

[0002] Processors such as Central Processing Units (CPUs) and Systems-on-Chip (SoCs) are capable of operating using out-of-order execution (sometimes called dynamic execution) to utilize instruction cycles that would otherwise be wasted. Out-of-order execution causes the processor to execute instructions in an order governed by the availability of input data and execution units, rather than by their original order in the program. Out-of-order execution can increase the amount of parallel processing and improve processor throughput. However, out-of-order execution is not always possible because some clients (sometimes called initiators or hosts) issue in-order transaction requests or commands. Some processors use a bridge between the clients and the memory system to accept in-order requests but support out-of-order execution toward the memory system. Such bridges typically add latency during the in-order-to-out-of-order transition, resulting in reduced processor throughput. Summary of the Invention

[0003] This document describes systems and techniques for low-latency bridges that support out-of-order execution. The described systems and techniques facilitate out-of-order execution of memory controllers with ordered transaction requests. When it receives a transaction response associated with an ordered transaction request, the bridge is able to send the first transaction response without storing it in a reordering cache. Similarly, the bridge is able to determine whether the next transaction response is available to be sent to the appropriate client. The bridge only introduces latency into the larger system (e.g., a SoC) if it receives a secondary response (e.g., a non-first) that precedes the ordered transaction response. In this way, the memory controller is able to handle transaction requests from one or more clients with the lowest possible latency introduced by the bridge and the smaller reordering cache.

[0004] For example, the apparatus includes a bridge and a memory controller. The memory controller is operatively connected to one or more memories (e.g., random access memory (RAM)). The memory controller is capable of processing transaction requests from one or more clients to access data in the memory. The bridge is operatively connected to the memory controller and the clients. The bridge includes a reordering cache and is capable of receiving transaction requests from a first client. The bridge is also capable of receiving transaction responses from the memory controller to return them in an ordered manner to the first client. Each transaction response is associated with a corresponding transaction request. In response to receiving a first transaction response, the bridge is capable of sending the data associated with the first transaction response to the first client and bypassing the storage of data in the reordering cache.

[0005] As another example, a method includes receiving multiple transaction requests from a first client, one of one or more clients, by a bridge. The bridge is operatively connected to the clients and includes a reordering cache. The method also includes receiving multiple transaction responses from a memory controller by the bridge. Each transaction response is associated with a corresponding transaction request. The bridge is capable of returning the multiple transaction responses to the first client in an ordered manner. The memory controller is operatively connected to one or more memories and is capable of processing transaction requests from clients to access data in the memories. The method further includes, in response to receiving a first transaction response among the multiple transaction responses, sending data associated with the first transaction response to the first client and bypassing the storage of data in the reordering cache.

[0006] This document also describes other methods, configurations, and systems for low-latency bridges that support out-of-order execution.

[0007] This invention provides a simplified concept for a low-latency bridge to support out-of-order execution, which will be further described in the following detailed description and accompanying drawings. This invention is not intended to identify essential features of the claimed subject matter, nor is it intended to define the scope of the claimed subject matter. Attached Figure Description

[0008] Referring to the following figures, details of one or more aspects of a low-latency bridge that supports out-of-order execution are described in this document. The same numbers are used throughout the figures to refer to the same features and components.

[0009] Figure 1 An example device diagram of a user equipment is shown, illustrating a system and technology that enables low-latency bridges to support out-of-order execution.

[0010] Figure 2 An example device diagram of a SoC is shown, illustrating a system and techniques for implementing low-latency bridges to support out-of-order execution.

[0011] Figure 3 An example diagram of a memory subsystem with a low-latency bridge that supports out-of-order execution is shown.

[0012] Figure 4 An example linked list is shown that supports the described low-latency bridge for out-of-order execution.

[0013] Figure 5-1 and 5-2 Example data associated with a transaction request and a transaction response for a low-latency bridge that supports out-of-order execution are shown.

[0014] Figure 6 A flowchart illustrating an example operation of a low-latency bridge that supports out-of-order execution in response to transaction requests is shown.

[0015] Figure 7 A flowchart illustrating an example operation of a low-latency bridge that supports out-of-order execution in response to transaction responses is shown.

[0016] Figure 8 This is a flowchart illustrating an example operation of a low-latency bridge that supports out-of-order execution.

[0017] Figure 9 An example SoC is shown that can implement various aspects of the described low-latency bridge that supports out-of-order execution. Detailed Implementation

[0018] Overview

[0019] This document describes systems and technologies for low-latency bridges that support out-of-order execution. Processors can issue transaction requests to the memory system in either an ordered or out-of-order manner. Processors utilize out-of-order execution to avoid wasted instruction cycles and reduced processor throughput. However, as mentioned above, out-of-order execution may be impossible because some clients issue ordered transaction requests and are not configured to handle out-of-order transaction responses. Therefore, some processors are able to use a bridge between the client and the memory subsystem to accept ordered requests but support out-of-order execution of the memory subsystem.

[0020] Some bridges add latency during ordered-to-outorder processing. These, along with others, require relatively large reordering caches. For example, engineers often resize reordering caches to store the maximum number of potentially incomplete transaction requests.

[0021] Conversely, the systems and techniques described for low-latency bridges support the out-of-order execution of ordered transaction requests with minimal or at least reduced latency. When it receives a transaction response associated with an ordered transaction request, the bridge is able to send the first transaction response without storing it in a reordering cache. Similarly, the bridge is able to determine whether the next transaction response is available to send to the appropriate client. The described low-latency bridge adds minimal latency to processor throughput because latency is typically only added when a secondary response to an ordered transaction request is received before the primary response. The bridge is also able to handle transaction requests from clients by sending the transaction response corresponding to the head (or head pointer) of the linked list to the appropriate client without caching the data of the head element.

[0022] As a non-limiting example, the apparatus or memory subsystem includes a memory controller and a bridge. The memory controller is operatively connected to one or more memories (e.g., RAM) and the bridge. The bridge is operatively connected to one or more clients. The memory controller is capable of processing transaction requests from clients to access data in memory. The bridge is capable of receiving transaction requests from a first client, the transaction requests including transaction requests to be returned in an ordered manner. The bridge is also capable of receiving transaction responses associated with the corresponding transaction requests from the memory controller. The transaction responses are returned in an ordered manner by the bridge to the first client. In response to receiving a first transaction response, the bridge is capable of sending the data associated with the first transaction response to the first client and bypassing the storage of data in a reordering cache.

[0023] This example is merely an illustration of a low-latency bridge that supports out-of-order execution to improve processor throughput or reduce bridge resource requirements. Other example configurations and methods are described throughout this document. This document describes additional example methods, configurations, and components for the described low-latency bridge to support out-of-order execution.

[0024] Example device

[0025] Figure 1 An example device diagram 100 of user equipment 102 is shown, illustrating systems and techniques capable of implementing a low-latency bridge 116 to support out-of-order execution. For clarity, user equipment 102 may include components from... Figure 1 Omitted additional components and interfaces.

[0026] User equipment 102 can be various consumer electronic devices. As a non-limiting example, user equipment 102 can be a mobile phone 102-1, a tablet device 102-2, a laptop computer 102-3, a desktop computer 102-4, a computerized watch 102-5, a wearable device 102-6, a portable video game console 102-7, or a voice assistant system 102-8.

[0027] User equipment 102 may include one or more radio frequency (RF) transceivers 104 for communicating over a wireless network. User equipment 102 may tune the RF transceivers 104 and supporting circuitry (e.g., antennas, front-end modules, amplifiers) to one or more frequency bands defined by various communication standards.

[0028] User equipment 102 also includes a SoC 106. The SoC 106 typically integrates several components of user equipment 102 into a single chip, including a central processing unit, memory, and input / output ports. The SoC 106 can include a single core or multiple cores. In the depicted embodiment, the SoC 106 includes one or more clients 108 and a memory subsystem 110. The SoC 106 can include other components, including communication units (e.g., a modem), input / output controllers, and system interfaces.

[0029] Client 108 provides transaction requests to read or write data to random access memory (RAM) 112 of memory subsystem 110. As a non-limiting example, client 108 may include the display system, graphics processing unit, central processing unit, communication unit, input / output controller, and system interface of SoC 106.

[0030] The memory subsystem 110 includes RAM 112, a memory controller 114, and a bridge 116. RAM 112 is a suitable storage device (e.g., static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), synchronous dynamic RAM (SDRAM)) for storing data accessible to client 108. In other embodiments, RAM 112 may be located external to SoC 106.

[0031] Memory controller 114 manages transaction requests from client 108 to RAM 112. Memory controller 114 can cache and serve transaction requests to RAM 112 to increase the bandwidth of memory subsystem 110. Specifically, memory controller 114 can schedule transaction requests to improve the bandwidth of the interface between RAM 112 and memory controller 114. Memory controller 114 can include hardware, firmware, software, or a combination thereof.

[0032] Bridge 116 can analyze transaction requests and identify the degree of reordering of transaction requests for a specific client 108. Bridge 116 can use cache 118 to temporarily store transaction requests or responses from client 108. By using reorder cache 118 for this dynamic reordering, bridge 116 can reduce the cache space of reorder cache 118 to support ordered execution. In this way, bridge 116 can minimize the introduced latency. Bridge 116 can comprise hardware, firmware, software, or a combination thereof.

[0033] structure( Figure 1(Not shown) is operably connected to client 108 via a corresponding virtual channel. The architecture is capable of forwarding transaction requests from client 108 to memory controller 114. In some embodiments, the architecture is a multiplexer. Bridge 116 can be implemented within the architecture, in any or all clients 108, as a standalone component within SoC 106, or as a standalone component outside of SoC 106.

[0034] User equipment 102 also includes a computer-readable storage medium (CRM) 120. CRM 120 is a suitable storage device (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), read-only memory (ROM), flash memory) for storing device data of user equipment 102. Device data can include an operating system, one or more applications, user data, and multimedia data. In other embodiments, CRM 120 can store a subset of the operating system and applications, user data, and multimedia data of SoC 106.

[0035] The operating system typically manages the hardware and software resources of user equipment 102 and provides public services. The operating system and applications can typically be executed by SoC 106 to enable communication and user interaction with user equipment 102, which may require access to data in RAM 112 of memory subsystem 110.

[0036] Figure 2 An example device diagram 200 of SoC 106 is shown, illustrating systems and techniques for implementing low-latency bridges to support out-of-order execution. SoC 106 and memory subsystem 110 can include... Figure 2 Additional components not shown.

[0037] SoC 106 includes multiple clients 108 and a memory subsystem 110. In the depicted embodiment, clients 108 include client A 108-1, client B 108-2, and client C 108-3. SoC 106 is capable of including fewer or additional clients 108. In this example, clients 108 are located outside the memory subsystem 110. In other embodiments, clients 108 or a portion of clients 108 may be located within the memory subsystem 110.

[0038] As described above, client 108 can provide transaction requests to RAM 112 for reading or writing data. One or more clients 108 can provide ordered requests 202 and unordered requests 204 to memory subsystem 110. Ordered request 202 represents a transaction request that must normally be returned in sequential order. Unordered request 204 represents a transaction request that can normally be performed in any order and does not need to be returned in sequential order. In this example, client A 108-1's transaction request includes both ordered request 202 and unordered request 204. Although not shown, client B 108-2 can provide only ordered request 202, and client C 108-3 can provide only unordered request 204.

[0039] The memory subsystem 110 includes RAM 112, a memory controller 114, and a bridge 116. RAM 112 includes at least one storage device. In the depicted embodiment, RAM 112 includes two storage devices: SDRAM 206-1 and SDRAM 206-2. SDRAM 206-1 and SDRAM 206-2 are capable of storing data of client 108 or data accessible to client 108. SDRAM 206-1 and SDRAM 206-2 are operatively connected to the memory controller 114.

[0040] The memory controller 114 may include a cache 208. The cache 208 temporarily stores transaction requests from the client 108. The cache 208 or another component of the memory controller 114 may also send transaction requests to SDRAM 206-1 and SDRAM 2062 to increase bandwidth at the memory interface. The memory controller 114 may include... Figure 2 Additional components not shown.

[0041] Bridge 116 may include a reordering cache 118 and a controller 210. The reordering cache 118 may temporarily store ordered requests 202 from client 108 or out-of-order responses received from memory controller 114. Bridge 116 may use controller 210 to analyze transaction requests from a particular client 108 and determine the possible degree of reordering of those transaction requests. In this way, bridge 116 can limit its use of cache space in reordering cache 118 to the amount of cache space required to support the degree of ordering for a particular client 108. Additionally, by directly passing out-of-order requests 204 and portions of ordered requests 202 that can be executed out of order, controller 210 of bridge 116 reduces latency in memory subsystem 110 when executing transactions.

[0042] This document is about Figure 3 The operation of the memory subsystem 110 is described in more detail, specifically the operation of the bridge 116 and the controller 210.

[0043] Example configuration

[0044] This section describes an example configuration of a hardware-based memory subsystem with a low-latency bridge that supports out-of-order execution, which can occur individually or together, in whole or in part. Example configurations are described with reference to the accompanying drawings for ease of reading.

[0045] Figure 3 Example Figure 300 illustrates a memory subsystem 110 with a low-latency bridge supporting out-of-order execution. The memory subsystem 110 is capable of including... Figure 3 Additional components, not shown, include a reorder cache 118 and a controller 210. The memory subsystem 110 provides hardware implementations to minimize latency from the client 108 during out-of-order execution of transaction requests. The memory subsystem 110 also provides hardware implementations to minimize latency of the bridge 116's reorder cache 118 (…). Figure 3 (The size is not shown in the diagram). In this way, bridge 116 is able to increase the throughput of SoC 106.

[0046] Similar to Figure 2 The memory subsystem 110 includes one or more RAMs 112 (e.g., SDRAM 206-1 and SDRAM 206-2), a memory controller 114, a bridge 116, and one or more clients 108 (e.g., client A 108-1, client B 108-2, client C 108-3). The memory subsystem 110 also includes a structure 308. Clients 108 are operatively connected to structure 308 via an internal bus. This document refers to the internal bus as a virtual channel 302. Each virtual channel 302 can be assigned a unique identifier.

[0047] In the depicted embodiment, client A 108-1 is operatively connected to structure 308 via virtual channel 302-1. Client B 108-2 is operatively connected to structure 308 via virtual channel 302-2, and client C 108-3 is operatively connected to structure 308 via virtual channel 302-3.

[0048] Structure 308 is operably connected to memory controller 114 via internal bus 304. Structure 308 sends memory transactions from client 108 to memory controller 114 via internal bus 304. Memory controller 114 temporarily stores transaction requests in cache 208. Figure 3 (Not shown in the text)

[0049] Memory controller 114 is operably connected to SDRAM 206 via internal bus 306. In the depicted embodiment, memory controller 114 is operably connected to SDRAM 206-1 and 206-2 via internal buses 306-1 and 306-2, respectively. Memory controller 114 provides transaction requests to SDRAM 206 via the respective internal buses 306.

[0050] Bridge 116 can temporarily store ordered requests 202 from client 108 using reorder cache 118. Bridge 116 can analyze transaction requests from a specific client 108 and determine the possible reordering levels of those transaction requests. (Regarding...) Figure 4 The analysis of transaction requests is described in more detail. In this way, the reorder cache 118 can limit its cache space usage to the amount of cache space required to support the degree of ordering of a particular client 108. In addition, by directly passing a portion of the out-of-order request 204 and the ordered request 202 that can be executed out of order, the bridge 116 reduces the latency of the memory subsystem 110 when executing transactions.

[0051] In operation, bridge 116 is able to handle requests from client 108 and responses from memory subsystem 110 to improve the throughput of SoC 106. About Figure 6 This describes in more detail how bridge 116 handles transaction requests. (Regarding...) Figure 7 The bridge 116 handles transaction responses in more detail.

[0052] like Figure 3 As depicted, the memory subsystem 110 can implement the bridge 116 in hardware. In other embodiments, out-of-order execution of transaction requests can be implemented at least in some parts at the kernel level or driver level.

[0053] Figure 4 An example linked list structure 402 is shown that supports the described low-latency bridge for out-of-order execution. Figure 4 The bridge can be Figures 1 to 3 Bridge 116.

[0054] Bridge 116 is capable of receiving read requests (e.g., read request 404 and read request 406). Read requests with the same Request ID (ARID) require responses to arrive in the same order. For example, read request 404 includes read requests 404-1, 404-2, and 404-3. Read requests 404-1, 404-2, and 404-3 have ARIDs corresponding to “X” as indicated by linked list entry 402-1. Similarly, read request 406 includes read requests 406-1, 406-2, 406-3, 406-4, and 406-5, which have ARIDs corresponding to “Y” as indicated by linked list entry 402-2. Read requests with different ARIDs can have reordered responses. Responses associated with read requests having the same ARID are returned to the corresponding client 108 in an ordered manner.

[0055] Bridge 116 is able to maintain linked list 402 to track read requests and sort their corresponding responses. The number of entries in linked list 402 is typically equal to the number of clients operatively connected to memory subsystem 110 and bridge 116.

[0056] When bridge 116 receives a transaction request (e.g., read request 404-1), it checks the associated ARID according to bit flags to determine if a pending read request 404 with the same ARID exists. If a match is found, bridge 116 appends the current read request (e.g., read request 404-2) to a linked list entry (e.g., linked list entry 402-1) for the given ARID. For example, if bridge 116 receives read request 404-2 after previously receiving read request 404-1, it appends read request 404-2 to the linked list entry 402-1 associated with ARID X. If no match is found, bridge 116 assigns read request 404 to a new linked list entry associated with read request 404.

[0057] Figure 5-1 and 5-2 Example data associated with transaction request 500 and transaction response 508 for a low-latency bridge used to support out-of-order execution is shown. Figure 4 The bridge can be Figures 1 to 3 Bridge 116.

[0058] like Figure 5-1As shown, bridge 116 can receive transaction requests (REQ) 500 (e.g., read request 404 and read request 406). Transaction request 500 can include a request ID (ARID) and the address of the data being requested. In order to process ordered requests from the client when responses can be returned out of order from the memory controller, bridge 116 can generate one or more variables or data associated with each transaction request. Examples of such values ​​are ID flag (IDF) 502, request queue number (RQN) 504, and request queue element (RQE) 506. Transaction request 500 or associated data can include... Figure 5-1 Additional content not shown in the image.

[0059] ID flag 502 is the flag for the Request ID (ARID) of transaction request 500. ID flag 502 is typically a one-bit flag. ID flag 502 can be initialized on reset and all bits can be set to zero after reset.

[0060] For each incoming request ID (ARID), bridge 116 stores the request queue number 504 of transaction request 500. Request queue number 504 indicates the sequence number (e.g., order) of transaction requests 500 within a group of transaction requests with the same ARID. Bridge 116 uses request queue number 504 to determine the order of transaction responses 508 associated with transaction request 500. Request queue number 504 provides a run counter for each ARID. The depth of request queue number 504 can be equal to the depth of two read data cache (RDB) elements 512 (e.g., 2^(RDB depth bits)). The counter for request queue number 504 can run from zero to its width minus one (e.g., 2^(RDB depth bits) - 1).

[0061] Bridge 116 stores the context associated with transaction request 500 in request queue element 506. Bridge 116 typically stores only the context required for reordering transaction response 508 and can omit other contexts to reduce memory requirements. In the example implementation, the bridge does not store the head or first element of any linked list in the reorder cache 118 to reduce latency or lower storage requirements (or both).

[0062] like Figure 5-2 As shown, bridge 116 can transmit a transaction response (RSP) 508 to the corresponding client. The transmission response 508 can include the accessed ARID or address and the data retrieved in response to the request. To handle out-of-order responses, bridge 116 can create a response sequence number (RSN) 510 and a read data buffer (RDB) element 512. The transmission response 508 can include... Figure 5-2 Additional content not shown in the image.

[0063] Response sequence number 510 indicates the sequence number of transaction response 508 within a group of transaction responses with the same ARID. Bridge 116 uses response sequence number 510 to determine the order of transaction responses 508. Response sequence number 510 provides a run counter for each ARID. The depth of response sequence number 510 is equal to the depth of two read data cache (RDB) elements 512 (e.g., 2^(RDB depth bits)). The counter used for response sequence number 510 is capable of running from zero to its width minus one (e.g., 2^(RDB depth bits) - 1).

[0064] Bridge 116 stores the read data cache element 512 corresponding to the read data associated with transaction response 508 in the reorder cache 118. Bridge 116 typically only stores read data associated with the reordered transaction response 508. The head or first element of any linked list is not stored in the reorder cache 118. Bridge 116 checks the response sequence number 510 to identify whether the incoming transaction response 508 is the head or first response of the linked list.

[0065] Figure 6 A flowchart of example operation 600 of a low-latency bridge that supports out-of-order execution in response to transaction requests is shown below. Figures 1 to 3 Operation 600 is described within the context of bridge 116. Operation 600 can be used with... Figure 6 The order shown may differ from the order shown, or may be performed with additional or fewer operations.

[0066] At 602, bridge 116 receives transaction requests. For example, client A 108-1 can send a read request to access data in SDRAM 206-1.

[0067] At 604, bridge 116 checks the request ID (ARID) of the transaction request according to the bit flag (IDF) to determine whether there is an pending transaction request with the same request ID. For example, bridge 116 can check whether the ID flag associated with the request ID is equal to 1 (e.g., IDF[ARID] == 1) or another value associated with the first transaction request in the ordered set of transaction requests.

[0068] At 606, if no ARID match is found, bridge 116 sets the value of the bit flag (IDF) and sets the value of the request ID (ARID) (e.g., out ID = {1, ARID, 0}).

[0069] At 608, operation 600 ends. At 610, if an ARID match is found, bridge 116 checks the availability of free IDs (e.g., free space) in the ID manager (IDM) (e.g., controller 210). If the outgoing transaction request is not the head or first item of a given linked list, the IDM assigns a free ID to the outgoing transaction request (e.g., a received read request is sent to memory controller 114). The free ID can uniquely represent a transaction request within a linked list.

[0070] At position 612, if a free ID is unavailable, bridge 116 waits for a free ID. For example, if no free ID is available, the transaction request is stopped.

[0071] At 614, if an idle ID is available, bridge 116 determines whether the linked list is being deallocated in the same cycle.

[0072] At 616, if the linked list has not been deallocated within the same cycle, bridge 116 selects an ID from the IDM. Bridge 116 appends the current transaction request to the linked list entry for the given ARID and increments the request queue number (RQN) incrementally (e.g., RQN[ARID] = RQN[ARID] + 1). The context or data associated with the current transaction request is stored in the request queue element (RQE) (e.g., RQE[IDM_ID] = {curr_seq_num, prev_tail_ptr, 1}). Additionally, the outID is set (e.g., outID = {0, ARID, IDM_ID}). Upon completion, bridge 116 proceeds to operation 608 and operation 600 ends.

[0073] If the linked list is not deallocated within the same cycle, bridge 116 performs operation 606. Specifically, bridge 116 sets the values ​​of the bit flag (IDF) and the request ID (ARID) (e.g., out ID = {1, ARID, 0}).

[0074] Figure 7 A flowchart of example operation 700 of a low-latency bridge that supports out-of-order execution in response to transaction responses is shown below. Figures 1 to 3 Operation 700 is described within the context of bridge 116. Operation 700 can be used with... Figure 7 The order shown may differ from the order shown, or may be performed with additional or fewer operations.

[0075] At 702, bridge 116 receives a transaction response. For example, memory controller 114 can send a read response from SDRAM 206-1 intended for client A 108-1.

[0076] At 704, bridge 116 determines whether the response sequence number (RSN) is equal to one (e.g., RSN[MSB] == 1?). For example, bridge 116 determines whether the transaction response is the head or first response of the linked list. Bridge 116 is also able to determine whether the transaction response is the next response in the linked list to be sent to client A 108-1. The response sequence number indicates the order in which transaction responses will be returned to client A 108-1.

[0077] At 706, if RSN is not equal to 1, bridge 116 writes the transaction response data to reorder cache 118. Bridge 116 is also able to mark entries associated with RSN as available.

[0078] At point 708, operation 700 ends.

[0079] At 710, if RSN equals one, bridge 116 sends the transaction response without storing it in reordering cache 118. For example, the transaction response can be sent to client A 108-1 and the storage of the transaction response is avoided (e.g., no cache).

[0080] At position 712, bridge 116 increments the response counter by one.

[0081] At 714, bridge 116 determines whether the next entry in the linked list is available. If the next entry is not available, operation 700 ends at operation 708.

[0082] At 716, if the next entry in the linked list is available, bridge 116 reads the response data from reordering cache 118 and sends the response to the corresponding client. Bridge 116 is also able to increment the response counter by one. Then, bridge 116 repeats operation 714 to check if the next entry in the linked list is available.

[0083] Example Method

[0084] Figure 8 This is a flowchart illustrating example operation 800 of a low-latency bridge that supports out-of-order execution. Figures 1 to 7 Operation 800 is described within the context of the memory subsystem 110. Operation 800 may be performed in a different order or with additional or fewer operations.

[0085] At 802, the bridge receives multiple transaction requests from a first client among one or more clients. The bridge is operatively connected to the device's memory controller and includes a reordering cache. The memory controller is operatively connected to one or more memories and processes transaction requests from one or more clients to access data in one or more memories. For example, the device can be a user equipment 102 including a SoC 106 with a memory subsystem 110. The device can also be a SoC 106 embedded in the user equipment 102. The memory subsystem 110 includes a memory controller 114 operatively connected to RAM 112. The memory controller 114 is capable of processing transaction requests from client 108, including ordered requests 202 and out-of-order requests 204, to access data in RAM 112. The memory subsystem 110 also includes a bridge 116, which includes a reordering cache 118 operatively connected to the memory controller 114 and client 108. The bridge 116 is capable of receiving transaction requests from client A 108-1.

[0086] At 804, multiple transaction responses can be received from the memory controller. Each transaction response is associated with a corresponding transaction request and will be returned in order by the bridge to the first client. For example, bridge 116 can receive transaction responses from memory controller 114. Each transaction response is associated with a corresponding transaction request. Bridge 116 returns the transaction responses in order to client A 108-1.

[0087] At 806, in response to receiving a first transaction response, data associated with the first transaction response is sent to the first client. The data is sent by the bridge and bypasses storage in the reordering cache. For example, in response to receiving the first transaction response out of a plurality of transaction responses, bridge 116 sends data associated with the first transaction response to client A108-1 and bypasses storage of data in reordering cache 118.

[0088] Bridge 116 is capable of transmitting multiple transaction responses to client A 108-1 based on response sequence numbers assigned to the transaction responses. The response sequence numbers indicate the order in which the transaction responses will be returned to client A 108-1. Upon receiving each transaction response from memory controller 114, bridge 116 is capable of determining the response sequence number associated with the transaction response. If the response sequence number corresponding to the transaction response is first (e.g., equal to 1) and is the head element of a linked list or the first transaction response, bridge 116 is capable of sending the data associated with the transaction response to client A 108-1. If the response sequence number not corresponding to a transaction response is the first or head entry of a linked list, bridge 116 is capable of writing the data associated with the transaction response to reorder cache 118 and marking the response sequence number as available for transmission to client A 108-1. Bridge 116 can also send data associated with the first transaction response to client A 108-1 without storing the data in reorder cache 118, based on the absence of a related out-of-order transaction request in reorder cache 118.

[0089] In response to sending a first transaction response to client A 108-1, bridge 116 is able to determine whether a second transaction response with a response sequence number corresponding to the second transaction response that is second (e.g., equal to two) is available to be sent to client A 108-1. In response to determining that the second transaction response is available to be sent to client A 108-1, bridge 116 is able to read the data associated with the second transaction response from reordering cache 118. Bridge 116 is then able to send the data associated with the second transaction response to client A 108-1 and increment the response counter value by one. The response counter value has an incrementing value (e.g., from one) and indicates the next transaction response to be sent to client A 108-1. The response sequence number and the response counter value are associated with a request identifier (ARID) indicating an ordered set of transaction requests to be returned by bridge 116.

[0090] In other implementations, and in response to receiving each transaction response from memory controller 114, bridge 116 is able to determine a response sequence number associated with the transaction response. The bridge is also able to determine a response counter value indicating the next transaction response to be sent to client A108-1. The response counter value increments incrementally (e.g., from one). In response to a response sequence number equal to the response counter value, bridge 116 is able to send the data associated with the transaction response to client A108-1. In response to a response sequence number not equal to the response counter value, bridge 116 is able to write the data associated with the transaction response to reorder cache 118 and mark the response sequence number as available for transmission to client A108-1.

[0091] In response to sending the first transaction response to client A 108-1, bridge 116 increments the response counter value by one. Bridge 116 then determines whether another transaction response with a response sequence number equal to the response counter value is available to be sent to client A 108-1. Upon determining that another transaction response with a response sequence number equal to the response counter value is available to be sent to client A 108-1, bridge 116 reads the data associated with the other transaction response from the reordering cache 118. Bridge 116 then sends the data associated with the other transaction response to client A 108-1 and increments the response counter value by one.

[0092] In response to receiving a first transaction request from client A 108-1, bridge 116 can determine the request identifier associated with the first transaction request. Bridge 116 can then determine whether the request identifier matches the request identifier of another transaction request pending in memory subsystem 110. In response to determining that the request identifier matches the request identifier of another transaction request pending in memory subsystem 110, bridge 116 can append the first transaction request to the linked list associated with the request identifier. Bridge 116 can also determine whether a response sequence number is available for the first transaction request. In response to determining that a response sequence number is available for the first transaction request, bridge 116 can assign a first response sequence number to the first transaction request. The first response sequence number can have a value that is incrementally greater than the response sequence number of the other transaction request. In response to determining that a response sequence number is not available for the first transaction request, bridge 116 can stop the execution of the first transaction request until a response sequence number becomes available.

[0093] In response to a determination that the request identifier does not match the request identifier of another transaction request pending in memory subsystem 110, bridge 116 can assign a value to an identifier flag of the request identifier associated with the first transaction request. The identifier flag can be a one-bit flag for the request identifier associated with the first transaction request. The identifier flag can be initialized and changed to zero after being reset by bridge 116.

[0094] Example devices and systems

[0095] Figure 9 An example SoC 900 is shown that can implement various aspects of the described low-latency bridge supporting out-of-order execution. The SoC 900 can be embodied as shown in the reference. Figures 1 to 8 Any type of user equipment 102, user equipment, apparatus, other device, or system described herein is intended to implement aspects of the described low-latency bridge. Although described with reference to a chip-based package, Figure 9The components shown can also be represented by other system or component configurations, such as FPGA, ASIC, Application Standard Product (ASSP), Digital Signal Processor (DSP), Complex Programmable Logic Device (CPLD), System-in-Package (SiP), Stack-in-Package (PoP), Processing and Communication Chipsets, Communication Coprocessors, Sensor Coprocessors, etc.

[0096] In this example, the SoC 900 includes one or more application processors 902 (e.g., processor cores) that process various computer-executable instructions to control the operation of the SoC 900 and implement techniques for the described low-latency bridge (e.g., bridge 116). Alternatively or additionally, the SoC 900 may use a combination of processing and control circuitry ( Figure 9 The SoC900 may be implemented using any one or a combination of hardware, firmware, or fixed logic circuitry (not shown). Although not shown, the SoC900 may also include structures of various components within a bus, interconnect, cross switch, or coupling system.

[0097] SoC 900 also includes information about Figures 1 to 8 The memory subsystem 110 described is similar to or the same as memory subsystem 904. Memory subsystem 904 includes memory 906 (e.g., a computer-readable storage medium), one or more memory circuits such as those enabling persistent or non-transitory data storage, and therefore does not include transient signals or carriers. Examples of memory 906 include RAM, non-volatile memory (e.g., ROM, EPROM, EEPROM, etc.), or flash memory. Memory 906 provides data storage for system data 908, as well as firmware 910, applications 912, and any other types of information or data related to various aspects of the operation of SoC 900. For example, firmware 910 can be maintained as processor-executable instructions of an operating system (e.g., a real-time OS) within memory 906 and executed on application processor 902.

[0098] Application 912 may include a system manager, such as any form of control application, software application, signal processing and control module, system-specific native code, abstraction module, or gesture module, etc. Memory 906 may also store system components or utilities used to implement various aspects of the described low-latency bridge.

[0099] The memory subsystem 904 also includes a memory controller 114 and a bridge 116 implemented according to one or more aspects of the described low-latency bridge. Typically, the memory controller 114 and bridge 116 are coupled between the application processor 902 and a functional block (e.g., client 108) of the SoC 900 to implement the techniques and methods of the described bridge 116. In this example, the SoC 900 also includes various functional blocks or processors 914 to 926, any one of which can be implemented as client 108, which issues ordered or unordered transaction requests to the memory subsystem 904 for processing by the bridge 116 as described herein.

[0100] like Figure 9 As shown, the SoC 900 includes a communication transceiver 914 and a wireless modem 916 capable of implementing wired or wireless communication of system data 908 (e.g., received data, data being received, data scheduled for broadcasting, packetization, etc.). In some aspects, the wireless modem 916 is a multi-mode, multi-band modem or baseband processor configurable to communicate according to various communication protocols or in different frequency bands. The wireless modem 916 may include a transceiver interface (not shown) for transmitting coded or modulated signals to transceiver circuitry (e.g., RF transceiver 104).

[0101] The SoC 900 may include one or more data inputs 918, through which it can receive any type of data, media content, or input, such as user input, user-selectable input (explicit or implicit), or any other type of audio, video, or image data received from content or a data source. Alternatively or additionally, the data inputs 918 may include a variety of data interfaces, which may be implemented as serial or parallel interfaces, wireless interfaces, network interfaces, and any one or more of any other type of communication interface capable of communicating with other devices or systems.

[0102] The SoC 900 also includes an additional processor or coprocessor (e.g., Figures 1 to 8The SoC 900 includes a client 908 to implement other functionalities, such as a graphics processor 920, an audio processor 922, and an image sensor processor 924. The graphics processor 920 can render graphical content associated with the user interface, operating system, or applications of the SoC 900. In some cases, the audio processor 922 encodes or decodes audio data and signals, such as audio signals and information associated with voice calls or encoded audio data, for playback. The image sensor processor 924 can be coupled to an image sensor and provides image data processing, video capture, and other visual media conditioning and processing functions. The SoC can also include a sensor interface 926. The sensor interface 926 enables the SoC 900 to receive data from various sensors, such as capacitive and motion sensors.

[0103] Example

[0104] Examples are provided in the following sections.

[0105] Example 1: An apparatus comprising: a memory controller operatively connected to one or more memories, the memory controller being configured to process transaction requests from one or more clients to access data in the one or more memories; and a bridge operatively connected to the memory controller and the one or more clients, the bridge including a reordering cache and configured to: receive a plurality of transaction requests from a first client among the one or more clients; receive a plurality of transaction responses from the memory controller, each transaction response being associated with a corresponding transaction request among the plurality of transaction requests, the plurality of transaction responses being returned in an ordered manner to the first client by the bridge; and in response to receiving the first transaction response among the plurality of transaction responses, bypassing the storage of data associated with the first transaction response in the reordering cache and sending the data to the first client.

[0106] Example 2: According to the apparatus of Example 1, the bridge is further configured to transmit multiple transaction responses to a first client based on response sequence numbers assigned to the multiple transaction responses, the response sequence numbers indicating the order in which the multiple transaction responses will be returned to the first client.

[0107] Example 3: According to the apparatus of Example 1, wherein, in response to receiving each of a plurality of transaction responses from the memory controller, the bridge is further configured to: determine a response sequence number associated with the transaction response; in response to a first response sequence number corresponding to the transaction response, send data associated with the transaction response, the transaction response being the first transaction response, to a first client; and in response to a first response sequence number not corresponding to the transaction response, write the data associated with the transaction response to a reordering cache and mark the response sequence number as available for transmission to the first client.

[0108] Example 4: According to the apparatus of Example 3, wherein, in response to sending a first transaction response to a first client, the bridge is further configured to: determine whether a second transaction response having a response sequence number of "second" corresponding to a second transaction response is available to be sent to the first client; and in response to the determination that the second transaction response is available to be sent to the first client: read data associated with the second transaction response from a reordering cache; send the data associated with the second transaction response to the first client; and increment a response counter value by one, the response counter value having an incrementally increasing value and indicating the next transaction response to be sent to the first client.

[0109] Example 5: According to the apparatus of Example 1, wherein, in response to receiving each of a plurality of transaction responses from a memory controller, the bridge is further configured to: determine a response sequence number associated with the transaction response; determine a response counter value having an incrementally increasing value and indicating the next transaction response to be sent to the first client; in response to the response sequence number being equal to the response counter value, send data associated with the transaction response to the first client; and in response to the response sequence number not being equal to the response counter value, write the data associated with the transaction response to a reordering cache and mark the response sequence number as available for sending to the first client.

[0110] Example 6: According to the apparatus of Example 5, wherein, in response to sending a transaction response to a first client, the bridge is further configured to: increment a response counter value by one; determine whether another transaction response having a response sequence number equal to the response counter value is available for sending to the first client; and in response to the determination that another transaction response having a response sequence number equal to the response counter value is available for sending to the client: read data associated with the other transaction response from a reordering cache; send the data associated with the other transaction response to the first client; and increment the response counter value by one.

[0111] Example 7: An apparatus according to any one of Examples 4 to 6, wherein a response sequence number and a response counter value are associated with a request identifier that indicates a set of transaction requests to be returned in an orderly manner by the bridge.

[0112] Example 8: An apparatus according to any one of Examples 1 to 7, wherein, in response to receiving a first transaction request from a first client, the bridge is further configured to: determine a request identifier associated with the first transaction request; determine whether the request identifier matches a request identifier of another transaction request pending in the memory subsystem; in response to the determination that the request identifier matches a request identifier of another transaction request pending in the memory subsystem, append the first transaction request to a linked list associated with the request identifier; and in response to the determination that the request identifier does not match a request identifier of another transaction request pending in the memory subsystem, assign a value to an identifier flag of the request identifier associated with the first transaction request.

[0113] Example 9: According to the apparatus of Example 8, wherein, in response to the determination that a request identifier matches a request identifier of another transaction request to be processed in the memory subsystem, the bridge is further configured to: determine whether a response sequence number is available for the first transaction request; and in response to the determination that the response sequence number is available for the first transaction request, assign a first response sequence number to the first transaction request, the first response sequence number having a value that is incrementally greater than the response sequence numbers of other transaction requests.

[0114] Example 10: According to the apparatus of Example 9, in response to the determination that the response sequence number is not available for the first transaction request, the bridge is further configured to stop the execution of the first transaction request until the response sequence number becomes available.

[0115] Example 11: An apparatus according to any one of Examples 8 to 10, wherein the identification flag includes a one-bit flag for a request identifier associated with the first transaction request.

[0116] Example 12: The apparatus according to Example 11, wherein the identification flag is initialized and changed to zero after being reset by the bridge.

[0117] Example 13: An apparatus according to any one of Examples 1 to 12, wherein the bridge is further configured to send data associated with a first transaction response to a first client, without storing the data in the reordering cache, based on the absence of a related out-of-order transaction request in the reordering cache.

[0118] Example 14: An apparatus according to any one of Examples 1 to 13, wherein the apparatus includes a system-on-a-chip (SoC) embedded in a user equipment.

[0119] Example 15: The apparatus according to Example 14, wherein the user equipment includes a mobile phone, a laptop computer, a tablet computer, a portable video game console, or a wearable device.

[0120] Example 16: An apparatus according to any one of Examples 1 to 12, wherein the memory controller includes an application-specific integrated circuit (ASIC) memory controller.

[0121] Example 17: A method comprising: receiving, by a bridge, a plurality of transaction requests from a first client among one or more clients, the bridge being operatively connected to the one or more clients and including a reordering cache; receiving, by the bridge, a plurality of transaction responses from a memory controller, each transaction response being associated with a corresponding transaction request among the plurality of transaction requests, the plurality of transaction responses being returned by the bridge in an ordered manner to the first client, the memory controller being operatively connected to the one or more memories and configured to process transaction requests from the one or more clients to access data in the one or more memories; and, in response to receiving the first transaction response among the plurality of transaction responses, bypassing the storage of data associated with the first transaction response in the reordering cache and sending the data to the first client.

[0122] Example 18: According to the method of Example 17, the method further includes: transmitting multiple transaction responses to a first client based on response sequence numbers assigned to the multiple transaction responses, the response sequence numbers indicating the order in which the multiple transaction responses will be returned to the first client.

[0123] Example 19: According to the method of Example 17, the method further includes, in response to receiving each of a plurality of transaction responses from a memory controller: determining a response sequence number associated with the transaction response; in response to the response sequence number corresponding to the transaction response being first, sending data associated with the transaction response, the transaction response being the first transaction response, to a first client; and in response to the response sequence number not corresponding to the transaction response being first, writing data associated with the transaction response to a reordering cache and marking the response sequence number as available for sending to the first client.

[0124] Example 20: According to the method of Example 19, the method further includes, in response to sending a first transaction response to a first client: determining whether a second transaction response having a response sequence number of "second" corresponding to a second transaction response is available to be sent to the first client; and in response to the determination that the second transaction response is available to be sent to the first client: reading data associated with the second transaction response from a reordering cache; sending the data associated with the second transaction response to the first client; and incrementing a response counter value by one, the response counter value having an incrementally increasing value and indicating the next transaction response to be sent to the first client.

[0125] Example 21: According to the method of Example 17, the method further includes: in response to receiving each of a plurality of transaction responses from a memory controller: determining a response sequence number associated with the transaction response; determining a response counter value, the response counter value having an incrementally increasing value and indicating the next transaction response to be sent to a first client; in response to the response sequence number being equal to the response counter value, sending data associated with the transaction response to the first client; and in response to the response sequence number not being equal to the response counter value, writing the data associated with the transaction response to a reordering cache and marking the response sequence number as available for sending to the first client.

[0126] Example 22: According to the method of Example 21, the method further includes, in response to sending a transaction response to a first client: incrementing a response counter value by one; determining whether another transaction response having a response sequence number equal to the response counter value is available to be sent to the first client; and in response to determining that another transaction response having a response sequence number equal to the response counter value is available to be sent to the client: reading data associated with the other transaction response from a reordering cache; sending the data associated with the other transaction response to the first client; and incrementing the response counter value by one.

[0127] Example 23: The method according to any one of Examples 20 to 22, wherein a response sequence number and a response counter value are associated with a request identifier that indicates a set of transaction requests to be returned in an orderly manner by the bridge.

[0128] Example 24: The method according to any one of Examples 17 to 23, the method further comprising, in response to receiving a first transaction request from a first client: determining a request identifier associated with the first transaction request; determining whether the request identifier matches a request identifier of another transaction request pending in a memory subsystem; in response to determining that the request identifier matches a request identifier of another transaction request pending in a memory subsystem, appending the first transaction request to a linked list associated with the request identifier; and in response to determining that the request identifier does not match a request identifier of another transaction request pending in a memory subsystem, assigning a value to an identifier flag of the request identifier associated with the first transaction request.

[0129] Example 25: According to the method of Example 24, the method further includes, in response to determining that a request identifier matches a request identifier of another transaction request pending in the memory subsystem: determining whether a response sequence number is available for the first transaction request; and in response to determining that the response sequence number is available for the first transaction request, assigning a first response sequence number to the first transaction request, the first response sequence number having a value that is incrementally greater than the response sequence numbers of other transaction requests.

[0130] Example 26: According to the method described in Example 9, the method further includes: in response to determining that the response sequence number is not available for the first transaction request, stopping the execution of the first transaction request until the response sequence number becomes available.

[0131] Example 27: The method according to any one of Examples 24 to 26, wherein the identification flag includes a one-bit flag for a request identifier associated with the first transaction request.

[0132] Example 28: The method described in Example 27, wherein the identification flag is initialized and changed to zero after being reset by the bridge.

[0133] Example 29: The method according to any one of Examples 17 to 28, the method further includes sending data associated with the first transaction response to the first client without storing the data in the reorder cache, based on the absence of a related out-of-order transaction request in the reorder cache.

[0134] in conclusion

[0135] While various configurations and methods for supporting low-latency bridges to enable out-of-order execution have been described in feature- and / or method-specific language, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as non-limiting examples of low-latency bridges to enable out-of-order execution.

Claims

1. An apparatus for supporting a low-latency bridge for out-of-order execution, comprising: A memory controller operatively connected to one or more memories, the memory controller being configured to process transaction requests from one or more clients to access data in the one or more memories; as well as A bridge, operatively connectable to the memory controller and the one or more clients, the bridge including a reordering cache and configured to: Receive multiple transaction requests from the first client among the one or more clients; The bridge receives multiple transaction responses from the memory controller, each transaction response being associated with a corresponding transaction request among the multiple transaction requests. The multiple transaction responses are then returned to the first client in an orderly manner by the bridge. as well as In response to receiving each of the plurality of transaction responses: Determine the response sequence number associated with the transaction response; Determine a response counter value, the response counter value having an incrementally increasing value and indicating the next transaction response to be sent to the first client; In response to the response sequence number being equal to the response counter value, data associated with the transaction response is sent to the first client; or In response to the response sequence number not being equal to the response counter value, the data associated with the transaction response is stored in the reorder cache and the response sequence number associated with the transaction response is set to available.

2. The apparatus according to claim 1, wherein, The response sequence number indicates the order in which the multiple transaction responses will be returned to the first client.

3. The apparatus according to claim 1, wherein, The transaction response includes a first transaction response associated with the corresponding transaction request from the first client.

4. The apparatus according to claim 3, wherein, The bridge is further configured to: Determine whether the response sequence number of the second transaction response among the plurality of transaction responses is next in the order of the plurality of transaction responses to be returned; as well as The data in response to the second transaction response, which is available in the reordering cache for determination of what to send to the first client, is: Read the data associated with the second transaction response from the reordering cache; Send the data associated with the second transaction response to the first client; as well as Increment the response counter value by one to indicate the next transaction response to be sent to the first client.

5. The apparatus according to claim 1, wherein, The bridge is further configured to: Determine whether the response sequence number associated with the transaction response is the first in the order of the plurality of transaction responses to be returned to the first client; as well as If the response sequence number of the transaction response is first in the order, the data associated with the transaction response is sent directly to the first client instead of being stored in the reorder cache; or If the response sequence number of the transaction response is not the first in the order, the data associated with the transaction response is stored in the reorder cache.

6. The apparatus according to claim 3, wherein, The bridge is further configured to: Determine whether the response sequence number of another transaction response among the plurality of transaction responses is equal to the response calculator value; and The determination that another transaction response having a response sequence number equal to the response counter value can be sent to the first client: Read the data associated with the other transaction response from the reorder cache; Send the data associated with the other transaction response to the first client; and Increment the response counter value by one.

7. The apparatus according to claim 1, wherein, The response sequence number or the response counter value is associated with the request identifier of the plurality of transaction responses to be returned in an orderly manner by the bridge.

8. The apparatus according to claim 1, wherein: The plurality of transaction requests includes a first transaction request; and In response to receiving the first transaction request from the first client, the bridge is further configured to: Determine the first request identifier associated with the first transaction request; Determine whether the first request identifier matches a second request identifier associated with a second transaction request pending in the device; as well as In response to the determination that the first request identifier matches the second request identifier associated with the second transaction request to be processed in the device, the first transaction request is appended to the linked list including the second transaction request. or In response to a determination that the first request identifier does not match the second request identifier associated with the second transaction request to be processed in the device, a value is assigned to the identifier flag of the first request identifier associated with the first transaction request.

9. The apparatus according to claim 8, wherein, The bridge is further configured to: Determine that the response sequence number is available for the first transaction request; and Assign a first response sequence number to the first transaction request, the first response sequence number having a value greater than the value of the second response sequence number of the second transaction request.

10. The apparatus according to claim 8, wherein, The bridge is further configured to: It is determined that the response sequence number is not available for the first transaction request; and Execution of the first transaction request is suspended until the response sequence number becomes available.

11. The apparatus according to claim 8, wherein, The identifier flag includes a one-bit flag for the first request identifier associated with the first transaction request.

12. The apparatus according to claim 11, wherein, The identifier flag is initialized and changed to zero after being reset by the bridge.

13. The apparatus according to claim 1, wherein, The bridge is further configured to send the data associated with the transaction response to the first client, without storing the data in the reordering cache, based on the absence of a related out-of-order transaction request in the reordering cache.

14. The apparatus according to any one of claims 1 to 13, wherein, The device includes a system-on-a-chip (SoC) embedded in a user equipment.

15. The apparatus according to claim 14, wherein, The user equipment includes mobile phones, laptop computers, tablet computers, portable video game consoles, or wearable devices.

16. A method for supporting a low-latency bridge for out-of-order execution, comprising: A bridge receives multiple transaction requests from a first client among one or more clients, the bridge being operatively connected to the one or more clients and including a reordering cache; The bridge receives multiple transaction responses from the memory controller, each of the multiple transaction responses being associated with a corresponding transaction request among the multiple transaction requests. The multiple transaction responses are returned in order by the bridge to the first client. The memory controller is operatively connected to one or more memories and configured to process transaction requests from the one or more clients to access data in the one or more memories. In response to receiving each of the plurality of transaction responses from the memory controller: Determine the response sequence number associated with the transaction response; Determine a response counter value, the response counter value having an incrementally increasing value and indicating the next transaction response to be sent to the first client; as well as In response to the response sequence number being equal to the response counter value, data associated with the transaction response is sent to the first client; or In response to the response sequence number not being equal to the response counter value, the data associated with the transaction response is stored in the reorder cache and the response sequence number associated with the transaction response is set to available.

17. The method according to claim 16, wherein, The transaction response includes a first transaction response associated with a corresponding transaction request from the first client, and the method further includes sending data associated with the first transaction response to the first client.

18. The method of claim 17, further comprising: Determine whether the response sequence number of the second transaction response among the plurality of transaction responses is next in the order of the plurality of transaction responses to be returned; as well as The data in response to the second transaction response, which is available in the reordering cache for determination of what to send to the first client, is: Read the data associated with the second transaction response from the reordering cache; The data associated with the second transaction response is sent to the first client; as well as Increment the response counter value by one to indicate the next transaction response to be sent to the first client.

19. The method of claim 18, further comprising: Determine whether the response sequence number of another transaction response among the plurality of transaction responses is equal to the response calculator value; as well as The determination that another transaction response having a response sequence number equal to the response counter value can be sent to the first client: Read the data associated with the other transaction response from the reorder cache; Send the data associated with the other transaction response to the first client; and Increment the response counter value by one.

20. The method of claim 16, wherein, The response sequence number or the response counter value is associated with the request identifier of the plurality of transaction responses to be returned in an orderly manner by the bridge.

21. The method according to claim 16, wherein, The plurality of transaction requests received from the first client include a first transaction request, and the method further includes: Determine the first request identifier associated with the first transaction request; Determine whether the first request identifier matches a second request identifier associated with a second transaction request to be processed in the bridge; and In response to the determination that the first request identifier matches a second request identifier associated with a second transaction request to be processed in the bridge, the first transaction request is appended to the linked list associated with the second request identifier; or In response to a determination that the first request identifier does not match the second request identifier associated with the second transaction request to be processed in the bridge, a value is assigned to the identifier flag of the first request identifier associated with the first transaction request.

22. The method of claim 21, further comprising: Determine that the response sequence number can be used for the first transaction request; as well as Assign a first response sequence number to the first transaction request, the first response sequence number having a value greater than the value of the second response sequence number of the second transaction request.

23. The method of claim 21, further comprising: It is determined that the response sequence number is not available for the first transaction request; as well as Execution of the first transaction request is suspended until the response sequence number becomes available.

24. The method according to claim 21, wherein, The identifier flag includes a one-bit flag for the first request identifier associated with the first transaction request.

25. The method of claim 16, further comprising: Determine whether the response sequence number associated with the transaction response is the first in the order of the plurality of transaction responses to be returned to the first client; as well as If the response sequence number of the transaction response is first in the order of the plurality of transaction responses to be returned, the data associated with the transaction response is sent directly to the first client without storing the data in the reordering cache; or If the response sequence number of the transaction response is not the first in the order of the plurality of transaction responses to be returned, the data associated with the transaction response is stored in the reorder cache.

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