Power supply circuit and chip

Abstract

The present disclosure provides a power supply circuit and a chip using the same. The power supply circuit comprises: a reference voltage generating circuit configured to generate a substrate reference voltage with a negative temperature coefficient; a voltage generating circuit configured to reduce a substrate voltage according to an enable signal; and an enable signal generating circuit connected to the reference voltage generating circuit and the voltage generating circuit, configured to output the enable signal to the voltage generating circuit when the substrate reference voltage is less than a conversion voltage proportional to the substrate voltage. The embodiment of the present disclosure can reduce the substrate voltage of a transistor when the temperature rises, thereby reducing the power consumption of the chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a power supply circuit and a chip applying the same. BACKGROUND

[0002] With the development of technology, the demand for low power consumption of integrated circuits is increasing. Related technologies usually optimize the power consumption of integrated circuits during signal transmission and signal processing. However, during standby or sleep of the integrated circuit, there is almost no signal transmission and signal processing, so the power consumption of the integrated circuit can be further reduced.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a power supply circuit and a chip applying the same, which can further reduce the power consumption of integrated circuits to at least some extent.

[0005] According to a first aspect of the present disclosure, a power supply circuit is provided, comprising:

[0006] a reference voltage generation circuit configured to generate a substrate reference voltage with a negative temperature coefficient;

[0007] a voltage generation circuit configured to reduce a substrate voltage according to an enable signal;

[0008] an enable signal generation circuit connected to the reference voltage generation circuit and the voltage generation circuit, configured to output the enable signal to the voltage generation circuit when the substrate reference voltage is less than a conversion voltage proportional to the substrate voltage.

[0009] In an exemplary embodiment of the present disclosure, the voltage generation circuit comprises:

[0010] an oscillation module having an input end configured to receive the enable signal and an output end configured to output an oscillation signal, the oscillation module being configured to generate the oscillation signal according to the enable signal;

[0011] a charge pump module having an input end connected to the oscillation module and an output end configured to output the substrate voltage, the charge pump module being configured to reduce the substrate voltage according to the oscillation signal.

[0012] In an exemplary embodiment of the present disclosure, the charge pump module comprises:

[0013] a first capacitor having a first end coupled to the output end of the oscillation module;

[0014] a first diode, a negative electrode of which is connected to ground, and a positive electrode of which is connected to a second end of the first capacitor;

[0015] a second diode, a negative electrode of which is connected to the second end of the first capacitor, and a positive electrode of which is used to output the substrate voltage.

[0016] In an exemplary embodiment of the present disclosure, the charge pump module further comprises a driving circuit connected between an output end of the oscillation module and a first end of the first capacitor, the driving circuit being used to increase an amplitude of the oscillation signal.

[0017] In an exemplary embodiment of the present disclosure, the charge pump module further comprises a second capacitor, a first end of the second capacitor being connected to a positive electrode of the second diode, and a second end of the second capacitor being connected to ground, the second capacitor being used to maintain an output voltage of the charge pump module.

[0018] In an exemplary embodiment of the present disclosure, the enable signal generation circuit comprises:

[0019] a voltage follower, a non-inverting input end of the voltage follower being used to receive the substrate reference voltage, and an inverting input end of the voltage follower being connected to an output end of the voltage follower;

[0020] a first voltage dividing unit, two input ends of the first voltage dividing unit being connected to the output end of the voltage follower and a power supply voltage respectively, and an output end of the first voltage dividing unit being used to output a first voltage dividing voltage generated based on the substrate reference voltage and the power supply voltage;

[0021] a second voltage dividing unit, two input ends of the second voltage dividing unit being connected to the output end of the voltage generation circuit and the power supply voltage respectively, and an output end of the second voltage dividing unit being used to output a second voltage dividing voltage generated based on the substrate voltage and the power supply voltage;

[0022] a comparator, a non-inverting input end of the comparator being connected to the output end of the first voltage dividing unit, and an inverting input end of the comparator being connected to the output end of the second voltage dividing unit;

[0023] an inverter, an input end of the inverter being connected to an output end of the comparator, and an output end of the inverter being connected to the voltage generation circuit, and being used to output the enable signal.

[0024] In an exemplary embodiment of the present disclosure, the first voltage dividing unit comprises a first voltage dividing resistor unit and a second voltage dividing resistor unit connected in series, a first end of the first voltage dividing resistor unit being connected to the power supply voltage, a first end of the second voltage dividing resistor unit being connected to a second end of the first voltage dividing resistor unit, and a second end of the second voltage dividing resistor unit being connected to the output end of the voltage follower; wherein a resistance ratio of the first voltage dividing resistor unit and the second voltage dividing resistor unit is 1: (K1-1), K1 being a first preset value.

[0025] In an example embodiment of the present disclosure, the second voltage dividing unit comprises a third voltage dividing resistor unit and a fourth voltage dividing resistor unit connected in series, a first end of the third voltage dividing resistor unit is connected to the power supply voltage, a first end of the fourth voltage dividing resistor unit is connected to a second end of the third voltage dividing resistor unit, and a second end of the fourth voltage dividing resistor unit is connected to the output end of the voltage generating circuit; wherein a resistance ratio of the third voltage dividing resistor unit and the fourth voltage dividing resistor unit is 1:(K2-1), and K2 is a second preset value.

[0026] In an example embodiment of the present disclosure, the resistance of the second voltage dividing resistor unit and the fourth voltage dividing resistor unit is adjustable.

[0027] In an example embodiment of the present disclosure, the second voltage dividing resistor unit and the fourth voltage dividing resistor unit each comprise a plurality of resistor sub-units connected in series, each of the resistor sub-units comprises one or more sub-resistors, each of the resistor sub-units is connected in parallel with a resistor adjusting switch tube, and a control end of each of the resistor adjusting switch tubes receives a control signal.

[0028] In an example embodiment of the present disclosure, the resistance of each of the sub-resistors is equal.

[0029] In an example embodiment of the present disclosure, the reference voltage generating circuit comprises:

[0030] a constant current generating module configured to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and generate a constant current according to the first current and the second current;

[0031] a substrate reference voltage generating module comprising a transistor, the substrate reference voltage generating module being coupled to the constant current generating module and configured to generate the substrate reference voltage with a negative temperature coefficient according to the constant current and transistor characteristics.

[0032] In an example embodiment of the present disclosure, the constant current generating module comprises:

[0033] a positive temperature coefficient current generating unit configured to generate the first current;

[0034] a negative temperature coefficient current generating unit connected to the positive temperature coefficient current generating unit and configured to generate the second current.

[0035] In an example embodiment of the present disclosure, the positive temperature coefficient current generating unit comprises:

[0036] a first amplifier;

[0037] a first feedback transistor, a source of the first feedback transistor being connected to a power voltage, a gate of the first feedback transistor being connected to an output terminal of the first amplifier, and a drain of the first feedback transistor being connected to a first node;

[0038] a first bridge arm, the first bridge arm comprising a first resistor and a plurality of first PN junction units connected in parallel in series, a first end of the first resistor being connected to the first node, and a second end of the first resistor being connected to an inverting input terminal of the first amplifier, positive poles of the first PN junction units being connected to the inverting input terminal of the first amplifier, and negative poles of the first PN junction units being grounded;

[0039] a second bridge arm, the second bridge arm comprising a second resistor, a third resistor and a plurality of second PN junction units connected in parallel in series, a first end of the second resistor being connected to the first node, and a second end of the second resistor being connected to a non-inverting input terminal of the first amplifier, a first end of the third resistor being connected to the non-inverting input terminal of the first amplifier, and a second end of the third resistor being connected to positive poles of the second PN junction units, and negative poles of the second PN junction units being grounded;

[0040] a first output transistor, a source of the first output transistor being connected to the power voltage, a gate of the first output transistor being connected to the output terminal of the first amplifier, and a drain of the first output transistor being used for outputting the first current.

[0041] In an exemplary embodiment of the present disclosure, the first resistor and the second resistor have equal resistance values.

[0042] In an exemplary embodiment of the present disclosure, the number of the second PN junction units is N, and N=(M+2) 2 -M 2 , and the number of the first PN junction units is M 2 , wherein M is an integer greater than or equal to 1.

[0043] In an exemplary embodiment of the present disclosure, the negative temperature coefficient current generation unit comprises:

[0044] a second amplifier, an inverting input terminal of the second amplifier being connected to the inverting input terminal of the first amplifier;

[0045] a second feedback transistor, a source of the second feedback transistor being connected to the power voltage, a gate of the second feedback transistor being connected to an output terminal of the second amplifier, and a drain of the second feedback transistor being connected to a non-inverting input terminal of the second amplifier;

[0046] a fourth resistor, one end of the fourth resistor being connected to the non-inverting input terminal of the second amplifier, and the other end of the fourth resistor being grounded;

[0047] a second output transistor, a source of the second output transistor being connected to the power voltage, a gate of the second output transistor being connected to the output terminal of the second amplifier, and a drain of the second output transistor being used for outputting the second current.

[0048] In an example embodiment of the present disclosure, the third resistor and the fourth resistor are adjustable resistors, and a derivative of (kT / q)*lnZ / R3+(kT / q*lnZ+VBE2) / R4 with respect to temperature T is zero, where R3 is the resistance of the third resistor, R4 is the resistance of the fourth resistor, K is the Boltzmann constant, q is the electronic charge, T is the working temperature of the power supply circuit, VBE2 is the voltage difference across the second PN junction unit, and Z is the quantity ratio of the second PN junction unit to the first PN junction unit.

[0049] In an example embodiment of the present disclosure, the substrate reference voltage generation module comprises:

[0050] A first N-type transistor, a drain and a gate of the first N-type transistor are connected to a second node, the second node connects a drain of the first output transistor and a drain of the second output transistor, a source of the first N-type transistor is grounded, and the second node is used to output the substrate reference voltage.

[0051] According to a second aspect of the present disclosure, a chip is provided, comprising the power supply circuit as claimed in any one of the above.

[0052] The embodiments of the present disclosure can automatically reduce the substrate voltage of the transistor by the enable signal control voltage output module when the temperature rises and the transistor drain current rises, reduce the transistor drain current, and thus reduce the power consumption of the integrated circuit by providing the substrate reference voltage with a negative temperature coefficient and the enable signal output module outputting the enable signal according to the reduction of the substrate reference voltage. When the power supply circuit is used to provide the substrate voltage of the N-type transistor, the substrate voltage of the N-type transistor in the integrated circuit can be automatically reduced when the temperature rises, and thus the drain current of the N-type transistor and the overall power consumption of the integrated circuit are reduced.

[0053] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0054] The drawings herein are incorporated into the description and form part of the description, show embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0055] Figure 1 is a schematic diagram of the power supply circuit 100 in an example embodiment of the present disclosure.

[0056] Figure 2is a schematic diagram of the voltage generation circuit 2 in one embodiment of the present disclosure.

[0057] Figure 3 is a schematic diagram of the voltage generation circuit 2 in another embodiment of the present disclosure.

[0058] Figure 4 is a schematic diagram of the enable signal generation circuit 3 in one embodiment of the present disclosure.

[0059] Figure 5A and Figure 5B are schematic diagrams of the adjustable resistance unit in embodiments of the present disclosure.

[0060] Figure 6 is a schematic diagram of the reference voltage generation circuit 1 in one embodiment of the present disclosure.

[0061] Figure 7 is a schematic diagram of the constant current generation module 11 in one embodiment of the present disclosure.

[0062] Figure 8 is a schematic diagram of the substrate reference voltage generation module 12 in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] Example implementations will now be described with reference to the drawings. However, example implementations can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. The described features, structures, or characteristics can be combined in one or more implementations in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of implementations of the present disclosure. One skilled in the relevant art will recognize, however, that the implementations of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures have not been described in detail so as not to obscure the aspects of the present disclosure.

[0064] Furthermore, the accompanying drawings are only schematic and are non-limiting detailed descriptions of the application, as with the same reference numerals denoting the same or similar parts throughout the several views, the drawings will be briefly described as follows. Some of the blocks in the block diagrams are functional entities that do not necessarily have to correspond to a physically and / or logically independent entity. These functional entities can be implemented in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0065] Example implementations of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0066] Figure 1 is a schematic diagram of a power supply circuit in an example embodiment of the present disclosure.

[0067] With reference to Figure 1 , the power supply circuit 100 can include:

[0068] a reference voltage generation circuit 1 for generating a substrate reference voltage Vref with a negative temperature coefficient;

[0069] a voltage generation circuit 2 for reducing the substrate voltage VBN according to an enable signal;

[0070] an enable signal generation circuit 3 connected to the reference voltage generation circuit 1 and the voltage generation circuit 2, for outputting an enable signal EN to the voltage generation circuit 2 when the substrate reference voltage Vref is less than a conversion voltage proportional to the substrate voltage VBN.

[0071] The embodiment of the present disclosure can automatically reduce the substrate voltage of the transistor when the temperature rises and the transistor leakage current rises by providing a substrate reference voltage with a positive temperature coefficient, thereby reducing the transistor leakage current and reducing the power consumption of the integrated circuit. When the power supply circuit 100 is used to provide the substrate voltage of the N-type transistor, the substrate voltage of the N-type transistor in the integrated circuit can be automatically reduced when the temperature rises, thereby reducing the leakage current of the N-type transistor and reducing the overall power consumption of the integrated circuit.

[0072] Figure 2 is a schematic diagram of a voltage generation circuit in an embodiment of the present disclosure.

[0073] With reference to Figure 2 In an embodiment, the voltage generation circuit 2 can include:

[0074] an oscillation module 21 having an input end for receiving an enable signal EN and an output end for outputting an oscillation signal OSC, the oscillation module 21 being configured to generate the oscillation signal OSC according to the enable signal EN;

[0075] a charge pump module 22 having an input end connected to the oscillation module 21 and an output end for outputting a substrate voltage VBN, the charge pump module 22 being configured to reduce the substrate voltage VBN according to the oscillation signal OSC.

[0076] The oscillation module 21 can be implemented by a controlled ring oscillator, which can include an odd number of input-output ring series elements with signal inversion function, such as inverters or NAND gates. The oscillation module 21 outputs the oscillation signal OSC when receiving the enable signal EN, and can stop outputting the oscillation signal OSC when not receiving the enable signal EN.

[0077] The charge pump module 22 can output a substrate voltage required for normal operation of the transistor, such as a ground voltage (0V), when the oscillation signal OSC is not received. When the oscillation signal OSC is received, the charge pump function can be started, and the output voltage, i.e., the substrate voltage VBN, can be reduced.

[0078] In Figure 2 In the embodiment shown, the charge pump module 22 includes:

[0079] a first capacitor C1, a first end of the first capacitor C1 being coupled to the output end of the oscillation module 21;

[0080] a first diode D1, a negative electrode being grounded, and a positive electrode being connected to a second end of the first capacitor C1;

[0081] a second diode D2, a negative electrode being connected to the second end of the first capacitor C1, and a positive electrode being used to output the substrate voltage VBN.

[0082] The charge pump module 22 can extract negative charges from the ground to the positive electrode of the second diode D2 according to the oscillation signal OSC, and thus reduce the voltage of the positive electrode of the second diode D2, thereby generating the substrate voltage VBN.

[0083] When the oscillation module 21 stops outputting the oscillation signal OSC, the voltage of the output end of the charge pump module 22, i.e., the voltage of the positive electrode of the second diode D2, no longer decreases.

[0084] Figure 3 is a schematic diagram of a voltage generation circuit in another embodiment of the present disclosure.

[0085] Referring to Figure 3 In another embodiment, in order to adjust the amplitude of the decrease of the output voltage of the charge pump module 22, the charge pump module 22 further includes a driving circuit DR connected between the output end of the oscillation module 21 and the first end of the first capacitor C1, and the driving circuit DR can be used to increase the amplitude of the oscillation signal OSC.

[0086] In addition, the charge pump module 22 can further include a second capacitor C2, a first end of the second capacitor C2 being connected to the positive electrode of the second diode D2, and a second end of the second capacitor C2 being grounded, and the second capacitor C2 being used to maintain the output voltage of the charge pump module 22. The second capacitor C2 can be used as a filter voltage to further smooth the output voltage of the charge pump module 22, and maintain the negative electrode voltage of the second diode D2 as a stable DC voltage during the output of the oscillation signal OSC.

[0087] Figure 4 is a schematic diagram of an enable signal generation circuit in an embodiment of the present disclosure.

[0088] Referring to Figure 4 In an embodiment, the enable signal generation circuit 3 can include:

[0089] Voltage follower 30, the non-inverting input terminal of voltage follower 30 is used to receive the substrate reference voltage Vref, and the inverting input terminal is connected to the output terminal;

[0090] The first voltage divider unit 31 has two input terminals connected to the output terminal of the voltage follower 30 and the power supply voltage VCC, respectively. The output terminal is used to output the first voltage divider voltage V1 generated based on the substrate reference voltage Vref and the power supply voltage VCC.

[0091] The second voltage divider unit 32 has two input terminals connected to the output terminal of the voltage generation circuit 2 and the power supply voltage VCC, respectively. The output terminal is used to output the second voltage divider voltage V2 generated based on the substrate voltage VBN and the power supply voltage VCC.

[0092] The comparator COMP has its non-inverting input connected to the output of the first voltage divider unit 31 and its inverting input connected to the output of the second voltage divider unit 32.

[0093] The inverter OP has its input connected to the output of the comparator COMP, and its output connected to the voltage generation circuit 2 to output the enable signal EN.

[0094] The voltage follower 30 is used to compensate for the weak current drive capability of the substrate reference voltage Vref with a negative temperature coefficient.

[0095] exist Figure 4 In the illustrated embodiment, the first voltage divider unit 31 includes a first voltage divider resistor unit RZ1 and a second voltage divider resistor unit RZ2 connected in series. The first terminal of the first voltage divider resistor unit RZ1 is connected to the power supply voltage VCC, the first terminal of the second voltage divider resistor unit RZ2 is connected to the second terminal of the first voltage divider resistor unit RZ1, and the second terminal of the second voltage divider resistor unit RZ2 is connected to the output terminal of the voltage follower 30. The resistance ratio of the first voltage divider resistor unit RZ1 and the second voltage divider resistor unit RZ2 is 1:(K1-1), where K1 is a first preset value.

[0096] The second voltage divider unit 32 includes a third voltage divider resistor unit RZ3 and a fourth voltage divider resistor unit RZ4 connected in series. The first terminal of the third voltage divider resistor unit RZ3 is connected to the power supply voltage VCC, the first terminal of the fourth voltage divider resistor unit RZ4 is connected to the second terminal of the third voltage divider resistor unit RZ3, and the second terminal of the fourth voltage divider resistor unit RZ4 is connected to the output terminal of the voltage generation circuit 2. The resistance ratio of the third voltage divider resistor unit RZ3 and the fourth voltage divider resistor unit RZ4 is 1:(K2-1), where K2 is a second preset value.

[0097] The resistance of the second voltage dividing resistor unit RZ2 is (K1-1)R, and the resistance of the fourth voltage dividing resistor unit RZ4 is (K2-1)R.

[0098] By analysis, the voltage at the non-inverting input of the comparator COMP is equal to VCC-(VCC-Vref) / K1, and the voltage at the inverting input of the comparator COMP is equal to VCC-(VCC-VBN) / K2. When the voltage at the non-inverting input of the comparator COMP is greater than the voltage at the inverting input, i.e., Vref>K1*VBN / K2-(K1-K2)VCC / K2, the comparator COMP outputs a high level, and the inverter OP outputs a low level, i.e., the enable signal EN is at a low level. When the enable signal EN is set to be active at a high level, the voltage generating circuit 2 does not reduce the substrate voltage VBN.

[0099] When the substrate reference voltage Vref gradually decreases to be less than K1*VBN / K2-(K1-K2)VCC / K2, the comparator COMP flips to output a low level, the inverter OP outputs a high level, the enable signal EN is at a high level, and the voltage generating circuit 2 starts to reduce the substrate voltage VBN.

[0100] Therefore, when the substrate reference voltage Vref with a negative temperature coefficient is applied to control the substrate voltage of the P-type transistor, when the temperature rises and the transistor drain current increases, the substrate reference voltage Vref decreases. When the substrate reference voltage Vref decreases to be less than K1*VBN / K2-(K1-K2)VCC / K2, the enable signal generating circuit 3 outputs an active enable signal EN to control the voltage generating circuit 2 to start to reduce the substrate voltage VBN, thereby automatically reducing the transistor drain current.

[0101] In one embodiment, the resistance of the second voltage dividing resistor unit RZ2 and the fourth voltage dividing resistor unit RZ4 is adjustable.

[0102] The second voltage dividing resistor unit RZ2 and the fourth voltage dividing resistor unit RZ4 can be implemented by the adjustable resistor units shown in FIGS. 1A and 1B. Figure 5A and Figure 5B

[0103] Figure 5A and Figure 5B are schematic diagrams of the adjustable resistor units in the embodiments of the present disclosure.

[0104] In one embodiment, the adjustable resistor unit can include a plurality of resistor sub-units connected in series, each resistor sub-unit including one or more sub-resistors, and each resistor sub-unit being connected in parallel with a resistor adjusting switch tube, and the control end of each resistor adjusting switch tube being connected with a controller. The resistance of each sub-resistor can be set to be equal. At this time, the adjustable resistor unit can be implemented by​Figure 5A The resistance string 501 shown is implemented.

[0105] Reference Figure 5A The resistance string 501 includes a plurality of series-connected sub-resistors R01, R02, R03, R04, R05, R06, and controllable resistance adjustment switch tubes Con1, Con2, Con3 connected to the first or second ends of the sub-resistors. The first and second ends of the resistance adjustment switch tube Con1 are connected to the two ends of the sub-resistor R01; the first and second ends of the resistance adjustment switch tube Con2 are connected to the second end of the sub-resistor R01 / the first end of the sub-resistor R02 / the second end of the sub-resistor R03 / the first end of the sub-resistor R04; and the first and second ends of the resistance adjustment switch tube Con3 are connected to the second end of the sub-resistor R03 / the first end of the sub-resistor R04 / the second end of the sub-resistor R06. Thus, the sub-resistor R01 constitutes a resistance sub-unit, the sub-circuits R02 and R03 constitute a resistance sub-unit, and the sub-resistors R04, R05, and R06 constitute a resistance sub-unit.

[0106] The control ends of the resistance adjustment switch tubes Con1, Con2, and Con3 all receive a control signal. The control signal is, for example, from a processor or a one-time programmable controller, and the present disclosure does not make special limitations thereon.

[0107] In Figure 5A In the embodiment shown, the resistance adjustment switch tubes are implemented by N-type transistors, and the gates of the N-type transistors serve as the control ends. In other embodiments of the present disclosure, the resistance adjustment switch tubes can also be implemented by other elements, and the present disclosure does not make special limitations thereon.

[0108] Suppose the resistance values of the sub-resistors R01, R02, R03, R04, R05, and R06 are all R0, and the resistance values of the resistance string 501 and the on / off states of the resistance adjustment switch tubes Con1, Con2, and Con3 are shown in Table 1:

[0109]

[0110] Table 1

[0111] The resistance value table above is different according to the number of resistors across which the resistance adjustment switch tubes Con1, Con2, and Con3 are connected, and those skilled in the art can adjust the number of sub-resistors, the resistance values, the number of switch elements, and the connection relationship between the switch elements and the sub-resistors according to the principles shown, so as to achieve a variety of resistance value settings. Figure 5A The resistance value table above is different according to the number of resistors across which the resistance adjustment switch tubes Con1, Con2, and Con3 are connected, and those skilled in the art can adjust the number of sub-resistors, the resistance values, the number of switch elements, and the connection relationship between the switch elements and the sub-resistors according to the principles shown, so as to achieve a variety of resistance value settings.

[0112] In addition, another resistance string can also be used to implement the adjustable resistance unit.

[0113] Reference Figure 5BThe resistor string 502 includes multiple sub-resistors R01, R02, R03, and R04 connected in series. The first end of sub-resistor R01 serves as the first end of the resistor string 502. The first ends of sub-resistors R02, R03, and R04 are respectively connected to the second ends of sub-resistors R01, R02, and R03. The second ends of sub-resistors R01, R02, and R03 are respectively connected to the second ends of resistance adjustment switches Con1, Con2, and Con3.

[0114] The first and second terminals of the resistance regulating switch Con1 are respectively connected to the two ends of the sub-resistor R01; the first and second terminals of the resistance regulating switch Con2 are respectively connected to the first terminal of the resistor string 502 and the second terminal of the sub-resistor R02; the first and second terminals of the resistance regulating switch Con3 are respectively connected to the first terminal of the resistor string 502 and the second terminal of the sub-resistor R03.

[0115] Assuming that the resistance values ​​of sub-resistors R01, R02, R03, and R04 are all R, then the resistance values ​​of resistor series 502 and the on / off states of resistor adjustment switches Con1, Con2, and Con3 are shown in Table 2:

[0116]

[0117] Table 2

[0118] As shown in Table 2, in Figure 5B In the illustrated embodiment, at most one switching element is controlled to be turned on to adjust the resistance value of resistor series 502. Although in Figure 5B In the illustrated embodiment, the second terminals of the two resistance-adjusting switches are separated by only one sub-resistor. However, in other embodiments of this disclosure, the second terminals of the two resistance-adjusting switches may be separated by a different number of sub-resistors, or sub-resistors of different resistance values, or sub-resistors of different numbers and resistance values. It should be noted that for the resistance-adjusting switch with the maximum number of sub-resistors across its two ends, its second terminal needs to be connected to a sub-resistor to prevent the resistance of the resistor series 502 from being zero.

[0119] Figure 6 This is a schematic diagram of a reference voltage generation circuit in one embodiment of the present disclosure.

[0120] refer to Figure 6 In one embodiment, the reference voltage generation circuit 1 includes:

[0121] The constant current generation module 11 is used to generate a first current I1 with a positive temperature coefficient and a second current I2 with a negative temperature coefficient, and to generate a constant current I based on the first current I1 and the second current I2.

[0122] The substrate reference voltage generation module 12 includes a transistor, and is coupled to the constant current generation module 11 and configured to generate a substrate reference voltage Vref with a negative temperature coefficient according to the constant current I and characteristics of the transistor.

[0123] Figure 6 The substrate reference voltage Vref generated in the illustrated embodiment is related to temperature characteristics of the transistor.

[0124] The threshold voltage of the transistor is related to temperature, the threshold voltage of an N-type transistor decreases with increasing temperature, and the absolute value of the threshold voltage of a P-type transistor decreases with increasing temperature. Since the threshold voltage of the P-type transistor is negative, the threshold voltage of the P-type transistor decreases with increasing temperature. Therefore, in the substrate reference voltage generation module 12, when the constant current I is input to the transistor, the threshold voltage Vth of the transistor changes with temperature, and finally the voltage output through the transistor is independent of current and only related to temperature.

[0125] Figure 7 FIG. 1 is a schematic diagram of the constant current generation module 11 in one embodiment of the present disclosure.

[0126] Reference Figure 7 In one embodiment, the constant current generation module 11 can include:

[0127] The positive temperature coefficient current generation unit 111 is configured to generate a first current I1.

[0128] The negative temperature coefficient current generation unit 112 is connected to the positive temperature coefficient current generation unit 111 and configured to generate a second current I2.

[0129] The first current I1 and the second current I2 together form the constant current I.

[0130] The substrate reference voltage generation module 12 is configured to output a substrate reference voltage Vref with a negative temperature coefficient according to the constant current I. The substrate reference voltage Vref with a negative temperature coefficient is, for example, a voltage output according to characteristics of an N-type transistor.

[0131] In Figure 7 In the illustrated embodiment, the positive temperature coefficient current generation unit 11 can include:

[0132] The first amplifier AMP1;

[0133] The first feedback transistor MB1 has its source connected to a power supply voltage VCC, its gate connected to an output terminal of the first amplifier AMP1, and its drain connected to a first node N1.

[0134] The first bridge arm B1 includes a first resistor R1 and a plurality of first PN junction units J1 connected in parallel, a first end of the first resistor R1 being connected to the first node N1, a second end of the first resistor R1 being connected to the inverting input terminal of the first amplifier AMP1 and the positive electrode of the first PN junction unit J1, the negative electrode of the first PN junction unit J1 being grounded.

[0135] The second bridge arm B2 includes a second resistor R2, a third resistor R3 and a second PN junction unit J2 connected in series, a first end of the second resistor R2 being connected to the first node N1, a second end of the second resistor R2 being connected to the non-inverting input terminal of the first amplifier AMP1; a first end of the third resistor R3 being connected to the non-inverting input terminal of the first amplifier AMP1, a second end of the third resistor R3 being connected to the positive electrode of the second PN junction unit J2, the negative electrode of the second PN junction unit J2 being grounded.

[0136] The first output transistor MO1 has a source connected to the power supply voltage VCC, a gate connected to the output terminal of the first amplifier AMP1, and a drain for outputting the first current I1.

[0137] The first feedback transistor MB1 and the first output transistor MO1 can be P-type transistors.

[0138] The number of the second PN junction units J2 can be multiple. The multiple second PN junction units J2 are connected in parallel, the positive electrode of each second PN junction unit being connected to the second end of the third resistor R3, and the negative electrode of each second PN junction unit being grounded. In an embodiment, the number of the second PN junction units can be N=(M+2) 2 -M 2 , and the number of the first PN junction units is M 2 , where M is an integer greater than or equal to 1. In this way, the second PN junction units J2 can be arranged around the first PN junction units J1 to form an (M+2)*(M+2) PN junction unit array during manufacturing.

[0139] For example, when M=1, N=3, the number of the first PN junction units J1 is 1, and the number of the second PN junction units J2 is 3*3-1=8, the first PN junction units J1 and the second PN junction units J2 are arranged in a 3*3 array.

[0140] When M=2, N=4, the number of the first PN junction units J1 is 4, and the number of the second PN junction units J2 is 4*4-4=12, the first PN junction units J1 and the second PN junction units J2 are arranged in a 4*4 array.

[0141] When M=3, N=5, the number of the first PN junction units J1 is 9, and the number of the second PN junction units J2 is 5*5-9=16, the first PN junction units J1 and the second PN junction units J2 are arranged in a 5*5 array. Similarly, when M=4, N=6, the number of the first PN junction units J1 is 16, and the number of the second PN junction units J2 is 6*6-16=20, the first PN junction units J1 and the second PN junction units J2 are arranged in a 6*6 array.

[0142] In Figure 7 In the embodiment shown, for simplicity of analysis, let M=1, N=3, the number of first PN junction units J1 is 1, and the number of second PN junction units J2 is 8.

[0143] In Figure 7 In the embodiment shown, the first resistance R1 and the second resistance R2 are the same. Due to the virtual short characteristic of the amplifier, the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the first resistance R1 between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the second resistance R2 between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, so the current on the first bridge arm B1 and the second bridge arm B2 is the same.

[0144] Continuing the inference, the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the PN junction voltage V BE1 of the first PN junction unit J1, so the voltage at the first end of the third resistance R1 is . Let the voltage at the second end of the third resistance R3, i.e. the positive electrode of the second PN junction unit J2, be According to the PN junction V-I characteristic expression, we have:

[0145] (1)

[0146] where, is the current of the PN junction unit, is the reverse saturation current of the PN junction unit (related to temperature, constant when the temperature is determined), V T is the thermal voltage, V T =kT / q, K is the Boltzmann constant, q is the electron charge, k=1.38×10 - 23 J / K (Joule / Kelvin), q=1.6×10 -19 C (Coulomb); T is the absolute temperature, in Kelvin. V T , also known as the voltage equivalent of temperature, refers to the potential difference in a closed circuit due to the temperature difference between two points. When T=300K (normal temperature), V T =kT / q≈0.026V. n is the emission coefficient, related to the size, material of the PN junction and the current passing through, between 1-2.

[0147] Since the currents on the first bridge arm B1 and the second bridge arm B2 are equal, the currents on the eight parallel second PN junction units J2 are equal to the currents on the first PN junction unit J1. Let the current on each second PN junction unit J2 be... Then the current on the first PN junction unit J1 is 8. .

[0148] When the number of the first PN junction unit J1 and the second PN junction unit J2 are other values, let the current of each second PN junction unit J2 be... Then the current on the first PN junction unit J1 is Z. Z represents the ratio of the number of second PN junction units J2 to the number of first PN junction units J1.

[0149] When V BE Much greater than V T When n=1, the 1 in the parentheses of formula (1) can be ignored, and we have:

[0150] (2)

[0151] thereby,

[0152] (3)

[0153] Similarly, we obtain V BE2 The formula:

[0154] (4)

[0155] Based on the same assumptions and derivations, we obtain:

[0156] (5)

[0157] Therefore, the voltage V across the third resistor R3 BE1 -V BE2 have:

[0158] (6)

[0159] Therefore, the current I on the second bridge arm B2 112 have:

[0160] (7)

[0161] Where R3 is the resistance value of the third resistor R3. Since N is fixed, and Proportional, V T The current I on the second bridge arm B2 is proportional to the temperature T. 112 It is proportional to temperature T and has a positive temperature coefficient.

[0162] In the above formula, when the number of the first PN junction unit J1 and the second PN junction unit J2 is other values, the number 8 in the formulas (2)-(7) can be replaced by the number ratio Z of the second PN junction unit J2 and the first PN junction unit J1.

[0163] Since the current on the first bridge arm B1 and the second bridge arm B2 is the same, the current of the first feedback transistor MB1 is equal to twice the current on the second bridge arm B2, that is, 2V T lnZ / R3.

[0164] The first feedback transistor MB1 and the first output transistor MO1 constitute a current mirror. In an embodiment, the ratio of the channel width-length ratio of the first feedback transistor MB1 and the first output transistor MO1 is 2:1, so that the first current I1 output by the drain of the first output transistor MO1 is equal to one half of the current on the first feedback transistor MB1, that is, equal to the current I 112 .

[0165] It can be seen that the current I1 output by the drain of the first output transistor MO1 is negatively related to the resistance value of the third resistor R3, so that the third resistor R3 can be set as an adjustable resistor to adjust the value of the first current I1.

[0166] In the embodiment shown in Figure 7 , the first PN junction unit J1 and the second PN junction unit J2 are implemented by a self-biasing transistor, which is an N-type transistor, and the gate and the source of the self-biasing transistor are both grounded. In other embodiments of the present disclosure, the implementation of the first PN junction unit J1 and the second PN junction unit J2 can also have many forms, and can also be directly implemented by a diode, which is not specially limited in the present disclosure.

[0167] Continuing to refer to the embodiment shown in Figure 7 , the negative temperature coefficient current generation unit 12 can include:

[0168] a second amplifier AMP2, the inverting input terminal of the second amplifier AMP2 is connected to the inverting input terminal of the first amplifier AMP1;

[0169] a second feedback transistor MB2, the source of the second feedback transistor MB2 is connected to the power supply voltage VCC, the gate is connected to the output terminal of the second amplifier AMP2, and the drain is connected to the non-inverting input terminal of the second amplifier AMP2;

[0170] a fourth resistor R4, one end of which is connected to the non-inverting input terminal of the second amplifier AMP2, and the other end is grounded;

[0171] The second output transistor MO2 has a source connected to the power voltage VCC, a gate connected to the output of the second amplifier AMP2, and a drain used for outputting the second current I2.

[0172] As can be seen from the analysis, the second output transistor MO2 and the second feedback transistor MB2 form a current mirror. The voltages at the non-inverting input and the inverting input of the second amplifier AMP2 are equal, and the voltage at the fourth resistor R4 is equal to the junction voltage V BE1 Therefore, the current at the second feedback transistor MB2 is equal to Assuming that the ratio of the channel width-length ratio of the second feedback transistor MB2 and the second output transistor MO2 is 1:1, and the second output transistor MO2 has the second current I2 output from the drain, it has:

[0173] (8)

[0174] According to formula (6), it is obtained that:

[0175] (9)

[0176] Therefore, it is obtained that:

[0177] (10)

[0178] The voltage drop generated by the PN junction when current flows through it is related to the forward current and the temperature. The greater the current, the greater the voltage drop, and the higher the temperature, the smaller the voltage drop. That is, the PN junction has a negative temperature coefficient voltage. Therefore, V BE2 is a negative temperature coefficient voltage, and I2 is a negative temperature coefficient current.

[0179] And the final output constant current I = I1 + I2, so the formula of the constant current I is:

[0180] (11)

[0181] wherein I1 is a positive temperature coefficient current, I2 is a negative temperature coefficient current, and are values related to the temperature T. By adjusting the resistance values of the third resistor R3 and the fourth resistor R4, when the derivative of formula (11) with respect to the temperature T is zero, the constant current I is a zero-temperature coefficient current.

[0182] In an exemplary embodiment of the present disclosure, the third resistor R3 and the fourth resistor R4 are both adjustable resistors, and both can be implemented by the embodiments shown in Figure 5A or Figure 5B , which will not be described here.

[0183] Figure 8 is a schematic diagram of a substrate reference voltage generation module in an embodiment of the present disclosure.

[0184] Reference Figure 8 In one embodiment, the substrate reference voltage generating module 12 can include:

[0185] a first N-type transistor MN1, a drain and a gate of the first N-type transistor MN1 are connected to a second node N2, the second node N2 is connected to a drain of a first output transistor MO1 and a drain of a second output transistor MO2, a source of the first N-type transistor MN1 is grounded, and the second node N2 is used to output a substrate reference voltage Vref with a negative temperature coefficient.

[0186] In Figure 8 In the embodiment shown, the substrate reference voltage Vref with a negative temperature coefficient is only affected by a constant current I and characteristics of the first N-type transistor MN1, and the constant current I is irrelevant to temperature, so the substrate reference voltage Vref with a negative temperature coefficient is only related to the characteristics of the first N-type transistor MN1.

[0187] According to the foregoing description, the threshold voltage (Vth) of the first N-type transistor MN1 decreases with the increase of temperature, and the current flowing through the first N-type transistor MN1 is a constant current I, which is proportional to the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) of the first N-type transistor MN1, so when the constant current I, the source voltage is unchanged, and the threshold voltage (Vth) decreases, the gate-source voltage (Vgs) of the first N-type transistor MN1, i.e. Vref, decreases. Therefore, the substrate reference voltage Vref is a negative temperature coefficient DE voltage, i.e. the higher the temperature, the smaller the voltage of the substrate reference voltage Vref. In addition, the faster the first N-type transistor MN1 opens, the smaller the threshold voltage Vth, i.e. the smaller the voltage of the substrate reference voltage Vref.

[0188] Therefore, the substrate reference voltage generating module 12 can automatically output the substrate reference voltage Vref with a negative temperature coefficient when the temperature changes.

[0189] According to a second aspect of the present disclosure, a chip is provided, which includes the power supply circuit according to any one of the above embodiments.

[0190] In one embodiment of the present disclosure, the power supply circuit providing the substrate voltage for the transistor can be switched according to the working mode of the chip by a switching circuit, for example, when the chip is normally working, the power supply circuit providing the substrate voltage for the transistor is the power supply voltage VCC, and when the chip enters the deep sleep mode (DSM), the power supply circuit of any one of the above embodiments is switched to provide the substrate voltage VBN for the chip.

[0191] In the embodiments of the present disclosure, the temperature is, for example, the working temperature (ambient temperature) of the chip. Assuming that a fixed power supply voltage VCC is used as the substrate voltage of the N-type transistor when the chip is normally working in a high-temperature environment, since the substrate voltage of the chip is the power supply voltage VCC which does not change with temperature when the chip is normally working, the power consumption caused by the leakage current can be ignored relative to the power consumption of the chip. When the chip enters the DSM mode, the power consumption caused by the leakage current accounts for a larger proportion, so at this time, the power supply circuit 100 of the embodiments of the present disclosure can be controlled to work by the switching circuit, and the substrate voltage of the N-type transistor is switched to the substrate voltage VBN of negative temperature coefficient (since VBN decreases with the decrease of Vref, and Vref is of negative temperature coefficient), so that the substrate voltage VBN will decrease or remain unchanged with the decrease of ambient temperature, thereby being able to reduce the leakage current caused by the increase of temperature, and thus reducing the power consumption of the chip in the DSM mode.

[0192] In the embodiments of the present disclosure, the power supply circuit providing the substrate voltage for the chip can be switched in various ways. For example, the enable of the driver DR can be controlled by the DSM signal, or a control switch is made between the oscillation module 21 and the charge pump module 22, or the enable of the reference voltage generation circuit 1 is directly controlled by the DSM signal, a selection circuit for selecting the source of the substrate voltage is made at the substrate end, and the like. There can be various ways to realize the switching of the substrate voltage, and the present disclosure does not specially limit this.

[0193] It should be noted that although several modules or units of the device for action execution are mentioned in the foregoing detailed description, such division is not mandatory. Indeed, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into several modules or units embodied.

[0194] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present application is intended to cover any and all variations which come within the scope of the present disclosure, taking into account the generic principles and features described herein and including modifications and equivalents thereof. The specification and examples are illustrative only and not restrictive of the true scope and spirit of the present disclosure. The true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A power supply circuit, characterized by comprising: include: A reference voltage generation circuit is used to generate a substrate reference voltage with a negative temperature coefficient. A voltage generation circuit is used to reduce the substrate voltage according to an enable signal; An enable signal generation circuit, connected to the reference voltage generation circuit and the voltage generation circuit, is used to output the enable signal to the voltage generation circuit when the substrate reference voltage is less than the conversion voltage proportional to the substrate voltage; The enable signal generation circuit includes: A voltage follower, wherein the non-inverting input terminal of the voltage follower is used to receive the substrate reference voltage, and the inverting input terminal is connected to the output terminal; The first voltage divider unit has two input terminals connected to the output terminal of the voltage follower and the power supply voltage, respectively, and the output terminal is used to output the first voltage divider voltage generated based on the substrate reference voltage and the power supply voltage. The second voltage divider unit has two input terminals connected to the output terminal of the voltage generation circuit and the power supply voltage, respectively, and the output terminal is used to output the second voltage divider voltage generated based on the substrate voltage and the power supply voltage. The comparator has its non-inverting input connected to the output of the first voltage divider unit and its inverting input connected to the output of the second voltage divider unit. An inverter, the input of which is connected to the output of the comparator, and the output of which is connected to the voltage generation circuit, are used to output the enable signal.

2. The power supply circuit of claim 1, wherein, The voltage generation circuit includes: An oscillation module has an input terminal for receiving the enable signal and an output terminal for outputting an oscillation signal. The oscillation module is used to generate the oscillation signal according to the enable signal. The charge pump module has its input terminal connected to the oscillation module and its output terminal used to output the substrate voltage. The charge pump module is used to reduce the substrate voltage according to the oscillation signal.

3. The power supply circuit of claim 2, wherein, The charge pump module includes: A first capacitor, the first terminal of which is coupled to the output terminal of the oscillation module; The first diode has its negative terminal grounded and its positive terminal connected to the second terminal of the first capacitor. The second diode has its negative terminal connected to the second terminal of the first capacitor, and its positive terminal used to output the substrate voltage.

4. The power supply circuit of claim 3, wherein, The charge pump module further includes a drive circuit connected between the output terminal of the oscillation module and the first terminal of the first capacitor, the drive circuit being used to increase the amplitude of the oscillation signal.

5. The power supply circuit of claim 3, wherein, The charge pump module further includes a second capacitor, the first end of which is connected to the positive terminal of the second diode, and the second end of which is grounded. The second capacitor is used to maintain the output voltage of the charge pump module.

6. The power supply circuit of claim 1, wherein, The first voltage divider unit includes a first voltage divider resistor unit and a second voltage divider resistor unit connected in series. The first end of the first voltage divider resistor unit is connected to the power supply voltage, the first end of the second voltage divider resistor unit is connected to the second end of the first voltage divider resistor unit, and the second end of the second voltage divider resistor unit is connected to the output terminal of the voltage follower. The resistance ratio of the first voltage divider resistor unit and the second voltage divider resistor unit is 1:(K1-1), where K1 is a first preset value.

7. The power supply circuit of claim 6, wherein, The second voltage dividing unit comprises a third voltage dividing resistor unit and a fourth voltage dividing resistor unit connected in series, a first end of the third voltage dividing resistor unit is connected to the power supply voltage, a first end of the fourth voltage dividing resistor unit is connected to a second end of the third voltage dividing resistor unit, and a second end of the fourth voltage dividing resistor unit is connected to an output end of the voltage generating circuit; wherein a resistance ratio of the third voltage dividing resistor unit and the fourth voltage dividing resistor unit is 1:(K2-1), and K2 is a second preset value.

8. The power supply circuit of claim 7, wherein, The resistance of the second voltage dividing resistor unit and the fourth voltage dividing resistor unit is adjustable.

9. The power supply circuit of claim 8, wherein, The second voltage dividing resistor unit and the fourth voltage dividing resistor unit each comprise a plurality of resistor sub-units connected in series, each resistor sub-unit comprises one or more sub-resistors, each resistor sub-unit is connected in parallel with a resistor adjusting switch tube, and a control end of each resistor adjusting switch tube receives a control signal.

10. The power supply circuit of claim 9, wherein, The resistance of each sub-resistor is equal.

11. The power supply circuit of claim 1, wherein, The reference voltage generating circuit comprises: a constant current generating module configured to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and generate a constant current according to the first current and the second current; a substrate reference voltage generating module comprising a transistor, the substrate reference voltage generating module being coupled to the constant current generating module and configured to generate the substrate reference voltage with a negative temperature coefficient according to the constant current and transistor characteristics.

12. The power supply circuit of claim 11, wherein, The constant current generating module comprises: a positive temperature coefficient current generating unit configured to generate the first current; a negative temperature coefficient current generating unit connected to the positive temperature coefficient current generating unit and configured to generate the second current.

13. The power supply circuit of claim 12, wherein, The positive temperature coefficient current generating unit comprises: a first amplifier; a first feedback transistor, a source of the first feedback transistor being connected to a power supply voltage, a gate of the first feedback transistor being connected to an output end of the first amplifier, and a drain of the first feedback transistor being connected to a first node; a first bridge arm, the first bridge arm comprising a first resistor and a plurality of first PN junction units connected in parallel in series, a first end of the first resistor being connected to the first node, a second end of the first resistor being connected to an inverting input end of the first amplifier, and positive poles of the first PN junction units being connected to the inverting input end of the first amplifier; a second bridge arm, the second bridge arm comprising a second resistor, a third resistor, and a plurality of second PN junction units connected in parallel in series, a first end of the second resistor being connected to the first node, a second end of the second resistor being connected to a non-inverting input end of the first amplifier; a first end of the third resistor being connected to the non-inverting input end of the first amplifier, a second end of the third resistor being connected to positive poles of the second PN junction units, and negative poles of the second PN junction units being grounded; a first output transistor, a source of the first output transistor being connected to the power supply voltage, a gate of the first output transistor being connected to the output end of the first amplifier, and a drain of the first output transistor being configured to output the first current.

14. The power supply circuit of claim 13, wherein, The resistance of the first resistor and the second resistor is equal.

15. The power supply circuit of claim 14, wherein, The number of the second PN junction units is N, N=(M+2) 2 -M 2 The number of the first PN junction units is M 2 , wherein M is an integer greater than or equal to 1.

16. The power supply circuit of claim 13, wherein, The negative temperature coefficient current generating unit comprises: a second amplifier, an inverting input end of the second amplifier being connected to the inverting input end of the first amplifier; a second feedback transistor, a source of the second feedback transistor is connected to the power supply voltage, a gate of the second feedback transistor is connected to an output terminal of the second amplifier, and a drain of the second feedback transistor is connected to a non-inverting input terminal of the second amplifier; a fourth resistor, one end of the fourth resistor is connected to the non-inverting input terminal of the second amplifier, and the other end of the fourth resistor is grounded; a second output transistor, a source of the second output transistor is connected to the power supply voltage, a gate of the second output transistor is connected to the output terminal of the second amplifier, and a drain of the second output transistor is used for outputting the second current.

17. The power supply circuit of claim 16, wherein, The third resistor and the fourth resistor are adjustable resistors, and a derivative of (kT / q)*lnZ / R3+(kT / q*lnZ+VBE2) / R4 with respect to temperature T is zero, where R3 is a resistance value of the third resistor, R4 is a resistance value of the fourth resistor, K is a Boltzmann constant, q is an electronic charge, T is a working temperature of the power supply circuit, VBE2 is a voltage difference between the second PN junction unit, and Z is a quantity ratio of the second PN junction unit to the first PN junction unit.

18. The power supply circuit of claim 16, wherein, The substrate reference voltage generation module comprises: a first N-type transistor, a drain and a gate of the first N-type transistor are connected to a second node, the second node is connected to a drain of the first output transistor and a drain of the second output transistor, a source of the first N-type transistor is grounded, and the second node is used for outputting the substrate reference voltage.

19. A chip, characterized by The power supply circuit comprises the substrate reference voltage generation module. The power supply circuit comprises the substrate reference voltage generation module.

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