Read retry method to enhance read performance and stability of 3D NAND memory

Abstract

The present disclosure provides a memory system for selecting from a plurality of read retry routines based on metadata. The memory system can include one or more memory devices and a memory controller. The memory controller can also detect a failure of a read operation. The memory controller can also analyze a set of values corresponding to a set of influencing factors of the read operation. The memory controller can select one or more read retry routines from the plurality of read retry routines based on the analysis. Each of the plurality of read retry routines can be associated with a different influencing factor of the set of influencing factors and a read voltage corresponding to the different influencing factor. The memory controller can also execute the selected one or more read retry routines at a portion of the one or more memory devices to eliminate the failure of the read operation.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more particularly to a method for enhancing read performance in 3D NAND memories. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, the miniaturization of planar memory cells faces challenges attributed to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND flash memory, multiple layers of memory cells can be vertically stacked, significantly increasing storage density per unit area. Vertically stacked memory cells form memory strings, with channels connecting the memory cells within each string. Each memory cell can be addressed via word lines and bit lines. Data (i.e., logical state) from memory cells sharing the same word line across an entire memory page can be read or programmed simultaneously. However, due to the aggressive scaling, reliability is likely a concern for 3D NAND flash memory. Summary of the Invention

[0004] This disclosure describes implementations of methods and systems for data protection in memory devices.

[0005] This disclosure describes a memory system for selecting from a plurality of read retry routines based on metadata to enhance read operations used by the memory system. In some embodiments, the memory system may include one or more memory devices and a memory controller coupled to the one or more memory devices. The one or more memory devices may store data. The memory controller may detect failures of read operations performed at a portion of the one or more memory devices. The memory controller may also analyze a set of values ​​corresponding to a set of factors influencing the read operation. The memory controller may also select one or more read retry routines from the plurality of read retry routines based on the analysis. Each of the plurality of read retry routines may be associated with a different influencing factor in the set of influencing factors and a read voltage corresponding to the different influencing factor. The memory controller may also execute the selected one or more read retry routines at a portion of the one or more memory devices to eliminate read operation failures.

[0006] In some implementations, the memory controller may also sense a set of values ​​at portions of one or more memory devices. The memory controller may also store the set of values ​​in the memory system based on the sensed values. The set of reference values ​​may include a set of references to the stored values.

[0007] In some implementations, the memory controller may also perform sensing of a set of values ​​at a designated trigger portion of one or more memory devices.

[0008] In some implementations, sensing a set of values ​​may include: assigning timestamps to portions of one or more memory devices for past programmed events.

[0009] In some implementations, sensing a set of values ​​may include sensing the temperature at a portion of one or more memory devices.

[0010] In some implementations, sensing a set of values ​​may include recording read counts at portions of one or more memory devices.

[0011] In some implementations, the memory controller may further include a non-transitory storage medium for storing a plurality of read retry routines.

[0012] In some implementations, one or more memory devices may include three-dimensional (3D) NAND memory devices.

[0013] In some implementations, the set of values ​​for the influencing factors may include timestamps of past programming events at portions of one or more memory devices. The selected one or more read retry routines may include read retry routines using read voltages corresponding to the time-based influencing factors of the read operation.

[0014] In some implementations, the set of values ​​for the influencing factors may include temperature at a portion of one or more memory devices. The selected one or more read retry routines may include read retry routines using a read voltage corresponding to the temperature-based influencing factors of the read operation.

[0015] In some implementations, the set of values ​​for influencing factors may include read counts at portions of one or more memory devices. The selected one or more read retry routines may include read retry routines using read voltages corresponding to the read count-based influencing factors of the read operation.

[0016] This disclosure provides an operation method for selecting from a plurality of read retry routines based on metadata to enhance read operations in a memory system. In some embodiments, the operation method may include storing data in one or more devices of the memory system. The operation method may also include detecting failures of read operations performed at a portion of the one or more memory devices. The operation method may further include analyzing a set of values ​​corresponding to a set of factors influencing the read operation. The operation method may further include selecting one or more read retry routines from the plurality of read retry routines based on the analysis. Each of the plurality of read retry routines may be associated with different influencing factors in the set of influencing factors and a read voltage corresponding to the different influencing factors. The operation method may further include performing the selected one or more read retry routines at a portion of the one or more memory devices to eliminate read operation failures.

[0017] In some embodiments, the method of operation may further include sensing a set of values ​​at a portion of one or more memory devices. The method of operation may further include storing the set of values ​​in a memory system based on the sensing. The set of reference values ​​may include a set of references to the stored values.

[0018] In some implementations, the method of operation may further include sensing a set of values ​​at a designated trigger portion of one or more memory devices.

[0019] In some implementations, sensing a set of values ​​may include: assigning timestamps to portions of one or more memory devices for past programmed events.

[0020] In some implementations, sensing a set of values ​​may include the temperature at a portion of one or more memory devices.

[0021] In some implementations, sensing a set of values ​​may include recording read counts at portions of one or more memory devices.

[0022] In some implementations, the method of operation may further include storing instructions for executing multiple read retry routines in a non-transitory storage medium of the memory controller.

[0023] In some implementations, the set of values ​​for the influencing factors may include timestamps of past programming events at portions of one or more memory devices. The selected one or more read retry routines may include read retry routines using read voltages corresponding to the time-based influencing factors of the read operation.

[0024] In some implementations, the set of values ​​for the influencing factors may include temperature at a portion of one or more memory devices. The selected one or more read retry routines may include read retry routines using a read voltage corresponding to the temperature-based influencing factors of the read operation.

[0025] In some implementations, the set of values ​​for influencing factors may include read counts at portions of one or more memory devices. The selected one or more read retry routines may include read retry routines using read voltages corresponding to the read count-based influencing factors of the read operation.

[0026] This disclosure provides a memory system for selecting from multiple read retry routines based on metadata to enhance read operations within the memory system. The memory system may include a memory controller coupled to one or more memory devices. The memory system may also include a non-transitory computer-readable medium. The non-transitory computer-readable medium may include instructions stored thereon, which, when executed by the memory controller, can cause one or more computing devices to perform the operations described above.

[0027] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings of this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0029] Figure 1 and Figure 2A-2B A storage system having one or more memory devices according to some embodiments is shown.

[0030] Figure 3 A schematic diagram of a memory die according to some embodiments is shown.

[0031] Figure 4 A schematic diagram of a three-dimensional (3D) memory die according to some embodiments is shown.

[0032] Figure 5 A perspective view of a portion of a 3D memory structure according to some embodiments is shown.

[0033] Figure 6 The threshold voltage V of a NAND flash memory according to some embodiments is shown. th distributed.

[0034] Figure 7 A diagram of the pages and dies of a 3D NAND memory according to some embodiments is shown.

[0035] Figure 8 A method for sensing a set of values ​​of influencing factors for a read operation, according to some embodiments, is shown.

[0036] Figure 9 A method for selecting from multiple read retry routines according to some implementations is shown.

[0037] The features and advantages of the invention will become more apparent when viewed in conjunction with the accompanying drawings, in which the same reference numerals consistently identify corresponding elements. In the drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral(s) of the corresponding reference numeral.

[0038] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0039] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0040] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in this specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment need not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0041] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context. It should be readily understood that the meaning of a "set" of elements can refer to one or more elements.

[0042] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only directly “on” something, but also includes the meaning of being “on” something with an intermediate feature or layer in between. Furthermore, “above” or “over” means not only “on” or “above” something, but also includes the meaning of being “on” or “over” something without an intermediate feature or layer in between (i.e., directly on something).

[0043] Furthermore, spatial relative terms, such as “below,” “under,” “down,” “above,” and “above,” are used herein for ease of description to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use of the equipment or process steps other than those depicted in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0044] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. Unless otherwise stated, the top surface of the substrate is typically where semiconductor devices are formed, and therefore the semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively distant from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0046] In this disclosure, for ease of description, the term "tier" is used to refer to elements that have substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as a "tier," a word line and the underlying insulating layer may be referred to together as a "tier," word lines having substantially the same height may be referred to as a "word line tier" or similar terms, and so on.

[0047] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the terms "approximately" or "approximately" indicate the value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the terms "approximately" or "approximately" can indicate the value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0048] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate.

[0049] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate.

[0050] Figure 1 A block diagram of a system S1 having a memory system 10 according to some embodiments is shown. In some embodiments, system S1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Memory system 10 (e.g., NAND memory system) may include a memory controller 20 and one or more semiconductor memory devices 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory device 25 (hereinafter referred to simply as a "memory device") may be a NAND chip (e.g., "flash memory", "NAND flash", or "NAND"). Memory system 10 may communicate with host computer 15 via memory controller 20, wherein memory controller 20 may be connected to one or more memory devices 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some implementations, each memory device 25 may be managed by the memory controller 20 via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n.

[0051] In some implementations, host computer 15 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host computer 15 may send data to be stored in memory system 10 and / or retrieve data from data stored in memory system 10.

[0052] In some implementations, memory controller 20 can process I / O requests received from host computer 15, ensure data integrity and efficient storage, and manage memory device 25. To perform these tasks, memory controller 20 can run firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller units, CPUs) of memory controller 20. For example, memory controller 20 can run firmware 21 to map logical addresses (e.g., addresses used by the host associated with host data) to physical addresses (e.g., the actual location where the data is stored) in memory device 25. Controller 20 also runs firmware 21 to manage defective memory blocks in memory device 25, where firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. Controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) that can be used to store various metadata used by firmware 21. In some implementations, memory controller 20 may also perform error recovery via error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors occurring within each memory device 25.

[0053] In some implementations, memory channel 30 may provide data and control communication between memory controller 20 and each memory device 25 via a data bus. Memory controller 20 may select one of the memory devices 25 based on an enable signal.

[0054] In some implementations... Figure 1 Each memory device 25 may include one or more memory dies 100, wherein each memory die may be a 3D NAND memory.

[0055] In some implementations, the memory controller 20 and one or more memory devices 25 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 10 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 20 and a single memory device 25 can be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA (Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a connector for connecting the memory card 26 to a host computer (e.g., Figure 1 The host computer 15) is coupled to the memory card connector 24. In such a way... Figure 2B In another example shown, the memory controller 20 and multiple memory devices 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host computer (e.g., Figure 1 The host computer 15) is coupled to the SSD connector 28.

[0056] Figure 3 A top view of a memory die 100 according to some embodiments is shown. Figure 3 The example configurations shown are given as non-limiting examples, and it should be understood that the memory is scalable. In some embodiments, the memory die 100 may include one or more memory faces 101, each of which may include multiple memory blocks 103. The same and concurrent operations may occur at each memory face 101. The size of the memory block 103 may be megabytes (MB), which is the minimum size to perform an erase operation. The memory die 100 may include, for example, four memory faces 101. Each memory face 101 may include, for example, six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell may be addressed by interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The orientation of the bit lines and word lines is... Figure 3 The memory blocks 103 are designated as "BL" and "WL". In this disclosure, memory block 103 is also referred to as a "memory array" or "array". A memory array is the core area in a memory device that performs storage functions.

[0057] In some embodiments, the memory die 100 may further include a peripheral circuitry region 105, i.e., the region surrounding the memory surface 101. The peripheral circuitry region 105 may include a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row decoders and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0058] In another embodiment, the peripheral circuit region 105 in the memory die 100 does not surround the memory surface 101, but the peripheral circuit region 105 in the memory die 100 can be disposed below the memory surface 101 by bonding together a first wafer for forming the peripheral circuit region 105 and a second wafer for forming the memory surface 101.

[0059] In some implementations... Figure 3 The arrangement of memory facets 101 in the memory die 100 and the arrangement of memory blocks 103 in each memory facet 101 shown are for illustrative purposes only and do not limit the scope of this disclosure.

[0060] Figure 4 A schematic diagram of a memory die 100 according to some embodiments is shown. In some embodiments, the memory die 100 may include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 may include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. Memory cells 340 sharing the same word line form memory pages 432. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, the at least one field-effect transistor being controlled by a lower select gate (“LSG”) 332 and a top select gate (“TSG”) 334, respectively. The lower select gate (“LSG”) may also be referred to as the bottom select gate (“BSG”). The drain terminal of the top select transistor 334-T may be connected to bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source (“ACS”) 430. The ACS 430 can be shared by memory string 212 throughout the memory block and is also referred to as the common source line.

[0061] In some embodiments, the memory die 100 may also include peripheral circuitry, which may include a variety of digital, analog, and / or mixed-signal circuits to support the functionality of the memory block 103, such as a page buffer / sensor amplifier 50, a row decoder / word line driver 40, a column decoder / bit line driver 52, control circuitry 70, a voltage generator 65, and an input / output buffer 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0062] In some implementations, memory block 103 may be coupled to line decoder / word line driver 40 via word line (“WL”) 333, lower select gate (“LSG”) 332, and top select gate (“TSG”) 334. Memory block 103 may be coupled to page buffer / sensor amplifier 50 via bit line (“BL”) 341. Line decoder / word line driver 40 may select one memory block of memory block 103 on memory die 100 in response to an X-path control signal provided by control circuitry 70. Line decoder / word line driver 40 may transmit voltage from voltage generator 65 to word line according to X-path control signal. During read and program operations, line decoder / word line driver 40 may transmit read voltage V according to X-path control signal received from control circuitry 70. read and programming voltage V pgm Transmitted to the selected word line, and will be transmitted through voltage V pass Transmitted to the non-selected word line.

[0063] In some implementations, the column decoder / bit line driver 52 can disable the voltage V based on a Y-path control signal received from the control circuitry 70. inhibit The data is transmitted to the unselected bit lines and the selected bit lines are connected to ground. That is, the column decoder / bit line driver 52 can be configured to select or deselect one or more memory strings 212 based on a Y-path control signal from the control circuitry 70. The page buffer / sensor amplifier 50 can be configured to read data from and program (write) data to the memory block 103 based on a Y-path control signal from the control circuitry 70. For example, the page buffer / sensor amplifier 50 can store a page of data to be programmed into a memory page 432. In another example, the page buffer / sensor amplifier 50 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sensor amplifier 50 can sense the current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification.

[0064] In some implementations, the input / output buffer 55 can transfer I / O data from / to the page buffer / sensor amplifier 50, and transfer address ADDR or command CMD to the control circuitry 70. In some implementations, the input / output buffer 55 can be used as a memory controller 20. Figure 1 The interface between the memory die 100 on the memory device 25 and the memory chip 100 on the memory device 25.

[0065] In some implementations, control circuitry 70 can control page buffer / sensor amplifier 50 and row decoder / word line driver 40 in response to command CMD transmitted by input / output buffer 55. During programming operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to program selected memory cells. During read operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to read selected memory cells. X-path control signals and Y-path control signals include row address X-ADDR and column address Y-ADDR, which can be used to locate selected memory cells in memory block 103. Row address X-ADDR may include page index PD, block index BD, and face index PL to identify memory page 432, memory block 103, and memory face 101, respectively. Figure 3 (In the middle). The column address Y-ADDR can identify a byte or word in the data of memory page 432.

[0066] In some implementations, voltage generator 65 can generate voltages to be supplied to word lines and bit lines under the control of control circuitry 70. The voltages generated by voltage generator 65 include the read voltage V. read Programming voltage V pgm Through voltage V pass Disabled voltage V inhibit wait.

[0067] Notice, Figure 1 , Figure 2A-2B and Figure 3-4 The arrangement of electronic components in the memory system 10 and memory die 100 is shown as a non-limiting example. In some embodiments, the memory system 10 and memory die 100 may have other arrangements and may include additional components. Figure 4 Components on the memory die 100 shown (e.g., control circuitry 70, I / O buffer 55) can also be removed from the memory die 100 as separate electrical components in the memory system 10. Figure 4Components on the memory die 100 shown (e.g., control circuitry 70, I / O buffer 55) can also be moved to other components in the memory system 10. For example, a portion of the control circuitry 70 can be combined with the memory controller 20, or vice versa.

[0068] Figure 5 A perspective view of a 3D memory structure 500 according to some embodiments is shown. In some embodiments, the memory die 100 may be a 3D NAND memory, and the 3D memory structure 500 may be a part of the memory die 100, for example, the 3D memory structure 500 in Figure 3 In region 108. The 3D memory structure 500 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include multiple memory strings 212, each memory string including multiple stacked memory cells 340. The stepped region 210 may include a stepped structure.

[0069] In some embodiments, the 3D memory structure 500 may include a substrate 330, an insulating film 331 above the substrate 330, a lower select gate (LSG) 332 above the insulating film 331, and multiple layers of a control gate 333 (also referred to as a "word line (WL)") stacked on top of the LSG 332 to form an alternating conductive and dielectric layer stack 335. For clarity, Figure 5 The dielectric layer adjacent to the layer of the control gate is not shown.

[0070] In some embodiments, the control gate of each layer is separated by slot structures 216-1 and 216-2 through the film stack 335. The 3D memory structure 500 may also include a layer of top select gate (TSG) 334 above the stack of control gates 333. The stack of TSG 334, control gate 333, and LSG 332 may also be referred to as a “gate electrode”. The 3D memory structure 500 may also include a doped source electrode region 344 in the portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 of the 3D memory structure 500 may include a channel via 336 extending through the film stack 335 of the insulating film 331 and alternating conductive and dielectric layers. The memory string 212 may also include a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core-fill film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. A portion of a channel layer 338 may be responsive to a corresponding control gate and is also referred to as the channel 338 of the memory cell. The 3D memory structure 500 also includes multiple bit lines (BLs) 341 that connect to the memory strings 212 above the TSG 334. The 3D memory structure 500 may also include multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each level of the gate electrode.

[0071] exist Figure 5 For illustrative purposes, a three-level hierarchy of control gates 333-1, 333-2, and 333-3 is shown together with one level of TSG 334 and one level of LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The 3D memory structure 500 may also include other structures such as TSG notches, common source contacts (i.e., arrayed common sources), and dummy memory strings. For simplicity, these structures are not shown. Figure 5 As shown in the image. Note that... Figure 5 The 3D memory structure 500 shown is for illustrative purposes only and does not limit the scope of this disclosure. Any other suitable 3D memory structure may be adopted.

[0072] Return to reference Figure 4In some embodiments, memory block 103 can be formed based on floating gate technology. In some embodiments, memory block 103 can be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. Logic states (“states”, such as the threshold voltage V of memory cell 340) th The stored data in the form of () depends on the number of charge carriers trapped in the memory membrane 337 of the memory cell 340.

[0073] In some implementations, in a NAND flash memory, read and write operations (also known as programming operations) can be performed on memory page 432, and erase operations can be performed on memory block 103.

[0074] In some implementations, in the NAND memory, memory cell 340 can be in an erase state ER or a programmable state P1. Initially, memory cell 340 in memory block 103 can be reset to the erase state ER, which is logic "1", by implementing a negative voltage difference between control gate 333 and channel 338 to remove trapped charge carriers in the memory film of memory cell 340. For example, this can be achieved by setting the control gate 333 of memory cell 340 to ground and applying a high positive voltage (erase voltage V). erase A negative voltage difference is applied to ACS 430 to induce a negative voltage difference. In the erase state ER (“state ER”), the threshold voltage V of memory cell 340... th It can be reset to the lowest value.

[0075] In some implementations, during programming (i.e., writing), a programming voltage V can be applied, for example, to the control gate 333. pgm (For example, a positive voltage pulse between 10V and 20V) and grounding the corresponding bit line 341 to establish a positive voltage difference between the control gate 333 and the channel 338. As a result, charge carriers (e.g., electrons) can be injected into the memory film of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. th Therefore, memory cell 340 can be programmed to programming state P1 (“state P1” or logic “0”).

[0076] In some implementations, the threshold voltage V of the memory cell can be measured or sensed. th This determines the state of the memory cell (e.g., state ER or state P1). During a read operation, the read voltage V can be... read It is applied to the control gate 333 of the memory cell, and the current flowing through the memory cell can be measured at bit line 341. The voltage V can be applied... passApply to the unselected word line to enable the unselected memory cell.

[0077] In some implementations, NAND flash memory can be configured to operate in single-level cell (SLC) mode. To increase storage capacity, NAND flash memory can be configured to operate in multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC) mode, or any combination of these modes. In SLC mode, the memory cell stores 1 bit and has two logical states (“states”): logic {1 and 0}, i.e., states ER and P1. In MLC mode, the memory cell stores 2 bits and has four logical states: logic {11, 10, 01, and 00}, i.e., states ER, P1, P2, and P3. In TLC mode, the memory cell stores 3 bits and has eight logical states: logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., states ER and states P1-P7. In QLC mode, the memory cell stores 4 bits and has 16 logic states. The memory controller 20 of the memory system 10 (see...) Figure 1 The data received from the host computer 15 can be converted into the corresponding logical state of the memory cell on the memory die 100, and vice versa.

[0078] Figure 6 The threshold voltage V of a NAND flash memory programmed in three-cell (TLC) mode according to some embodiments is shown. th Distribution. In some implementations, each state of a memory cell may correspond to a threshold voltage V. th A specific range, where the threshold voltage V for each state th The distribution can be represented by a probability density function. In some implementations, the eight TLC states can be programmed using an incremental step pulse programming (ISPP) scheme, where step pulses V are added. step To incrementally increase the programming voltage V pgm Therefore, the eight TLC states can be programmed from state P1 with a lower threshold voltage to state P7 with the highest threshold voltage.

[0079] In some implementations, after programming, verification can be performed during the verification process using one or more read reference voltages V. R1 -V R7To verify the eight TLC states ER and P1-P7. This is done by reading one or more reference voltages V. R1 -V R7 The control gate applied to the target memory cell can determine the threshold voltage V of the memory cell. th The range. For example, to verify whether a memory cell is in state ER, a read reference voltage V can be used. R1 If the target memory cell is in state ER, then the threshold voltage V of the target memory cell... th Below the reading reference voltage V R1 The target memory cell can be switched on and a conductive path can be formed in the channel. If the target memory cell is in any of states P1-P7, the threshold voltage V of the target memory cell... th Higher than the reading reference voltage V R1 The target memory cell is thus turned off. The threshold voltage V of the target memory cell can be verified by measuring or sensing the current flowing through the target memory cell at the corresponding bit line via the page buffer / sensor amplifier 50. th Or state.

[0080] In some implementations, as described above, determining the two states ER and P1 stored in SLC mode relies solely on the read reference voltage V. R1 That's sufficient. To determine the four states ER and P1-P3 in MLC mode, the reference voltage V can be read. R1 V R2 and V R3 To determine the eight states ER and P1-P7 of the TLC mode, the reference voltage V can be read. R1 -V R7 For example, in TLC mode, the threshold voltage of state ER is lower than V. R1 And the threshold voltage of state P7 is higher than V. R7 The threshold voltage of state P1 is V R1 With V R2 Between these points, states P2-P6 can be similarly determined.

[0081] In some implementations, it is desirable to provide reliable and convenient read operations to retrieve programmed data from one or more memory cells. In practice, unintended electronic behavior in 3D NAND memory can cause read operations to fail. The likelihood of read errors may increase with the number of layers (e.g., from SLC to MLC or TLC). See again Figure 6Certain conditions in 3D NAND memory (e.g., temperature changes) can interfere with the distribution of threshold voltages. For example, the distribution of the threshold voltage for state ER can be disturbed as shown in distribution 602. Higher states may also be similarly disturbed. Figure 6 Non-limiting examples of variations of threshold voltage distributions 604, 606, and 608 corresponding to the distributions of states P1, P2, and P3 are shown (higher states may be similarly affected). If the effect on the threshold voltage distribution is significant enough, the read operation may fail (e.g., reading an incorrect value that is different from the value programmed in the memory cell).

[0082] In some implementations, the memory system 10 ( Figure 1 The 3D NAND flash memory (or its sub-components) can undergo power cycles (e.g., power outages, hibernation, wake-ups, etc.). When powered off or operating with limited power, one or more memory cells of the 3D NAND flash memory may experience significant temperature changes (e.g., from well above room temperature to near room temperature). In a non-limiting example, the operating temperature could be approximately 70-100°C and the room temperature could be approximately 20-30°C (which may vary depending on environmental conditions). When the 3D NAND flash memory is powered back on, the temperature difference may affect the threshold voltage distribution. Note that even if the programmed data in the memory cells is not corrupted, read failures may still occur in the manner described above. In this case, the programmed data is not lost, and the read operation can be modified and / or retried to retrieve the programmed data.

[0083] In some implementations, a method for resolving read errors may include executing a set of read retry routines. An exemplary read retry routine may simply include repeating the read operation that caused the read failure. Alternatively, a slightly more complex read retry routine may include a modified version of the read operation that addresses different influencing factors of the read operation. Influencing factors of the read operation may include phenomena affecting the read operation. These factors may include, for example, the time elapsed since the last programming of the memory cell, the time elapsed since the last read operation, the temperature of the memory cell, the time elapsed since the last temperature check, the number of previous reads performed on the memory cell, etc. Those skilled in the art will understand that other influencing factors of the read operation can be envisioned. Read retry attempts can be optimized for different conditions of the 3D NAND memory. Optimization may be based on the collection of metadata (e.g., timestamps, temperature, read interference, etc.) of various aspects of the 3D NAND memory.

[0084] Figure 7 A diagram illustrating the pages and dies of a 3D NAND memory 700 according to some embodiments is shown. In some embodiments, the 3D NAND memory 700 may be a memory system 10 ( Figure 1 Another representation of ). Unless otherwise stated, the previous references to Figure 1 The structure and function of the components described in (and other relevant figures) can also be applied to the reference. Figure 7 Similar elements as described.

[0085] In some implementations, the 3D NAND memory 700 may include multiple dies (e.g., memory die 100). Figure 1 , 3 Each die is labeled die-n, where n ranges from 0 to N. Each die may include multiple pages (e.g., memory page 432). Figure 4 Each page is labeled page-m, where m ranges from 0 to M. Sensing and storing metadata for each of the m pages in each of n dies can be time-consuming and require significant storage space. The implementations described herein are aimed at improving the read speed and operational efficiency of NAND memory devices. Therefore, in some implementations, the sensing and storage of metadata can be configured to occur at a designated trigger portion of the 3D NAND memory 700. For example, a given page of a given die can be selected as the trigger point. The association of the given page as the trigger point can be programmed, for example, in firmware 21 ( Figure 1 )middle. Figure 7 Trigger points 702 and 704 are shown as non-limiting examples. Typically, multiple portions of the 3D NAND memory 700 can be associated with corresponding trigger points.

[0086] In some implementations, operations can be performed at trigger points 702 and / or 704 (e.g., also referred to as "trigger portions of a NAND memory system or device" or "designated trigger portions"). The operation can be, for example, a read operation (sensing data stored in a page) or a programming operation (programming data into a page). Because the read / programming operation encounters a trigger point, one or more influencing factors of the read / programming operation can be sensed and recorded.

[0087] Figure 8 A method 800 for sensing a set of values ​​of influencing factors for a read operation, according to some embodiments, is illustrated. In some embodiments, the read operation may be performed on a device including 3D NAND memory (e.g., 3D NAND memory 700). Figure 7 Data storage system (e.g., memory system 10) Figure 1 The read operation is performed at a part of the ))

[0088] In some implementations, in step S802, method 800 may include checking whether the operation is related to a trigger point (e.g., Figure 7The trigger point 702) interacts with the data. As previously described, a check can be triggered when a read or program operation is performed at the portion of the 3D NAND memory associated with the trigger point. If so, in step S804, method 800 may include sensing and recording a timestamp associated with the trigger point. The trigger point may be, for example, a portion of the 3D NAND memory (e.g., as referenced in [reference]). Figure 7 The trigger point can be a given page, block, superblock (e.g., multiple blocks), etc. Timestamps can also be associated with programming events, temperature sensing events, read events, and / or other events.

[0089] In some implementations, in step S806, method 800 may include sensing and recording the temperature associated with the trigger point (e.g., at a given portion of the 3D NAND memory). If step S802 checks the trigger point and finds that it is not a trigger point, method 800 may skip to step S808 and perform one or more operations (e.g., proceed to the next page) at the next location.

[0090] In some implementations, if the operation performed at the trigger point is a read operation, method 800 may include recording read events (e.g., tracking the number of read counts performed on a specific portion of the 3D NAND memory). Read operations may slightly interfere with memory cells (e.g., read interference). A large number of read counts may accumulate interference to memory cells.

[0091] In some implementations, the sensed values ​​of different influencing factors of the read operation can be recorded as metadata in RAM 23 ( Figure 1 )middle.

[0092] Figure 9 A method 900 for selecting from multiple read retry routines according to some embodiments is illustrated. In some embodiments, the selection and subsequent execution from multiple read retry routines may be performed based on metadata collected using method 800. In some embodiments, for example, steps of method 900 may be triggered when a read operation fails. Steps of method 900 may access and compare the trigger point with the portion of the 3D NAND memory where the read operation failed (e.g., Figure 7 The metadata associated with the trigger point 702. The collection of values ​​of factors influencing the read operation (stored as metadata, for example, in a list or table) may include timestamps, temperature, read counts, one or more other factors or combinations thereof.

[0093] In some implementations, a read retry routine can be used when a standard read operation fails. The read retry routine may include a modified read operation for retrying the read, which is specifically designed to overcome different failure conditions of the standard read operation (e.g., failure due to temperature, failure due to read interference, etc.).

[0094] In some implementations, in step S902, method 900 may include checking or determining whether a set of data retention conditions has been met. The term "data retention" may refer to the ability of a memory cell to retain its data. Over time, electrons may leak (e.g., electron tunneling) into the charge trapping layer (e.g., memory film 337). Figure 4 Electron leakage can occur from the charge trapping layer or from other sources. Electron leakage can lead to programmed distributions (e.g., see...). Figure 6 This can lead to widening and / or shifting. To address this effect, instead of performing regular read retries using an unadjusted read voltage, read retries based on data retention metadata can be performed using an adjusted read voltage.

[0095] In some implementations, the memory controller 20 ( Figure 1 The method 900 can analyze the length of time elapsed since the last operation was performed at the memory cell associated with the trigger point (e.g., comparing the current time with a timestamp from metadata). If the set of data retention conditions is not met, method 900 can skip step S904. If the set of data retention conditions is met, method 900 can proceed to step S904, where S904 selects one of a plurality of read retry routines associated with data retention (e.g., using an adjusted read voltage). The read retry routine selected from the plurality of read retry routines in step S904 can include one based on the memory system 10 ( Figure 1 A read operation associated with a timestamp (e.g., a read voltage adjustment can be based on a timestamp). This part of the memory system can be, for example, trigger point 702 ( Figure 7 The read retry routine may include, for example, a read operation that includes an adjusted prepulse duration that differs from the prepulse duration used in a failed read operation.

[0096] In some implementations, one or more parameters for read retry based on data retention can be determined based on large-scale experiments (e.g., in a factory). For example, a large sample of memory devices and memory cells can be tested to determine the optimal read voltage (adjusted read voltage) for memory cells used to retain data for approximately 1 year, 2 years, 3 years, etc. The testing can be further refined using temperature data. For example, the optimal read voltage can be determined for memory cells that retain data for 1 year at 40°C, 1 year at 55°C, 3 years at 40°C, 3 years at 55°C, etc. The resulting voltage adjustment and triggering conditions (e.g., data retention conditions) can be stored in the memory controller 20. Figure 1 ( ) in non-transitory storage media or in pages of NAND memory devices.

[0097] In some implementations, in step S906, method 900 may include checking whether a set of temperature conditions has been met. For example, the parameter of interest may be a temperature difference. An example of a temperature difference could be a comparison between a programming operation performed on a memory cell with an elevated temperature and a read operation performed on a memory cell with the memory cell at a temperature below the elevated temperature. Another example could be a comparison between a programming operation performed on a memory cell with a low temperature and a read operation performed on the memory cell with the memory cell at an elevated temperature. Other temperature difference scenarios are conceivable. Temperature differences can lead to a distribution of programming (e.g., see...). Figure 6 This can lead to widening and / or shifting. To address this effect, read retries based on temperature condition metadata can use an adjusted read voltage specifically tailored to temperature conditions, compared to performing regular read retries using an unadjusted read voltage.

[0098] In some implementations, the memory controller 20 ( Figure 1 The memory controller 20 can record the temperature of the memory cell (e.g., at a trigger point) while programming the memory cell. When reading data back from the memory cell later, the memory controller 20... Figure 1 The current temperature of the memory cell can be analyzed by comparing a set of temperature conditions associated with the trigger point with an earlier recorded programming temperature. If the set of temperature conditions is not met, method 900 can skip step S908. If the set of temperature conditions is met, method 900 can proceed to step S908, whereby S908 selects one of a plurality of read retry routines associated with the temperature. The read retry routine selected from the plurality of read retry routines in step S908 may include one based on the memory system 10 ( Figure 1 Part of (e.g., trigger point 702) Figure 7 The associated temperature reading operation.

[0099] In some implementations, one or more parameters of the temperature-based read retry can be determined based on large-scale experiments (e.g., in a factory). For example, a large sample of memory devices and memory cells can be tested to determine the optimal read voltage (adjusted read voltage) for memory cells having a temperature difference range associated with programming and read operations. The resulting voltage adjustment and triggering conditions (e.g., temperature conditions) can be stored in the memory controller 20. Figure 1 ( ) in non-transitory storage media or in pages of NAND memory devices.

[0100] In some implementations, in step S910, method 900 may include checking whether a set of read interference conditions has been met. For example, reads of NAND pages on the same physical block may be performed multiple times. This can lead to program distribution (e.g., see...). Figure 6 ) Shift. To address this effect, instead of performing regular read retries using an unadjusted read voltage, read retries based on read interference metadata can use an adjusted read voltage specifically tailored for different amounts of read interference.

[0101] In some implementations, the memory controller 20 ( Figure 1 The memory controller 20 can record counts of read operations performed on memory cells (e.g., at trigger points). When data is read back from the memory cell later, the memory controller 20... Figure 1 The read count of the record associated with the trigger point can be analyzed. Erase counts can also be used. If the set of read interference conditions is not met, method 900 can skip step S912. If the set of read interference conditions is met, method 900 can proceed to step S912, where S912 is used to select one of a plurality of read retry routines associated with the read interference. In this case, the selected read retry routine from the plurality of read retry routines may include one based on the memory system 10 ( Figure 1 Part of ) (e.g., trigger point 702) Figure 7 The read operation is the read count of the associated record.

[0102] In some implementations, one or more parameters for read retry based on read interference can be determined based on large-scale experiments (e.g., in a factory). For example, a large sample of memory devices and memory cells can be tested to determine the optimal read voltage (adjusted read voltage) for memory cells with read counts of 3000, 10000, etc. Erasure counts can also be used. The resulting voltage adjustment and triggering conditions (e.g., read interference conditions) can be stored in the memory controller 20. Figure 1( ) in non-transitory storage media or in pages of NAND memory devices.

[0103] In some implementations, in step S914, method 900 may include checking whether a given set of other category conditions has been met. For example, a routine may analyze the timestamp and temperature of a record associated with a trigger point. If the given set of other category conditions is not met, method 900 may skip step S916. If the given set of other category conditions is met, method 900 may proceed to step S916, whereby S916 selects one of a plurality of read retry routines associated with other categories. In this case, the selection of one read retry routine from the plurality of read retry routines may include selection based on the memory system 10 ( Figure 1 Part of (e.g., trigger point 702) Figure 7 The read operation is for another category of metadata associated with the read operation at step S916. The read operation in step S916 may have one or more parameters that are different from the read operations in steps S904, S908 and / or S912.

[0104] In some implementations, using method 900 to select read retry routines can significantly improve the performance of data storage systems (e.g., enterprise-class solid-state drives). In contrast, data storage systems that do not use metadata-related methods may need to use all read retry routines, or even randomly select from read retry routines, which can severely impact readback speeds and increase read latency.

[0105] The method steps in the embodiments disclosed herein can be performed in any conceivable order, and it is not required that all steps be performed.

[0106] In summary, this disclosure describes a memory system for selecting from a plurality of read retry routines based on metadata to enhance read operations used by the memory system. In some embodiments, the memory system may include one or more memory devices and a memory controller coupled to the one or more memory devices. The one or more memory devices may store data. The memory controller may detect failures of read operations at a portion of the one or more memory devices. The memory controller may also analyze a set of values ​​corresponding to a set of factors influencing read operations. The memory controller may also select one or more read retry routines from the plurality of read retry routines based on the analysis. Each of the plurality of read retry routines may be associated with different influencing factors in the set of influencing factors and a read voltage corresponding to the different influencing factors. The memory controller may also execute the selected one or more read retry routines on a portion of the one or more memory devices to eliminate read operation failures.

[0107] This disclosure also provides an operation method for selecting from a plurality of read retry routines based on metadata to enhance read operations in a memory system. In some embodiments, the operation method may include storing data in one or more devices of the memory system. The operation method may also include detecting failures of read operations performed at a portion of the one or more memory devices. The operation method may further include analyzing a set of values ​​corresponding to a set of influencing factors of the read operation. The operation method may further include selecting one or more read retry routines from the plurality of read retry routines based on the analysis, each of the plurality of read retry routines being associated with a different influencing factor in the set of influencing factors and a read voltage corresponding to the different influencing factor. The operation method may further include performing the selected one or more read retry routines at a portion of the one or more memory devices to eliminate read operation failures.

[0108] This disclosure also provides a memory system for selecting from multiple read retry routines based on metadata to enhance read operations within the memory system. The memory system may include a memory controller coupled to one or more memory devices. The memory system may also include a non-transitory computer-readable medium. The non-transitory computer-readable medium may include instructions stored thereon that, when executed by the memory controller, cause one or more computing devices to perform the operations described above.

[0109] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt these specific embodiments for various applications by applying knowledge of the art without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on this disclosure and guidance.

[0110] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0111] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore are not intended to limit this disclosure and the appended claims in any way.

[0112] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory system, comprising: One or more memory devices are configured to store data; as well as A memory controller, coupled to the one or more memory devices, is configured to: Detect failures of read operations performed at a portion of the one or more memory devices; Determine the trigger portion closest to the portion of the one or more memory devices where a read operation failure was detected, wherein the trigger portion is one or more memory blocks or one or more memory pages, and wherein the trigger portion is a designated portion of the memory system that senses and stores a set of values ​​of a set of influencing factors as metadata; Access the set of values ​​of the set of influencing factors of the read operation associated with the trigger portion; An analysis is performed on the set of values ​​of the set of factors influencing the read operation that are associated with the portion of the one or more memory devices. Based on the analysis, one or more read retry routines are selected from a plurality of read retry routines, wherein each of the plurality of read retry routines is associated with: different influencing factors from the set of influencing factors, and a read voltage corresponding to the different influencing factors; and Execute the selected one or more read retry routines at the portion of the one or more memory devices to eliminate the failure of the read operation.

2. The memory system according to claim 1, wherein, The memory controller is also configured to: Sensing the set of values ​​at said portions of said one or more memory devices; and The set of values ​​is stored in the memory system based on the sensing.

3. The memory system according to claim 2, wherein, The memory controller is also configured to execute the read retry routine with an adjusted prepulse duration that is different from the prepulse duration used in the failed read operation.

4. The memory system according to claim 2, wherein, Sensing the set of values ​​at the portion of the one or more memory devices includes assigning timestamps to past programming events at the portion of the one or more memory devices.

5. The memory system according to claim 2, wherein, Sensing the set of values ​​at the portion of the one or more memory devices includes: sensing the temperature at the portion of the one or more memory devices.

6. The memory system according to claim 2, wherein, Sensing the set of values ​​at the portion of the one or more memory devices includes recording read counts at the portion of the one or more memory devices.

7. The memory system according to claim 1, wherein, The memory controller includes a non-transitory storage medium configured to store the plurality of read retry routines.

8. The memory system according to claim 1, wherein, The one or more memory devices include three-dimensional (3D) NAND memory devices.

9. The memory system according to claim 1, wherein: The set of values ​​for the influencing factors includes timestamps of past programming events at the portion of the one or more memory devices; and The selected one or more read retry routines include read retry routines that use a read voltage corresponding to the time-based impact factors of the read operation.

10. The memory system according to claim 1, wherein: The set of values ​​for the influencing factors includes the temperature at the portion of the one or more memory devices; and The selected read retry routines include read retry routines that use a read voltage corresponding to the temperature-based influencing factors of the read operation.

11. The memory system according to claim 1, wherein: The set of values ​​for the influencing factors includes read counts at the portions of the one or more memory devices; and The selected one or more read retry routines include read retry routines that use read voltages corresponding to the read count-based influencing factors of the read operation.

12. A method of operating a memory system, comprising: The data is stored in one or more memory devices of the memory system; Detect failures of read operations performed at a portion of the one or more memory devices; Determine the trigger portion closest to the portion of the one or more memory devices where a read operation failure was detected, wherein the trigger portion is one or more memory blocks or one or more memory pages, and wherein the trigger portion is a designated portion of the memory system that senses and stores a set of values ​​of a set of influencing factors as metadata; Access the set of values ​​of the set of influencing factors of the read operation associated with the trigger portion; An analysis is performed on the set of values ​​of the set of factors influencing the read operation that are associated with the portion of the one or more memory devices. Based on the analysis, one or more read retry routines are selected from a plurality of read retry routines, wherein each of the plurality of read retry routines is associated with: different influencing factors from the set of influencing factors, and a read voltage corresponding to the different influencing factors; and Execute one or more selected read retry routines on the portion of the one or more memory devices to eliminate the failure of the read operation.

13. The operating method according to claim 12, further comprising: Sensing the set of values ​​at the portion of the one or more memory devices; as well as The set of values ​​is stored in the memory system based on the sensing, wherein the set of references to the values ​​includes the set of references to the stored values.

14. The operating method according to claim 13, further comprising: The read retry routine is executed using an adjusted prepulse duration that differs from the prepulse duration used in the failed read operation.

15. The operating method according to claim 13, wherein, Sensing the set of values ​​at the portion of the one or more memory devices includes assigning timestamps to past programming events at the portion of the one or more memory devices.

16. The operating method according to claim 13, wherein, Sensing the set of values ​​at the portion of the one or more memory devices: sensing the temperature at the portion of the one or more memory devices.

17. The operating method according to claim 13, wherein, Sensing the set of values ​​at the portion of the one or more memory devices: recording the read count at the portion of the one or more memory devices.

18. The operating method according to claim 12, further comprising: Instructions for executing the plurality of read retry routines are stored in the non-transitory storage medium of the memory controller.

19. The operating method according to claim 12, wherein: The set of values ​​for the influencing factors includes timestamps of past programming events at the portion of the one or more memory devices; and The selected one or more read retry routines include read retry routines that use a read voltage corresponding to the time-based impact factors of the read operation.

20. The operating method according to claim 12, wherein: The set of values ​​for the influencing factors includes the temperature at the portion of the one or more memory devices; and The selected read retry routines include read retry routines that use a read voltage corresponding to the temperature-based influencing factors of the read operation.

21. The operating method according to claim 12, wherein: The set of values ​​for the influencing factors includes read counts at the portions of the one or more memory devices; and The selected one or more read retry routines include read retry routines that use read voltages corresponding to the read count-based influencing factors of the read operation.

22. A memory system, comprising: A memory controller, coupled to one or more memory devices of the memory system; as well as A non-transitory computer-readable medium having instructions stored thereon, which, when executed by the memory controller, cause the memory controller to perform an operating method according to any one of claims 12 to 21.

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