Array substrate and manufacturing method thereof, and display panel

Abstract

The present application discloses an array substrate, a manufacturing method thereof, and a display panel. The manufacturing method of the array substrate includes: forming a bridging metal layer and a gate on a substrate; forming a gate insulating layer, a semiconductor layer, a second metal layer, and a first protective layer on the substrate, wherein the gate insulating layer covers the gate and the bridging metal layer; forming a three-segment photoresist with different thicknesses on the first protective layer, and using the three-segment photoresist as a mask, patterning the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, after patterning, a portion of the photoresist remains on the first protective layer; continuing to form a transparent conductive connection layer on the substrate; stripping off the remaining portion of the photoresist so that the transparent conductive connection layer forms a conductive connection layer and a pixel electrode arranged at intervals; etching the first protective layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode. The present application aims to reduce the number of masks required for producing array substrates, simplify the process flow, and reduce production costs.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become one of the mainstream display technologies. The manufacturing process of TFT array substrates has a significant impact on panel production costs. The TFT array substrate manufacturing process includes film formation, exposure, development, and etching. The thin film transistor (TFT) gate, gate insulation layer, semiconductor layer, source electrode, drain electrode, and protective layer all require patterning. During the patterning process, each layer requires multiple exposures, which require the use of multiple photomasks.

[0003] The manufacturing process for TFT array substrates has evolved from a seven-mask process to the current five- or four-mask process, which has become the mainstream process for TFT array substrate production. However, the display panel market is increasingly demanding on the production efficiency of TFT array substrates. The production of existing TFT array substrates requires five or four masks, which results in a large number of masks and a complex process flow, leading to high production costs.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0005] The purpose of this application is to provide an array substrate and a manufacturing method thereof, and a display panel, aiming to reduce the number of masks required for producing the array substrate, simplify the process flow, and reduce production costs.

[0006] To solve the above problems, the technical solutions of this application are as follows:

[0007] This application proposes a method for manufacturing an array substrate, which includes the following steps:

[0008] forming a first metal layer on the substrate;

[0009] patterning the first metal layer to form a bridging metal layer and a gate;

[0010] forming a stacked gate insulating layer, a semiconductor layer, a second metal layer and a first protective layer in sequence on the substrate, wherein the gate insulating layer covers the gate and the bridge metal layer;

[0011] forming a three-stage photoresist with different thicknesses on the first protective layer, and using the three-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, wherein after patterning, a portion of the photoresist remains on the first protective layer;

[0012] continuing to form a transparent conductive layer on the substrate;

[0013] Stripping the remaining portion of the photoresist so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart; and

[0014] The first protection layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode are etched.

[0015] In one embodiment of the present application, the step of forming a three-segment photoresist with different thicknesses on the first protective layer, and using the three-segment photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, and leaving the remaining portion of the photoresist on the first protective layer after patterning, includes:

[0016] forming a three-stage photoresist with different thicknesses on the first protective layer, the three-stage photoresist including a hollow portion, a first photoresist portion, a second photoresist portion, and a third photoresist portion, wherein the thickness of the first photoresist portion is smaller than that of the second photoresist portion, the thickness of the second photoresist portion is smaller than that of the third photoresist portion, and the hollow portion exposes a portion of the first protective layer;

[0017] Etching a portion of the first protective layer exposed to the hollow portion to form the first via hole and the second via hole in the first protective layer;

[0018] peeling off the first photoresist portion;

[0019] forming a second protective layer in the first via hole and the second via hole, wherein the second protective layer covers the second metal layer exposed by the first via hole and the second via hole;

[0020] Using the second photoresist portion, the third photoresist portion, and the second protective layer as a mask, patterning the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer exposed by the first photoresist portion; and

[0021] The second protective layer and the second photoresist are peeled off.

[0022] In one embodiment of the present application, the step of forming three-stage photoresist with different thicknesses on the first protective layer includes:

[0023] forming a photoresist film on the first protective layer;

[0024] The photoresist film is etched to form two first photoresist portions spaced apart from each other, the third photoresist portion located between the two first photoresist portions, two second photoresist portions connected between the third photoresist portion and the two first photoresist portions, and the hollow portions in the two second photoresist portions, wherein one of the first photoresist portions is located above the bridging metal layer, and the third photoresist portion corresponds to the gate.

[0025] In one embodiment of the present application, the step of etching the first protective layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode includes:

[0026] Etching the first protective layer not covered by the conductive connection layer and the pixel electrode to form a first electrode protective layer and a second electrode protective layer that are spaced apart; and

[0027] The second metal layer exposed through the first electrode protection layer and the second electrode protection layer is etched to form a first electrode and a second electrode that are spaced apart.

[0028] This application proposes a method for manufacturing an array substrate, which includes the following steps:

[0029] forming a first metal layer on the substrate;

[0030] patterning the first metal layer to form a bridging metal layer and a gate;

[0031] forming a stacked gate insulating layer, a semiconductor layer, a second metal layer and a first protective layer in sequence on the substrate, wherein the gate insulating layer covers the gate and the bridge metal layer;

[0032] forming a two-stage photoresist with different thicknesses on the first protective layer, and using the two-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, wherein after patterning, a portion of the photoresist remains on the first protective layer;

[0033] continuing to form a transparent conductive layer on the substrate;

[0034] Stripping the remaining portion of the photoresist so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart; and

[0035] The first protection layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode are etched.

[0036] In one embodiment of the present application, the step of forming a two-stage photoresist with different thicknesses on the first protective layer, and using the two-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, and leaving the remaining portion of the photoresist on the first protective layer after patterning, includes:

[0037] forming a two-stage photoresist with different thicknesses on the first protective layer, the two-stage photoresist comprising a hollow portion, a second photoresist portion, and a third photoresist portion, wherein the thickness of the second photoresist portion is smaller than that of the third photoresist portion, and the hollow portion exposes a portion of the first protective layer;

[0038] Etching a portion of the first protective layer exposed to the hollow portion to form a first via hole, a second via hole, a third via hole, and a fourth via hole in the first protective layer;

[0039] forming a second protective layer in the first via hole and the second via hole, wherein the second protective layer covers the second metal layer exposed by the first via hole and the second via hole;

[0040] Using the second photoresist portion, the third photoresist portion, and the second protective layer as masks, patterning the second metal layer, the semiconductor layer, and the gate insulating layer exposed through the third via hole and the fourth via hole; and

[0041] The second protective layer and the second photoresist are peeled off.

[0042] In one embodiment of the present application, the step of forming the two-stage photoresist with different thicknesses on the first protective layer includes:

[0043] forming a photoresist film on the first protective layer;

[0044] The photoresist film is etched to form the third photoresist portion corresponding to the gate and two second photoresist portions connected on both sides of the third photoresist portion, and two spaced-apart hollow portions are formed on each of the second photoresist portions, one of the hollow portions is located above the bridging metal layer.

[0045] The present application proposes an array substrate, comprising: a substrate; a first metal layer, disposed on the substrate, comprising a bridging metal layer and a gate arranged at intervals; a gate insulating layer, disposed on the substrate and covering the bridging metal layer and the gate; a semiconductor layer, disposed on the gate insulating layer; a first electrode and a second electrode, the first electrode and the second electrode being spaced apart and disposed on the semiconductor layer; a first protective layer, disposed on the first electrode and the second electrode, the first protective layer having a first via hole provided at a position corresponding to the first electrode, and the first protective layer having a second via hole provided at a position corresponding to the second electrode; a conductive connecting layer, disposed on the first protective layer, the conductive connecting layer being connected to the bridging metal layer and to the first electrode via the first via hole; and a pixel electrode, disposed on the first protective layer, the pixel electrode being connected to the second electrode via the second via hole, a portion of the pixel electrode extending onto the gate insulating layer, and a distance from the portion of the pixel electrode disposed on the gate insulating layer to the substrate being equal to the thickness of the first metal layer.

[0046] In one embodiment of the present application, the first protective layer includes a first electrode protective layer and a second electrode protective layer, the projection of the first electrode protective layer on the substrate overlaps with the projection of the first electrode on the substrate, and the projection of the second electrode protective layer on the substrate overlaps with the projection of the second electrode on the substrate.

[0047] The present application provides a display panel, comprising an array substrate, the array substrate comprising: a substrate; a first metal layer, disposed on the substrate, comprising a bridging metal layer and a gate arranged at intervals; a gate insulating layer, disposed on the substrate and covering the bridging metal layer and the gate; a semiconductor layer, the semiconductor layer disposed on the gate insulating layer; a first electrode and a second electrode, the first electrode and the second electrode being spaced apart and disposed on the semiconductor layer; a first protective layer, disposed on the first electrode and the second electrode, the first protective layer having a first via hole at a position corresponding to the first electrode, and the first protective layer having a second via hole at a position corresponding to the second electrode; a conductive connecting layer, disposed on the first protective layer, the conductive connecting layer being connected to the bridging metal layer and to the first electrode via the first via hole; and a pixel electrode, disposed on the first protective layer, the pixel electrode being connected to the second electrode via the second via hole, a portion of the pixel electrode extending onto the gate insulating layer, and a distance from the portion of the pixel electrode disposed on the gate insulating layer to the substrate being equal to the thickness of the first metal layer.

[0048] In the present application, the preparation of the array substrate only requires 2 photomasks. Compared with the existing array substrate process that requires 5 or 4 photomasks, the array substrate manufacturing method of the present application greatly reduces the number of photomasks required to produce the array substrate, simplifies the process flow of array substrate production, improves the production efficiency of the array substrate, and reduces the production cost of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a first flow chart of the method for manufacturing an array substrate of the present application;

[0050] Figure 2 is a schematic diagram of the array substrate of the present application;

[0051] Figure 3A-3S is a schematic diagram of steps 101-107 in the first flow chart of the method for manufacturing an array substrate of the present application;

[0052] Figure 4 is a second flow chart of the method for manufacturing an array substrate of the present application;

[0053] Figure 5A-5R It is a schematic diagram of steps 201-207 in the second flow chart of the method for manufacturing an array substrate of the present application. DETAILED DESCRIPTION

[0054] The meanings of the terms used in this specification and claims correspond to those commonly understood by persons of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are intended solely to facilitate the description and understanding of this application and are not intended to limit this application to the narrow interpretations of the specific terms used in the specification and claims.

[0055] Reference Figure 1 The present application proposes a method for manufacturing an array substrate 100, which includes the following steps:

[0056] Step 101 : forming a first metal layer 20 on a substrate 10 .

[0057] Specifically, see Figure 3A The substrate 10 may be a glass substrate 10 or a polyimide (PI) substrate 10. The first metal layer 20 may be made of metals such as copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or alloys such as brass, cast iron, aluminum-tungsten alloy, and molybdenum-aluminum alloy.

[0058] After the first metal layer 20 is formed, step 102 is continued: the first metal layer 20 is patterned to form a bridge metal layer 21 and a gate 22 .

[0059] Specifically, see Figure 3B First, a photoresist 85 is coated on the first metal layer 20; then Figure 3C , using a first preset mask to expose and develop the photoresist 85, and remove the photoresist 85 corresponding to the bridge metal layer 21 and the gate 22; and then Figure 3D , the first metal layer 20 not covered by the photoresist 85 is etched away, and the patterning of the first metal layer 20 is completed to form a bridge metal layer 21 and a gate 22. The bridge metal layer 21 and the gate 22 are spaced apart and arranged on the substrate 10. Finally, as shown in FIG. Figure 3E As shown, the photoresist 85 covering the bridge metal layer 21 and the gate 22 is removed by development.

[0060] During the process of removing the first metal layer 20 not covered by the photoresist 85 by etching, when the material of the first metal layer 20 is Al (Aluminum), the first metal layer 20 is etched using wet etching, wherein the active ingredients of the etching solution include nitric acid, phosphoric acid, acetic acid, and deionized water. When the material of the first metal layer 20 is Cu (Copper), the first metal layer 20 is etched using wet etching, wherein the active ingredients of the etching solution include hydrogen peroxide, iminodiacetic acid, 5-aminotetrazole, hydrogen fluoride, and water.

[0061] After forming the spaced-apart bridging metal layer 21 and the gate 22 , step 103 is continued: a stacked gate insulating layer 30 , a semiconductor layer 40 , a second metal layer 50 and a first protective layer 60 are sequentially formed on the substrate 10 , wherein the gate insulating layer 30 covers the gate 22 and the bridging metal layer 21 .

[0062] See also Figure 3F A gate insulating layer 30 is formed on the bridging metal layer 21 and the gate 22, and the gate insulating layer 30 covers the gate 22 and the bridging metal layer 21; a semiconductor layer 40 is formed on the gate insulating layer 30; a second metal layer 50 is formed on the semiconductor layer 40; and a first protective layer 60 is formed on the second metal layer 50.

[0063] The gate insulating layer 30 is made of one of silicon nitride, silicon oxide or silicon oxynitride, or the gate insulating layer 30 is a stacked structure of silicon nitride / silicon oxide, silicon nitride / silicon oxide / aluminum oxide, etc. The material of the semiconductor layer 40 can be selected from crystalline or amorphous oxide semiconductors or other types of semiconductors with high stability, such as single crystal silicon, single crystal non-metallic or metal oxides with low leakage current such as IGZO, IGTO, IGO, IZO, AIZO, ATZO, etc. The semiconductor layer 40 is connected to the first electrode 51 and the second electrode 52 ( Figure 2(shown in the figure) to form an ohmic contact, forming a channel. The material of the second metal layer 50 can be copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum or other metals or alloy materials such as brass, cast iron, aluminum-tungsten alloy, molybdenum-aluminum alloy. During the formation of the semiconductor layer 40, ion implantation can be performed on the semiconductor layer 40: heavy doping ion implantation is performed to form a heavily doped source or drain region. Specifically, the heavily doped ions are implanted below the first electrode 51 and the second electrode 52 to form a heavily doped source or drain region.

[0064] After forming the stacked gate insulating layer 30, semiconductor layer 40, second metal layer 50 and first protective layer 60, continue to step 104: form a three-stage photoresist with different thicknesses on the first protective layer 60, and use the three-stage photoresist as a mask to pattern the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30. After patterning, the photoresist remains on the first protective layer 60.

[0065] Specifically, see Figure 3G First, a photoresist is coated on the first protective layer 60 to form a photoresist film 80; then Figure 3H , use a second preset mask to expose and develop the photoresist film 80, remove the photoresist portion, and form a three-stage photoresist with different thicknesses; then Figure 3I As shown, the first protective layer 60 is patterned using a three-stage photoresist as a mask; then as shown in FIG. Figures 3J to 3L As shown, the second metal layer 50 is patterned; then as shown Figure 3M As shown, the semiconductor layer 40 is patterned; then as shown Figure 3N As shown, the gate insulating layer 30 is patterned; after patterning, as shown Figure 3O As shown, after a portion of the photoresist is stripped off, a remaining portion of the photoresist is formed on the first protective layer 60 .

[0066] In the process of patterning the first protective layer 60 , dry etching is used to etch the first protective layer 60 , wherein the etchant may be one of sulfur hexafluoride gas, nitrogen trifluoride gas and chlorine gas.

[0067] like Figure 3I As shown, during the process of patterning the first protective layer 60, a first via 61 and a second via 62 are formed in the first protective layer 60, the first via 61 exposes a portion of the second metal layer 50, and the second via 62 exposes a portion of the second metal layer 50, and the first via 61 and the second via are spaced apart.

[0068] During the patterning process of the first protective layer 60, a third via hole 63 and a fourth via hole 64 are formed in the first protective layer 60, the second metal layer 50, the semiconductor layer 40, and the gate insulating layer 30. The third via hole 63 exposes a portion of the gate insulating layer, and the fourth via hole 64 exposes a portion of the bridging metal layer 21. The distance from the bottom wall of the third via hole 63 to the substrate 10 is equal to the thickness of the first metal layer 20.

[0069] In the process of patterning the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30 using the three-stage photoresist as a mask, multiple ashing steps are performed to remove the smaller photoresist layers in the three-stage photoresist in turn, and then continue to etch each film layer using the remaining photoresist as a mask.

[0070] After patterning the first protection layer 60 , the second metal layer 50 , the semiconductor layer 40 and the gate insulating layer 30 , step 105 is continued to form a transparent conductive layer 70 on the substrate 10 .

[0071] Specifically, see Figure 3P A transparent conductive layer 70 is plated on a surface of the array substrate 100 facing away from the substrate 10. The material of the transparent conductive layer 70 includes indium tin oxide (ITO), wherein the indium tin oxide can be transparent indium tin oxide, and the transparent conductive layer 70 can also be an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) stacked layer.

[0072] The portion of the transparent conductive layer 70 covering the first protective layer 60 is connected to the second metal layer 50 through the first via 61 and the second via 62, a portion of the transparent conductive layer 70 extends through the third via 63 and is disposed on the gate insulating layer 30, another portion of the transparent conductive layer 70 is connected to the bridging metal layer 21 through the fourth via 64, and the remaining portion of the transparent conductive layer 70 covers the remaining portion of the photoresist.

[0073] After the transparent conductive layer 70 is formed on the substrate 10 , step 106 is continued: the remaining portion of the photoresist is stripped off to form the conductive connecting layer 71 and the pixel electrode 72 which are spaced apart from each other on the transparent conductive layer 70 .

[0074] Specifically, see Figure 3Q, peel off the remaining photoresist and the portion of the transparent conductive layer covering the surface of the remaining photoresist to form a conductive connection layer 71 and a pixel electrode 72 that are spaced apart, wherein the conductive connection layer 71 is connected to the second metal layer 50 and the bridging metal layer 21 through the first via 61 and the fourth via 64, the first part of the pixel electrode 72 is covered on the first protective layer 60, the second part of the pixel electrode 72 is connected to the second metal layer 50 through the second via 62, and the third part of the pixel electrode 72 extends to the gate insulating layer 30 through the third via 63.

[0075] After stripping off the remaining portion of the photoresist, proceed to step 107 : etching the first protection layer 60 and the second metal layer 50 that are not covered by the conductive connection layer 71 and the pixel electrode 72 .

[0076] Specifically, see Figure 3R and Figure 3S After the remaining photoresist is stripped, a portion of the first protective layer 60 is exposed to the transparent conductive layer 70. The portion of the first protective layer 60 exposed to the transparent conductive layer 70 is etched to form a fifth via hole 65 in the first protective layer 60 and the second metal layer 50.

[0077] On the first aspect, the fifth via 65 enables the first protective layer 60 to form a first electrode protective layer 66 and a second electrode protective layer 67 which are spaced apart, wherein the first electrode protective layer 66 is provided with a first via 61, and the second electrode protective layer 67 is provided with a second via 62, and the first electrode protective layer 66 and the second electrode protective layer 67 are spaced apart on the second metal layer 50.

[0078] Secondly, the fifth via 65 forms a first electrode 51 and a second electrode 52 spaced apart from each other on the second metal layer 50. A first electrode protection layer 66 is disposed on the first electrode 51, and the first via 61 exposes at least a portion of the first electrode 51. A second electrode protection layer 67 is disposed on the second electrode 52, and the second via 62 exposes at least a portion of the second electrode 52. A conductive connection layer 71 connects the first electrode 51 and the bridging metal layer 21, and a pixel electrode 72 connects to the second electrode 52 via the second via 62.

[0079] The fifth via 65 exposes a portion of the semiconductor layer 40. In one embodiment, the portion of the semiconductor layer 40 exposed by the fifth via 65 is oxidized to form an oxide film thereon, thereby improving the stability of the thin film transistor structure. The first electrode 51 serves as either the source or the drain of the thin film transistor, and the second electrode 52 serves as the other of the source or the drain of the thin film transistor.

[0080] In the process of manufacturing the array substrate 100, only two photomasks are used in step 102 and step 104. Compared with the technical solution of the existing array substrate 100 process that requires 5 or 4 photomasks, the manufacturing method of the array substrate 100 of the present application greatly reduces the number of photomasks required for producing the array substrate 100, simplifies the process flow of the array substrate 100 production, improves the production efficiency of the array substrate 100, and reduces the production cost of the array substrate 100.

[0081] In one embodiment of the present application, the step of forming a three-stage photoresist with different thicknesses on the first protective layer 60, and using the three-stage photoresist as a mask to pattern the first protective layer 60, the second metal layer 50, the semiconductor layer 40, and the gate insulating layer 30, and removing the remaining portion of the photoresist on the first protective layer 60 after patterning, includes:

[0082] Step 104a: Forming the three-section photoresist with different thicknesses on the first protective layer 60, wherein the three-section photoresist includes a hollow portion 81, a first photoresist portion 82, a second photoresist portion 83 and a third photoresist portion 84, the thickness of the first photoresist portion 82 is less than the thickness of the second photoresist portion 83, the thickness of the second photoresist portion 83 is less than the thickness of the third photoresist portion 84, and the hollow portion 81 exposes a portion of the first protective layer 60.

[0083] Specifically, see Figure 3G and Figure 3H , photoresist is coated on the first protective layer 60 to form a photoresist film 80 .

[0084] A second preset mask plate is used to expose and develop the photoresist film 80. The second preset mask plate is a three-section mask, which includes a light-shielding part, a first transmission part, a second transmission part and a full transmission part, wherein the light transmittance of the full transmission part is greater than the light transmittance of the first transmission part, the light transmittance of the first transmission part is greater than the light transmittance of the second transmission part, and the light transmittance of the second transmission part is greater than the light transmittance of the light-shielding part; the light transmittance of each part of the photoresist film 80 is adjusted by the three-section mask, and the photoresist film 80 is exposed and developed to form a hollow part 81 and a first photoresist part 82, a second photoresist part 83 and a third photoresist part 84 with different heights. Among them, the fully transparent part has the largest light transmittance, corresponding to the hollow portion 81 formed in the photoresist film 80; the first transparent part has a larger light transmittance, corresponding to the first light resist portion 82 with a thinner thickness formed in the photoresist film 80; the second transparent part has a smaller light transmittance, corresponding to the second light resist portion 83 with a thicker thickness formed in the photoresist film 80; the light shielding part has the smallest light transmittance, corresponding to the third light resist portion 84 with the thickest thickness formed in the photoresist film 80.

[0085] After forming three-stage photoresist with different thicknesses on the first protective layer 60 , proceed to step 104 b : etching the portion of the first protective layer 60 exposed to the hollow portion 81 to form the first via hole 61 and the second via hole 62 in the first protective layer 60 .

[0086] Specifically, see Figure 3H and 3I The photoresist film 80 includes at least two hollow portions 81 spaced apart from each other, and the portion of the first protective layer 60 exposed to the two hollow portions 81 spaced apart from each other is etched to form a first via hole 61 and a second via hole 62 in the first protective layer 60, wherein the first via hole 61 and the second via hole 62 respectively expose portions of the second metal layer 50.

[0087] After the first via hole 61 and the second via hole 62 are formed in the first protective layer 60 , step 104 c is continued: the first photoresist portion 82 is peeled off.

[0088] Specifically, see Figure 3J The three-stage photoresist is subjected to a first ashing process to remove the first photoresist portion 82, which is relatively thin. This exposes the portion of the first protective layer 60 originally covered by the first photoresist portion 82 to the photoresist film 80. During the first ashing process, the thicknesses of the second photoresist portion 83 and the third photoresist portion 84 are reduced accordingly, but the thickness of the second photoresist portion 83 is still less than that of the third photoresist portion 84.

[0089] After the first photoresist portion 82 is peeled off, step 104 d is continued: forming a second protective layer 90 in the first via hole 61 and the second via hole 62 , wherein the second protective layer 90 covers the second metal layer 50 exposed by the first via hole 61 and the second via hole 62 .

[0090] Specifically, see Figure 3J A second protective layer 90 is formed in the first via hole 61 and the second via hole 62 by inkjet printing technology (IJP). The material of the second protective layer 90 is an organic material, which can be PFA (Polymer Film on Array). PFA becomes transparent after curing and can replace the first protective layer 60 to play an insulating role.

[0091] After forming the second protective layer 90 in the first via hole 61 and the second via hole 62, continue to step 104e: using the second photoresist portion 83, the third photoresist portion 84 and the second protective layer 90 as mask templates, the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30 exposed by the first photoresist portion 82 are patterned.

[0092] Specifically, see Figure 3K 、 Figure 3L 、 Figure 3M and Figure 3N , the portion of the first protective layer 60 exposed to the second photoresist portion 83, the third photoresist portion 84 and the second protective layer 90 is etched, and a third via hole 63 and a fourth via hole 64 are formed on the upper surface of the first protective layer 60, wherein the third via hole 63 and the fourth via hole 64 respectively expose a portion of the second metal layer 50, the fourth via hole 64 is located on the side of the first via hole 61 away from the second via hole 62, and the third via hole 63 is located on the side of the second via hole 62 away from the first via hole 61.

[0093] See also Figure 3L , etching the portion of the second metal layer 50 exposed to the third via 63 and the portion of the second metal layer 50 exposed to the fourth via 64 so that the third via 63 and the fourth via 64 extend to expose a portion of the semiconductor layer 40 respectively.

[0094] See also Figure 3M , etching the portion of the semiconductor layer 40 exposed to the third via hole 63 and the portion of the semiconductor layer 40 exposed to the fourth via hole 64 so that the third via hole 63 and the fourth via hole 64 extend to expose a portion of the gate insulating layer 30 respectively.

[0095] See also Figure 3N , the portion of the gate insulating layer 30 exposed to the fourth via 64 is etched so that the fourth via 64 extends to expose at least a portion of the bridging metal layer 21, and the portion of the gate insulating layer 30 exposed to the third via 63 is etched so that the third via 63 extends into the gate insulating layer 30. At this time, the distance from the bottom wall of the third via 63 to the substrate 10 is equal to the thickness of the bridging metal layer 21.

[0096] Due to the limited accuracy of the process, in actual products, the distance from the bottom wall of the third via 63 to the substrate 10 is basically equal to the thickness of the bridging metal layer 21, where basically equal means that the ratio of the distance from the bottom wall of the third via 63 to the substrate 10 to the thickness of the bridging metal layer 21 is in the range of 0.9 to 1.1.

[0097] After patterning the first protective layer 60 , the second metal layer 50 , the semiconductor layer 40 and the gate insulating layer 30 , step 104 f is continued: stripping the second protective layer 90 and the second photoresist portion 83 .

[0098] Specifically, see Figure 3OStep 104f1: Etch the second protective layer 90 to remove the second protective layer 90 covering the first via hole 61 and the second via hole 62. The second protective layer 90 can be removed by dry etching or by ashing.

[0099] Step 104f2: A second ashing is performed on the second and third photoresist portions 83, 84. This removes the portion of the second photoresist portion 83 that is thinner than the third photoresist portion 84, thereby exposing the portion of the first protective layer 60 previously covered by the second photoresist portion 83 to the photoresist film 80. During the second ashing process, the thickness of the third photoresist portion 84 is also reduced accordingly, but the third photoresist portion 84 is not removed during the second ashing process. After the second ashing process, the third photoresist portion 84 still has a certain thickness. Furthermore, if any residue of the second protective layer 90 remains from step 104f1, the second ashing process can completely remove the residue.

[0100] In an optional embodiment, step 104f1 may not be performed and only step 104f2 may be performed. In this case, the second ashing may also remove the second protective layer 90 .

[0101] Alternatively, in an optional embodiment, step 104f2 may not be performed and only step 104f1 may be performed, that is, when the second protective layer 90 is removed by ashing, the second photoresist portion 83 is peeled off at the same time.

[0102] Regarding step 106: the remaining portion of the photoresist is stripped off, so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart.

[0103] Specifically, see Figure 3O Step 106a: Flocking the third light-resisting portion 84 to form a rough surface structure. The rough surface structure includes a plurality of nanopillars, and the height of the nanopillars is within the range of 100 nm to 200 nm. Specifically, the rough surface structure of the third light-resisting portion 84 is a velvet surface.

[0104] After the third photoresist portion 84 is flocked, step 106b is continued: a transparent conductive layer 70 is formed in the first via hole 61 , the second via hole 62 , the third via hole 63 , the fourth via hole 64 , the upper surface of the first protective layer 60 , and the outer surface of the third photoresist portion 84 .

[0105] Specifically, see Figure 3PThe material of the transparent conductive layer 70 includes indium tin oxide (ITO), wherein the indium tin oxide can be transparent indium tin oxide, and the transparent conductive layer 70 can also be an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) stack. During the deposition of the transparent conductive layer 70 on the third photoresist portion 84, a rough structure composed of multiple nano-pillars is formed on the surface of the third photoresist portion 84. Part of the transparent conductive layer 70 adheres to the nano-pillars and cannot fall onto the surface of the third photoresist portion 84. As a result, most of the area on the outer surface of the third photoresist portion 84 is not covered by the transparent conductive layer 70, thereby facilitating the peeling of the third photoresist portion 84 and the transparent conductive layer 70 located on the surface of the third photoresist portion 84.

[0106] After the transparent conductive layer 70 is formed, step 106 c is continued to be performed: the third photoresist portion 84 is peeled off, so that the transparent conductive layer 70 forms a conductive connection layer 71 and a pixel electrode 72 that are spaced apart.

[0107] The third photoresist portion 84 is the remaining portion of the photoresist mentioned above. Figure 3Q Because the rough structure on the surface of the third photoresist portion 84 is formed by a plurality of nanopillars, with numerous gaps between the nanopillars, the developer or etching solution can easily pass through the gaps and fully contact and act on the third photoresist portion 84, thereby completing the stripping of the third photoresist portion 84 where the transparent conductive layer 70 has been deposited. After the third photoresist portion 84 is stripped, the first protective layer 60 previously covered by the third photoresist portion 84 is exposed to the photoresist film 80, and the transparent conductive layer 70 forms a conductive connecting layer 71 and a pixel electrode 72 that are spaced apart.

[0108] In one embodiment of the present application, the step of forming three-stage photoresist with different thicknesses on the first protective layer 60 includes:

[0109] Step 104 a 1 : forming a photoresist film 80 on the first protective layer 60 .

[0110] Specifically, please refer to Figure 3G , photoresist is coated on the first protective layer 60 to form a photoresist film 80 .

[0111] After forming the photoresist film 80 on the first protective layer 60, continue to perform step 104a2: the photoresist film 80 is etched to form two first photoresist portions 82 spaced apart, the third photoresist portion 84 located between the two first photoresist portions 82, two second photoresist portions 83 connected between the third photoresist portion 84 and the two first photoresist portions 82, and the hollow portion 81 in the two second photoresist portions 83, wherein one of the first photoresist portions 82 is located above the bridging metal layer 21, and the third photoresist portion 84 corresponds to the gate 22.

[0112] Specifically, please refer to Figure 3H A three-segment light mask is provided on the photoresist film 80, the three-segment light mask including a light-shielding portion, a first transmissive portion, a second transmissive portion, and a fully transmissive portion, the light-shielding portion being used to shield light of a preset wavelength band, the first transmissive portion, the second transmissive portion, and the fully transmissive portion being used to transmit at least a portion of the light, the light transmittance of the fully transmissive portion being greater than the light transmittance of the first transmissive portion, the light transmittance of the first transmissive portion being greater than the light transmittance of the second transmissive portion, and the light transmittance of the second transmissive portion being greater than the light transmittance of the light-shielding portion;

[0113] The light transmittance of each portion of the three-segment mask is different, and the exposure amount of each portion of the photoresist film 80 is adjusted by the three-segment mask.

[0114] The photoresist film 80 is exposed and developed, and the hollow portion 81 of the first protective layer 60 is formed on the photoresist film 80 corresponding to the fully transmissive portion, the first photoresist portion 82 is formed on the photoresist film 80 corresponding to the first transmissive portion, the second photoresist portion 83 is formed on the photoresist film 80 corresponding to the second transmissive portion, and the third photoresist portion 84 is formed on the photoresist film 80 corresponding to the light-shielding portion.

[0115] Light of a preset wavelength band is transmitted through the fully transmissive part, the first transmissive part, the second transmissive part and the light-shielding part of the three-segment mask to expose the photoresist film 80; the photoresist film 80 exposed by the three-segment mask is developed to form a hollow portion 81 and a first photoresist portion 82, a second photoresist portion 83 and a third photoresist portion 84 of different thicknesses.

[0116] In one embodiment of the present application, the step of etching the first protective layer 60 and the second metal layer 50 that are not covered by the conductive connection layer 71 and the pixel electrode 72 includes:

[0117] Step 107 a : etching the first protection layer 60 that is not covered by the conductive connection layer 71 and the pixel electrode 72 to form a first electrode protection layer 66 and a second electrode protection layer 67 that are spaced apart.

[0118] Specifically, see Figure 3Q and Figure 3R The first electrode protection layer 66 is provided with the first via hole 61 , and the second electrode protection layer 67 is provided with the second via hole 62 .

[0119] After etching the first protective layer 60 not covered by the conductive connection layer 71 and the pixel electrode 72, proceed to step 107b: etching the second metal layer 50 exposed by the first electrode protective layer 66 and the second electrode protective layer 67 to form the first electrode 51 and the second electrode 52 arranged at intervals.

[0120] Specifically, see Figure 3S , a fifth via hole 65 is formed in the first protection layer 60 and the second metal layer 50 .

[0121] On the first aspect, the fifth via 65 enables the first protective layer 60 to form a first electrode protective layer 66 and a second electrode protective layer 67 which are spaced apart, wherein the first electrode protective layer 66 is provided with a first via 61, and the second electrode protective layer 67 is provided with a second via 62, and the first electrode protective layer 66 and the second electrode protective layer 67 are spaced apart on the second metal layer 50.

[0122] Secondly, the fifth via 65 forms a first electrode 51 and a second electrode 52 spaced apart from each other on the second metal layer 50. A first electrode protection layer 66 is disposed on the first electrode 51, and the first via 61 exposes at least a portion of the first electrode 51. A second electrode protection layer 67 is disposed on the second electrode 52, and the second via 62 exposes at least a portion of the second electrode 52. A conductive connection layer 71 connects the first electrode 51 and the bridging metal layer 21, and a pixel electrode 72 connects to the second electrode 52 via the second via 62.

[0123] In order to improve the stability of the thin film transistor structure, after completing step 107b, ozone may be introduced above the semiconductor layer 40. After the ozone treatment, an oxide protective layer will be formed above the semiconductor layer 40, thereby improving the stability of the thin film transistor structure.

[0124] Reference Figure 4 , the present application also proposes a method for manufacturing an array substrate, the manufacturing method comprising the following steps:

[0125] Step 201 : forming a first metal layer 20 on a substrate 10 .

[0126] Specifically, see Figure 5A The substrate 10 can be a glass substrate 10 or a polyimide (PI) substrate 10; the material of the first metal layer 20 can be a metal such as copper, gold, silver, platinum, palladium, iridium, tungsten, molybdenum, or an alloy material such as brass, cast iron, aluminum-tungsten alloy, or molybdenum-aluminum alloy.

[0127] After the first metal layer 20 is formed, step 202 is continued: the first metal layer 20 is patterned to form a bridge metal layer 21 and a gate 22 .

[0128] Specifically, see Figure 5B First, a photoresist 85 is coated on the first metal layer 20; then Figure 5C , using a first preset mask to expose and develop the photoresist 85, and remove the photoresist 85 corresponding to the bridge metal layer 21 and the gate 22; and then Figure 5D , the first metal layer 20 not covered by the photoresist 85 is etched away, and the patterning of the first metal layer 20 is completed to form a bridge metal layer 21 and a gate 22. The bridge metal layer 21 and the gate 22 are spaced apart and arranged on the substrate 10. Finally, as shown in FIG. Figure 5E As shown, the photoresist 85 covering the bridge metal layer 21 and the gate 22 is removed by development.

[0129] During the process of removing the first metal layer 20 not covered by the photoresist 85 by etching, when the material of the first metal layer 20 is Al (Aluminum), the first metal layer 20 is etched using wet etching, wherein the active ingredients of the etching solution include nitric acid, phosphoric acid, acetic acid, and deionized water. When the material of the first metal layer 20 is Cu (Copper), the first metal layer 20 is etched using wet etching, wherein the active ingredients of the etching solution include hydrogen peroxide, iminodiacetic acid, 5-aminotetrazole, hydrogen fluoride, and water.

[0130] After forming the spaced-apart bridging metal layer 21 and the gate 22 , step 203 is continued: a stacked gate insulating layer 30 , a semiconductor layer 40 , a second metal layer 50 and a first protective layer 60 are sequentially formed on the substrate 10 , wherein the gate insulating layer 30 covers the gate 22 and the bridging metal layer 21 .

[0131] See also Figure 5F A gate insulating layer 30 is formed on the bridging metal layer 21 and the gate 22, and the gate insulating layer 30 covers the gate 22 and the bridging metal layer 21; a semiconductor layer 40 is formed on the gate insulating layer 30; a second metal layer 50 is formed on the semiconductor layer 40; and a first protective layer 60 is formed on the second metal layer 50.

[0132] The gate insulating layer 30 is made of silicon nitride, silicon oxide, or silicon oxynitride, or it may be a stacked structure of silicon nitride / silicon oxide, silicon nitride / silicon oxide / aluminum oxide, or the like. The semiconductor layer 40 may be made of a crystalline or amorphous oxide semiconductor or other type of semiconductor with high stability, such as single crystal silicon, single crystal non-metallic materials, or metal oxides with low leakage current, such as IGZO, IGTO, IGO, IZO, AIZO, and ATZO. The semiconductor layer 40 is in ohmic contact with the first electrode 51 and the second electrode 52 to form a channel. The second metal layer 50 may be made of a metal such as copper, gold, silver, platinum, palladium, iridium, tungsten, or molybdenum, or an alloy such as brass, cast iron, aluminum-tungsten alloy, or molybdenum-aluminum alloy. During the formation of the semiconductor layer 40, ion implantation may be performed on the semiconductor layer 40 to form a heavily doped source or drain region. Specifically, heavily doped ions are implanted below the first electrode 51 and the second electrode 52 to form a heavily doped source or drain region.

[0133] After forming the stacked gate insulating layer 30, semiconductor layer 40, second metal layer 50 and first protective layer 60, continue to step 204: form a two-stage photoresist with different thicknesses on the first protective layer 60, and use the two-stage photoresist as a mask to pattern the first protective layer 60, the second metal layer 50, the semiconductor layer 40 and the gate insulating layer 30. After patterning, the photoresist remains on the first protective layer 60.

[0134] Specifically, see Figure 5G First, a photoresist is coated on the first protective layer 60 to form a photoresist film 80; then Figure 5H , use a second preset mask to expose and develop the photoresist film 80, remove the photoresist portion, and form a two-stage photoresist with different thicknesses; then Figure 5I As shown, the first protective layer 60 is patterned using a two-stage photoresist as a mask; then as shown in FIG. Figure 5J and Figure 5K As shown, the second metal layer 50 is patterned; then as shown Figure 5L As shown, the semiconductor layer 40 is patterned; then as shown Figure 5M As shown, the gate insulating layer 30 is patterned; after patterning, as shown Figure 5N As shown, after a portion of the photoresist is stripped off, a portion of the photoresist remains on the first protective layer 60 .

[0135] In the process of patterning the first protective layer 60 , dry etching is used to etch the first protective layer 60 , wherein the etchant may be one of sulfur hexafluoride gas, nitrogen trifluoride gas and chlorine gas.

[0136] like Figure 5IAs shown, during the process of patterning the first protective layer 60, a first via 61 and a second via 62 are formed in the first protective layer 60, the first via 61 exposes a portion of the second metal layer 50, and the second via 62 exposes a portion of the second metal layer 50, and the first via 61 and the second via are spaced apart.

[0137] During the patterning process of the first protective layer 60, a third via hole 63 and a fourth via hole 64 are formed in the first protective layer 60, the second metal layer 50, the semiconductor layer 40, and the gate insulating layer 30. The third via hole 63 exposes a portion of the gate insulating layer, and the fourth via hole 64 exposes a portion of the bridging metal layer 21. The distance from the bottom wall of the third via hole 63 to the substrate 10 is equal to the thickness of the first metal layer 20.

[0138] Due to the limited accuracy of the process, in actual products, the distance from the bottom wall of the third via 63 to the substrate 10 is basically equal to the thickness of the bridging metal layer 21, where basically equal means that the ratio of the distance from the bottom wall of the third via 63 to the substrate 10 to the thickness of the bridging metal layer 21 is in the range of 0.9 to 1.1.

[0139] After patterning the first protection layer 60 , the second metal layer 50 , the semiconductor layer 40 and the gate insulating layer 30 , step 205 is continued to form a transparent conductive layer 70 on the substrate 10 .

[0140] Specifically, see Figure 5O A transparent conductive layer 70 is plated on a surface of the array substrate 100 facing away from the substrate 10. The material of the transparent conductive layer 70 includes indium tin oxide (ITO), wherein the indium tin oxide can be transparent indium tin oxide, and the transparent conductive layer 70 can also be an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) stacked layer.

[0141] The portion of the transparent conductive layer 70 covering the first protective layer 60 is connected to the second metal layer 50 through the first via 61 and the second via 62, a portion of the transparent conductive layer 70 extends through the third via 63 and is disposed on the gate insulating layer 30, another portion of the transparent conductive layer 70 is connected to the bridging metal layer 21 through the fourth via 64, and the remaining portion of the transparent conductive layer 70 covers the remaining portion of the photoresist.

[0142] After the transparent conductive layer 70 is formed on the substrate 10 , step 206 is continued: the remaining portion of the photoresist is stripped off to form a conductive connection layer 71 and a pixel electrode 72 that are spaced apart from each other on the transparent conductive layer 70 .

[0143] Specifically, see Figure 5P, peel off the remaining photoresist and the portion of the transparent conductive layer covering the surface of the remaining photoresist to form a conductive connection layer 71 and a pixel electrode 72 that are spaced apart, wherein the conductive connection layer 71 is connected to the second metal layer 50 and the bridging metal layer 21 through the first via 61 and the fourth via 64, the first part of the pixel electrode 72 is covered on the first protective layer 60, the second part of the pixel electrode 72 is connected to the second metal layer 50 through the second via 62, and the third part of the pixel electrode 72 extends to the gate insulating layer 30 through the third via 63.

[0144] After stripping off the remaining portion of the photoresist, proceed to step 207 : etching the first protection layer 60 and the second metal layer 50 that are not covered by the conductive connection layer 71 and the pixel electrode 72 .

[0145] Specifically, see Figure 5Q and Figure 5R After the remaining photoresist is stripped, a portion of the first protective layer 60 is exposed to the transparent conductive layer 70. The portion of the first protective layer 60 exposed to the transparent conductive layer 70 is etched to form a fifth via hole 65 in the first protective layer 60 and the second metal layer 50.

[0146] On the first aspect, the fifth via 65 enables the first protective layer 60 to form a first electrode protective layer 66 and a second electrode protective layer 67 which are spaced apart, wherein the first electrode protective layer 66 is provided with a first via 61, and the second electrode protective layer 67 is provided with a second via 62, and the first electrode protective layer 66 and the second electrode protective layer 67 are spaced apart on the second metal layer 50.

[0147] Secondly, the fifth via 65 forms a first electrode 51 and a second electrode 52 spaced apart from each other on the second metal layer 50. A first electrode protection layer 66 is disposed on the first electrode 51, and the first via 61 exposes at least a portion of the first electrode 51. A second electrode protection layer 67 is disposed on the second electrode 52, and the second via 62 exposes at least a portion of the second electrode 52. A conductive connection layer 71 connects the first electrode 51 and the bridging metal layer 21, and a pixel electrode 72 connects to the second electrode 52 via the second via 62.

[0148] The fifth via 65 exposes a portion of the semiconductor layer 40. In one embodiment, the portion of the semiconductor layer 40 exposed by the fifth via 65 is oxidized to form an oxide film thereon, thereby improving the stability of the thin film transistor structure. The first electrode 51 serves as either the source or the drain of the thin film transistor, and the second electrode 52 serves as the other of the source or the drain of the thin film transistor.

[0149] In the process of manufacturing the array substrate 100, only two photomasks are used in step 202 and step 204. Compared with the technical solution of the existing array substrate 100 process that requires 5 or 4 photomasks, the manufacturing method of the array substrate 100 of the present application greatly reduces the number of photomasks required for the production of the array substrate 100, simplifies the process flow of the array substrate 100 production, improves the production efficiency of the array substrate 100, and reduces the production cost of the array substrate 100.

[0150] In one embodiment of the present application, the step of forming a two-stage photoresist with different thicknesses on the first protective layer 60, and using the two-stage photoresist as a mask to pattern the first protective layer 60, the second metal layer 50, the semiconductor layer 40, and the gate insulating layer 30, and removing the remaining portion of the photoresist on the first protective layer 60 after patterning, includes:

[0151] Step 204a: Forming the two-stage photoresist with different thicknesses on the first protective layer 60, wherein the two-stage photoresist includes a hollow portion 81, a second photoresist portion 83 and a third photoresist portion 84, the thickness of the second photoresist portion 83 is less than the thickness of the third photoresist portion 84, and the hollow portion 81 exposes a portion of the first protective layer 60.

[0152] Specifically, see Figure 5G and Figure 5H , photoresist is coated on the first protective layer 60 to form a photoresist film 80 .

[0153] The photoresist film 80 is exposed and developed using a second preset mask. The second preset mask is a two-stage mask, comprising a light-shielding portion, a semi-transmissive portion, and a fully transmissive portion. The fully transmissive portion transmits more light than the semi-transmissive portion, which in turn transmits more light than the light-shielding portion. The light transmittance of each portion of the photoresist film 80 is adjusted using the two-stage mask. The photoresist film 80 is then exposed and developed to form a hollow portion 81 and a second and third photoresist portions 83 and 84 of varying heights. The fully transmissive portion transmits the most light, corresponding to the hollow portion 81 formed in the photoresist film 80. The semi-transmissive portion transmits less light, corresponding to the thicker second photoresist portion 83 formed in the photoresist film 80. The light-shielding portion transmits the least light, corresponding to the thickest third photoresist portion 84 formed in the photoresist film 80.

[0154] After forming a two-stage photoresist with different thicknesses on the first protective layer 60 , proceed to step 204 b : etching the portion of the first protective layer 60 exposed to the hollow portion 81 to form a first via hole 61 , a second via hole 62 , a third via hole 63 , and a fourth via hole 64 in the first protective layer 60 ;

[0155] Specifically, see Figure 5H and Figure 5I The photoresist film 80 includes at least four hollow portions 81 spaced apart from each other. The portion of the first protective layer 60 exposed to the four hollow portions 81 spaced apart from each other is etched, and a first via hole 61, a second via hole 62, a third via hole 63 and a fourth via hole 64 spaced apart from each other are formed on the upper surface of the first protective layer 60. The first via hole 61, the second via hole 62, the third via hole 63 and the fourth via hole 64 respectively expose portions of the second metal layer 50. The fourth via hole 64 is located on a side of the first via hole 61 away from the second via hole 62, and the third via hole 63 is located on a side of the second via hole 62 away from the first via hole 61.

[0156] After forming the first via 61, the second via 62, the third via 63 and the fourth via 64 on the upper surface of the first protective layer 60, proceed to step 204c: forming a second protective layer 90 in the first via 61 and the second via 62, wherein the second protective layer 90 covers the second metal layer 50 exposed by the first via 61 and the second via 62.

[0157] Specifically, see Figure 5J A second protective layer 90 is formed in the first via hole 61 and the second via hole 62 by inkjet printing technology (IJP). The material of the second protective layer 90 is an organic material, which can be PFA (Polymer Film on Array). PFA becomes transparent after curing and can replace the first protective layer 60 to play an insulating role.

[0158] After forming the second protective layer 90 in the first via hole 61 and the second via hole 62, proceed to step 204d: using the second photoresist portion 83, the third photoresist portion 84 and the second protective layer 90 as a mask, pattern the second metal layer 50, the semiconductor layer 40 and the gate insulation layer 30 exposed through the third via hole 63 and the fourth via hole 64.

[0159] Specifically, see Figure 5K , etching the portion of the second metal layer 50 exposed to the third via 63 and the portion of the second metal layer 50 exposed to the fourth via 64 so that the third via 63 and the fourth via 64 extend to expose a portion of the semiconductor layer 40 respectively.

[0160] See also Figure 5L , etching the portion of the semiconductor layer 40 exposed to the third via hole 63 and the portion of the semiconductor layer 40 exposed to the fourth via hole 64 so that the third via hole 63 and the fourth via hole 64 extend to expose a portion of the gate insulating layer 30 respectively.

[0161] See also Figure 5M , the portion of the gate insulating layer 30 exposed to the fourth via 64 is etched so that the fourth via 64 extends to expose at least a portion of the bridging metal layer 21, and the portion of the gate insulating layer 30 exposed to the third via 63 is etched so that the third via 63 extends into the gate insulating layer 30. At this time, the distance from the bottom wall of the third via 63 to the substrate 10 is equal to the thickness of the bridging metal layer 21.

[0162] Due to the limited accuracy of the process, in actual products, the distance from the bottom wall of the third via 63 to the substrate 10 is basically equal to the thickness of the bridging metal layer 21, where basically equal means that the ratio of the distance from the bottom wall of the third via 63 to the substrate 10 to the thickness of the bridging metal layer 21 is in the range of 0.9 to 1.1.

[0163] After patterning the first protective layer 60 , the second metal layer 50 , the semiconductor layer 40 and the gate insulating layer 30 , step 204 e is continued: the second protective layer 90 and the second photoresist portion 83 are stripped off.

[0164] Specifically, see Figure 5N Step 204e1: Etch the second protective layer 90 to remove the second protective layer 90 covering the first via hole 61 and the second via hole 62. The second protective layer 90 can be removed by dry etching or by ashing.

[0165] Step 204e2: Ashing is performed on the second and third photoresist portions 83, 84. The portion of the second photoresist portion 83 that is thinner than the third photoresist portion 84 is removed, thereby exposing the portion of the first protective layer 60 previously covered by the second photoresist portion 83 to the photoresist film 80. During the ashing process, the thickness of the third photoresist portion 84 is also reduced, but the third photoresist portion 84 is not removed during the ashing process. After ashing, the third photoresist portion 84 still has a certain thickness. Furthermore, if any residue of the second protective layer 90 remains from step 204e1, ashing can be performed to remove the residue.

[0166] In an optional embodiment, step 204 e 1 may not be performed and only step 204 e 2 may be performed. In this case, the second protective layer 90 may be removed by ashing.

[0167] Alternatively, in an optional embodiment, step 204 e 2 may not be performed and only step 204 e 1 may be performed, that is, when the second protective layer 90 is removed by ashing, the second photoresist portion 83 is peeled off at the same time.

[0168] Regarding step 206: the remaining portion of the photoresist is stripped off, so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart.

[0169] Specifically, see Figure 5N Step 206a: Flocking the third light-resisting portion 84 to form a rough surface structure. The rough surface structure includes a plurality of nanopillars, and the height of the nanopillars is within the range of 100 nm to 200 nm. Specifically, the rough surface structure of the third light-resisting portion 84 is a velvet surface.

[0170] After the third photoresist portion 84 is flocked, step 206b is continued: a transparent conductive layer 70 is formed in the first via hole 61 , the second via hole 62 , the third via hole 63 , the fourth via hole 64 , the upper surface of the first protective layer 60 , and the outer surface of the third photoresist portion 84 .

[0171] Specifically, see Figure 5O The material of the transparent conductive layer 70 includes indium tin oxide (ITO), wherein the indium tin oxide can be transparent indium tin oxide, and the transparent conductive layer 70 can also be an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) stack. During the deposition of the transparent conductive layer 70 on the third photoresist portion 84, a rough structure composed of multiple nano-pillars is formed on the surface of the third photoresist portion 84. Part of the transparent conductive layer 70 adheres to the nano-pillars and cannot fall onto the surface of the third photoresist portion 84. As a result, most of the area on the outer surface of the third photoresist portion 84 is not covered by the transparent conductive layer 70, thereby facilitating the peeling of the third photoresist portion 84 and the transparent conductive layer 70 located on the surface of the third photoresist portion 84.

[0172] After the transparent conductive layer 70 is formed, step 206 c is continued to be performed: the third photoresist portion 84 is peeled off, so that the transparent conductive layer 70 forms a conductive connection layer 71 and a pixel electrode 72 that are spaced apart.

[0173] The third photoresist portion 84 is the remaining portion of the photoresist mentioned above. Figure 5P Because the rough structure on the surface of the third photoresist portion 84 is formed by a plurality of nanopillars, with numerous gaps between the nanopillars, the developer or etching solution can easily pass through the gaps and fully contact and act on the third photoresist portion 84, thereby completing the stripping of the third photoresist portion 84 where the transparent conductive layer 70 has been deposited. After the third photoresist portion 84 is stripped, the first protective layer 60 previously covered by the third photoresist portion 84 is exposed to the photoresist film 80, and the transparent conductive layer 70 forms a conductive connecting layer 71 and a pixel electrode 72 that are spaced apart.

[0174] In one embodiment of the present application, the step of forming the two-stage photoresist with different thicknesses on the first protective layer 60 includes:

[0175] Step 204a1: forming a photoresist film 80 on the first protective layer 60;

[0176] Specifically, please refer to Figure 5G , photoresist is coated on the first protective layer 60 to form a photoresist film 80 .

[0177] After forming the photoresist film 80 on the first protective layer 60, continue to execute step 204a2: the photoresist film 80 is etched to form the third photoresist portion 84 corresponding to the gate 22 and two second photoresist portions 83 connected on both sides of the third photoresist portion 84, and two spaced-apart hollow portions 81 are formed on each of the second photoresist portions 83, one of the hollow portions 81 is located above the bridging metal layer 21.

[0178] Specifically, see Figure 5H The photoresist film 80 is exposed and developed using a second preset mask. The second preset mask is a halftone mask. The halftone mask includes a light-shielding portion, a semi-transmissive portion, and a fully transmissive portion. The fully transmissive portion transmits more light than the semi-transmissive portion, which in turn transmits more light than the light-shielding portion. The halftone mask is used to adjust the light transmittance of various portions of the photoresist film 80. The photoresist film 80 is exposed and developed to form a hollow portion 81 and a second photoresist portion 83 and a third photoresist portion 84 of varying heights. The fully transmissive portion transmits the most light, corresponding to the hollow portion 81 formed in the photoresist film 80. The semi-transmissive portion transmits the most light, corresponding to the thinner second photoresist portion 83 formed in the photoresist film 80. The light-shielding portion transmits the least light, corresponding to the thickest third photoresist portion 84 formed in the photoresist film 80.

[0179] The step of etching the photoresist film 80 includes:

[0180] A half-tone mask is provided on the photoresist film 80. The half-tone mask includes a light-shielding portion, a semi-transmitting portion, and a fully-transmitting portion. The light-shielding portion is used to shield light of a preset wavelength band, the semi-transmitting portion is used to transmit part of the light, and the fully-transmitting portion is used to fully transmit the light. The light transmittance of the fully-transmitting portion is greater than that of the semi-transmitting portion.

[0181] The light transmittance of each portion of the halftone mask is different, and the exposure amount of each portion of the photoresist film 80 is adjusted through the halftone mask.

[0182] The photoresist film 80 is exposed and developed, and the hollow portion 81 of the first protective layer 60 is formed in the photoresist film 80 corresponding to the fully transparent portion, the second photoresist portion 83 is formed in the photoresist film 80 corresponding to the semi-transmissive portion, and the third photoresist portion 84 is formed in the photoresist film 80 corresponding to the shading portion.

[0183] Light of a preset wavelength band passes through the fully transmissive part, the semi-transmissive part and the light-shielding part of the half-tone mask to expose the photoresist film 80; the photoresist film 80 exposed by the half-tone mask is developed to form a hollow portion 81 and a second photoresist portion 83 and a third photoresist portion 84 of different thicknesses.

[0184] Reference Figure 2 The present application proposes an array substrate 100, comprising a substrate 10, a first metal layer 20, a gate insulating layer 30, a semiconductor layer 40, a first electrode 51 and a second electrode 52, a first protective layer 60, a conductive connection layer 71, and a pixel electrode 72. The first metal layer 20 is provided on the substrate 10, and comprises a bridge metal layer 21 and a gate 22 spaced apart; the gate insulating layer 30 is provided on the substrate 10 and covers the bridge metal layer 21 and the gate 22; the semiconductor layer 40 is provided on the gate insulating layer 30; the first electrode 51 and the second electrode 52 are spaced apart on the semiconductor layer 40; the first protective layer 60 is provided on the first electrode 51 and the second electrode 52, and the first protective layer 60 is provided with a first via 61 at a position corresponding to the first electrode 51, and the first protective layer 60 is provided with a first via 61 at a position corresponding to the second electrode 52. A second via 62 is provided at a corresponding position; a conductive connection layer 71 is provided on the first protective layer 60, the conductive connection layer 71 is connected to the bridging metal layer 21, and is connected to the first electrode 51 through the first via 61; a pixel electrode 72 is provided on the first protective layer 60, the pixel electrode 72 is connected to the second electrode 52 through the second via 62, a portion of the pixel electrode 72 is extended and provided on the gate insulating layer 30, and the distance from the portion of the pixel electrode 72 provided on the gate insulating layer 30 to the substrate 10 is equal to the thickness of the first metal layer 20.

[0185] The array substrate 100 in the present application can be manufactured through only 2 photomasks. Compared with the existing array substrate 100 process that requires 5 or 4 photomasks, the array substrate 100 in the present application greatly reduces the number of photomasks required to produce the array substrate 100, simplifies the process flow of the array substrate 100 production, improves the production efficiency of the array substrate 100, and reduces the production cost of the array substrate 100.

[0186] The distance between the portion of the pixel electrode 72 disposed on the gate insulating layer 30 and the substrate 10 is equal to the thickness of the first metal layer 20. "Equal" here means that the lengths of the two are substantially equal, because due to process errors during the production process, the absolute equality of the thicknesses of the two cannot be guaranteed. "Substantially equal" specifically means that the ratio of the distance between the portion of the pixel electrode 72 disposed on the gate insulating layer 30 and the substrate 10 to the thickness of the first metal layer 20 is within a range of 0.9 to 1.1.

[0187] The portion of the pixel electrode 72 disposed on the gate insulating layer 30 is located at the third via hole 63 ( Figure 2 (shown in FIG), the pixel electrode 72 is connected to the drain of the thin film transistor through the second via hole 62.

[0188] Reference Figure 2 In one embodiment of the present application, the first protective layer 60 includes a first electrode protective layer 66 and a second electrode protective layer 67, the projection of the first electrode protective layer 66 on the substrate 10 overlaps with the projection of the first electrode 51 on the substrate 10, and the projection of the second electrode protective layer 67 on the substrate 10 overlaps with the projection of the second electrode 52 on the substrate 10.

[0189] Specifically, a first electrode protection layer 66 is provided on the first electrode 51. The first electrode protection layer 66 is provided with a first via 61. The first via 61 exposes a portion of the first electrode 51. One end of the conductive connection layer 71 passes through the first via 61 and connects to the first electrode 51. A second electrode protection layer 67 is provided on the second electrode 52. The second electrode protection layer 67 is provided with a second via 62. The second via 62 exposes a portion of the second electrode 52. The pixel electrode 72 is connected to the second electrode 52 via the second via 62. A fifth via 65 is formed between the first electrode protection layer 66 and the first electrode 51 and the second electrode protection layer 67 and the second electrode 52. The fifth via 65 exposes a portion of the semiconductor layer 40.

[0190] In one embodiment of the present application, a third protection layer is disposed in the fifth via hole 65 , and the third protection layer covers the portion of the semiconductor layer 40 exposed by the fifth via hole 65 .

[0191] Because the fifth via 65 exposes a portion of the semiconductor layer 40, the stability of the thin-film transistor structure is reduced. To improve the stability of the thin-film transistor structure, ozone is introduced into the fifth via 65. This ozone treatment forms an oxide film on the exposed semiconductor layer 40. This oxide film forms the aforementioned third protective layer, thereby improving the stability of the thin-film transistor structure.

[0192] The present application proposes a display panel, which may be an LCD, an LED, an OLED, or an MLED. The display panel includes an array substrate 100 .

[0193] The above describes in detail the specific embodiments of the present application. The embodiments described herein are merely preferred embodiments of the present application. Persons skilled in the art will readily appreciate that numerous variations and modifications may be made without departing from the spirit of the present application. Such variations and modifications are intended to fall within the scope of protection defined by the claims of the present application.

Claims

1. A method for manufacturing an array substrate, characterized in that: The method for manufacturing the array substrate comprises the following steps: forming a first metal layer on the substrate; patterning the first metal layer to form a bridging metal layer and a gate; forming a stacked gate insulating layer, a semiconductor layer, a second metal layer and a first protective layer in sequence on the substrate, wherein the gate insulating layer covers the gate and the bridge metal layer; forming a three-stage photoresist with different thicknesses on the first protective layer, and using the three-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, wherein after patterning, a portion of the photoresist remains on the first protective layer; continuing to form a transparent conductive layer on the substrate; Stripping the remaining portion of the photoresist so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart; and The first protection layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode are etched.

2. The method for manufacturing an array substrate according to claim 1, wherein: The step of forming three-segment photoresist with different thicknesses on the first protective layer, and using the three-segment photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, and removing the remaining portion of the photoresist on the first protective layer after patterning comprises: forming a three-stage photoresist with different thicknesses on the first protective layer, the three-stage photoresist including a hollow portion, a first photoresist portion, a second photoresist portion, and a third photoresist portion, wherein the thickness of the first photoresist portion is smaller than that of the second photoresist portion, the thickness of the second photoresist portion is smaller than that of the third photoresist portion, and the hollow portion exposes a portion of the first protective layer; Etching a portion of the first protective layer exposed to the hollow portion to form a first via hole and a second via hole in the first protective layer; peeling off the first photoresist portion; forming a second protective layer in the first via hole and the second via hole, wherein the second protective layer covers the second metal layer exposed by the first via hole and the second via hole; Using the second photoresist portion, the third photoresist portion, and the second protective layer as a mask, patterning the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer exposed by the first photoresist portion; and The second protective layer and the second photoresist are peeled off.

3. The method for manufacturing an array substrate according to claim 2, wherein: The step of forming three-stage photoresist with different thicknesses on the first protective layer includes: forming a photoresist film on the first protective layer; The photoresist film is etched to form two first photoresist portions spaced apart from each other, the third photoresist portion located between the two first photoresist portions, two second photoresist portions connected between the third photoresist portion and the two first photoresist portions, and the hollow portions in the two second photoresist portions, wherein one of the first photoresist portions is located above the bridging metal layer, and the third photoresist portion corresponds to the gate.

4. The method for manufacturing an array substrate according to claim 1, wherein: The step of etching the first protective layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode comprises: Etching the first protective layer not covered by the conductive connection layer and the pixel electrode to form a first electrode protective layer and a second electrode protective layer that are spaced apart; and The second metal layer exposed through the first electrode protection layer and the second electrode protection layer is etched to form a first electrode and a second electrode that are spaced apart.

5. A method for manufacturing an array substrate, characterized in that: The method for manufacturing the array substrate comprises the following steps: forming a first metal layer on the substrate; patterning the first metal layer to form a bridging metal layer and a gate; forming a stacked gate insulating layer, a semiconductor layer, a second metal layer and a first protective layer in sequence on the substrate, wherein the gate insulating layer covers the gate and the bridge metal layer; forming a two-stage photoresist with different thicknesses on the first protective layer, and using the two-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, wherein after patterning, a portion of the photoresist remains on the first protective layer; continuing to form a transparent conductive layer on the substrate; Stripping the remaining portion of the photoresist so that the transparent conductive layer forms a conductive connection layer and pixel electrodes that are spaced apart; and The first protection layer and the second metal layer that are not covered by the conductive connection layer and the pixel electrode are etched.

6. The method for manufacturing an array substrate according to claim 5, wherein: The step of forming a two-stage photoresist with different thicknesses on the first protective layer, and using the two-stage photoresist as a mask to pattern the first protective layer, the second metal layer, the semiconductor layer, and the gate insulating layer, and removing the remaining portion of the photoresist on the first protective layer after patterning comprises: forming a two-stage photoresist with different thicknesses on the first protective layer, the two-stage photoresist comprising a hollow portion, a second photoresist portion, and a third photoresist portion, wherein the thickness of the second photoresist portion is smaller than that of the third photoresist portion, and the hollow portion exposes a portion of the first protective layer; Etching a portion of the first protective layer exposed to the hollow portion to form a first via hole, a second via hole, a third via hole, and a fourth via hole in the first protective layer; forming a second protective layer in the first via hole and the second via hole, wherein the second protective layer covers the second metal layer exposed by the first via hole and the second via hole; Using the second photoresist portion, the third photoresist portion, and the second protective layer as masks, patterning the second metal layer, the semiconductor layer, and the gate insulating layer exposed through the third via hole and the fourth via hole; and The second protective layer and the second photoresist are peeled off.

7. The method for manufacturing an array substrate according to claim 6, wherein: The step of forming the two-stage photoresist with different thicknesses on the first protective layer includes: forming a photoresist film on the first protective layer; The photoresist film is etched to form the third photoresist portion corresponding to the gate and two second photoresist portions connected on both sides of the third photoresist portion, and two spaced-apart hollow portions are formed on each of the second photoresist portions, one of the hollow portions is located above the bridging metal layer.

8. An array substrate, characterized in that: include: substrate; A first metal layer is provided on the substrate and includes a bridge metal layer and a gate that are spaced apart; a gate insulating layer, disposed on the substrate and covering the bridging metal layer and the gate; a semiconductor layer, the semiconductor layer being disposed on the gate insulating layer; a first electrode and a second electrode, wherein the first electrode and the second electrode are spaced apart and arranged on the semiconductor layer; a first protective layer disposed on the first electrode and the second electrode, wherein the first protective layer is provided with a first via hole at a position corresponding to the first electrode, and a second via hole at a position corresponding to the second electrode; a conductive connection layer, disposed on the first protective layer, the conductive connection layer being connected to the bridging metal layer and connected to the first electrode through the first via hole; as well as A pixel electrode is arranged on the first protective layer, the pixel electrode is connected to the second electrode through the second via hole, a portion of the pixel electrode is extended and arranged on the gate insulating layer, and the distance from the portion of the pixel electrode arranged on the gate insulating layer to the substrate is equal to the thickness of the first metal layer.

9. The array substrate according to claim 8, wherein: The first protective layer includes a first electrode protective layer and a second electrode protective layer. The projection of the first electrode protective layer on the substrate overlaps with the projection of the first electrode on the substrate. The projection of the second electrode protective layer on the substrate overlaps with the projection of the second electrode on the substrate.

10. A display panel, characterized in that: The invention comprises an array substrate as described in any one of claims 8 to 9.

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