A synchronous rectification Vcc power supply method and power supply circuit

Abstract

The application provides a synchronous rectification Vcc power supply method and a power supply circuit, and aims at solving the technical problem that the existing synchronous rectification Vcc power supply circuit using a diode to prevent current backflow will generate a diode voltage drop, and thus lead to a VCC port voltage drop and an under-voltage lock state. The synchronous rectification Vcc power supply method is as follows: a backflow prevention unit composed of a MOS tube P1 and a MOS tube P2 is arranged between a VD port and a VCC port, the conduction or turn-off of the power supply circuit is controlled according to the comparison results of a VCC port voltage Vcc and a starting voltage vth1 or an under-voltage protection threshold vth2, the comparison result of the VCC port voltage Vcc and a sampling voltage vdla, and the comparison result of the VCC port voltage Vcc and a VCC port reference voltage Vref; when the VD port voltage is less than the VCC port voltage, the gates of the MOS tube P1 and the MOS tube P2 are connected to Vcc to form an equivalent diode, so as to prevent the VCC port from being discharged reversely; and when the VD port voltage is greater than the VCC port voltage, the VCC port is charged through the equivalent diode, so as to avoid the appearance of a diode voltage drop.

Description

Technical Field

[0001] This invention relates to synchronous rectification circuits, and more particularly to a synchronous rectification Vcc power supply method and power supply circuit. Background Technology

[0002] In a synchronous rectification Vcc power supply circuit, the VD port is used to charge the chip's VCC port. The existing circuit topology of a synchronous rectification Vcc power supply circuit is shown below. Figure 1 As shown in the diagram. However, when the voltage at the VD port is lower than the voltage at the VCC port, reverse current usually occurs. Currently, a diode is typically added between the VD and VCC ports to prevent reverse current flow through the diode's reverse characteristics. The specific circuit is shown in the diagram. Figure 2 As shown. However, when the power supply circuit is forward-biased and charging at both the VD and VCC ports, a diode voltage drop will occur between the VD and VCC ports. Under light load conditions, when the output voltage Vout supplies power to the VCC port through the VD port, the VCC port voltage will decrease. An excessively low VCC port voltage will cause the synchronous rectifier chip to enter an undervoltage lockout state. The chip can only restart after the power supply voltage reaches the set value again. If the power supply voltage does not reach the required value, the chip will remain inactive, affecting the normal power supply of the circuit. Summary of the Invention

[0003] The purpose of this invention is to solve the technical problem that existing synchronous rectification Vcc power supply circuits that use diodes to prevent reverse current flow will generate diode voltage drop, which in turn leads to a decrease in the VCC port voltage and an undervoltage lockout state. The invention provides a new synchronous rectification Vcc power supply method and power supply circuit.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows:

[0005] A synchronous rectification Vcc power supply method includes the following steps:

[0006] 1. An anti-reverse current unit is set between the VD port and the VCC port of the chip; the anti-reverse current unit includes MOSFET P1 and MOSFET P2; the drain of MOSFET P1 is used to receive the charging voltage provided by the VD port, the drain of MOSFET P2 is connected to the voltage input terminal of the VCC port, the source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent current reverse flow; the PN junction between the source of MOSFET P1 and the substrate forms a physical diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a physical diode D2.

[0007] 2】Charging begins when the voltage at the VD port is greater than or equal to the voltage at the VCC port. The gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode. The VD port of the chip charges the VCC port through the equivalent diode.

[0008] 3) As the VCC port voltage Vcc increases, determine whether the VCC port voltage Vcc is greater than the startup voltage Vth1 or the undervoltage protection threshold Vth2, whether the VCC port voltage Vcc is less than the sampling voltage Vdla, and whether the VCC port voltage Vcc is less than the VCC port reference voltage Vref. If all three are true, control MOSFETs P1 and P2 to turn on and continue charging the VCC port. If any of the three are false, control the gates of MOSFETs P1 and P2 to connect to Vcc to form an equivalent diode to prevent reverse discharge of the VCC port.

[0009] Specifically, when the VCC port voltage Vcc is on the rising edge, it is compared with the startup voltage vth1; when the VCC port voltage Vcc is on the falling edge, it is compared with the undervoltage protection threshold vth2. The startup voltage vth1 is the startup voltage of the VCC port, the undervoltage protection threshold vth2 is the undervoltage protection threshold of the VCC port, and the sampling voltage vdla is the sampling voltage of the charging voltage.

[0010] Furthermore, the NMOS transistor N1 is a high-voltage NMOS transistor;

[0011] The PMOS transistors P1 and P2 are medium-voltage PMOS transistors.

[0012] The present invention also provides a synchronous rectification Vcc power supply circuit for implementing the above-mentioned synchronous rectification Vcc power supply method, including a charge pump unit, a logic control unit and an anti-reverse current unit; the special feature is that the logic control unit includes comparator cmp1, comparator cmp2, ​​comparator cmp3, NOT gate and NAND gate;

[0013] The positive input of comparator cmp1, the inverting input of comparator cmp2, ​​and the positive input of comparator cmp3 are all connected to the VCC port of the chip to receive the VCC port voltage Vcc, respectively. The inverting input of comparator cmp1 is used to receive the reference voltage vref of the VCC port, and its output is connected to the input of the NOT gate. The positive input of comparator cmp2 is used to receive the sampling voltage vdla of the VCC port. The inverting input of comparator cmp3 is used to receive the start-up voltage vth1 or the undervoltage protection threshold vth2 of the VCC port.

[0014] The three input terminals of the NAND gate are respectively connected to the output terminals of the NOT gate, comparator cmp2, ​​and comparator cmp3, and are used to control the output of the NAND gate according to the output of the NOT gate, comparator cmp2, ​​and comparator cmp3;

[0015] The anti-backflow unit includes MOSFET P1 and MOSFET P2;

[0016] The drain of MOSFET P1 is used to receive the charging voltage provided by the VD port of the chip. The drain of MOSFET P2 is connected to the voltage input terminal of the VCC port. The source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent reverse current flow. The PN junction between the source of MOSFET P1 and the substrate forms a physical diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a physical diode D2.

[0017] The gates of MOSFETs P1 and P2 are both connected to the output of a NAND gate. If the NAND gate output is low, MOSFETs P1 and P2 are turned on to continue charging the VCC port. If the NAND gate output is high, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode to prevent reverse current flow.

[0018] The charge pump unit is used to control the power supply from the VD port to the VCC port.

[0019] Furthermore, the comparator cmp3 is a hysteresis comparator.

[0020] Furthermore, the charge pump unit includes a charge pump and a MOS transistor N1; the two input terminals of the charge pump are used to receive the VD port voltage vd and the control signal vdL, respectively, and its output terminal is connected to the gate of the MOS transistor N1, which is used to control the conduction and turn-off of the MOS transistor N1 through the charge pump; the drain of the MOS transistor N1 is used to receive the VD port voltage vd, and its source is connected to the drain of the MOS transistor P1, which is used to supply power to the VCC port through the VD port.

[0021] Furthermore, the NMOS transistor N1 is a high-voltage NMOS transistor; the PMOS transistors P1 and PMOS transistor P2 are medium-voltage PMOS transistors.

[0022] Furthermore, the chip is a synchronous rectification chip.

[0023] The advantages of this invention compared to the prior art are as follows:

[0024] 1. The present invention provides a synchronous rectification Vcc power supply method, which sets up an anti-reverse current unit composed of MOSFETs P1 and P2 between the VD port and the VCC port of the chip. Based on the comparison results of the VCC port voltage Vcc with the start-up voltage vth1 or the undervoltage protection threshold vth2, the comparison results of the VCC port voltage Vcc with the sampling voltage vdla, and the comparison results of the VCC port voltage Vcc with the VCC port reference voltage Vref, the MOSFETs P1 and P2 are controlled to be turned on or off, thereby controlling whether to charge the VCC port. When the VD port voltage is less than the VCC port voltage, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode to prevent reverse discharge of the VCC port, that is, to prevent current reversal. When the VD port voltage is greater than the VCC port voltage, the VCC port is charged through the equivalent diode, avoiding the occurrence of diode voltage drop, thereby preventing the VCC port voltage from dropping and entering the undervoltage lockout state.

[0025] 2. The present invention provides a synchronous rectification Vcc power supply circuit with a simple circuit structure. It performs logical processing on the comparison result of the VCC port voltage and the reference voltage vref of the VCC port using a NOT gate. Simultaneously, it performs logical processing on the comparison result of the output of the NAND gate, the VCC port voltage with the sampling voltage vdla, and the VCC port voltage with the start-up voltage vth1 or the undervoltage protection threshold vth2. Then, it controls the conduction or cutoff of MOSFETs P1 and P2 based on the output of the NAND gate. That is, through the synchronous rectification Vcc power supply circuit of the present invention, it can ensure that when the VD port voltage is less than the VCC port voltage, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode, preventing reverse discharge of the VCC port. When the VD port voltage is greater than the VCC port voltage, the equivalent diode charges the VCC port. Attached Figure Description

[0026] Figure 1 The circuit topology diagram for the existing synchronous rectification Vcc power supply circuit;

[0027] Figure 2 The circuit topology diagram is shown for an existing synchronous rectification Vcc power supply circuit that uses diodes to prevent reverse current flow.

[0028] Figure 3 This is a circuit topology diagram of a synchronous rectification Vcc power supply circuit according to the present invention;

[0029] Figure 4 This is a waveform diagram of the operation of a synchronous rectification Vcc power supply circuit according to an embodiment of the present invention.

[0030] The specific figures are labeled as follows: 1-charge pump. Detailed Implementation

[0031] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] A synchronous rectification Vcc power supply method specifically includes the following steps:

[0033] 1. A reverse current prevention unit is set between the VD and VCC ports of the chip. In this embodiment, the chip is a synchronous rectification chip. Specifically, the reverse current prevention unit includes MOSFETs P1 and P2, both of which are medium-voltage PMOS transistors. The drain of MOSFET P1 is used to receive the charging voltage provided by the VD port, and the drain of MOSFET P2 is connected to the voltage input terminal of the VCC port. The source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent current reverse flow. The PN junction between the source of MOSFET P1 and the substrate forms a body diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a body diode D2. If only one MOSFET is set, its body diode is conducting. However, if two MOSFETs, namely MOSFETs P1 and P2, are set up in the above manner, MOSFETs P1 and P2 can be set back to back, and neither body diode D1 nor body diode D2 will conduct.

[0034] The voltage at the VD port is used to charge the VCC port through MOSFETs P1 and P2. When the voltage at the VD port is less than the voltage at the VCC port...

[0035] 2. Charging begins when the voltage at the VD port is greater than or equal to the voltage at the VCC port. At this time, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode, and the VD port of the chip charges the VCC port through the equivalent diode.

[0036] 3】The voltage Vcc at the VCC port continuously increases. At this time, the power supply circuit is controlled to turn on and off by comparing the results of three sets of values.

[0037] Specifically, it determines whether the VCC port voltage Vcc is greater than the startup voltage vth1 or the undervoltage protection threshold vth2, whether the VCC port voltage Vcc is less than the sampling voltage vdla, and whether the VCC port voltage Vcc is less than the VCC port reference voltage Vref. If all three are true, then MOSFETs P1 and P2 are turned on to continue charging the VCC port. If at least one of the three is false, then the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode to prevent reverse discharge at the VCC terminal, i.e., to prevent the phenomenon of reverse current.

[0038] Once the VCC port is fully charged, charging to the VCC port stops. Specifically, stopping charging to the VCC port is controlled by the control signal vdL on the charge pump.

[0039] Specifically, when the VCC port voltage Vcc is on the rising edge, it is compared with the startup voltage vth1; when the VCC port voltage Vcc is on the falling edge, it is compared with the undervoltage protection threshold vth2. The startup voltage vth1 is the startup voltage of the VCC port, the undervoltage protection threshold vth2 is the undervoltage protection threshold of the VCC port, and the sampling voltage vdla is the sampling voltage of the charging voltage.

[0040] To implement the aforementioned synchronous rectification Vcc power supply method, this invention also provides a synchronous rectification Vcc power supply circuit, such as... Figure 3 As shown, it includes a logic control unit, an anti-backflow unit, and a charge pump unit.

[0041] The logic control unit includes comparator cmp1, comparator cmp2, ​​comparator cmp3, NOT gate, and NAND gate.

[0042] The positive input of comparator cmp1 is connected to the VCC port of the chip, and its negative input is used to receive the reference voltage vref of the VCC port for comparison. The output of comparator cmp1 is connected to the input of the NOT gate for logical NOT operation. That is, when the VCC port voltage is greater than or equal to the reference voltage vref of the VCC port, the output vdl of comparator cmp1 is high and the output of the NOT gate is low. When the VCC port voltage is less than the reference voltage vref of the VCC port, the output vdl of comparator cmp1 is low and the output of the NOT gate is high.

[0043] The positive input of comparator cmp2 is used to receive the sampled voltage vdla from the VCC port, and its inverting input is connected to the VCC port of the chip. When the voltage at the VCC port is less than the sampled voltage vdla, the output of comparator cmp2 is high, and when the voltage at the VCC port is less than the sampled voltage vdla, the output of comparator cmp2 is low.

[0044] Comparator cmp3 is a hysteresis comparator. Its positive input is connected to the chip's VCC port, and its inverting input receives the VCC port's startup voltage Vth1 or undervoltage protection threshold Vth2. When the VCC port voltage is greater than or equal to the startup voltage Vth1 or the undervoltage protection threshold Vth2, the output uvloH of comparator cmp3 is high; when the VCC port voltage is less than the startup voltage Vth1 or the undervoltage protection threshold Vth2, the output uvloH of comparator cmp3 is low. Specifically, when the VCC port voltage Vcc is on its rising edge, it compares the VCC port voltage Vcc with the startup voltage Vth1; when the VCC port voltage Vcc is on its falling edge, it compares the VCC port voltage Vcc with the undervoltage protection threshold Vth2.

[0045] The three inputs of the NAND gate are connected to the outputs of the NOT gate, comparator cmp2, ​​and comparator cmp3, respectively, to control the output of the NAND gate based on the outputs of the NOT gate, comparator cmp2, ​​and comparator cmp3. Specifically, when the outputs of the NOT gate, comparator cmp2, ​​and comparator cmp3 are all high, the output Vcccharge of the NAND gate is low; when at least one of the outputs of the NOT gate, comparator cmp2, ​​and comparator cmp3 is low, the output Vcccharge of the NAND gate is high.

[0046] The anti-reverse current unit includes MOSFETs P1 and P2. The drain of MOSFET P1 is used to receive the charging voltage provided by the VD port, and the drain of MOSFET P2 is connected to the voltage input terminal of the VCC port. The source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent current reverse flow. The PN junction between the source of MOSFET P1 and the substrate forms a body diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a body diode D2. Neither body diodes D1 nor D2 is conducting.

[0047] The gates of MOSFETs P1 and P2 are both connected to the output of a NAND gate, which controls the on / off state of MOSFETs P1 and P2 based on the output of the NAND gate. Specifically, if the NAND gate output is low, MOSFETs P1 and P2 are turned on; if the NAND gate output is high, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode, preventing reverse discharge at the VCC terminal.

[0048] The charge pump unit includes a charge pump 1 and a MOS transistor N1, and the MOS transistor N1 is a high-voltage NMOS transistor. The two input terminals of the charge pump 1 are respectively used to receive the VD port voltage vd and the control signal vdL, and its output terminal is connected to the gate of the MOS transistor N1 for boosting the VD port voltage. In this embodiment, the boosting multiple is set to 2 times. The drain of the MOS transistor N1 is used to receive the VD port voltage vd, and its source is connected to the drain of the MOS transistor P1 for driving the MOS transistor P1 and the MOS transistor P2 to work through the boosted voltage. Among them, the control signal vdL is at a high level when Vcc>vref and at a low level when Vcc<vref.

[0049] As Figure 4 shown, it is a voltage waveform diagram of the VD port voltage vd, the output uvloH of the comparator cmp3, the VCC port voltage Vcc, the sampling voltage Vd1a, and the output Vcccharge of the NAND gate in the synchronous rectification Vcc power supply circuit of the present invention. In the figure, the horizontal axis represents time and the vertical axis represents voltage. When the chip starts to work, the charge pump 1 is powered by the VD port voltage vd. At this time, the MOS transistor N1 is turned on, and the charge pump 1 pulls up the gate potential of the MOS transistor N1. The gates of the MOS transistor P1 and the MOS transistor P2 are connected to Vcc to form an equivalent diode, and the VD port of the chip charges the VCC port through the equivalent diode. The VCC port voltage Vcc continuously increases. When the VCC port voltage Vcc is greater than the startup voltage vth1 or the undervoltage protection threshold vth2, that is, at the moment t1 in the figure, the output uvloH of the comparator comp2 is high. If at this time the VCC port voltage is less than the sampling voltage Vd1a and the VCC port voltage is less than the reference voltage vref, at this time, the output Vccchage of the NAND gate is low, and the MOS transistor P1 and the MOS transistor P2 are turned on to continue charging the VCC port; when the VCC port voltage is greater than the reference voltage vref or the VCC port voltage is greater than the sampling voltage Vd1a, the output Vccchage of the NAND gate is high. At this time, the control of the charge pump 1 and the MOS transistor N1 are both turned off, and the gates of the MOS transistor P1 and the MOS transistor P2 are connected to Vcc to form an equivalent diode to prevent the VCC port from discharging reversely.

[0050] As described above, it is only used to illustrate the technical solution of the present invention and is not a limitation thereof. For those of ordinary skill in the art, the specific technical solution recorded in the above embodiment can be modified, or some technical features can be equivalently replaced. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution protected by the present invention.

Claims

1. A synchronous rectification Vcc power supply method, characterized in that, Includes the following steps:

1. An anti-reverse current unit is set between the VD port and the VCC port of the chip; the anti-reverse current unit includes MOSFET P1 and MOSFET P2; the drain of MOSFET P1 is used to receive the charging voltage provided by the VD port, the drain of MOSFET P2 is connected to the voltage input terminal of the VCC port, the source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent current reverse flow; the PN junction between the source of MOSFET P1 and the substrate forms a physical diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a physical diode D2. 2】Charging begins when the voltage at the VD port is greater than or equal to the voltage at the VCC port. The gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode. The VD port of the chip charges the VCC port through the equivalent diode. 3) As the VCC port voltage Vcc increases, determine whether the VCC port voltage Vcc is greater than the startup voltage Vth1 or the undervoltage protection threshold Vth2, whether the VCC port voltage Vcc is less than the sampling voltage Vdla, and whether the VCC port voltage Vcc is less than the VCC port reference voltage Vref. If all three are true, control MOSFETs P1 and P2 to turn on and continue charging the VCC port. If any of the three are false, control the gates of MOSFETs P1 and P2 to connect to Vcc to form an equivalent diode to prevent reverse discharge of the VCC port. Specifically, when the VCC port voltage Vcc is on the rising edge, it is compared with the startup voltage vth1; when the VCC port voltage Vcc is on the falling edge, it is compared with the undervoltage protection threshold vth2. The startup voltage vth1 is the startup voltage of the VCC port, the undervoltage protection threshold vth2 is the undervoltage protection threshold of the VCC port, and the sampling voltage vdla is the sampling voltage of the charging voltage.

2. The synchronous rectification Vcc power supply method according to claim 1, characterized in that: The MOS transistors P1 and P2 are medium-voltage PMOS transistors.

3. A synchronous rectification Vcc power supply circuit, used to implement the synchronous rectification Vcc power supply method as described in claim 1 or 2, comprising a charge pump unit, a logic control unit, and an anti-reverse current unit; characterized in that: The logic control unit includes comparator cmp1, comparator cmp2, ​​comparator cmp3, NOT gate, and NAND gate; The positive input of comparator cmp1, the inverting input of comparator cmp2, ​​and the positive input of comparator cmp3 are all connected to the VCC port of the chip to receive the VCC port voltage Vcc, respectively. The inverting input of comparator cmp1 is used to receive the reference voltage vref of the VCC port, and its output is connected to the input of the NOT gate. The positive input of comparator cmp2 is used to receive the sampling voltage vdla of the VCC port. The inverting input of comparator cmp3 is used to receive the start-up voltage vth1 or the undervoltage protection threshold vth2 of the VCC port. The three input terminals of the NAND gate are respectively connected to the output terminals of the NOT gate, comparator cmp2, ​​and comparator cmp3, and are used to control the output of the NAND gate according to the output of the NOT gate, comparator cmp2, ​​and comparator cmp3; The anti-backflow unit includes MOSFET P1 and MOSFET P2; The drain of MOSFET P1 is used to receive the charging voltage provided by the VD port of the chip. The drain of MOSFET P2 is connected to the voltage input terminal of the VCC port. The source of MOSFET P1 is connected to the source of MOSFET P2, and its gate is connected to the gate of MOSFET P2 to prevent reverse current flow. The PN junction between the source of MOSFET P1 and the substrate forms a physical diode D1, and the PN junction between the source of MOSFET P2 and the substrate forms a physical diode D2. The gates of MOSFETs P1 and P2 are both connected to the output of a NAND gate. If the NAND gate output is low, MOSFETs P1 and P2 are turned on to continue charging the VCC port. If the NAND gate output is high, the gates of MOSFETs P1 and P2 are connected to Vcc to form an equivalent diode to prevent reverse current flow. The charge pump unit is used to control the power supply from the VD port to the VCC port.

4. The synchronous rectification Vcc power supply circuit according to claim 3, characterized in that: The comparator cmp3 is a hysteresis comparator.

5. The synchronous rectification Vcc power supply circuit according to claim 4, characterized in that: The charge pump unit includes a charge pump (1) and a MOS transistor N1; The two input terminals of the charge pump (1) are used to receive the VD port voltage vd and the control signal vdL, respectively. Its output terminal is connected to the gate of the MOS transistor N1 and is used to control the conduction and turn-off of the MOS transistor N1 through the charge pump (1). The drain of the MOS transistor N1 is used to receive the voltage vd at the VD port, and its source is connected to the drain of the MOS transistor P1, so as to supply power to the VCC port through the VD port.

6. The synchronous rectification Vcc power supply circuit according to claim 5, characterized in that: The MOS transistor N1 is a high-voltage NMOS transistor; The MOS transistors P1 and P2 are medium-voltage PMOS transistors.

7. The synchronous rectification Vcc power supply circuit according to claim 6, characterized in that: The chip is a synchronous rectification chip.

Images