Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is in the third dielectric layer and across the capacitor structure. The channel structure is in the third dielectric layer and around the word line and a portion of the third dielectric layer. The gate dielectric has a first portion between sidewalls of the word line and the channel structure and a second portion separate from the first portion and between an inner wall of the third dielectric layer and the channel structure. The semiconductor structure with the word line and the channel structure can overcome problems with critical dimension variation and overlay shift in conventional designs of a word line around a channel, thereby improving the ability to control the gate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for manufacturing a semiconductor structure. Background Technology

[0002] Traditional dynamic random access memory (DRAM) cells consist of transistors and capacitors coupled to the transistors. As DRAM density increases, the channel length of traditional planar transistors decreases, leading to short-channel effects, including drain-induced barrier losses and other similar effects. Reducing device size decreases the distance between word lines and bit lines, ultimately resulting in higher parasitic capacitance between word lines and bit lines. Buried word line DRAM structures are one way to address this problem, where the word lines are buried in the substrate. However, as the structure shrinks further, the etch depth of shallow trench isolation (STI) varies drastically, eventually causing word lines to interfere with each other after the buried word lines are formed.

[0003] Therefore, in vertical transistor memories with a gate-all-around (GAA) design, the gate metal of the transistor (i.e., the word line) needs to completely surround the channel region of the transistor. However, if the predetermined space between the gate metal and the channel region is too small (i.e., 5 nanometers), critical dimension (CD) variations and overlap (OVL) displacements during the process may expose a portion of the channel region for the word line, resulting in a decrease in gate control capability. Summary of the Invention

[0004] The technical state disclosed herein is a semiconductor structure.

[0005] According to some embodiments disclosed herein, a semiconductor structure includes a first dielectric layer, a second dielectric layer, a capacitor structure, a third dielectric layer, a word line, a channel structure, and a gate dielectric. The second dielectric layer is located on the first dielectric layer. The capacitor structure is located between the first and second dielectric layers. The third dielectric layer is located on the second dielectric layer. The word line is located in the third dielectric layer and crosses the capacitor structure, wherein a portion of the third dielectric layer is located between the word line and the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and this portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is located between the sidewall of the word line and the channel structure, and the second portion is located between the inner wall of the third dielectric layer and the channel structure.

[0006] In some implementations, the width of the bottom of the character line is greater than the width of the top of the character line.

[0007] In some implementations, the top of the aforementioned character line contacts the channel structure.

[0008] In some embodiments, the first portion of the gate dielectric extends to the bottom of that portion of the third dielectric layer.

[0009] In some embodiments, the semiconductor structure further includes a source region between the top of the capacitor structure and the bottom of the portion of the third dielectric layer of the source region.

[0010] In some embodiments, the bottom of the first portion of the gate dielectric is in contact with the source region.

[0011] In some embodiments, the bottom of the second portion of the gate dielectric is in contact with the source region.

[0012] In some implementations, the bottom of the channel structure is in contact with the source region.

[0013] In some embodiments, the second portion of the gate dielectric surrounds the channel structure.

[0014] In some embodiments, the semiconductor structure described above also includes a drain region located on top of the channel structure.

[0015] In some embodiments, the semiconductor structure described above also includes bit lines that are electrically contacted with the drain region.

[0016] In some embodiments, the semiconductor structure further includes a connection pad between the drain region and the bit line.

[0017] In some embodiments, the semiconductor structure further includes a fourth dielectric layer and a fifth dielectric layer. The fourth dielectric layer is located on a bit line. The fifth dielectric layer is located on the fourth dielectric layer, wherein the material of the fifth dielectric layer is different from that of the fourth dielectric layer.

[0018] In some embodiments, the capacitor structure includes a semiconductor material, a first electrode, a high-dielectric-constant dielectric, and a second electrode. The first electrode surrounds the semiconductor material. The high-dielectric-constant dielectric surrounds the first electrode. The second electrode surrounds the bottom of the high-dielectric-constant dielectric.

[0019] Another technical aspect disclosed herein is a method for manufacturing a semiconductor structure.

[0020] According to some embodiments disclosed herein, a method for manufacturing a semiconductor structure includes forming a capacitor structure in a first dielectric layer and a second dielectric layer located on the first dielectric layer; forming a third dielectric layer and a word line on the second dielectric layer, wherein the word line is located in the third dielectric layer and crosses the capacitor structure, and a portion of the third dielectric layer is located between the word line and the capacitor structure; forming a via in the third dielectric layer to expose the word line; forming a first portion and a second portion of a gate dielectric on the sidewall of the word line and the inner wall of the third dielectric layer, respectively; and forming a channel structure in the via of the third dielectric layer, wherein the channel structure surrounds the word line and the portion of the third dielectric layer.

[0021] In some embodiments, the formation of the third dielectric layer and the word line on the second dielectric layer is such that the width of the bottom of the word line is greater than the width of the top of the word line.

[0022] In some embodiments, the first and second portions of the gate dielectric are formed such that the first portion of the gate dielectric extends to the sidewall of that portion of the third dielectric layer.

[0023] In some embodiments, forming the channel via in the third dielectric layer includes using an etchant with a high etch selectivity between the third dielectric layer and the character line.

[0024] In some embodiments, the formation of the third dielectric layer and the word line on the second dielectric layer results in the width of the word line being in the range of 10 nanometers to 12 nanometers.

[0025] In some embodiments, the formation of the channel hole in the third dielectric layer results in a channel hole radius in the range of 40 nanometers to 44 nanometers.

[0026] In the embodiments disclosed above, since a portion of the third dielectric layer is located between the word line and the capacitor structure, and the channel structure surrounding this portion of the word line and the third dielectric layer can serve as a transistor channel, gate control of the semiconductor structure can be achieved through the outer sidewalls of the word line. Due to this configuration, the semiconductor structure having the word line and channel structure overcomes the problems of critical dimension (CD) variation and overlap (OVL) displacement in conventional designs of word lines surrounding the channel, thereby improving the ability to control the gate. Attached Figure Description

[0027] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0028] Figure 1 Cross-sectional views of semiconductor structures according to some embodiments of this disclosure are shown.

[0029] Figure 2 Cross-sectional views of semiconductor structures according to some embodiments of this disclosure are shown.

[0030] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure is shown.

[0031] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 and Figure 14 A top view illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure at an intermediate stage.

[0032] Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 Draw a cross-sectional view of the semiconductor structure manufacturing process at an intermediate stage, where... Figure 5 for Figure 4 A cross-sectional view along line 5-5, and Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional position and Figure 5 The cross-sectional positions are the same. Detailed Implementation

[0033] The following description of embodiments provides many different implementations, or examples, of various features for achieving the provided objectives. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, specify the relationship between the various embodiments and / or configurations discussed.

[0034] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0035] Figure 1 A cross-sectional view of a semiconductor structure 100 according to some embodiments of this disclosure is shown. Figure 1As shown, the semiconductor structure 100 includes a first dielectric layer 110, a second dielectric layer 120, a capacitor structure 130, a third dielectric layer 140, a word line 150, a channel structure 160, and a gate dielectric 170. The second dielectric layer 120 is located on the first dielectric layer 110. In some embodiments, the first dielectric layer 110 and the second dielectric layer 120 comprise different materials. For example, the first dielectric layer 110 may be made of oxide, and the second dielectric layer 120 may be made of nitride. The capacitor structure 130 is located within the first dielectric layer 110 and the second dielectric layer 120. The third dielectric layer 140 is located on the second dielectric layer 120, and the third dielectric layer 140 may be made of oxide. The third dielectric layer 140 may include multiple oxide layers located below, around, and above the word line 150, respectively. The character line 150 is located in the third dielectric layer 140, wherein a portion 142 of the third dielectric layer 140 lies between the character line 150 and the capacitor structure 130. In some embodiments, the character line 150 may be made of tungsten, but this is not intended to limit this disclosure. The character line 150 may be aligned with the capacitor structure 130.

[0036] Channel structure 160 is located within third dielectric layer 140 and surrounds word line 150 and a portion 142 of third dielectric layer 140. The material of channel structure 160 may be indium gallium zinc oxide (IGZO), but this is not intended to limit this disclosure. Furthermore, gate dielectric 170 has a first portion 172 and a second portion 174 separate from the first portion 172. The first portion 172 of gate dielectric 170 is located between the sidewall 152 of word line 150 and channel structure 160, and the second portion 174 of gate dielectric 170 is located between the inner wall 144 of third dielectric layer 140 and channel structure 160.

[0037] In some embodiments, the semiconductor structure 100 may be referred to as dynamic random access memory (DRAM) and includes vertical transistor memory and DRAM capacitors (i.e., capacitor structure 130). In addition, word lines 150 may serve as gate metal for gate control, while channel structure 160 may serve as transistor channels.

[0038] Specifically, because a portion 142 of the third dielectric layer 140 is located between the word line 150 and the capacitor structure 130, the channel structure 160 surrounds the word line 150, and the portion 142 of the third dielectric layer 140 can serve as a transistor channel, gate control of the semiconductor structure 100 can be achieved through the outer sidewall 152 of the word line 150. Due to this configuration, the semiconductor structure 100 with the word line 150 and the channel structure 160 can overcome the problems of critical dimension (CD) variation and overlap (OVL) displacement in conventional designs of word lines surrounding the channel, thereby improving the ability to control the gate.

[0039] In some embodiments, the width W1 of the bottom of the word line 150 is greater than the width W2 of the top of the word line 150. The width W2 of the word line 150 is in the range of 10 nanometers to 12 nanometers. The top of the word line 150 contacts the channel structure 160. Furthermore, a first portion 172 of the gate dielectric 170 extends to the sidewall 143 of a portion 142 of the third dielectric layer 140. A second portion 174 of the gate dielectric 170 surrounds the channel structure 160.

[0040] In addition, the capacitor structure 130 includes a semiconductor material 132, a first electrode 134, a high-dielectric-constant dielectric 136, and a second electrode 138. The first electrode 134 surrounds the semiconductor material 132. The high-dielectric-constant dielectric 136 surrounds the first electrode 134. The second electrode 138 surrounds the bottom of the high-dielectric-constant dielectric 136. The high-dielectric-constant dielectric 136 is located between the first electrode 134 and the second electrode 138 to form a metal-insulator-metal (MIM) structure. The first electrode 134 and the second electrode 138 can serve as the upper electrode and the lower electrode, respectively. The semiconductor material 132 can be polycrystalline silicon, but this is not intended to limit this disclosure.

[0041] In some embodiments, the semiconductor structure 100 further includes a source region 182 and a drain region 184. The source region 182 is located between the top of the capacitor structure 130 and the bottom of a portion 142 of the third dielectric layer 140. The drain region 184 is located on the top of the channel structure 160. In some embodiments, the bottom of the first portion 172 of the gate dielectric 170 and the bottom of the second portion 174 of the gate dielectric 170 may contact the source region 182. Furthermore, the bottom of the channel structure 160 may contact the source region 182.

[0042] The semiconductor structure 100 also includes a bit line 192, a barrier layer 193, a fourth dielectric layer 194, and a fifth dielectric layer 195. The bit line 192 is electrically contacted with the drain region 184. The fourth dielectric layer 194 is located on the bit line 192. The fifth dielectric layer 195 is located on the fourth dielectric layer 194, wherein the material of the fifth dielectric layer 195 is different from the material of the fourth dielectric layer 194. For example, the material of the fourth dielectric layer 194 may be an oxide, while the material of the fifth dielectric layer 195 may be a nitride.

[0043] It should be understood that the component connections, materials, and functions already described will not be repeated, but will be stated in the preceding text. Other forms of semiconductor structures will be described in the following description.

[0044] Figure 2A cross-sectional view of a semiconductor structure 100a according to some embodiments of this disclosure is shown. The semiconductor structure 100a includes a first dielectric layer 110, a second dielectric layer 120, a capacitor structure 130, a third dielectric layer 140, a word line 150, a channel structure 160, and a gate dielectric 170. This embodiment and... Figure 1 The difference in the implementation is that the semiconductor structure 100a also includes a connection pad 196 located between the drain region 184 and the bit line 192. In this configuration, the bit line 192 is electrically connected to the drain region 184 via the connection pad 196.

[0045] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure is provided. The method for manufacturing a semiconductor structure includes the following steps: In step S1, a capacitor structure is formed in a first dielectric layer and a second dielectric layer located on the first dielectric layer. Then, in step S2, a third dielectric layer and a word line are formed on the second dielectric layer, wherein the word line is located in the third dielectric layer and crosses the capacitor structure, and a portion of the third dielectric layer is located between the word line and the capacitor structure. Next, in step S3, a via is formed in the third dielectric layer to expose the word line. Then, in step S4, a first portion and a second portion of the gate dielectric are formed on the sidewall of the word line and the inner wall of the third dielectric, respectively. Next, in step S5, a channel structure is formed in the via of the third dielectric layer, wherein the channel structure surrounds the word line and this portion of the third dielectric layer. The method for manufacturing a semiconductor structure is not limited to the above-described steps S1 to S5. In some embodiments, the method for manufacturing a semiconductor structure may further include other steps in any two of the above steps. Furthermore, each of steps S1 to S5 may contain multiple detailed steps. In the following description, at least steps S1 to S5 described above will be explained.

[0046] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 and Figure 14 The illustration shows a semiconductor structure 100a according to some embodiments of this disclosure (see reference). Figure 2 A top view of the manufacturing process at an intermediate stage. Figure 5 , Figure 7 , Figure 9 , Figure 11 and Figure 13 A cross-sectional view of the manufacturing process of semiconductor structure 100a at an intermediate stage is drawn, in which... Figure 5 for Figure 4 A cross-sectional view along line 5-5, and Figure 7 , Figure 9 , Figure 11 and Figure 13 The cross-sectional position and Figure 5 The cross-sectional positions are the same.

[0047] See also Figure 4 and Figure 5 A capacitor structure 130 is formed in a first dielectric layer 110 and a second dielectric layer 120 located on the first dielectric layer 110. The formation of the capacitor structure 130 may include the following steps: An opening may be formed in the stacked first dielectric layer 110 and second dielectric layer 120, followed by the sequential formation of a second electrode 138 and a high-dielectric-constant dielectric 136 on the sidewalls of the opening. Next, a first electrode 134 is formed on the high-dielectric-constant dielectric 136 such that the lower portion of the high-dielectric-constant dielectric 136 is located between the first electrode 134 and the second electrode 138. Then, a semiconductor material 132 fills the opening, and a source region 182 is formed on top of the semiconductor material 132 using epitaxial growth, thus obtaining the capacitor structure 130.

[0048] See also Figure 6 and Figure 7 After forming the capacitor structure 130, a third dielectric layer 140 and a word line 150 are formed on the second dielectric layer 120. The word line 150 is located in the third dielectric layer 140 and spans the capacitor structure 130, while a portion 142 of the third dielectric layer 140 is located between the word line 150 and the capacitor structure 130. The formation of the third dielectric layer 140 and the word line 150 may include forming a first layer of the third dielectric layer 140 covering the second dielectric layer 120 and the source region 182, forming a trench in the first layer of the third dielectric layer 140, forming the word line 150 in the trench, and forming a second layer of the third dielectric layer 140 covering the word line 150 and the first layer of the third dielectric layer 140. Compared with conventional designs, the critical dimension (CD) for forming the word line 150 is smaller. In some implementations, a third dielectric layer 140 and a word line 150 are formed on a second dielectric layer 120 such that the word line 150 has a width W2 in the range of 10 nanometers to 12 nanometers, and the width W1 at the bottom of the word line 150 is greater than the width W2 at the top of the word line 150.

[0049] See also Figure 8 and Figure 9 After forming the character line 150 and the third dielectric layer 140, a via O is formed in the third dielectric layer 140 to expose the character line 150. Compared to conventional designs, forming the via O and the subsequent channel structure 160 (see...) Figure 11The critical dimension (CD) of the via is relatively large. In some embodiments, the via O has a diameter D in the range of 40 nanometers to 44 nanometers, for example 42 nanometers. In addition, the via O is formed in the third dielectric layer 140 by including an etchant with a high etch selectivity between the third dielectric layer 140 and the word line 150, thereby preventing damage to the word line 150 (i.e., the gate metal).

[0050] See also Figure 10 and Figure 11 Subsequently, a first portion 172 and a second portion 174 of the gate dielectric 170 are formed on the sidewall 152 of the word line 150 and the inner wall 144 of the third dielectric layer 140, respectively. The gate dielectric 170 can be formed by deposition and patterning. Furthermore, the formation of the first portion 172 and the second portion 174 of the gate dielectric 170 is such that the first portion 172 of the gate dielectric 170 extends to the sidewall 143 of a portion 142 of the third dielectric layer 140.

[0051] Next, a channel structure 160 is formed in a channel hole O of the third dielectric layer 140, such that the channel structure 160 surrounds the word line 150 and a portion 142 of the third dielectric layer 140. The diameter of the channel structure 160 may be similar to the diameter D of the channel hole O, for example, between 40 nanometers and 44 nanometers (for example, 42 nanometers). In addition, a first portion 172 of the gate dielectric 170 is located between the word line 150 and the channel structure 160, and a second portion 174 of the gate dielectric 170 is located between the channel structure 160 and the third dielectric layer 140.

[0052] See also Figure 12 and Figure 13 After the channel structure 160 is filled with channel hole O, the drain region 184 can be formed on top of the channel structure 160 by epitaxial growth. Subsequently, the third layer of the third dielectric layer 140 and the connecting pad 196 are optionally formed on the second layer of the third dielectric layer 140 and the drain region 184. The connecting pad 196 is aligned with and electrically connected to the drain region 184.

[0053] See also Figure 14 and Figure 2 After the third dielectric layer 140 and the connecting pad 196 are formed, the bit line 192, the barrier layer 193, the fourth dielectric layer 194, and the fifth dielectric layer 195 are sequentially formed on the third dielectric layer 140 and the connecting pad 196, such that the connecting pad 196 is located between the drain region 184 and the bit line 192, and the bit line 192 is electrically connected to the drain region 184 through the connecting pad 196. Accordingly, it is possible to obtain... Figure 2 The semiconductor structure 100a.

[0054] See also Figure 13 and Figure 1 Assuming the connection pad 196 is not formed, the bit line 192 can be directly formed on the drain region 184 and the third dielectric layer 140 without the connection pad 196. Subsequently, the barrier layer 193, the fourth dielectric layer 194, and the fifth dielectric layer 195 are sequentially formed on the bit line 192. Therefore, we can obtain... Figure 1 The semiconductor structure 100.

[0055] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

[0056] [Symbol Explanation]

[0057] 100, 100a: Semiconductor structure

[0058] 110: First dielectric layer

[0059] 120: Second dielectric layer

[0060] 130: Capacitor Structure

[0061] 132: Semiconductor Materials

[0062] 134: First electrode

[0063] 136: High dielectric constant dielectric material

[0064] 138: Second electrode

[0065] 140: Third dielectric layer

[0066] 142: Part

[0067] 143: Sidewall

[0068] 144: Inner wall

[0069] 150: Character Line

[0070] 152: Sidewall

[0071] 160: Channel Structure

[0072] 170: Gate Dielectric

[0073] 172: Part One

[0074] 174: Part Two

[0075] 182: Source Region

[0076] 184: Drain region

[0077] 192: Bitline

[0078] 193: Barrier Layer

[0079] 194: Fourth dielectric layer

[0080] 195: Fifth dielectric layer

[0081] 196: Connecting pad

[0082] D: Diameter

[0083] O: Channel hole

[0084] W1: Width

[0085] W2: Width.

Claims

1. A semiconductor structure, characterized in that, include: First dielectric layer; The second dielectric layer is located on the first dielectric layer; A capacitor structure is located between the first dielectric layer and the second dielectric layer; The third dielectric layer is located on the second dielectric layer; A character line is located in the third dielectric layer and crosses the capacitor structure, wherein a portion of the third dielectric layer is located between the character line and the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the character line and this portion of the third dielectric layer; as well as The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is located between the sidewall of the word line and the channel structure, and the second portion is located between the inner wall of the third dielectric layer and the channel structure.

2. The semiconductor structure according to claim 1, characterized in that, The width of the bottom of the character line is greater than the width of the top of the character line.

3. The semiconductor structure according to claim 2, characterized in that, The top of the character line contacts the channel structure.

4. The semiconductor structure according to claim 1, characterized in that, The first portion of the gate dielectric extends to the sidewall of that portion of the third dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: The source region is located between the top of the capacitor structure and the bottom of this portion of the third dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The bottom of the first portion of the gate dielectric is in contact with the source region.

7. The semiconductor structure according to claim 5, characterized in that, The bottom of the second portion of the gate dielectric is in contact with the source region.

8. The semiconductor structure according to claim 5, characterized in that, The bottom of the channel structure is in contact with the source region.

9. The semiconductor structure according to claim 1, characterized in that, The channel structure is surrounded by the second portion of the gate dielectric.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: The drain region is located at the top of the channel structure.

11. The semiconductor structure according to claim 10, characterized in that, Also includes: The bit line is electrically connected to the drain region.

12. The semiconductor structure according to claim 11, characterized in that, Also includes: A connection pad is located between the drain region and the bit line.

13. The semiconductor structure according to claim 11, characterized in that, Also includes: The fourth dielectric layer is located on this bit line; as well as A fifth dielectric layer is located on the fourth dielectric layer, wherein the material of the fifth dielectric layer is different from that of the fourth dielectric layer.

14. The semiconductor structure according to claim 1, characterized in that, The capacitor structure includes: Semiconductor materials; The first electrode surrounds the semiconductor material; A high dielectric constant dielectric material surrounds the first electrode; and The second electrode surrounds the bottom of the high dielectric constant dielectric.

15. A method for manufacturing a semiconductor structure, characterized in that, include: A capacitor structure is formed in a first dielectric layer and a second dielectric layer located on the first dielectric layer; A third dielectric layer and a word line are formed on the second dielectric layer, wherein the word line is located in the third dielectric layer and crosses the capacitor structure, and a portion of the third dielectric layer is located between the word line and the capacitor structure. A via is formed in the third dielectric layer to expose the character line; The first and second portions of the gate dielectric are respectively formed on the sidewall of the word line and the inner wall of the third dielectric layer; as well as A channel structure is formed in the channel hole of the third dielectric layer, wherein the channel structure surrounds the character line and the portion of the third dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The third dielectric layer and the character line are formed on the second dielectric layer such that the width of the bottom of the character line is greater than the width of the top of the character line.

17. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The first portion and the second portion forming the gate dielectric are such that the first portion of the gate dielectric extends to the sidewall of that portion of the third dielectric layer.

18. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, Forming the channel hole in the third dielectric layer includes using an etchant with a high etch selectivity between the third dielectric layer and the character line.

19. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The third dielectric layer and the character line are formed on the second dielectric layer such that the character line has a width in the range of 10 nanometers to 12 nanometers.

20. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The channel hole is formed in the third dielectric layer such that the channel hole has a radius in the range of 40 nanometers to 44 nanometers.

Images