Display control method, display control unit, and display device

Abstract

The present disclosure provides a display control method, a display control unit and a display device. The display control method comprises: after the refresh frequency of a display panel is reduced from a first refresh frequency to a second refresh frequency, a display period comprises a refresh stage and a holding stage arranged in sequence; the holding stage comprises at least one independent light-emitting control time period; the display control method comprises: in the refresh stage, a plurality of pixel circuits included in the display panel are sequentially connected to corresponding data voltages under the control of corresponding write control signals; in the holding stage, the plurality of pixel circuits included in the display panel stop being connected to the corresponding data voltages under the control of the corresponding write control signals; and in the light-emitting control time period, a light-emitting control circuit controls the communication between a first end of a driving circuit and a power supply voltage end and the communication between a second end of the driving circuit and a light-emitting element under the control of a light-emitting control signal.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display control method, a display control unit, and a display device. Background Technology

[0002] OLED, also known as organic light-emitting diode, has a different light-emitting principle than LCD (liquid crystal display). OLED display technology has advantages such as self-illumination, wide viewing angle, almost infinite contrast, low power consumption, and extremely high response speed, and is now widely used in mobile display terminal devices.

[0003] When the display panel is in operation, if the refresh rate is reduced from the first refresh rate to the second refresh rate, a large difference in brightness will occur, resulting in display flickering. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display control method applied to a display panel, the display panel including a multi-row pixel circuit; the pixel circuit including a light-emitting control circuit, a driving circuit, and a light-emitting element; the display control method includes: after the refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one mutually independent light-emitting control time period; the display control method includes:

[0005] During the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to corresponding data voltages under the control of corresponding write control signals;

[0006] During the holding phase, the multi-row pixel circuits included in the display panel stop receiving the corresponding data voltage under the control of the corresponding write control signal;

[0007] During the light emission control period, under the control of the corresponding light emission control signal, the light emission control circuit controls the connection between the first terminal of the driving circuit and the power supply voltage terminal, and controls the connection between the second terminal of the driving circuit and the light emission element.

[0008] Optionally, during the refresh phase and the hold phase, the absolute value of the difference between the frequency of the light emission control signal and the first frequency is less than a predetermined frequency difference.

[0009] The first frequency is the frequency of the light emission control signal during the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

[0010] Optionally, during the refresh phase and the hold phase, the frequency of the light emission control signal is equal to the first frequency.

[0011] Optionally, the pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit, and the connection node, respectively; the compensation control circuit is electrically connected to the compensation control terminal, the connection node, and the second terminal of the driving circuit, respectively; the display control method further includes:

[0012] During the holding phase, the on / off control circuit, under the control of the on / off control signal provided by the on / off control terminal, controls the control terminal of the drive circuit to disconnect from the connection node, and the compensation control circuit, under the control of the compensation control signal provided by the compensation control terminal, controls the connection node to disconnect from the second terminal of the drive circuit.

[0013] Optionally, the pixel circuit further includes a first reset circuit; the first reset circuit is electrically connected to the scanning terminal, the first initial voltage terminal, and the first electrode of the light-emitting element, respectively; after the refresh frequency of the display panel decreases from the first refresh frequency to the second refresh frequency, the holding phase includes at least one set time period; the display control method further includes:

[0014] During the set time period, the first reset circuit, under the control of the scan signal, writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element.

[0015] Optionally, the pixel circuit further includes a setting circuit; the setting circuit is electrically connected to the scanning terminal, the setting voltage terminal, and the first terminal of the driving circuit, respectively.

[0016] The display control method further includes:

[0017] During the set time period, the set circuit, under the control of the scan signal provided by the scan terminal, writes the set voltage provided by the set voltage terminal into the first terminal of the drive circuit.

[0018] Optionally, the setting time period and the light emission control time period are independent of each other;

[0019] The number of light-emitting control time periods is N times the number of setting time periods; N is a positive integer.

[0020] Optionally, the absolute value of the difference between the duration of the refresh phase and the first time is less than a predetermined time difference;

[0021] The first time is the duration of the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

[0022] Optionally, during the refresh phase and when the refresh frequency of the display panel is the first refresh frequency, the waveform of the light emission control signal is the same and the waveform of the scan signal is the same during the display cycle of the display panel.

[0023] Optionally, the duration of the refresh phase is equal to that of the first time.

[0024] Optionally, the pixel circuit further includes a setting circuit, a first reset circuit, a data writing circuit, an energy storage circuit, a second reset circuit, an on / off control circuit, and a compensation control circuit; the refresh phase includes a first time period, a second time period, a third time period, and a first light emission phase set sequentially; the first light emission phase includes a first light emission time period and a first reset time period that are independent of each other;

[0025] The display control method further includes:

[0026] During the first time period, the set circuit, under the control of the scan signal, writes the set voltage into the first terminal of the driving circuit; the second reset circuit, under the control of the scan signal, writes the second initial voltage into the connection node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the connection node and the control terminal of the driving circuit to write the second initial voltage into the control terminal of the driving circuit; the first reset circuit, under the control of the scan signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0027] During the second time period, the data writing circuit, under the control of the writing control signal, writes the data voltage to the first terminal of the driving circuit. Under the control of the compensation control signal, the compensation control circuit controls the connection between the connection node and the second terminal of the driving circuit. Under the control of the on / off control signal, the on / off control circuit controls the connection between the connection node and the control terminal of the driving circuit.

[0028] At the beginning of the second time period, the driving circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the driving circuit, and charges the energy storage circuit through the data voltage to change the potential of the control terminal of the driving circuit until the driving circuit is turned off.

[0029] During the third time period, the setting circuit, under the control of the scanning signal, writes the setting voltage into the first terminal of the driving circuit, and the first reset circuit, under the control of the scanning signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0030] During the first light emission period, under the control of the corresponding light emission control signal, the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light emission element, and the driving circuit drives the light emission element to emit light.

[0031] During the first reset time period, the set circuit, under the control of the scan signal provided by the scan terminal, writes the set voltage provided by the set voltage terminal into the first terminal of the driving circuit, and the first reset circuit, under the control of the scan signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0032] In a second aspect, embodiments of this disclosure provide a display control unit applied to a display panel, the display panel including a multi-row pixel circuit; the pixel circuit including a light-emitting control circuit, a driving circuit, and a light-emitting element; after the refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one mutually independent light-emitting control time period; the display control unit includes a display control circuit;

[0033] The display control circuit is used to control the write control signal so that, during the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to the corresponding data voltages under the control of the corresponding write control signal.

[0034] The display control circuit is also used to control the write control signal during the holding phase, so that the multi-row pixel circuit included in the display panel stops receiving the corresponding data voltage under the control of the corresponding write control signal, and is also used to control the light emission control signal during the light emission control period, so that the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and the second terminal of the driving circuit to connect with the light emission element under the control of the corresponding light emission control signal.

[0035] Optionally, the pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit, and the connection node, respectively; the compensation control circuit is electrically connected to the compensation control terminal, the connection node, and the second terminal of the driving circuit, respectively.

[0036] The display control circuit is further configured to, during the holding phase, control the on / off control signal and the compensation control signal to disconnect the control terminal of the drive circuit from the connection node under the control of the on / off control signal, and to disconnect the connection node from the second terminal of the drive circuit under the control of the compensation control signal.

[0037] Optionally, the pixel circuit further includes a setting circuit and a first reset circuit; the setting circuit is electrically connected to the scanning end, the setting voltage end and the first end of the driving circuit respectively; the first reset circuit is electrically connected to the scanning end, the first initial voltage end and the first electrode of the light-emitting element respectively; after the refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, the holding phase includes at least one setting time period.

[0038] The display control circuit is further configured to control the scan signal so that, during the set time period, the set circuit, under the control of the scan signal, writes the set voltage provided by the set voltage terminal into the first terminal of the driving circuit, and the first reset circuit, under the control of the scan signal, writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element.

[0039] In a third aspect, embodiments of this disclosure provide a display device including the display control unit described above. Attached Figure Description

[0040] Figure 1 This is a structural diagram of at least one embodiment of the pixel circuitry included in the display device described in this disclosure;

[0041] Figure 2 This is a circuit diagram of at least one embodiment of the pixel circuitry included in the display device described in this disclosure;

[0042] Figure 3 This disclosure is made when the refresh rate is 120Hz. Figure 2 The timing diagram of at least one embodiment of the pixel circuit shown;

[0043] Figure 4 This disclosure is made after the refresh rate is changed from 120Hz to 80Hz. Figure 2 The timing diagram of at least one embodiment of the pixel circuit shown;

[0044] Figure 5 This disclosure is made after the refresh rate is changed from 120Hz to 30Hz. Figure 2 The timing diagram of at least one embodiment of the pixel circuit shown;

[0045] Figure 6This disclosure is made when the refresh rate is 120Hz. Figure 2 The timing diagram of at least one embodiment of the pixel circuit shown;

[0046] Figure 7 This disclosure is made after the refresh rate is changed from 120Hz to 30Hz. Figure 2 The timing diagram of at least one embodiment of the pixel circuit shown;

[0047] Figure 8 This is a table showing the correspondence between the number of scan signal pulses and the number of light emission control signal pulses inserted during the holding phase and the refresh frequency;

[0048] Figure 9 This is a table showing the correspondence between the number of scan signal pulses and the number of light emission control signal pulses inserted during the holding phase and the refresh frequency;

[0049] Figure 10 This is a structural diagram of a display control unit according to at least one embodiment of the present disclosure. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0051] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0052] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0053] The display control method described in this disclosure is applied to a display panel, the display panel including a multi-row pixel circuit; the pixel circuit includes a light-emitting control circuit, a driving circuit, and a light-emitting element; the display control method includes: after the refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one mutually independent light-emitting control time period; the display control method includes:

[0054] During the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to corresponding data voltages under the control of corresponding write control signals;

[0055] During the holding phase, the multi-row pixel circuits included in the display panel stop receiving the corresponding data voltage under the control of the corresponding write control signal;

[0056] During the light emission control period, under the control of the corresponding light emission control signal, the light emission control circuit controls the connection between the first terminal of the driving circuit and the power supply voltage terminal, and controls the connection between the second terminal of the driving circuit and the light emission element.

[0057] In the display control method described in this embodiment, after the refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, the duration of the display cycle is increased by setting the display period to include a hold phase after the refresh phase. During the hold phase, the pixel circuits included in the display panel are not connected to data voltage. With the above settings, when the refresh frequency of the display panel changes, the frequency of the light emission control signal can be controlled to change little or not at all, so that a set of gamma settings can be used to ensure that the brightness change of the display panel is small or not at all when the refresh frequency changes, thereby improving the flickering phenomenon when the refresh frequency is switched.

[0058] In at least one embodiment of this disclosure, during the refresh phase and the hold phase, the absolute value of the difference between the frequency of the light emission control signal and the first frequency is less than a predetermined frequency difference.

[0059] The first frequency is the frequency of the light emission control signal during the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

[0060] In specific implementation, during the refresh phase and the holding phase, the frequency of the light emission control signal can be set to be approximately the same as the first frequency, where the first frequency is the refresh frequency of the display panel, and the frequency of the light emission control signal is the same during the display cycle of the display panel.

[0061] In at least one embodiment of this disclosure, during the refresh phase and the hold phase, the frequency of the light emission control signal is equal to the first frequency.

[0062] In a preferred embodiment, during the refresh phase and the hold phase, the frequency of the light emission control signal is the same as the first frequency.

[0063] Optionally, the pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit, and the connection node, respectively; the compensation control circuit is electrically connected to the compensation control terminal, the connection node, and the second terminal of the driving circuit, respectively; the display control method further includes:

[0064] During the holding phase, the on / off control circuit, under the control of the on / off control signal provided by the on / off control terminal, controls the control terminal of the drive circuit to disconnect from the connection node, and the compensation control circuit, under the control of the compensation control signal provided by the compensation control terminal, controls the connection node to disconnect from the second terminal of the drive circuit.

[0065] In a specific implementation, the pixel circuit may further include an on / off control circuit and a compensation control circuit; during the holding phase, the on / off control circuit, under the control of the on / off control signal, controls the control terminal of the driving circuit to disconnect from the connection node, and the compensation control circuit, under the control of the compensation control signal, controls the connection node to disconnect from the second terminal of the driving circuit, so as to control the disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit, so that the potential of the control terminal of the driving circuit can remain unchanged.

[0066] Optionally, the pixel circuit further includes a first reset circuit; the first reset circuit is electrically connected to the scanning terminal, the first initial voltage terminal, and the first electrode of the light-emitting element, respectively.

[0067] After the refresh rate of the display panel decreases from the first refresh rate to the second refresh rate, the holding phase includes at least one set time period; the display control method further includes:

[0068] During the set time period, the first reset circuit, under the control of the scan signal, writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element.

[0069] In a specific implementation, the pixel circuit may further include a first reset circuit. The holding phase includes a setting time period. During the setting time period, under the control of the scanning signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element to set the potential of the first electrode of the light-emitting element.

[0070] In related technologies, due to the parasitic capacitance inherent in the light-emitting element, the potential maintained by the parasitic capacitance differs between the refresh phase and the holding phase. This results in a brightness difference when the light-emitting control circuit controls the connection between the first terminal of the driving circuit and the power supply voltage terminal, and the connection between the second terminal of the driving circuit and the light-emitting element, under the control of the corresponding light-emitting control signal. This difference causes flickering when switching between different refresh frequencies. Therefore, in at least one embodiment of this disclosure, after the refresh frequency is changed, the holding phase needs to be set to include at least one set time period. During the set time period, the first reset circuit writes the first initial voltage to the first pole of the light-emitting element to reduce the brightness difference after the refresh frequency switch and improve the flickering phenomenon.

[0071] In at least one embodiment of this disclosure, the pixel circuit further includes a setting circuit; the setting circuit is electrically connected to the scanning terminal, the setting voltage terminal, and the first terminal of the driving circuit, respectively.

[0072] The display control method further includes:

[0073] During the set time period, the set circuit, under the control of the scan signal provided by the scan terminal, writes the set voltage provided by the set voltage terminal into the first terminal of the drive circuit.

[0074] In a specific implementation, the pixel circuit may further include a setting circuit. During the setting time period, the setting circuit writes a setting voltage to the first terminal of the driving circuit to set the potential of the first terminal of the driving circuit.

[0075] Optionally, the setting time period and the light emission control time period are independent of each other;

[0076] The number of light-emitting control time periods is N times the number of setting time periods; N is a positive integer.

[0077] For example, N can be 1 or 2, but is not limited to this.

[0078] In at least one embodiment of this disclosure, by adjusting the number of pulses of the light emission control signal and the number of pulses of the scan signal inserted during the holding phase, the waveform of the scan signal can be changed, thereby achieving a finer refresh rate change, adapting to more application scenarios, reducing the overall power consumption of the display panel included in the display device, and extending the normal use time of the display panel.

[0079] In at least one embodiment of this disclosure, the refresh phase includes a first light-emitting phase, the first light-emitting phase including a first light-emitting time period and a first reset time period that are independent of each other; the display control method includes:

[0080] During the first light emission period, under the control of the corresponding light emission control signal, the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light emission element, and the driving circuit drives the light emission element to emit light.

[0081] During the first reset time period, the set circuit, under the control of the scan signal provided by the scan terminal, writes the set voltage provided by the set voltage terminal into the first terminal of the driving circuit, and the first reset circuit, under the control of the scan signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0082] In at least one embodiment of this disclosure, when the refresh frequency of the display panel is a first refresh frequency, the display cycle includes a second light-emitting phase; the second light-emitting phase includes a second light-emitting time period and a second reset time period that are independent of each other; the display control method includes:

[0083] During the second light-emitting period, under the control of the corresponding light-emitting control signal, the light-emitting control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light-emitting element, and the driving circuit drives the light-emitting element to emit light.

[0084] During the second reset time period, the setting circuit, under the control of the scanning signal provided by the scanning terminal, writes the setting voltage provided by the setting voltage terminal into the first terminal of the driving circuit, and the first reset circuit, under the control of the scanning signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0085] Optionally, the absolute value of the difference between the duration of the refresh phase and the first time is less than a predetermined time difference;

[0086] The first time is the duration of the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

[0087] In practice, the duration of the refresh phase can be approximately equal to the duration of the display cycle before the refresh frequency switch, after the refresh frequency switch. During the refresh phase, the waveforms of each control signal can be approximately the same as the waveforms of each control signal before the refresh frequency switch, in order to improve the frequency switching flickering phenomenon.

[0088] In at least one embodiment of this disclosure, the duration of the refresh phase is equal to that of the first time.

[0089] In a preferred embodiment, the duration of the refresh phase is equal to the duration of the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

[0090] Optionally, the pixel circuit further includes a setting circuit, a first reset circuit, a data writing circuit, an energy storage circuit, a second reset circuit, an on / off control circuit, and a compensation control circuit; the refresh phase includes a first time period, a second time period, and a third time period set sequentially; the third time period is set before the first light-emitting phase; the display control method further includes:

[0091] During the first time period, the set circuit, under the control of the scan signal, writes the set voltage into the first terminal of the driving circuit; the second reset circuit, under the control of the scan signal, writes the second initial voltage into the connection node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the connection node and the control terminal of the driving circuit to write the second initial voltage into the control terminal of the driving circuit; the first reset circuit, under the control of the scan signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0092] During the second time period, the data writing circuit, under the control of the writing control signal, writes the data voltage to the first terminal of the driving circuit. Under the control of the compensation control signal, the compensation control circuit controls the connection between the connection node and the second terminal of the driving circuit. Under the control of the on / off control signal, the on / off control circuit controls the connection between the connection node and the control terminal of the driving circuit.

[0093] At the beginning of the second time period, the driving circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the driving circuit, and charges the energy storage circuit through the data voltage to change the potential of the control terminal of the driving circuit until the driving circuit is turned off.

[0094] During the third time period, the setting circuit, under the control of the scanning signal, writes the setting voltage into the first terminal of the driving circuit, and the first reset circuit, under the control of the scanning signal, writes the first initial voltage into the first electrode of the light-emitting element.

[0095] like Figure 1 As shown, at least one embodiment of the pixel circuit may include a light-emitting control circuit 11, a driving circuit 10, a light-emitting element E0, an on / off control circuit 12, a compensation control circuit 13, a setting circuit 14, a first reset circuit 15, a data writing circuit 16, an energy storage circuit 17, and a second reset circuit 18.

[0096] The light-emitting control circuit 11 is electrically connected to the light-emitting control terminal E1, the first terminal of the driving circuit 10, the power supply voltage terminal VDD, the second terminal of the driving circuit 10, and the first electrode of the light-emitting element E0, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal E1, it controls the connection or disconnection between the first terminal of the driving circuit 10 and the power supply voltage terminal VDD, and controls the connection or disconnection between the second terminal of the driving circuit 10 and the first electrode of the light-emitting element E0; the second electrode of the light-emitting element E0 is electrically connected to the low voltage terminal VSS.

[0097] The on / off control circuit 12 is electrically connected to the on / off control terminal NG, the control terminal of the drive circuit 10 and the connection node J1, respectively, and is used to control the connection or disconnection between the control terminal of the drive circuit 10 and the connection node J1 under the control of the on / off control signal provided by the on / off control terminal NG.

[0098] The compensation control circuit 13 is electrically connected to the compensation control terminal PG1, the connection node J1 and the second terminal of the drive circuit 10 respectively, and is used to control the connection node J1 and the second terminal of the drive circuit 10 to be connected or disconnected under the control of the compensation control signal provided by the compensation control terminal PG.

[0099] The first reset circuit 15 is electrically connected to the scanning terminal S0, the first initial voltage terminal I1 and the first pole of the light-emitting element E0, respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first pole of the light-emitting element E0 under the control of the scanning signal provided by the scanning terminal S0.

[0100] The setting circuit 14 is electrically connected to the scanning terminal S0, the setting voltage terminal VR, and the first terminal of the driving circuit 10, respectively, and is used to write the setting voltage Vref provided by the setting voltage terminal VR into the first terminal of the driving circuit 10 under the control of the scanning signal provided by the scanning terminal S0.

[0101] The data writing circuit 16 is electrically connected to the write control terminal PG2, the data line D1 and the first terminal of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line D1 into the first terminal of the driving circuit 10 under the control of the write control signal provided by the write control terminal PG2.

[0102] The first terminal of the energy storage circuit 17 is electrically connected to the control terminal of the drive circuit 10, and the second terminal of the energy storage circuit 17 is electrically connected to the power supply voltage terminal VDD. The energy storage circuit 17 is used to store electrical energy.

[0103] The second reset circuit 18 is electrically connected to the scanning terminal S0, the second initial voltage terminal I2 and the connection node J1 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the connection node J1 under the control of the scanning signal.

[0104] In at least one embodiment of this disclosure, the compensation control terminal PG1 and the write control terminal PG2 may be the same control terminal.

[0105] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the pixel circuit shown, the second reset circuit includes a first transistor T1, the compensation control circuit includes a second transistor T2, the driving circuit includes a third transistor T3, the data writing circuit includes a fourth transistor T4, the light-emitting control circuit includes a fifth transistor T5 and a sixth transistor T6, the first reset circuit includes a seventh transistor T7, the on / off control circuit includes an eighth transistor T8, and the set circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst; and the light-emitting element is an organic light-emitting diode O1.

[0106] The gate of T1 is electrically connected to the scan terminal S0, the source of T1 is electrically connected to the second initial voltage terminal I2, and the drain of T1 is electrically connected to the connection node J1.

[0107] The gate of T2 is electrically connected to the first control terminal PG, the source of T2 is electrically connected to the connection node J1, and the drain of T2 is electrically connected to the drain of T3.

[0108] The gate of T3 is electrically connected to the first terminal of Cst;

[0109] The gate of T4 is electrically connected to the first control terminal PG, the source of T4 is electrically connected to the data line D1, and the drain of T4 is electrically connected to the source of T3.

[0110] The gate of T5 is electrically connected to the light-emitting control terminal E1, the source of T5 is electrically connected to the power supply voltage terminal VDD, and the drain of T5 is electrically connected to the source of T3.

[0111] The gate of T6 is electrically connected to the light-emitting control terminal E1, the source of T6 is electrically connected to the drain of T3, the drain of T6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low voltage terminal VSS.

[0112] The gate of T7 is electrically connected to the scan terminal S0, the source of T7 is electrically connected to the first initial voltage terminal I1, and the drain of T7 is electrically connected to the anode of O1.

[0113] The gate of T8 is electrically connected to the on / off control terminal NG, the source of T8 is electrically connected to the gate of T3, and the drain of T8 is electrically connected to the connection node J1.

[0114] The gate of T9 is electrically connected to the scan terminal S0, the source of T9 is electrically connected to the set voltage terminal VR, and the drain of T9 is electrically connected to the source of T3.

[0115] The first terminal of Cst is electrically connected to the gate of T3, and the second terminal of Cst is electrically connected to the power supply voltage terminal VDD.

[0116] exist Figure 2 In at least one embodiment shown, Vdata is the data voltage corresponding to the grayscale.

[0117] exist Figure 2 In at least one embodiment shown, T8 is an n-type transistor, T1, T2, T3, T4, T5, T6, T7 and T9 are p-type transistors, T3 is a driving transistor, T8 is an oxide thin film transistor, and T1, T2, T3, T4, T5, T6, T7 and T9 are LTPS (low-temperature polycrystalline silicon) thin film transistors, but are not limited thereto.

[0118] exist Figure 2 In at least one embodiment shown, the compensation control terminal PG1 and the write control terminal PG2 are first control terminals PG.

[0119] Figure 3 When the refresh rate is 120Hz, Figure 2 The diagram shows the timing of operation of at least one embodiment of the pixel circuit. Figure 3 In the text, the label TZ indicates the display cycle.

[0120] like Figure 3 As shown, the display period TZ includes a first display time period S31, a second display time period S32, a third display time period S33, and a second light-emitting stage S02, which are set sequentially.

[0121] The second light-emitting stage S02 includes a first second light-emitting time period S021, a second second light-emitting time period S022, a first second reset time period F21, a third second light-emitting time period S023, and a fourth second light-emitting time period S024, which are set sequentially.

[0122] During the first display time period S31, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a high voltage signal, T8 is turned on, and T1, T7 and T9 are all turned on. I2 provides a second initial voltage Vi2 to the gate connecting nodes J1 and T3, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0123] During the second display period S32, E1 provides a high voltage signal, S0 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4 and T2 are turned on, T8 is turned on, data line D1 provides data voltage Vdata to the source of T3, and the gate of T3 is connected to the drain of T3.

[0124] At the start of the second display time period S32, T3 is turned on to charge Cst through Vdata, thereby changing the potential of the gate of T3 until T3 is turned off. At this time, the gate potential of T3 is Vdata + Vth, where Vth is the gate voltage of T3.

[0125] During the third display time period S33, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I1 provides the first initial voltage Vi1 to the anode of O1, and VR provides the set voltage Vref to the source of T3.

[0126] During the first second light emission period S021, the second second light emission period S022, the third second light emission period S023, and the fourth second light emission period S024, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0127] During the first second reset time period F21, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0128] exist Figures 3-7 In this context, Vy is the frame synchronization signal, and DE is the data enable signal.

[0129] like Figure 2 At least one embodiment of the pixel circuit shown, when in operation, after the refresh rate is changed from 120Hz to 80Hz, as... Figure 4 As shown, the display cycle may include a refresh phase Ts and a hold phase Tb that are set sequentially.

[0130] The refresh phase Ts includes a first time period S41, a second time period S42, a third time period S43 and a first light-emitting phase S01 set sequentially; the first light-emitting phase S01 includes a first first light-emitting time period S011, a second first light-emitting time period S012, a first first reset time period F11, a third first light-emitting time period S013 and a fourth first light-emitting time period S04 set sequentially.

[0131] During the first time period S41, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a high voltage signal, T8 is turned on, and T1, T7 and T9 are all turned on. I2 provides a second initial voltage Vi2 to the gate connecting nodes J1 and T3, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0132] During the second time period S42, E1 provides a high voltage signal, S0 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4 and T2 are turned on, T8 is turned on, data line D1 provides data voltage Vdata to the source of T3, and the gate of T3 is connected to the drain of T3.

[0133] At the start of the second time period S42, T3 is turned on to charge Cst through Vdata, thereby changing the potential of the gate of T3 until T3 is turned off. At this time, the gate potential of T3 is Vdata + Vth, where Vth is the gate voltage of T3.

[0134] During the third time period S43, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I1 provides the first initial voltage Vi1 to the anode of O1, and VR provides the set voltage Vref to the source of T3.

[0135] During the first first light emission period S011, the second first light emission period S012, the third first light emission period S013, and the fourth first light emission period S014, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0136] During the first reset time period F11, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0137] The holding phase Tb includes a first setting time period Sz1, a first light emission control time period Sb1, and a second light emission control time period Sb2, which are set sequentially.

[0138] During the first light emission control period Sb1 and the second light emission control period Sb2, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, T3 drives O1 to emit light, and T1, T2, T4, T7, T8 and T9 are turned off.

[0139] During the first set time period Sz1, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are turned on, and T2, T3, T4, T5, T6 and T8 are turned off. I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0140] like Figure 4 As shown, during the hold phase Tb, the number of light emission control time periods is twice the number of set time periods.

[0141] like Figure 3 and Figure 4 As shown, during the refresh phase Ts and the first cycle TZ1, the waveforms of the light emission control signal provided by E1 are the same, the waveforms of the scan signal provided by S0 are the same, the waveforms of the first control signal provided by PG are the same, and the waveforms of the on / off control signal provided by NG are the same.

[0142] like Figure 3 and Figure 4 As shown, by inserting two light-emitting control pulses and one scanning pulse during the holding phase Tb, the frame time is extended by one frame, causing the refresh frequency to change from 120Hz to 80Hz. Furthermore, during the refresh phase and when the refresh frequency is 120Hz, the timing sequence of each control signal is the same in the display cycle. This allows the same set of gamma settings to be used during refresh frequency switching, maintaining small or no brightness differences and improving the frequency switching flicker phenomenon.

[0143] like Figure 2 At least one embodiment of the pixel circuit shown, when in operation, after the refresh rate is changed from 120Hz to 30Hz, as... Figure 5 As shown, the display cycle may include a refresh phase Ts and a hold phase Tb that are set sequentially.

[0144] The refresh phase Ts includes a first time period S41, a second time period S42, a third time period S43 and a first light-emitting phase S01 set sequentially; the first light-emitting phase S01 includes a first first light-emitting time period S011, a second first light-emitting time period S012, a first first reset time period F11, a third first light-emitting time period S013 and a fourth first light-emitting time period S04 set sequentially.

[0145] During the first time period S41, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a high voltage signal, T8 is turned on, and T1, T7 and T9 are all turned on. I2 provides a second initial voltage Vi2 to the gate connecting nodes J1 and T3, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0146] During the second time period S42, E1 provides a high voltage signal, S0 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4 and T2 are turned on, T8 is turned on, data line D1 provides data voltage Vdata to the source of T3, and the gate of T3 is connected to the drain of T3.

[0147] At the start of the second time period S42, T3 is turned on to charge Cst through Vdata, thereby changing the potential of the gate of T3 until T3 is turned off. At this time, the gate potential of T3 is Vdata + Vth, where Vth is the gate voltage of T3.

[0148] During the third time period S43, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I1 provides the first initial voltage Vi1 to the anode of O1, and VR provides the set voltage Vref to the source of T3.

[0149] During the first first light emission period S011, the second first light emission period S012, the third first light emission period S013, and the fourth first light emission period S014, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0150] During the first reset time period F11, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0151] The holding phase Tb includes the following sequentially set periods: first setting time Sz1, first light emission control time Sb1, second light emission control time, second setting time, third light emission control time, fourth light emission control time, third setting time, fifth light emission control time, sixth light emission control time, fourth setting time, seventh light emission control time, eighth light emission control time, fifth setting time, ninth light emission control time, tenth light emission control time, sixth setting time, eleventh light emission control time, and twelfth light emission control time.

[0152] During the first set time period Sz1, the second set time period, the third set time period, the fourth set time period, the fifth set time period, and the sixth set time period, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7, and T9 are turned on, and T2, T3, T4, T5, T6, and T8 are turned off. I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0153] During the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth light-emitting control periods (Sb1, S0, PG, and NG), E1 provides a low-voltage signal, S0 provides a high-voltage signal, PG provides a high-voltage signal, NG provides a low-voltage signal, T5 and T6 are turned on, T3 drives O1 to emit light, and T1, T2, T4, T7, T8, and T9 are turned off.

[0154] exist Figure 5 In at least one of the embodiments shown, the number of light emission control time periods is twice the number of set time periods.

[0155] exist Figure 5 In the middle, due to insufficient horizontal length, the time periods other than the first setting time period Sz1 and the first light emission control time period Sb1 are not labeled, and all time periods other than the first setting time period Sz1 and the first light emission control time period Sb1 are not shown.

[0156] Figure 6 When the refresh rate is 120Hz, Figure 2 The diagram shows the timing of operation of at least one embodiment of the pixel circuit. Figure 6 In the text, the label TZ indicates the display cycle.

[0157] like Figure 6As shown, when the refresh rate is 120Hz, the display period TZ includes the first display time period S31, the second display time period S32, the third display time period S33, and the second light emission stage S02, which are set sequentially.

[0158] The second light-emitting stage S02 includes a first second light-emitting time period S021, a first second reset time period F21, a second second light-emitting time period S022, a second second reset time period F22, a third second light-emitting time period S023, a third second reset time period F23, and a fourth second light-emitting time period S024, which are set sequentially.

[0159] During the first display time period S31, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a high voltage signal, T8 is turned on, and T1, T7 and T9 are all turned on. I2 provides a second initial voltage Vi2 to the gate connecting nodes J1 and T3, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0160] During the second display period S32, E1 provides a high voltage signal, S0 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4 and T2 are turned on, T8 is turned on, data line D1 provides data voltage Vdata to the source of T3, and the gate of T3 is connected to the drain of T3.

[0161] At the start of the second display time period S32, T3 is turned on to charge Cst through Vdata, thereby changing the potential of the gate of T3 until T3 is turned off. At this time, the gate potential of T3 is Vdata + Vth, where Vth is the gate voltage of T3.

[0162] During the third display time period S33, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I1 provides the first initial voltage Vi1 to the anode of O1, and VR provides the set voltage Vref to the source of T3.

[0163] During the first second light emission period S021, the second second light emission period S022, the third second light emission period S023, and the fourth second light emission period S024, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0164] During the first second reset time period F21, the second second reset time period F22, and the third second reset time period F23, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7, and T9 are all turned on, I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0165] like Figure 2 At least one embodiment of the pixel circuit shown, when in operation, after the refresh rate is changed from 120Hz to 30Hz, as... Figure 7 As shown, the display cycle may include a refresh phase Ts and a hold phase Tb that are set sequentially.

[0166] The refresh phase Ts includes a first time period S41, a second time period S42, a third time period S43, and a first light-emitting phase S01, which are set sequentially. The first light-emitting phase S01 includes a first first light-emitting time period S011, a first first reset time period F11, a second first light-emitting time period S012, a second first reset time period F12, a third first light-emitting time period S013, a third first reset time period F13, and a fourth first light-emitting time period S04, which are set sequentially.

[0167] During the first time period S41, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a high voltage signal, T8 is turned on, and T1, T7 and T9 are all turned on. I2 provides a second initial voltage Vi2 to the gate connecting nodes J1 and T3, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0168] During the second time period S42, E1 provides a high voltage signal, S0 provides a high voltage signal, PG provides a low voltage signal, NG provides a high voltage signal, T4 and T2 are turned on, T8 is turned on, data line D1 provides data voltage Vdata to the source of T3, and the gate of T3 is connected to the drain of T3.

[0169] At the start of the second time period S42, T3 is turned on to charge Cst through Vdata, thereby changing the potential of the gate of T3 until T3 is turned off. At this time, the gate potential of T3 is Vdata + Vth, where Vth is the gate voltage of T3.

[0170] During the third time period S43, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7 and T9 are all turned on, I1 provides the first initial voltage Vi1 to the anode of O1, and VR provides the set voltage Vref to the source of T3.

[0171] During the first first light emission period S011, the second first light emission period S012, the third first light emission period S013, and the fourth first light emission period S014, E1 provides a low voltage signal, S0 provides a high voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T5 and T6 are turned on, and T3 drives O1 to emit light.

[0172] During the first first reset time period F11, the second first reset time period F12, and the third first reset time period F13, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7, and T9 are all turned on, I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0173] The holding phase Tb includes the following sequentially set time periods: first set time period Sz1, first light emission control time period Sb1, second set time period Sz2, second light emission control time period, third set time period, third light emission control time period, fourth set time period, fourth light emission control time period, fifth set time period, fifth light emission control time period, sixth set time period, sixth light emission control time period, seventh set time period, seventh light emission control time period, eighth set time period, eighth light emission control time period, ninth set time period, ninth light emission control time period, tenth set time period, tenth light emission control time period, eleventh set time period, eleventh light emission control time period, twelfth set time period, and twelfth light emission control time period.

[0174] During the first set time period Sz1, the second set time period Sz2, the third set time period, the fourth set time period, the fifth set time period, the sixth set time period, the seventh set time period, the eighth set time period, the ninth set time period, the tenth set time period, the eleventh set time period, and the twelfth set time period, E1 provides a high voltage signal, S0 provides a low voltage signal, PG provides a high voltage signal, NG provides a low voltage signal, T1, T7, and T9 are turned on, and T2, T3, T4, T5, T6, and T8 are turned off. I2 provides a second initial voltage Vi2 to the connection node J1, VR provides a set voltage Vref to the source of T3, and I1 provides a first initial voltage Vi1 to the anode of O1.

[0175] During the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth light-emitting control periods (Sb1, S0, PG, and NG), E1 provides a low-voltage signal, S0 provides a high-voltage signal, PG provides a high-voltage signal, NG provides a low-voltage signal, T5 and T6 are turned on, T3 drives O1 to emit light, and T1, T2, T4, T7, T8, and T9 are turned off.

[0176] exist Figure 7 In at least one of the embodiments shown, the number of light emission control time periods is equal to the number of set time periods.

[0177] exist Figure 7 In the middle, due to insufficient horizontal length, the time periods other than the first setting time period Sz1, the first light emission control time period Sb1 and the second setting time period Sz2 are not labeled, and all time periods other than the first setting time period Sz1, the first light emission control time period Sb1 and the second setting time period Sz2 are not shown.

[0178] Figure 8 and Figure 9 A table showing the correspondence between the number of scan signal pulses and the number of light emission control signal pulses inserted during the holding phase and the refresh frequency is provided.

[0179] In at least one embodiment of this disclosure, when the refresh rate is 120Hz and four downward light emission control signal pulses are provided within one frame, such as Figure 8 As shown, after the refresh rate is reduced,

[0180] When two light-emitting control signal pulses and one scan signal pulse are inserted during the holding phase, the refresh rate becomes 80Hz;

[0181] When four light-emitting control signal pulses and two scan signal pulses are inserted during the holding phase, the refresh rate becomes 60Hz;

[0182] When 6 light-emitting control signal pulses and 3 scan signal pulses are inserted during the holding phase, the refresh rate becomes 48Hz;

[0183] When 8 light-emitting control signal pulses and 4 scan signal pulses are inserted during the holding phase, the refresh rate becomes 40Hz;

[0184] When 10 light-emitting control signal pulses and 5 scan signal pulses are inserted during the holding phase, the refresh rate becomes 34.29Hz;

[0185] When 12 light-emitting control signal pulses and 6 scan signal pulses are inserted during the holding phase, the refresh rate becomes 30Hz;

[0186] When 14 light emission control signal pulses and 7 scan signal pulses are inserted during the holding phase, the refresh rate becomes 26.67Hz;

[0187] When 16 light-emitting control signal pulses and 8 scan signal pulses are inserted during the holding phase, the refresh rate becomes 24Hz;

[0188] When 18 light-emitting control signal pulses and 9 scan signal pulses are inserted during the holding phase, the refresh rate becomes 21.82Hz;

[0189] When 20 light-emitting control signal pulses and 10 scan signal pulses are inserted during the holding phase, the refresh rate becomes 20Hz;

[0190] When 22 light-emitting control signal pulses and 11 scan signal pulses are inserted during the holding phase, the refresh rate becomes 18.46Hz;

[0191] When 24 light-emitting control signal pulses and 12 scan signal pulses are inserted during the holding phase, the refresh rate becomes 17.14Hz;

[0192] When 26 light-emitting control signal pulses and 13 scan signal pulses are inserted during the holding phase, the refresh rate becomes 16Hz;

[0193] When 28 light-emitting control signal pulses and 14 scan signal pulses are inserted during the holding phase, the refresh rate becomes 15Hz;

[0194] When 30 light-emitting control signal pulses and 15 scan signal pulses are inserted during the holding phase, the refresh rate becomes 14.12Hz;

[0195] When 32 light emission control signal pulses and 16 scan signal pulses are inserted during the holding phase, the refresh rate becomes 13.33Hz;

[0196] When 34 light-emitting control signal pulses and 17 scan signal pulses are inserted during the holding phase, the refresh rate becomes 12.63Hz;

[0197] When 36 light-emitting control signal pulses and 18 scan signal pulses are inserted during the holding phase, the refresh rate becomes 12Hz;

[0198] When 38 light-emitting control signal pulses and 19 scan signal pulses are inserted during the holding phase, the refresh rate becomes 11.43Hz;

[0199] When 40 light-emitting control signal pulses and 20 scan signal pulses are inserted during the holding phase, the refresh rate becomes 10.91Hz;

[0200] When 42 light-emitting control signal pulses and 21 scan signal pulses are inserted during the holding phase, the refresh rate becomes 10.43Hz;

[0201] When 44 light emission control signal pulses and 22 scan signal pulses are inserted during the holding phase, the refresh rate becomes 10Hz;

[0202] When one light-emitting control signal pulse and one scan signal pulse are inserted during the holding phase, the refresh rate becomes 96Hz;

[0203] When two light-emitting control signal pulses and two scan signal pulses are inserted during the holding phase, the refresh rate becomes 80Hz;

[0204] When three light-emitting control signal pulses and three scan signal pulses are inserted during the holding phase, the refresh rate becomes 68.57Hz;

[0205] When four light-emitting control signal pulses and four scan signal pulses are inserted during the holding phase, the refresh rate becomes 60Hz.

[0206] When 5 light-emitting control signal pulses and 5 scan signal pulses are inserted during the holding phase, the refresh rate becomes 53.33Hz;

[0207] When 6 light-emitting control signal pulses and 6 scan signal pulses are inserted during the holding phase, the refresh rate becomes 48Hz;

[0208] When 7 light-emitting control signal pulses and 7 scan signal pulses are inserted during the holding phase, the refresh rate becomes 43.64Hz;

[0209] When 8 light-emitting control signal pulses and 8 scan signal pulses are inserted during the holding phase, the refresh rate becomes 40Hz;

[0210] When nine light-emitting control signal pulses and nine scan signal pulses are inserted during the holding phase, the refresh rate becomes 36.92Hz;

[0211] When 10 light control signal pulses and 10 scan signal pulses are inserted during the holding phase, the refresh rate becomes 34.29Hz;

[0212] When 11 light-emitting control signal pulses and 11 scan signal pulses are inserted during the holding phase, the refresh rate becomes 32Hz;

[0213] When 12 light emission control signal pulses and 12 scan signal pulses are inserted during the holding phase, the refresh rate becomes 30Hz;

[0214] When 13 light emission control signal pulses and 13 scan signal pulses are inserted during the holding phase, the refresh rate becomes 28.24Hz;

[0215] When 14 light-emitting control signal pulses and 14 scan signal pulses are inserted during the holding phase, the refresh rate becomes 26.67Hz;

[0216] When 15 light emission control signal pulses and 15 scan signal pulses are inserted during the holding phase, the refresh rate becomes 25.26Hz;

[0217] When 16 light-emitting control signal pulses and 16 scan signal pulses are inserted during the holding phase, the refresh rate becomes 24Hz;

[0218] When 17 light-emitting control signal pulses and 17 scan signal pulses are inserted during the holding phase, the refresh rate becomes 22.86Hz;

[0219] When 18 light-emitting control signal pulses and 18 scan signal pulses are inserted during the holding phase, the refresh rate becomes 21.82Hz;

[0220] When 19 light-emitting control signal pulses and 19 scan signal pulses are inserted during the holding phase, the refresh rate becomes 20.87Hz;

[0221] When 20 light emission control signal pulses and 20 scan signal pulses are inserted during the holding phase, the refresh rate becomes 20Hz;

[0222] When 21 light-emitting control signal pulses and 21 scan signal pulses are inserted during the holding phase, the refresh rate becomes 19.2Hz;

[0223] When 22 light emission control signal pulses and 22 scan signal pulses are inserted during the holding phase, the refresh rate becomes 18.46Hz.

[0224] In at least one embodiment of this disclosure, when the refresh rate is 120Hz and 16 downward light emission control signal pulses are set within one frame, such as Figure 9 As shown, after the refresh rate is reduced,

[0225] When one light-emitting control signal pulse and one scan signal pulse are inserted during the holding phase, the refresh frequency becomes 112.94Hz;

[0226] When two light-emitting control signal pulses and two scan signal pulses are inserted during the holding phase, the refresh frequency becomes 106.67Hz;

[0227] When three light-emitting control signal pulses and three scan signal pulses are inserted during the holding phase, the refresh rate becomes 101.05Hz;

[0228] When four light-emitting control signal pulses and four scan signal pulses are inserted during the holding phase, the refresh rate becomes 96Hz;

[0229] When 5 light-emitting control signal pulses and 5 scan signal pulses are inserted during the holding phase, the refresh rate becomes 91.43Hz;

[0230] When 6 light-emitting control signal pulses and 6 scan signal pulses are inserted during the holding phase, the refresh rate becomes 87.27Hz;

[0231] When 7 light-emitting control signal pulses and 7 scan signal pulses are inserted during the holding phase, the refresh rate becomes 83.48Hz;

[0232] When 8 light-emitting control signal pulses and 8 scan signal pulses are inserted during the holding phase, the refresh rate becomes 80Hz;

[0233] When nine light-emitting control signal pulses and nine scan signal pulses are inserted during the holding phase, the refresh rate becomes 76.8Hz;

[0234] When 10 light control signal pulses and 10 scan signal pulses are inserted during the holding phase, the refresh rate becomes 73.85Hz;

[0235] When 11 light-emitting control signal pulses and 11 scan signal pulses are inserted during the holding phase, the refresh frequency becomes 71.11Hz;

[0236] When 12 light emission control signal pulses and 12 scan signal pulses are inserted during the holding phase, the refresh rate becomes 68.57Hz;

[0237] When 13 light emission control signal pulses and 13 scan signal pulses are inserted during the holding phase, the refresh rate becomes 66.21Hz;

[0238] When 14 light-emitting control signal pulses and 14 scan signal pulses are inserted during the holding phase, the refresh rate becomes 64Hz;

[0239] When 15 light control signal pulses and 15 scan signal pulses are inserted during the holding phase, the refresh rate becomes 61.94Hz;

[0240] When 16 light-emitting control signal pulses and 16 scan signal pulses are inserted during the holding phase, the refresh rate becomes 60Hz;

[0241] When 17 light emission control signal pulses and 17 scan signal pulses are inserted during the holding phase, the refresh rate becomes 58.18Hz;

[0242] When 18 light-emitting control signal pulses and 18 scan signal pulses are inserted during the holding phase, the refresh rate becomes 56.47Hz;

[0243] When 19 light-emitting control signal pulses and 19 scan signal pulses are inserted during the holding phase, the refresh rate becomes 54.86Hz;

[0244] When 20 light emission control signal pulses and 20 scan signal pulses are inserted during the holding phase, the refresh rate becomes 53.33Hz;

[0245] When 21 light-emitting control signal pulses and 21 scan signal pulses are inserted during the holding phase, the refresh rate becomes 51.89Hz;

[0246] When 22 light emission control signal pulses and 22 scan signal pulses are inserted during the holding phase, the refresh rate becomes 50.53Hz;

[0247] When 23 light emission control signal pulses and 23 scan signal pulses are inserted during the holding phase, the refresh rate becomes 49.23Hz;

[0248] When 24 light emission control signal pulses and 24 scan signal pulses are inserted during the holding phase, the refresh rate becomes 48Hz.

[0249] The display control unit described in at least one embodiment of this disclosure is applied to a display panel, the display panel including a multi-row pixel circuit; the pixel circuit includes a light-emitting control circuit, a driving circuit, and a light-emitting element; after the refresh frequency of the display panel is reduced from a first refresh frequency to a second refresh frequency, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one mutually independent light-emitting control time period; such as Figure 10 As shown, the display control unit includes a display control circuit 80;

[0250] The display control circuit 80 is used to control the write control signal Sp so that, during the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to the corresponding data voltages under the control of the corresponding write control signal Sp.

[0251] The display control circuit is also used to control the write control signal during the holding phase, causing the multi-row pixel circuits included in the display panel to stop receiving the corresponding data voltage under the control of the corresponding write control signal Sp, and to control the light emission control signal Se during the light emission control period, so that the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and the second terminal of the driving circuit to connect with the light emission element under the control of the corresponding light emission control signal Se.

[0252] In at least one embodiment of this disclosure, the pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit, and the connection node, respectively; the compensation control circuit is electrically connected to the compensation control terminal, the connection node, and the second terminal of the driving circuit, respectively.

[0253] like Figure 10 As shown, the display control circuit 80 is further configured to control the on / off control signal Sn and the compensation control signal Sa, so that during the holding phase, the on / off control circuit, under the control of the on / off control signal Sn, controls the control terminal of the drive circuit to disconnect from the connection node, and the compensation control circuit, under the control of the compensation control signal Sa, controls the connection node to disconnect from the second terminal of the drive circuit.

[0254] In at least one embodiment of this disclosure, the pixel circuit further includes a setting circuit and a first reset circuit; the setting circuit is electrically connected to the scanning end, the setting voltage end, and the first end of the driving circuit, respectively; the first reset circuit is electrically connected to the scanning end, the first initial voltage end, and the first electrode of the light-emitting element, respectively; after the refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, the holding phase includes at least one setting time period;

[0255] like Figure 10 As shown, the display control circuit is further configured to control the scan signal Sc so that, during the set time period, the set circuit, under the control of the scan signal Sc, writes the set voltage provided by the set voltage terminal into the first terminal of the driving circuit, and the first reset circuit, under the control of the scan signal Sc, writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element.

[0256] The display device described in this disclosure includes the display control unit described above.

[0257] Optionally, the display device described in the embodiments of this disclosure may further include a display panel;

[0258] The display panel may include multiple rows of pixel circuits; the structure of the pixel circuits can be... Figure 1 The structure shown is not limited to this.

[0259] The display device provided in this disclosure can be any product or component with display function, such as OLED (organic light-emitting diode), NB (notebook computer), mobile phone, tablet computer, television, monitor, digital photo frame, navigator, etc.

[0260] In related technologies, OLED notebook displays can be based on LTPO (Low-Temperature Polycrystalline Oxide) backplane technology. LTPO backplane technology combines the high mobility of LTPS (Low-Temperature Polycrystalline Silicon) TFTs (Thin Film Transistors) with the low cutoff leakage current of Oxide TFTs, enabling lower refresh rates and thus significantly reducing display power consumption. By incorporating LTPO backplane technology into OLED notebook displays, corresponding refresh rates can be matched to different application scenarios, improving the user experience while also reducing power consumption and extending the uptime of notebook products.

[0261] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display control method applied to a display panel, the display panel including a multi-row pixel circuit; The pixel circuit includes a light-emitting control circuit, a driving circuit, and a light-emitting element; characterized in that, The display control method includes: after the refresh rate of the display panel is reduced from a first refresh rate to a second refresh rate, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one independent light emission control time period; the display control method includes: During the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to corresponding data voltages under the control of corresponding write control signals; During the holding phase, the multi-row pixel circuits included in the display panel stop receiving the corresponding data voltage under the control of the corresponding write control signal; During the light emission control period, under the control of the corresponding light emission control signal, the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light emission element. The pixel circuit further includes a first reset circuit; the first reset circuit is electrically connected to the scanning terminal, the first initial voltage terminal, and the first electrode of the light-emitting element; after the refresh frequency of the display panel decreases from the first refresh frequency to the second refresh frequency, the holding phase includes at least one set time period; the display control method further includes: During the set time period, under the control of the scan signal, the first reset circuit writes the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element; The positioning time period and the light emission control time period are independent of each other; The number of light-emitting control time periods is N times the number of setting time periods; N is a positive integer.

2. The display control method as described in claim 1, characterized in that, During the refresh phase and the hold phase, the absolute value of the difference between the frequency of the light emission control signal and the first frequency is less than a predetermined frequency difference. The first frequency is the frequency of the light emission control signal during the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

3. The display control method as described in claim 2, characterized in that, During the refresh phase and the hold phase, the frequency of the light emission control signal is equal to the first frequency.

4. The display control method as described in claim 1, characterized in that, The pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit and the connection node respectively, and the compensation control circuit is electrically connected to the compensation control terminal, the connection node and the second terminal of the driving circuit respectively. The display control method further includes: During the holding phase, the on / off control circuit, under the control of the on / off control signal provided by the on / off control terminal, controls the control terminal of the drive circuit to disconnect from the connection node, and the compensation control circuit, under the control of the compensation control signal provided by the compensation control terminal, controls the connection node to disconnect from the second terminal of the drive circuit.

5. The display control method as described in claim 1, characterized in that, The pixel circuit further includes a setting circuit; the setting circuit is electrically connected to the scanning terminal, the setting voltage terminal, and the first terminal of the driving circuit, respectively. The display control method further includes: During the set time period, under the control of the scan signal provided by the scan terminal, the set circuit writes the set voltage provided by the set voltage terminal into the first terminal of the drive circuit.

6. The display control method according to any one of claims 1 to 4, characterized in that, The absolute value of the difference between the duration of the refresh phase and the first time is less than the predetermined time difference; The first time is the duration of the display cycle of the display panel when the refresh frequency of the display panel is the first refresh frequency.

7. The display control method as described in claim 1, characterized in that, During the refresh phase and when the refresh frequency of the display panel is the first refresh frequency, the waveforms of the light emission control signal and the scanning signal are the same during the display cycle of the display panel.

8. The display control method as described in claim 6, characterized in that, The duration of the refresh phase is equal to that of the first phase.

9. The display control method as described in claim 6, characterized in that, The pixel circuit further includes a setting circuit, a first reset circuit, a data writing circuit, an energy storage circuit, a second reset circuit, an on / off control circuit, and a compensation control circuit; the refresh stage includes a first time period, a second time period, a third time period, and a first light emission stage set sequentially. The first emission phase includes a first emission time period and a first reset time period, which are independent of each other; The display control method further includes: During the first time period, the set circuit, under the control of the scan signal, writes the set voltage into the first terminal of the driving circuit; the second reset circuit, under the control of the scan signal, writes the second initial voltage into the connection node; the on / off control circuit, under the control of the on / off control signal, controls the connection between the connection node and the control terminal of the driving circuit to write the second initial voltage into the control terminal of the driving circuit; the first reset circuit, under the control of the scan signal, writes the first initial voltage into the first electrode of the light-emitting element. During the second time period, the data writing circuit, under the control of the writing control signal, writes the data voltage to the first terminal of the driving circuit. Under the control of the compensation control signal, the compensation control circuit controls the connection between the connection node and the second terminal of the driving circuit. Under the control of the on / off control signal, the on / off control circuit controls the connection between the connection node and the control terminal of the driving circuit. At the beginning of the second time period, the driving circuit, under the control of the potential of its control terminal, controls the connection between the first terminal and the second terminal of the driving circuit, and charges the energy storage circuit through the data voltage to change the potential of the control terminal of the driving circuit until the driving circuit is turned off. During the third time period, the setting circuit, under the control of the scanning signal, writes the setting voltage into the first terminal of the driving circuit, and the first reset circuit, under the control of the scanning signal, writes the first initial voltage into the first electrode of the light-emitting element. During the first light emission period, under the control of the corresponding light emission control signal, the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light emission element, and the driving circuit drives the light emission element to emit light. During the first reset time period, under the control of the scan signal provided by the scan terminal, the set circuit writes the set voltage provided by the set voltage terminal into the first terminal of the driving circuit, and under the control of the scan signal, the first reset circuit writes the first initial voltage into the first electrode of the light-emitting element.

10. A display control unit, applied to a display panel, the display panel including a multi-row pixel circuit; the pixel circuit including a light-emitting control circuit, a driving circuit, and a light-emitting element; characterized in that, After the refresh rate of the display panel is reduced from the first refresh rate to the second refresh rate, the display cycle of the display panel includes a refresh phase and a hold phase set sequentially; the hold phase includes at least one independent light emission control time period; the display control unit includes a display control circuit; The display control circuit is used to control the write control signal so that, during the refresh phase, the multi-row pixel circuits included in the display panel are sequentially connected to the corresponding data voltages under the control of the corresponding write control signal. The display control circuit is also used to control the write control signal during the holding phase, so that the multi-row pixel circuit included in the display panel stops receiving the corresponding data voltage under the control of the corresponding write control signal, and is also used to control the light emission control signal during the light emission control period, so that the light emission control circuit controls the first terminal of the driving circuit to connect with the power supply voltage terminal and controls the second terminal of the driving circuit to connect with the light emission element under the control of the corresponding light emission control signal. The pixel circuit further includes a setting circuit; the setting circuit is electrically connected to the scanning end, the setting voltage end and the first end of the driving circuit respectively; the first reset circuit is electrically connected to the scanning end, the first initial voltage end and the first electrode of the light-emitting element respectively; after the refresh frequency of the display panel is reduced from the first refresh frequency to the second refresh frequency, the holding phase includes at least one setting time period. The first reset circuit is used to write the first initial voltage provided by the first initial voltage terminal into the first electrode of the light-emitting element under the control of the scan signal during the set time period; The positioning time period and the light emission control time period are independent of each other; The number of light-emitting control time periods is N times the number of setting time periods; N is a positive integer.

11. The display control unit as claimed in claim 10, characterized in that, The pixel circuit further includes an on / off control circuit and a compensation control circuit; the on / off control circuit is electrically connected to the on / off control terminal, the control terminal of the driving circuit and the connection node respectively, and the compensation control circuit is electrically connected to the compensation control terminal, the connection node and the second terminal of the driving circuit respectively. The display control circuit is further configured to, during the holding phase, control the on / off control signal and the compensation control signal to disconnect the control terminal of the drive circuit from the connection node under the control of the on / off control signal, and to disconnect the connection node from the second terminal of the drive circuit under the control of the compensation control signal.

12. The display control unit as claimed in claim 10, characterized in that, The pixel circuit also includes a setting circuit; The display control circuit is also used to control the scan signal so that, during the set time period, the set circuit, under the control of the scan signal, writes the set voltage provided by the set voltage terminal into the first terminal of the drive circuit.

13. A display device, characterized in that, Includes the display control unit as described in any one of claims 10 to 12.

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