A lightweight asynchronous controller circuit and timing control method

Abstract

The application discloses a kind of lightweight asynchronous controller circuit and timing control method, the circuit includes double-end asynchronous controller, source controller, receiving end controller, multi-channel handshake control multiplexer and demultiplexer, double-end asynchronous controller includes first double-end asynchronous controller, second double-end asynchronous controller, third double-end asynchronous controller and fourth double-end asynchronous controller;The control method includes: the cyclic transmission of the output request signal and response signal of each module in asynchronous controller circuit is carried out.The application can reduce the power consumption of asynchronous controller circuit and reduce the area of asynchronous controller circuit chip.The application can be widely applied to asynchronous circuit control technical field as a kind of lightweight asynchronous controller circuit and timing control method.

Description

Technical Field

[0001] This invention relates to the field of asynchronous circuit control technology, and in particular to a lightweight asynchronous controller circuit and timing control method. Background Technology

[0002] With technological advancements, designing low-power computing chips has become a primary requirement for many emerging applications. However, the complex global clock tree network in synchronous circuits incurs significant power consumption. Unlike synchronous circuits, asynchronous circuits do not rely on a single global clock to trigger all registers. Data communication between modules is achieved through an asynchronous handshake protocol, reducing the power loss caused by the clock tree network. Therefore, asynchronous circuits have a potential advantage in low power consumption. Since there is no global clock, asynchronous circuits require an asynchronous controller to generate local clock pulses to drive their operation. Existing technologies for asynchronous control circuits initially established a Muller pipeline using C-cells and inverters to construct an asynchronous pipeline structure for asynchronous control. However, C-cells are custom-designed units with low compatibility with synchronous EDA tools. The presence of C units makes timing analysis more challenging than with typical synchronous circuits. Existing asynchronous control using the Mousetrap pipeline, with its asynchronous controller composed of latches and XOR gates, eliminates the need for custom circuitry. However, this structure relies on latches, which, as level-sensitive elements, are highly sensitive to timing changes, potentially leading to malfunctions in the asynchronous circuit. The Click structure, widely used as the asynchronous controller in many circuits, leverages flip-flops and standard cells for high compatibility with synchronous EDA tools. However, the Click structure exhibits significant phase skew between its local clock pulses, which negatively impacts chip power consumption and area, and limits the maximum frequency of the asynchronous circuit. Therefore, the asynchronous handshake mechanism introduces additional overhead, causing phase skew between the local clock pulses generated by the asynchronous controller, further increasing chip power consumption and area. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a lightweight asynchronous controller circuit and timing control method that can reduce the power consumption of the asynchronous controller circuit and decrease the area of ​​the asynchronous controller circuit chip.

[0004] The first technical solution adopted in this invention is: a lightweight asynchronous controller circuit, including a dual-ended asynchronous controller, a source controller, a receiver controller, a multi-channel handshake control multiplexer, and a demultiplexer. The dual-ended asynchronous controller includes a first-stage dual-ended asynchronous controller, a second-stage dual-ended asynchronous controller, a third-stage dual-ended asynchronous controller, and a fourth-stage dual-ended asynchronous controller. The output terminal of the source controller is connected to the input terminal of the first-stage dual-ended asynchronous controller. The output terminal of the first-stage dual-ended asynchronous controller is connected to the input terminal of the second-stage dual-ended asynchronous controller. The output terminal of the second-stage dual-ended asynchronous controller is connected to the input terminal of the demultiplexer. The first output terminal of the demultiplexer is connected to the input terminal of the third-stage dual-ended asynchronous controller. The second output terminal of the demultiplexer is connected to the input terminal of the fourth-stage dual-ended asynchronous controller. The output terminal of the third-stage dual-ended asynchronous controller is connected to the first input terminal of the multi-channel handshake control multiplexer. The output terminal of the fourth-stage dual-ended asynchronous controller is connected to the second input terminal of the multi-channel handshake control multiplexer. The output terminal of the multi-channel handshake control multiplexer is connected to the input terminal of the receiver controller.

[0005] The source controller is used to receive an external start signal, output a first request signal to the first-level dual-ended asynchronous controller, generate a clock pulse signal t1, and control the opening and closing of the lightweight asynchronous controller circuit.

[0006] The first-stage dual-ended asynchronous controller is used to receive the first request signal from the source controller, output a second request signal to the second-stage dual-ended asynchronous controller, feed back a first response signal to the source controller, and generate a clock pulse signal t2.

[0007] The second-level dual-ended asynchronous controller is used to receive the second request signal from the first-level dual-ended asynchronous controller, feed back the second response signal to the first-level dual-ended asynchronous controller, output the third request signal to the demultiplexer, and generate a clock pulse signal t3;

[0008] The demultiplexer is used to receive the third request signal from the second-level dual-ended asynchronous controller, and select one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first output terminal and the second output terminal of the demultiplexer, output the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feed back the third response signal to the second-level dual-ended asynchronous controller, and generate a clock pulse signal t4;

[0009] The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller are used to receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2.

[0010] The multi-channel handshake control multiplexer is used to receive the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and select one of the input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first input terminal and the second input terminal of the multi-channel handshake control multiplexer, output the sixth request signal to the receiving end controller, feed back the fifth response signal to the demultiplexer, and generate a clock pulse signal t6;

[0011] The receiver controller is used to receive the sixth request signal from the multiplexer, feed back the sixth response signal to the demultiplexer, and generate a clock pulse signal t7.

[0012] Furthermore, the source controller includes a multiplexer M1, an XOR gate U1, an XNOR gate U2, an AND gate U3, and a delay unit D1. The first and second inputs of the multiplexer M1 are connected to the input of the delay unit D1. The output of the delay unit D1 is connected to the first input of the XOR gate U1. The third and second inputs of the multiplexer M1 and the XOR gate U1 are connected to the input of the XNOR gate U2. The output of the XNOR gate U2 is connected to the input of the AND gate U3. The output of the AND gate U3 is connected to the fourth input of the multiplexer M1. Wherein:

[0013] The multiplexer M1 is used to initialize the handshake signal, transmit the first output request signal, or keep the handshake signal state unchanged.

[0014] The XOR gate U1 is used to generate clock pulses;

[0015] The XNOR gate U2 is used to determine whether the phase of the first output request signal is consistent with the phase of the first response signal;

[0016] The AND gate U3 is used to determine whether the external start signal and the output signal of the XNOR gate U2 are both high. When the external start signal and the output signal of the XNOR gate U2 are both high, the multiplexer M1 outputs the signal of the first port; otherwise, the multiplexer M1 outputs the signal of the second port, and the handshake signal state remains unchanged.

[0017] The delay unit D1 is used to adjust the clock pulse width.

[0018] Furthermore, each stage of the asynchronous controller includes a multiplexer M2, an XOR gate U4, a XNOR gate U5, and a delay unit D2. The first output of the multiplexer M2 is connected to the input of the delay unit D2, the output of the delay unit D2 is connected to the first input of the XOR gate U4, the second output of the multiplexer M2, the second input of the XOR gate U4, and the input of the XNOR gate U5 are connected, and the output of the XNOR gate U5 is connected to the input of the multiplexer M2. Wherein:

[0019] The multiplexer M2 is used to initialize the handshake signal, transmit the output request signal, or keep the handshake signal state unchanged.

[0020] The XOR gate U4 is used to generate clock pulses;

[0021] The XOR gate U5 is used to determine whether the phase of the output request signal is consistent with the phase of the input response signal. When the determination result is consistent, the multiplexer M2 outputs the signal at the first end; otherwise, the multiplexer M2 outputs the signal at the second end, and the handshake signal state remains unchanged.

[0022] The delay unit D2 is used to adjust the clock pulse width.

[0023] Furthermore, the receiver controller includes a multiplexer M3, an XOR gate U6, and a delay unit D3. The output of the multiplexer M3 is connected to the first input of the XOR gate U6, the input of the multiplexer M3 is connected to the input of the delay unit D3, and the output of the delay unit D3 is connected to the second input of the XOR gate U6, wherein:

[0024] The multiplexer M3 is used to initialize the handshake signal, transmit the sixth output request signal, or keep the handshake signal state unchanged.

[0025] The XOR gate U6 is used to generate clock pulses;

[0026] The delay unit D3 is used to adjust the clock pulse width.

[0027] Furthermore, in the source controller:

[0028] When the first output request signal is received, the multiplexer M1 initializes the handshake signal to 0 and the multiplexer M1 initializes the reset signal to 1.

[0029] The multiplexer M1 transmits the handshake signal to the AND gate U3 to request output. The output request signal is 0, and the reset signal is set to 1.

[0030] If the output signal of AND gate U3 is 1, then the output request signal is inverted and output.

[0031] If the output signal of AND gate U3 is 0, then the output request signal is maintained.

[0032] Furthermore, in the asynchronous controller:

[0033] The multiplexer M2 is initialized with a handshake signal of 0 and an initial reset signal of 1.

[0034] After initialization, the reset signal is set to 0, and the multiplexer M1 transmits the handshake signal to the XOR gate U5 to request output.

[0035] If the output signal of the XNOR gate U5 is 1, then the handshake signal is inverted and output.

[0036] If the output signal of the XOR gate U5 is 0, then the handshake signal output is maintained.

[0037] Furthermore, in the receiver controller:

[0038] When the multiplexer M3 receives an input request signal, it initializes the reset signal to 0 and outputs an acknowledgment signal to 0.

[0039] After initialization, the reset signal is set to 1, and the response signal is output.

[0040] Furthermore, in the demultiplexer:

[0041] The demultiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal;

[0042] The selected handshake channel is valid for the response signal from the next level controller, and the output signal of the selected handshake channel is toggled to trigger a local pulse. The next level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller.

[0043] For unselected handshake channels, the response signal from the next-level controller is invalid, and the output signal of the unselected handshake channel remains unchanged.

[0044] Furthermore, in the multi-channel handshake control multiplexer:

[0045] The multi-channel handshake control multiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal;

[0046] The selected handshake channel is valid for the response signal from the next level controller, and the output signal of the selected handshake channel is toggled to notify the next level controller to correctly transmit data and trigger a local pulse. The next level controller refers to the receiving end controller, and the next level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller.

[0047] For unselected handshake channels, the response signal from the next-level controller is invalid, and the output signal of the unselected handshake channel remains unchanged.

[0048] The second technical solution adopted in this invention is: a timing control method for a lightweight asynchronous controller circuit, comprising the following steps:

[0049] S1. The source controller receives an external start signal, outputs a first request signal to the first-level dual-ended asynchronous controller, generates a clock pulse signal t1, and controls the opening and closing of the lightweight asynchronous controller circuit.

[0050] S2. The first-stage dual-ended asynchronous controller receives the first request signal from the source controller, outputs a second request signal to the second-stage dual-ended asynchronous controller, feeds back a first response signal to the source controller, and generates a clock pulse signal t2.

[0051] S3. The second-level dual-ended asynchronous controller receives the second request signal from the first-level dual-ended asynchronous controller, feeds back the second response signal to the first-level dual-ended asynchronous controller, outputs the third request signal to the demultiplexer, and generates a clock pulse signal t3.

[0052] S4. The demultiplexer receives the third request signal from the second-level dual-ended asynchronous controller, and selects one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first output terminal and the second output terminal of the demultiplexer, outputs the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feeds back the third response signal to the second-level dual-ended asynchronous controller, and generates a clock pulse signal t4.

[0053] S5. The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2.

[0054] S6. The multi-channel handshake control multiplexer receives the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and selects one of its input terminals based on the first and second input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, outputs the sixth request signal to the receiving end controller, feeds back the fifth response signal to the demultiplexer, and generates a clock pulse signal t6.

[0055] S7. The receiver controller receives the sixth request signal from the multiplexer, feeds back the sixth response signal to the demultiplexer, and generates a clock pulse signal t7.

[0056] S8. Repeat steps S1-S7 above to achieve timing control of the lightweight asynchronous controller circuit.

[0057] The beneficial effects of the circuit and control method of this invention are as follows: This invention designs an asynchronous controller, a source controller, and a receiver controller to form the simplest data processing pipeline. Furthermore, by replacing the traditional register structure with a multiplexer, the multiplexer has lower power consumption, smaller area, and faster speed than the register. Moreover, the clock skew in the circuit is only the delay of the multiplexer plus the delay of the XOR gate. Compared with the traditional Click structure, it can bring smaller clock skew, further reducing the chip's power consumption and area. Finally, by introducing a multi-channel handshake controller multiplexer and demultiplexer structure, selective handshake operation is realized, triggering the register of each channel only when necessary, increasing the chip's power consumption benefits. Attached Figure Description

[0058] Figure 1 This is a structural block diagram of a lightweight asynchronous controller circuit according to the present invention;

[0059] Figure 2 This is a flowchart illustrating the timing control method for a lightweight asynchronous controller circuit according to the present invention.

[0060] Figure 3 This is a schematic diagram illustrating the relationship between the local clock pulse and the phase skew.

[0061] Figure 4 This is a simplified timing control pipeline diagram of a specific embodiment of the present invention;

[0062] Figure 5 This is a schematic diagram of the source controller in a specific embodiment of the present invention;

[0063] Figure 6 This is a schematic diagram of the asynchronous controller in a specific embodiment of the present invention;

[0064] Figure 7 This is a timing diagram of the asynchronous controller in a specific embodiment of the present invention;

[0065] Figure 8 This is a schematic diagram of the receiver controller in a specific embodiment of the present invention;

[0066] Figure 9 This is a schematic diagram of the structure of the multi-channel handshake controller multiplexer and the multiplexer in a specific embodiment of the present invention;

[0067] Figure 10 This is a flowchart illustrating a specific embodiment of the five-stage asynchronous pipeline of the present invention;

[0068] Figure 11 This is a schematic diagram illustrating the clock skew of the asynchronous controller in a specific embodiment of the present invention. Detailed Implementation

[0069] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0070] Asynchronous handshake mechanisms incur additional overhead. For a preceding asynchronous controller to generate the next clock pulse, it must receive an acknowledgment signal from the next stage. The generation of the next stage's acknowledgment signal depends on the clock pulse of its corresponding stage. In other words, there will be a certain phase skew between the local pulses generated by the preceding and following asynchronous controllers; they cannot be generated simultaneously. Figure 3 As shown, phase skew is the additional overhead introduced by the handshake mechanism. For forward pipeline propagation, phase skew tightens the setup time. For reverse pipeline propagation, phase skew relaxes the setup time, but places high demands on the hold time. The larger the phase skew, the greater the negative impact.

[0071] In addition, it should be noted that the lightweight nature of this invention is reflected in the fact that, compared with the current mainstream asynchronous controller C unit (which is a customized unit), Click (which has registers in its circuit structure) and Mousetrap (which has latches in its circuit structure), the circuit in this invention consists only of a multiplexer and simple logic gates, and has low power consumption and small area, which reflects the lightweight nature of the circuit structure.

[0072] Based on this, the present invention proposes an asynchronous controller that is simple, has low power consumption, small area, and high speed. It can minimize the phase skew problem of asynchronous circuits and precisely adjust the width of the generated clock pulse without worsening the phase skew. The proposed asynchronous controller circuit includes a basic lightweight asynchronous controller, such as... Figure 4 As shown, the proposed asynchronous controller circuit includes a source controller, a receiver controller, a multi-channel handshake controller multiplexer, and a demultiplexer, all designed based on a basic lightweight asynchronous controller. The proposed asynchronous controller circuit is applied to the asynchronous control path of asynchronous circuits to generate local clock pulses for the asynchronous pipeline. The source controller is used at the beginning of the asynchronous pipeline, the basic lightweight asynchronous controller is used in the middle section, and the receiver controller is used at the end. When the pipeline is more complex and involves multiple data streams requiring asynchronous handshake channel selection, the demultiplexer selects one of the multiple output channels to handshake with the input channel, and the multiplexer selects one of the multiple input channels to handshake with the output channel. All proposed asynchronous controllers can be implemented using standard cell libraries, supporting traditional EDA tools and design flows, and can be widely applied to the control path of asynchronous circuits.

[0073] Reference Figure 1 This invention provides a lightweight asynchronous controller circuit, including a dual-ended asynchronous controller, a source controller, a receiver controller, a multi-channel handshake control multiplexer, and a demultiplexer. The dual-ended asynchronous controller includes a first-stage dual-ended asynchronous controller, a second-stage dual-ended asynchronous controller, a third-stage dual-ended asynchronous controller, and a fourth-stage dual-ended asynchronous controller. The output of the source controller is connected to the input of the first-stage dual-ended asynchronous controller. The output of the first-stage dual-ended asynchronous controller is connected to the input of the second-stage dual-ended asynchronous controller. The output of the second-stage dual-ended asynchronous controller is connected to the input of the demultiplexer. The first output of the demultiplexer is connected to the input of the third-stage dual-ended asynchronous controller. The second output of the demultiplexer is connected to the input of the fourth-stage dual-ended asynchronous controller. The output of the third-stage dual-ended asynchronous controller is connected to the first input of the multi-channel handshake control multiplexer. The output of the fourth-stage dual-ended asynchronous controller is connected to the second input of the multi-channel handshake control multiplexer. The output of the multi-channel handshake control multiplexer is connected to the input of the receiver controller.

[0074] The source controller is used to receive an external start signal, output a first request signal to the first-level dual-ended asynchronous controller, generate a clock pulse signal t1, and control the opening and closing of the lightweight asynchronous controller circuit.

[0075] Specifically, the source controller includes a multiplexer M1, an XOR gate U1, an XNOR gate U2, an AND gate U3, and a delay unit D1. The first input terminal and the second input terminal of the multiplexer M1 are connected to the input terminal of the delay unit D1. The output terminal of the delay unit D1 is connected to the first input terminal of the XOR gate U1. The third input terminal of the multiplexer M1 and the second input terminal of the XOR gate U1 are connected to the input terminal of the XNOR gate U2. The output terminal of the XNOR gate U2 is connected to the input terminal of the AND gate U3. The output terminal of the AND gate U3 is connected to the fourth input terminal of the multiplexer M1.

[0076] Furthermore, the multiplexer M1 is used to initialize the handshake signal, transmit the first output request signal, or keep the handshake signal state unchanged; the XOR gate U1 is used to generate a clock pulse; the XNOR gate U2 is used to determine whether the phase of the first output request signal is consistent with the phase of the first response signal; the AND gate U3 is used to determine whether the output signal of the external start signal and the output signal of the XNOR gate U2 are both high. When the external start signal and the output signal of the XNOR gate U2 are both high, the multiplexer M1 outputs the signal of the first port; otherwise, the multiplexer M1 outputs the signal of the second port, and the handshake signal state remains unchanged; the delay unit D1 is used to adjust the clock pulse width.

[0077] Furthermore, when the first output request signal is received, the multiplexer M1 initializes the handshake signal to 0 and the multiplexer M1 initializes the reset signal to 1; the multiplexer M1 transmits the handshake signal to the AND gate U3 to request output, the output request signal is 0, and the reset signal is set to 1; if the output signal of the AND gate U3 is 1, the output request signal is inverted and output; if the output signal of the AND gate U3 is 0, the output request signal is kept output.

[0078] In this embodiment, the LAC is the most basic asynchronous controller structure. Based on the LAC structure, this invention proposes a source controller LAC-Source and a receiver controller LAC-Sink for constructing a complete asynchronous pipeline. The XOR gates and delay units in the source and receiver controllers function the same as in the LAC, respectively for generating clock pulses and adjusting the clock pulse width. Their reset signals also serve the same purpose as in the LAC, initializing the handshake signal to 0.

[0079] Figure 5The LAC-Source is an asynchronous controller based on LAC. A source-side controller only has output request and input acknowledge signals, not input request and output acknowledge signals, and is used for the initial part of a pipeline. The source-side controller consists of a 3-to-1 multiplexer, an XOR gate, an XNOR gate, an AND gate, and a delay unit. The start signal acts as a switch for the asynchronous controller, used to start and stop the circuit from external control. When we need to start the circuit, we only need to pull the start signal high, and the entire asynchronous circuit starts working. The condition for generating a pulse is that "the start signal is high, and the output request equals the input acknowledge," meaning that the current data has been received by the next stage. During initialization, the reset signal is 1, the multiplexer passes 0 to the output (i.e., port 0 of M1), and the output request signal is 0. After initialization, the reset signal is 0, and the output of the multiplexer is determined by the output of the AND gate. If the AND gate output is 1, it passes the inverted signal of the output request (i.e., port 1 of M1); if the AND gate output is 0, it keeps the output unchanged (i.e., port 2 of M1).

[0080] The first-stage dual-ended asynchronous controller is used to receive the first request signal from the source controller, output the second request signal to the second-stage dual-ended asynchronous controller, feed back the first response signal to the source controller, and generate a clock pulse signal t2.

[0081] The second-level dual-ended asynchronous controller is used to receive the second request signal from the first-level dual-ended asynchronous controller, feed back the second response signal to the first-level dual-ended asynchronous controller, output the third request signal to the demultiplexer, and generate a clock pulse signal t3.

[0082] Specifically, each stage of the asynchronous controller includes a multiplexer M2, an XOR gate U4, a XNOR gate U5, and a delay unit D2. The first output of the multiplexer M2 is connected to the input of the delay unit D2, the output of the delay unit D2 is connected to the first input of the XOR gate U4, the second output of the multiplexer M2, the second input of the XOR gate U4, and the input of the XNOR gate U5 are connected, and the output of the XNOR gate U5 is connected to the input of the multiplexer M2.

[0083] The multiplexer M2 is used to initialize the handshake signal, transmit the output request signal, or keep the handshake signal state unchanged; the XOR gate U4 is used to generate a clock pulse; the XNOR gate U5 is used to determine whether the phase of the output request signal is consistent with the phase of the input response signal. When the determination result is consistent, the multiplexer M2 outputs the signal at the first end; otherwise, the multiplexer M2 outputs the signal at the second end, and the handshake signal state remains unchanged; the delay unit D2 is used to adjust the clock pulse width.

[0084] Furthermore, the multiplexer M2 initializes the handshake signal to 0 and the reset signal to 1; after initialization, the reset signal is set to 0, and the multiplexer M1 transmits the handshake signal to the XNOR gate U5 to request output; if the output signal of the XNOR gate U5 is 1, the handshake signal is inverted and output; if the output signal of the XNOR gate U5 is 0, the handshake signal output is maintained.

[0085] In this embodiment, Figure 6 The diagram shows the circuit structure of the Lightweight Asynchronous Controller (LAC) proposed in this invention. This controller consists of a 3-to-1 multiplexer, an XOR gate, an XNOR gate, and a delay unit. The conditions for generating pulses can be summarized as "input request ≠ output response, output request = input response." That is, the input channel has new data sent from the previous stage (input request ≠ output response), and the current data has been received by the next stage (output request = input response). During initialization, the reset signal is 1, and the multiplexer transmits 0 to the output (i.e., port 0 of M2), and all handshake signals are 0. After initialization, the reset signal is 0, and the output of the multiplexer is determined by signal A. If signal A is 1, an input request is transmitted (i.e., port 1 of M2); if signal A is 0, the output remains unchanged (i.e., port 2 of M2).

[0086] Figure 7 The timing diagram of the asynchronous controller is shown. After initial reset, all handshake signals are low. When the previous stage sends data, the input request signal at the second input of the multiplexer is pulled high (rising edge 'a' in the diagram), while the other three handshake signals remain 0. Therefore, the output signal A of the XOR gate is 1, which propagates the value of the second input to the output, making the output acknowledge and output request signals high (rising edges 'b' and 'c' in the diagram). The clock pulse signal is generated by an XOR gate, whose two inputs are the output signal of the multiplexer and the output signal of the multiplexer after a delay unit (delay). The advantage of this design is that the pulse width can be precisely controlled by adjusting the value of the delay unit. When the output of the multiplexer changes, the two inputs of the XOR gate immediately become different, making its output 1 and pulling the clock pulse signal high (rising edge 'd' in the diagram). After a delay of one delay unit, the two inputs of the XOR gate become the same again, and the clock pulse signal is pulled low (falling edge 'e' in the diagram), thus completing one two-phase handshake process. During the handshake process, if signal A is 0, it means that the current data has not yet been received by the next level. The multiplexer will select the third input terminal, that is, keep the output value unchanged until the input acknowledgment signal sent by the next level flips.

[0087] The demultiplexer is used to receive the third request signal from the second-level dual-ended asynchronous controller, and select one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first and second output terminals of the demultiplexer, output the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feed back the third response signal to the second-level dual-ended asynchronous controller, and generate a clock pulse signal t4.

[0088] Specifically, the demultiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal; the selected handshake channel is valid for the response signal from the next-level controller and its output signal is toggled to trigger a local pulse, where the next-level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller; the unselected handshake channel is invalid for the response signal from the next-level controller, and its output signal remains unchanged.

[0089] In this embodiment, as Figure 9 As shown, the demultiplexer (LAC-DEMUX) is a one-to-many control structure that sends input requests to a specific output port based on selection signals. Taking a one-to-two demultiplexer as an example, before the input request signal arrives, selection signals sel1 and sel2 first reach the inputs of two AND gates. These selection signals essentially select between two handshake channels. The selected handshake channel, when the input response signal from the next stage is valid, will toggle its output request signal and trigger a local pulse. The output request of the unselected handshake channel remains unchanged, achieving the demultiplexer's gating and handshake effect. When gating signal sel1 is valid, {input request, output response} shakes hands with the first channel's {output request 1, input response 1}; when gating signal sel2 is valid, {input request, output response} shakes hands with the second channel's {output request 2, input response 2}.

[0090] The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller are used to receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2.

[0091] The multi-channel handshake control multiplexer is used to receive the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and select one of the input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first input terminal and the second input terminal of the multi-channel handshake control multiplexer, output the sixth request signal to the receiving end controller, feed back the fifth response signal to the demultiplexer, and generate a clock pulse signal t6;

[0092] Specifically, the multi-channel handshake control multiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal. For the selected handshake channel, the response signal from the next-level controller is valid, and the output signal of the selected handshake channel is toggled to notify the next-level controller to correctly transmit data and trigger a local pulse. The next-level controller refers to the receiving end controller, and the next-level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller. For the unselected handshake channel, the response signal from the next-level controller is invalid, and the output signal of the unselected handshake channel remains unchanged.

[0093] In this embodiment, as Figure 9 As shown, similar to the structure of a demultiplexer (LAC-DEMUX), a multiplexer (LAC-MUX) is a many-to-one control structure. It selects one input from multiple inputs based on a selection signal and sends it to the output port. Taking a two-to-one multiplexer as an example, when a handshake channel is selected by the selection signal, the output signal of that channel inverts to notify the previous stage that data can be transmitted correctly and to generate a local pulse. The output response signal of the unselected handshake channel does not invert. When the strobe signal sel1 is valid, {output request, input response} handshakes with {input request 1, output response 1} of the first channel; when the strobe signal sel2 is valid, {output request, input response} handshakes with {input request 2, output response 2} of the second channel. A clock pulse signal is generated when any set of handshake signals is valid.

[0094] The receiver controller is used to receive the sixth request signal from the multiplexer, feed back the sixth response signal to the demultiplexer, and generate a clock pulse signal t7.

[0095] Specifically, the receiver controller includes a multiplexer M3, an XOR gate U6, and a delay unit D3. The output of the multiplexer M3 is connected to the first input of the XOR gate U6, the input of the multiplexer M3 is connected to the input of the delay unit D3, and the output of the delay unit D3 is connected to the second input of the XOR gate U6.

[0096] Furthermore, the multiplexer M3 is used to initialize the handshake signal, transmit the sixth output request signal, or keep the handshake signal state unchanged; the XOR gate U6 is used to generate clock pulses; and the delay unit D3 is used to adjust the clock pulse width.

[0097] Furthermore, when the multiplexer M3 receives an input request signal, it initializes the reset signal to 0 and outputs the response signal to 0; after initialization, it sets the reset signal to 1 and outputs the response signal.

[0098] In this embodiment, Figure 8 The LAC-Sink is an asynchronous receiver controller based on LAC (Local Controller Architecture). It only has input request and output acknowledge signals, not output request and input acknowledge signals, and is used at the end of a pipeline. The receiver controller consists of a 2-to-1 multiplexer, an XOR gate, and a delay unit. The condition for generating a pulse is "input request ≠ output acknowledge," meaning the input channel has new data transmitted from the previous stage. During initialization, the reset signal is 1, the multiplexer passes 0 to the output (i.e., port 0 of M3), and the output acknowledge signal is 0. After initialization, the reset signal is 0, and the multiplexer passes the input request signal (i.e., port 1 of M3).

[0099] Reference Figure 2 A timing control method for a lightweight asynchronous controller circuit includes the following steps:

[0100] S1. The source controller receives an external start signal, outputs a first request signal to the first-level dual-ended asynchronous controller, generates a clock pulse signal t1, and controls the opening and closing of the lightweight asynchronous controller circuit.

[0101] S2. The first-stage dual-ended asynchronous controller receives the first request signal from the source controller, outputs a second request signal to the second-stage dual-ended asynchronous controller, feeds back a first response signal to the source controller, and generates a clock pulse signal t2.

[0102] S3. The second-level dual-ended asynchronous controller receives the second request signal from the first-level dual-ended asynchronous controller, feeds back the second response signal to the first-level dual-ended asynchronous controller, outputs the third request signal to the demultiplexer, and generates a clock pulse signal t3.

[0103] S4. The demultiplexer receives the third request signal from the second-level dual-ended asynchronous controller, and selects one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first output terminal and the second output terminal of the demultiplexer, outputs the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feeds back the third response signal to the second-level dual-ended asynchronous controller, and generates a clock pulse signal t4.

[0104] S5. The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2.

[0105] S6. The multi-channel handshake control multiplexer receives the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and selects one of its input terminals based on the first and second input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, outputs the sixth request signal to the receiving end controller, feeds back the fifth response signal to the demultiplexer, and generates a clock pulse signal t6.

[0106] S7. The receiver controller receives the sixth request signal from the multiplexer, feeds back the sixth response signal to the demultiplexer, and generates a clock pulse signal t7.

[0107] S8. Repeat steps S1-S7 above to achieve timing control of the lightweight asynchronous controller circuit.

[0108] Furthermore, based on the asynchronous control circuit of this invention, a five-stage asynchronous pipeline embodiment is described. The asynchronous controller (LAC), the source end (LAC-Source), and the receiving end (LAC-Sink) are the three most basic structures for building a complete asynchronous pipeline. Figure 10This diagram illustrates a classic five-stage asynchronous pipeline built using these three asynchronous controllers. The pipeline begins with the source (LAC-Source) and ends with the sink (LAC-Sink), with four asynchronous controllers (LACs) connected in series. Clock pulse 1 generated by the source serves as the program counter trigger signal. Clock pulses 2-5 generated by the four LACs trigger the registers between the fetch, decode, execute, memory access, and write-back stages, respectively. Clock pulse 6 generated by the sink triggers the write-back operation. The diagram illustrates a multi-data-stream asynchronous pipeline constructed using these five controller structures: the asynchronous controller (LAC), the source (LAC-Source), the sink (LAC-Sink), the demultiplexer (LAC-DEMUX), and the multiplexer (LAC-MUX). The position and number of asynchronous controllers can be adjusted based on the actual data flow. Furthermore, the demultiplexer (LAC-DEMUX) and the multiplexer (LAC-MUX) can be expanded to have multiple pairs of outputs and input handshake signals, allowing for flexible design based on the asynchronous circuit architecture.

[0109] It should be noted that the local clock pulse signal of the asynchronous circuit replaces the global clock signal in the synchronous circuit. Each clock pulse signal is responsible for controlling the triggering state of each stage of the pipeline. The handshake controllers send "request" and "response" signals to transmit the prepared data.

[0110] In summary, the innovative technical points of the present invention include:

[0111] 1) The proposed asynchronous controller is simple. Compared with the most mainstream asynchronous controller Click, this invention uses a multiplexer instead of a register to maintain the phase state. The multiplexer has lower power consumption, smaller area and faster speed than the register, making the asynchronous controller proposed in this invention more advantageous in terms of power consumption, area and speed.

[0112] 2) such as Figure 11 As shown, the present invention proposes that the clock skew of the asynchronous controller is only the delay of the multiplexer plus the delay of the XOR gate. The extremely small clock skew can relax the setup time requirement for the forward pipeline, allowing the chip's maximum frequency to be further increased; for the reverse pipeline, it can relax the hold time, reducing the large amount of buffer inserted by EDA tools to correct hold time violations, thereby bringing benefits in both chip power consumption and area.

[0113] 3) An asynchronous controller is proposed that can meet the asynchronous local pulse width requirements of some macrocells. The clock pulse width generated by the controller is the delay of the inserted delay, which is independent of other logic gates. The clock pulse width can be flexibly adjusted by simply adjusting the delay size, while ensuring that clock skew is not affected.

[0114] 4) The proposed multi-channel handshake controller multiplexer and demultiplexer structure based on the proposed lightweight asynchronous controller is a manifestation of the event-driven characteristics of asynchronous circuits. It realizes selective handshake operation and triggers the register of each channel only when necessary, which can achieve further power consumption benefits compared with synchronous circuits.

[0115] The content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0116] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A lightweight asynchronous controller circuit, characterized in that, The system includes a dual-ended asynchronous controller, a source controller, a receiver controller, a multi-channel handshake control multiplexer, and a demultiplexer. The dual-ended asynchronous controller comprises a first-level dual-ended asynchronous controller, a second-level dual-ended asynchronous controller, a third-level dual-ended asynchronous controller, and a fourth-level dual-ended asynchronous controller. The output of the source controller is connected to the input of the first-level dual-ended asynchronous controller. The output of the first-level dual-ended asynchronous controller is connected to the input of the second-level dual-ended asynchronous controller. The output of the second-level dual-ended asynchronous controller is connected to the input of the demultiplexer. The first output of the demultiplexer is connected to the input of the third-level dual-ended asynchronous controller. The second output of the demultiplexer is connected to the input of the fourth-level dual-ended asynchronous controller. The output of the third-level dual-ended asynchronous controller is connected to the first input of the multi-channel handshake control multiplexer. The output of the fourth-level dual-ended asynchronous controller is connected to the second input of the multi-channel handshake control multiplexer. The output of the multi-channel handshake control multiplexer is connected to the input of the receiver controller. Wherein: The source controller is used to receive an external start signal, output a first request signal to the first-level dual-ended asynchronous controller, generate a clock pulse signal t1, and control the opening and closing of the lightweight asynchronous controller circuit. The first-stage dual-ended asynchronous controller is used to receive the first request signal from the source controller, output a second request signal to the second-stage dual-ended asynchronous controller, feed back a first response signal to the source controller, and generate a clock pulse signal t2. The second-level dual-ended asynchronous controller is used to receive the second request signal from the first-level dual-ended asynchronous controller, feed back the second response signal to the first-level dual-ended asynchronous controller, output the third request signal to the demultiplexer, and generate a clock pulse signal t3; The demultiplexer is used to receive the third request signal from the second-level dual-ended asynchronous controller, and select one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first output terminal and the second output terminal of the demultiplexer, output the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feed back the third response signal to the second-level dual-ended asynchronous controller, and generate a clock pulse signal t4; The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller are used to receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2. The multi-channel handshake control multiplexer is used to receive the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and select one of the input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first input terminal and the second input terminal of the multi-channel handshake control multiplexer, output the sixth request signal to the receiving end controller, feed back the fifth response signal to the demultiplexer, and generate a clock pulse signal t6; The receiver controller is used to receive the sixth request signal from the multiplexer, feed back the sixth response signal to the demultiplexer, and generate a clock pulse signal t7.

2. The lightweight asynchronous controller circuit according to claim 1, characterized in that, The source controller includes a multiplexer M1, an XOR gate U1, an XNOR gate U2, an AND gate U3, and a delay unit D1. The first and second inputs of the multiplexer M1 are connected to the input of the delay unit D1. The output of the delay unit D1 is connected to the first input of the XOR gate U1. The third and second inputs of the multiplexer M1 and the XOR gate U1 are connected to the input of the XNOR gate U2. The output of the XNOR gate U2 is connected to the input of the AND gate U3. The output of the AND gate U3 is connected to the fourth input of the multiplexer M1. Wherein: The multiplexer M1 is used to initialize the handshake signal, transmit the first request signal, or keep the handshake signal state unchanged. The XOR gate U1 is used to generate clock pulses; The XNOR gate U2 is used to determine whether the phase of the first request signal is consistent with the phase of the first response signal; The AND gate U3 is used to determine whether the external start signal and the output signal of the XNOR gate U2 are both high. When the external start signal and the output signal of the XNOR gate U2 are both high, the multiplexer M1 outputs the signal of the first port; otherwise, the multiplexer M1 outputs the signal of the second port, and the handshake signal state remains unchanged. The delay unit D1 is used to adjust the clock pulse width.

3. The lightweight asynchronous controller circuit according to claim 1, characterized in that, Each stage of the asynchronous controller includes a multiplexer M2, an XOR gate U4, a XNOR gate U5, and a delay unit D2. The first output of the multiplexer M2 is connected to the input of the delay unit D2, the output of the delay unit D2 is connected to the first input of the XOR gate U4, the second output of the multiplexer M2, the second input of the XOR gate U4, and the input of the XNOR gate U5 are connected, and the output of the XNOR gate U5 is connected to the input of the multiplexer M2. Wherein: The multiplexer M2 is used to initialize the handshake signal, transmit the output request signal, or keep the handshake signal state unchanged; wherein, the output request signal is the second request signal, the third request signal, or the fifth request signal; The XOR gate U4 is used to generate clock pulses; The XOR gate U5 is used to determine whether the phase of the output request signal is consistent with the phase of the input response signal. When the determination result is consistent, the multiplexer M2 outputs the signal at the first end; otherwise, the multiplexer M2 outputs the signal at the second end, and the handshake signal state remains unchanged. The delay unit D2 is used to adjust the clock pulse width.

4. The lightweight asynchronous controller circuit according to claim 1, characterized in that, The receiver controller includes a multiplexer M3, an XOR gate U6, and a delay unit D3. The output of the multiplexer M3 is connected to the first input of the XOR gate U6, the input of the multiplexer M3 is connected to the input of the delay unit D3, and the output of the delay unit D3 is connected to the second input of the XOR gate U6. The multiplexer M3 is used to initialize the handshake signal, transmit the sixth request signal, or keep the handshake signal state unchanged. The XOR gate U6 is used to generate clock pulses; The delay unit D3 is used to adjust the clock pulse width.

5. The lightweight asynchronous controller circuit according to claim 2, characterized in that, In the source controller: When the first request signal is received, the multiplexer M1 initializes the handshake signal to 0 and the multiplexer M1 initializes the reset signal to 1. The multiplexer M1 transmits the handshake signal to the AND gate U3 to request output, and the first request signal is 0, while the reset signal is set to 1. If the output signal of AND gate U3 is 1, then the first request signal is inverted and output. If the output signal of AND gate U3 is 0, then the first request signal output is maintained.

6. The lightweight asynchronous controller circuit according to claim 3, characterized in that, In the asynchronous controller: The multiplexer M2 is initialized with a handshake signal of 0 and an initial reset signal of 1. After initialization, the reset signal is set to 0, and the multiplexer M1 transmits the handshake signal to the XOR gate U5 to request output. If the output signal of the XNOR gate U5 is 1, then the handshake signal is inverted and output. If the output signal of the XOR gate U5 is 0, then the handshake signal output is maintained.

7. The lightweight asynchronous controller circuit according to claim 4, characterized in that, In the receiver controller: When the multiplexer M3 receives the sixth request signal, the initialization reset signal is 0 and the output response signal is 0; After initialization, the reset signal is set to 1, and the response signal is output.

8. The lightweight asynchronous controller circuit according to claim 1, characterized in that, In the demultiplexer: The demultiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal; The selected handshake channel is valid for the response signal from the next level controller, and the output signal of the selected handshake channel is toggled to trigger a local pulse. The next level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller. For unselected handshake channels, the response signal from the next-level controller is invalid, and the output signal of the unselected handshake channel remains unchanged.

9. The lightweight asynchronous controller circuit according to claim 1, characterized in that, In the multi-channel handshake control multiplexer: The multi-channel handshake control multiplexer selects the corresponding handshake channel for handshake using a first selection signal and a second selection signal; The selected handshake channel is valid for the response signal from the next level controller, and the output signal of the selected handshake channel is toggled to notify the next level controller to correctly transmit data and trigger a local pulse. The next level controller refers to the receiving end controller, and the next level controller refers to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller. For unselected handshake channels, the response signal from the next-level controller is invalid, and the output signal of the unselected handshake channel remains unchanged.

10. A timing control method applied to the lightweight asynchronous controller circuit according to any one of claims 1-9, characterized in that, Includes the following steps: S1. The source controller receives an external start signal, outputs a first request signal to the first-level dual-ended asynchronous controller, generates a clock pulse signal t1, and controls the opening and closing of the lightweight asynchronous controller circuit. S2. The first-stage dual-ended asynchronous controller receives the first request signal from the source controller, outputs a second request signal to the second-stage dual-ended asynchronous controller, feeds back a first response signal to the source controller, and generates a clock pulse signal t2. S3. The second-level dual-ended asynchronous controller receives the second request signal from the first-level dual-ended asynchronous controller, feeds back the second response signal to the first-level dual-ended asynchronous controller, outputs the third request signal to the demultiplexer, and generates a clock pulse signal t3. S4. The demultiplexer receives the third request signal from the second-level dual-ended asynchronous controller, and selects one of the output terminals of the demultiplexer to handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller based on the first output terminal and the second output terminal of the demultiplexer, outputs the fourth request signal to the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, feeds back the third response signal to the second-level dual-ended asynchronous controller, and generates a clock pulse signal t4. S5. The third-level dual-ended asynchronous controller and the fourth-level dual-ended asynchronous controller receive the fourth request signal from the demultiplexer, feed back the fourth response signal to the demultiplexer, and output the fifth request signal to the multi-channel handshake control multiplexer. The third-level dual-ended asynchronous controller generates a clock pulse signal t5_1, and the fourth-level dual-ended asynchronous controller generates a clock pulse signal t5_2. S6. The multi-channel handshake control multiplexer receives the fifth request signal from the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, and selects one of its input terminals based on the first and second input terminals of the multi-channel handshake control multiplexer to perform a handshake with the third-level dual-ended asynchronous controller or the fourth-level dual-ended asynchronous controller, outputs the sixth request signal to the receiving end controller, feeds back the fifth response signal to the demultiplexer, and generates a clock pulse signal t6. S7. The receiver controller receives the sixth request signal from the multiplexer, feeds back the sixth response signal to the demultiplexer, and generates a clock pulse signal t7. S8. Repeat steps S1-S7 above to achieve timing control of the lightweight asynchronous controller circuit.

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