A cache access method, a cache control module, and related devices

Abstract

The present invention discloses a cache access method, a cache control module and related devices. The cache includes n first memories, and the n first memories include n cache groups. Each cache group includes n cache units, and the n cache units are respectively located in the n first memories. The cache access method includes: receiving a first cache access request for writing first data into a first cache group, where the width of the first data is equal to the width of data of m×n memory blocks; in response to the first cache access request, dividing the first data into n first sub-data with different byte segments, and writing the n first sub-data into the n cache units of the first cache group respectively, where different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories, so as to improve the data processing rate of the cache.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and particularly to a cache access method, a cache control module, and related devices. Background Art

[0002] Since the performance improvement speed of the Central Processing Unit (CPU) is much faster than that of the Memory, the data read / write speed of the Memory far lags behind the operation speed of the processor. Although this problem can be solved by data caching, where data in the Memory is temporarily stored in the cache (Cache), which is a high-speed buffer memory inside the processor, and the processor accesses the cache to obtain data in the Memory, the current data processing rate of the cache needs to be further improved. Summary of the Invention

[0003] The present invention discloses a cache access method, a cache control module, and related devices to improve the data processing rate of the cache.

[0004] In a first aspect, the present invention discloses a cache access method applied to a processor. The processor includes a cache control module and a cache. The cache includes n first memories, the n first memories include n cache groups, each cache group includes n cache units, the n cache units are respectively located in the n first memories, and each cache unit is used to store data of m memory blocks. n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1. The cache access method includes the following operations performed by the cache control module: receiving a first cache access request for writing first data into a first cache group, where the first cache group is any one of the n cache groups, and the width of the first data is equal to the width of data of m×n memory blocks; in response to the first cache access request, dividing the first data into n first sub-data with different byte segments, the width of each first sub-data being equal to the width of data of m memory blocks, and writing the n first sub-data into the n cache units of the first cache group respectively, where different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

[0005] In some optional examples, the addresses of the n cache units of the first cache group are different from each other; or, the addresses of the n cache units of the first cache group are the same.

[0006] In some alternative examples, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively. Assuming that the address of the cache unit of the first cache group in any first memory is the ith address, where i is any integer between 1 and n. When the addresses of the n cache units of the first cache group are different from each other, if i - 1 > 0, then the address of the cache unit of the first cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit of the first cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit of the first cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit of the first cache group in the previous first memory is the (i + 1)th address.

[0007] In some alternative examples, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively, and the n cache groups are the 1st cache group to the nth cache group respectively. Assuming that the first cache group is the jth cache group, and the address of the cache unit of the jth cache group in any first memory is the ith address, where both j and i are any integers between 1 and n. When the addresses of the n cache units of the first cache group are different from each other, if j is an even number and i - 1 > 0, then the address of the cache unit of the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit of the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit of the jth cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit of the jth cache group in the previous first memory is the (i + 1)th address; if j is an odd number and i + 1 > n, then the address of the cache unit of the jth cache group in the next first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit of the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache unit of the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit of the jth cache group in the previous first memory is the nth address.

[0008] In some alternative examples, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively, and the n cache groups are the 1st cache group to the nth cache group respectively. Assuming that the first cache group is the jth cache group, then when the addresses of the n cache units of the first cache group are the same, the address of the cache unit of the jth cache group in any first memory is the jth address, where j is any integer between 1 and n.

[0009] In some alternative examples, the first cache access request carries a write address and an identifier of the first cache group. The step of writing the n first sub-data into the n cache units of the first cache group respectively includes: selecting the first cache group from the n cache groups according to the identifier of the first cache group; performing address encoding on the n cache units of the first cache group according to the write address, and making the addresses of the n cache units of the first cache group different from or the same as each other; and writing the n first sub-data into the n cache units of the first cache group respectively according to the addresses of the n cache units of the first cache group obtained by encoding.

[0010] In some alternative examples, it further includes: receiving a second cache access request for reading second data of a second cache group, where the second cache group is any one of the n cache groups, and the width of the second data is equal to the width of data of m memory blocks; in response to the second cache access request, reading data of n cache units corresponding to the same byte segment as the read address from the n first memories respectively, where the data of the n cache units with the same byte segment are data of the n cache groups respectively, and selecting the data of the cache units of the second cache group from the data of the n cache units with the same byte segment to obtain the second data.

[0011] In some alternative examples, the second cache access request carries an identifier of the second cache group. The step of selecting the data of the cache units of the second cache group from the data of the n cache units with the same byte segment includes: selecting the data of the cache units of the second cache group from the data of the n cache units with the same byte segment according to the identifier of the second cache group to obtain the second data.

[0012] In some alternative examples, the addresses of the n cache units with the same data byte segment are the same, or the addresses of the n cache units with the same data byte segment are different from each other.

[0013] Second aspect, the present invention discloses a cache control module, which is applied to a processor. The processor includes a cache, and the cache includes n first memories. The n first memories include n cache groups. Each cache group includes n cache units, and the n cache units are respectively located in the n first memories. Each cache unit is used to store data of m memory blocks. n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1. The cache control module includes a first address encoding unit; the first address encoding unit is configured to receive a first cache access request for writing first data into a first cache group, where the first cache group is any one of the n cache groups, and the width of the first data is equal to the width of data of m×n memory blocks. In response to the first cache access request, the first data is divided into n first sub-data with different byte segments, and the width of each first sub-data is equal to the width of data of m memory blocks. The n first sub-data are respectively written into the n cache units of the first cache group. Among them, different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

[0014] In some optional examples, the addresses of the n cache units of the first cache group are different from each other; or, the addresses of the n cache units of the first cache group are the same.

[0015] In some optional examples, the addresses of the n cache units of the first memory are respectively the 1st address to the nth address. Assume that the address of the cache unit of the first cache group in any one of the first memories is the ith address, where i is any integer between 1 and n. When the addresses of the n cache units of the first cache group are different from each other, if i - 1 > 0, the address of the cache unit of the first cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, the address of the cache unit of the first cache group in the next first memory is the nth address; if i + 1 > n, the address of the cache unit of the first cache group in the previous first memory is the 1st address; if i + 1 ≤ n, the address of the cache unit of the first cache group in the previous first memory is the (i + 1)th address.

[0016] In some alternative examples, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively, and the n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group, and the address of the cache unit in any first memory of the jth cache group is the ith address. Both j and i are any integers between 1 and n. When the addresses of the n cache units in the first cache group are different from each other, if j is an even number and if i - 1 > 0, then the address of the cache unit in the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit in the jth cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the previous first memory is the (i + 1)th address. If j is an odd number and if i + 1 > n, then the address of the cache unit in the jth cache group in the next first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache unit in the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the previous first memory is the nth address.

[0017] In some alternative examples, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively, and the n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group. When the addresses of the n cache units in the first cache group are the same, the address of the cache unit in any first memory of the jth cache group is the jth address, where j is any integer between 1 and n.

[0018] In some alternative examples, the first cache access request carries a write address and an identifier of the first cache group. The first address encoding unit is configured to select the first cache group from the n cache groups according to the identifier of the first cache group, perform address encoding on the n cache units of the first cache group according to the write address, and make the addresses of the n cache units of the first cache group different from each other or the same. According to the addresses of the n cache units of the first cache group obtained by encoding, write the n first sub - data into the n cache units of the first cache group respectively.

[0019] In some alternative examples, the cache control module further includes a second address encoding unit and a multiplexing unit; the second address encoding unit is configured to receive a second cache access request for reading second data of a second cache group, where the second cache group is any one of the n cache groups, and the width of the second data is equal to the width of data of m memory blocks. In response to the second cache access request, according to the read address carried in the second cache access request, data of n cache units corresponding to the same byte segment as the read address are respectively read from the n first memories, and the data of the n cache units with the same byte segment are respectively the data of the n cache groups. The multiplexing unit is controlled to select the data of the cache unit of the second cache group from the data of the n cache units with the same byte segment to obtain the second data.

[0020] In some alternative examples, the second cache access request carries an identifier of the second cache group, and the second address encoding unit is configured to control the multiplexing unit to select the data of the cache unit of the second cache group from the data of the n cache units with the same byte segment according to the identifier of the second cache group to obtain the second data.

[0021] In some alternative examples, the addresses of the n cache units with the same data byte segment are the same, or the addresses of the n cache units with the same data byte segment are different from each other.

[0022] In a third aspect, the present invention discloses a processor, including a cache and the cache control module as described in any one of the above; alternatively, the processor includes a cache control module and a cache, and the cache control module is configured to execute the cache access method as described in any one of the above.

[0023] In a fourth aspect, the present invention discloses an electronic device, including the processor as described above.

[0024] In a fifth aspect, the present invention discloses a computer-readable storage medium, on which instructions for executing the cache access method as described in any one of the above are stored.

[0025] The cache access method, cache control module, and related devices disclosed by the present invention. The processor includes a cache control module and a cache. The cache includes n first memories. The n first memories include n cache groups. Each cache group includes n cache units. The n cache units are respectively located in the n first memories, and each cache unit is used to store data of m memory blocks. The cache control module can receive a first cache access request. The first cache access request is used to write first data into a first cache group. The first cache group is any one of the n cache groups. The width of the first data is equal to the width of data of m×n memory blocks. In response to the first cache access request, the first data is divided into n first sub-data with different byte segments. The width of each first sub-data is equal to the width of data of m memory blocks. The n first sub-data are respectively written into the n cache units of the first cache group, so that data of m×n memory blocks can be written into the cache within one clock cycle, thereby improving the data writing rate of the cache, that is, the data processing rate. Moreover, because different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories, data of m×n memory blocks with the same byte segment can be read out within one clock cycle, thereby improving the data reading rate of the cache, and further improving the data processing rate of the cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the drawings required for use in the embodiments of the present invention or the background art will be described below.

[0027] Figure 1 It is a schematic structural diagram of a processor disclosed by an embodiment of the present invention.

[0028] Figure 2 It is a schematic structural diagram of a cache.

[0029] Figure 3 It is a schematic structural diagram of a cache disclosed by an embodiment of the present invention.

[0030] Figure 4 It is a schematic flow diagram of a cache access method disclosed by an embodiment of the present invention.

[0031] Figure 5 It is a schematic structural diagram of a cache disclosed by an embodiment of the present invention.

[0032] Figure 6 It is a schematic structural diagram of another cache disclosed by an embodiment of the present invention.

[0033] Figure 7 It is a schematic structural diagram of another cache disclosed by an embodiment of the present invention.

[0034] Figure 8 Another structural schematic diagram of a cache disclosed in an embodiment of the present invention.

[0035] Figure 9 Another structural schematic diagram of a cache disclosed in an embodiment of the present invention.

[0036] Figure 10 A flowchart of another cache access method disclosed in an embodiment of the present invention.

[0037] Figure 11 Another structural schematic diagram of a cache disclosed in an embodiment of the present invention.

[0038] Figure 12 A structural schematic diagram of a cache and a cache control module disclosed in an embodiment of the present invention.

[0039] Figure 13 Another structural schematic diagram of a cache and a cache control module disclosed in an embodiment of the present invention. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0041] As Figure 1 shown, the processor includes one or more processor cores 10, a cache control module 11, and two or more levels of caches. Among them, Figure 1 only the example where the processor includes a first-level cache L1, a second-level cache L2, and a third-level cache L3 is used for illustration. The operating speeds of the first-level cache L1, the second-level cache L2, and the third-level cache L3 decrease in sequence, but the capacities increase in sequence. The first-level cache L1 is used to cache instructions or data that are frequently hit by the processor core 10. The second-level cache L2 is used to cache data exclusive to the processor core 10. The data stored in the third-level cache L3 is shared by each processor core 10. It can be understood that the cache in the embodiment of the present invention can be any one of the first-level cache L1, the second-level cache L2, and the third-level cache L3, which will not be elaborated herein.

[0042] Among them, the cache control module 11 is used to perform operations such as writing the data at the corresponding address of the memory 12 into the cache or reading the data at the corresponding address of the memory 12 temporarily stored in the cache according to the request of the processor core 10. In the specific implementation process, each level of cache can have its own control logic, that is Figure 1The cache control module 11 shown can be deployed separately in each cache at different levels, or can be the overall control logic of a cache architecture. Moreover, the cache control module 11 can be integrated as an independent component inside the processor, or integrated in the processor core 10, with the processor core 10 implementing the functions of the cache control module 11.

[0043] As Figure 2 shown, each cache includes n cache groups, which can be Way1 to Wayn respectively. Each cache group includes n data memories and n address memories. The n data memories of the n cache groups, that is, n×n data memories, are S11 to Snn respectively, and the n address memories of the n cache groups, that is, n×n address memories, are SR11 to SRnn respectively, where n is an integer greater than 2. Among them, both the data memory and the address memory are SRAM.

[0044] Among them, the data memory is used to store data, and the address memory is used to store the common address (tag) of the data. Moreover, the data stored in one data memory of each row in each cache group is the data of a cache line, and the address stored in one address memory of each row in each cache group is the common address of a cache line. The data size of a cache line is equal to the data size of a memory bank of the memory 12, and the data of a memory bank is the minimum unit of data of the memory 12. That is to say, Figure 2 in the cache shown, n×n memories are used to store the data of n×n memory blocks.

[0045] As Figure 2 shown, after receiving the first cache access request from the processor core 10, the cache control module 11 indexes multiple cache lines according to the index address in the write address carried in the first cache access request, such as indexing out multiple cache lines Cache line 12 to Cache line n2, and then selects one cache line such as Cache line 12 from the multiple cache lines such as Cache line 12 to Cache line n2 according to the common address (tag) in the write address, and then writes the data of 1 memory block into the selected cache line such as Cache line 12. It should be noted that each memory can only write or read data once within one clock cycle.

[0046] As Figure 2As shown, after the cache control module 11 receives the second cache access request from the processor core 10, it indexes multiple cache lines based on the index address (index) in the read address carried in the second cache access request. For example, it indexes multiple cache lines Cache line 12 to Cache line n2, and then selects one cache line such as Cache line 12 from the multiple cache lines such as Cache line 12 to Cache line n2 according to the common address (tag) in the read address. Then, it obtains the data of the required bytes from the data of this cache line such as Cache line 12 according to the offset address (offset) in the read address.

[0047] Although Figure 2 the miss rate of the set-associative cache shown is relatively low, however, the inventors have found through research that this cache uses a relatively large number of memories, resulting in a larger area and higher cost of the processor. Also, only one memory block of data can be written within each clock cycle, resulting in a relatively low data processing efficiency of the cache.

[0048] Based on this, the present invention discloses a cache structure. The cache includes n first memories, and the n first memories include n cache groups. Each cache group includes n cache units, and the n cache units are respectively located in n memories. And each cache unit is used to store at least one memory block of data. Thus, n memories can be used to store n×m×n memory blocks of data, thereby reducing the number of memories in the cache and decreasing the area and cost of the processor. Also, by storing the data of m×n memory blocks into the n cache units of the same cache group respectively, m×n memory blocks of data can be written into the cache within one clock cycle, thereby improving the data writing rate of the cache, that is, the data processing rate. And because different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories, so, m×n memory blocks of data with the same byte segment can be read out within one clock cycle, thereby improving the data reading rate of the cache, and further improving the data processing rate of the cache.

[0049] As an optional implementation of the disclosed content of the present invention, an embodiment of the present invention discloses a processor. Refer to Figure 1 , this processor includes a cache control module and a cache. Of course, this processor also includes one or more processor cores, which will not be elaborated here.

[0050] As Figure 3As shown, the cache disclosed in the embodiments of the present invention includes n first memories, which are S1 to Sn respectively. And, the first memory is a data memory, or rather, the first memory is used to store data. Wherein, n is an integer greater than or equal to 2. Among them, the first memory can be SRAM.

[0051] Among them, these n first memories include n cache groups, which are way1 to wayn respectively. Each cache group includes n cache units, and these n cache units are located in n memories respectively. For example, way1-S1 in S1, way1-S2 in S2, way1-S3 in S3... way1-Sn in Sn are the n cache units of the cache group way1, and way2-S1 in S1, way2-S2 in S2, way2-S3 in S3... way2-Sn in Sn are the n cache units of the cache group way2.

[0052] Or rather, each first memory includes n cache units, and these n cache units belong to n cache groups respectively. For example, these n cache units of way1-S1, way2-S1, way3-S1... way3-S1 in S1 belong to the n cache groups of way1 to wayn respectively, and these n cache units of way1-S2, way2-S2, way3-S2... way3-S2 in S2 also belong to the n cache groups of way1 to wayn respectively.

[0053] And, each cache unit is used to store data of m memory blocks, where m is an integer greater than or equal to 1. That is to say, each first memory can store data of m×n memory blocks, and n first memories can store data of n×m×n memory blocks. Compared with Figure 2 the cache that uses n×n memories to store data of n×n memory blocks as shown, the cache disclosed in the embodiments of the present invention can store data of n×n memory blocks only by using n memories, so that the cache can store the same capacity or even larger capacity of data with fewer memories, and further, the area and cost of the processor can be reduced.

[0054] In some embodiments of the present invention, the cache may further include n×n second memories. The second memory is an address memory, or rather, the second memory is used to store the addresses of data. The second memory can also be SRAM. Of course, the present invention is not limited thereto. In some other embodiments, the cache may further include n second memories, and these n second memories are used to store the common addresses of data of n×n memory blocks, which will not be elaborated here.

[0055] On this basis, an embodiment of the present invention further discloses a cache access method, which is applied to a processor. The processor includes a cache control module and a cache, and the cache is the above-mentioned cache disclosed in the embodiment of the present invention, such as Figure 4 shown. The cache access method includes the following operations executed by the cache control module:

[0056] S101: Receive a first cache access request, where the first cache access request is used to write first data into a first cache group.

[0057] Among them, the first cache group is any one of the n cache groups of the n first memories disclosed in the embodiment of the present invention. Of course, the first cache group needs to be any one of the n idle cache groups or the cache groups that do not store data. The width of the first data is equal to the width of the data of m×n memory blocks. In some embodiments of the present invention, the width of the first data may also be equal to the width of the data of n memory blocks. In other embodiments, the width of the first data may also be equal to the width of the data of 2×n memory blocks, 3×n memory blocks, 4×n memory blocks, etc., which will not be elaborated here.

[0058] S102: In response to the first cache access request, divide the first data into n first sub-data with different byte segments, and write the n first sub-data into the n cache units of the first cache group respectively. Among them, different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

[0059] After the cache control module receives the first cache access request sent by the processor or the processor core, in response to the first cache access request, the first data is divided into n first sub-data with different byte segments, such as Figure 5 shown. These n first sub-data are data1 to datan respectively. Then, the cache control module writes the n first sub-data of data1 to datan into the n cache units of the first cache group of the n first memories of S1 to Sn respectively. Taking the first cache group as the way3 cache group as an example, the n first sub-data of data1 to datan can be written into the n cache units of way3-S1, way3-S2, way3-S3... way3-Sn respectively.

[0060] Among them, if the width of the first data is equal to the width of the data of n memory blocks, then the width of each first sub-data is equal to the width of the data of 1 memory block; if the width of the first data is equal to the width of the data of 2×n memory blocks, then the width of each first sub-data is equal to the width of the data of 2 memory blocks, and so on. It can be known that the width of each first sub-data is equal to the width of the data of m memory blocks.

[0061] Since the n cache units of the first cache group are respectively located in n first memories, therefore, writing the n first sub-datas into the n cache units of the first cache group respectively means writing the n first sub-datas into the n first memories respectively within one clock cycle. Also, since the width of each first sub-data is equal to the width of the data of m memory blocks, therefore, writing the n first sub-datas into the n cache units of the first cache group respectively means writing the data of m×n memory blocks into the n first memories (caches) within one clock cycle, thereby improving the data writing rate of the cache, that is, the data processing rate.

[0062] Since different first datas are stored in the cache units of different cache groups, and the first sub-datas of the same byte segment of different first datas are stored in the cache units of different first memories, therefore, the data of n cache units with the same byte segment can be read out within one clock cycle. Also, since the data of each cache unit is the data of m memory blocks, therefore, the data of m×n memory blocks can be read out within one clock cycle, thereby improving the data reading rate of the cache, and further improving the data processing rate of the cache.

[0063] In some embodiments of the present invention, the addresses of the n cache units of the first cache group are different from each other, or rather, the addresses of the n cache units in any cache group of the n first memories are different from each other. For example, the addresses of the n cache units such as way3-S1, way3-S2, way3-S3... way3-Sn are different from each other. In some embodiments, the addresses of the n cache units of any first memory are respectively the same as the addresses of the n cache units of another first memory. For example, the addresses of the n cache units of the first memory S1 are respectively the same as the addresses of the n cache units of the first memory S2, and the addresses of the n cache units of the first memory S2 are respectively the same as the addresses of the n cache units of the first memory S3.

[0064] In some embodiments, the addresses of the n cache units of the first cache group decrease in sequence. Such as Figure 6As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way4 are arranged in sequence from left to right. Among them, the addresses increase in sequence from right to left, and the addresses of the cache units in the same column are the same. In some other embodiments, the addresses of the n cache units of the first cache group increase in sequence. As Figure 7 As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way4 are arranged in sequence from right to left.

[0065] In some other embodiments, the addresses of the n cache units of the first cache group increase first and then decrease. As Figure 6 As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way1 are arranged from right to left first and then from left to right. In some other embodiments, the addresses of the n cache units of the first cache group decrease first and then increase. As Figure 6 As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way3 are arranged from left to right first and then from right to left.

[0066] In some other embodiments, the addresses of the n cache units of the first cache group decrease first, then increase, and then decrease. As Figure 6 As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way2 are arranged from left to right first, then from right to left, and then from left to right. In some other embodiments, the addresses of the n cache units of the first cache group increase first, then decrease, and then increase. As Figure 7 As shown, taking n equal to 4 as an example for illustration, the 4 cache units of cache group way2 are arranged from right to left first, then from left to right, and then from right to left.

[0067] In addition, in some embodiments, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively, where the 1st address to the nth address can increase in sequence or decrease in sequence. Assuming that the address of the cache unit of the first cache group or any cache group in any first memory is the i-th address, where i is any integer between 1 and n, including the endpoint values 1 and n, in the case where the addresses of the n cache units of the first cache group or any cache group are different from each other, if i - 1 > 0, then the address of the cache unit of the first cache group or any cache group in the next first memory is the (i - 1)-th address, if i - 1 ≤ 0, then the address of the cache unit of the first cache group or any cache group in the next first memory is the nth address, if i + 1 > n, then the address of the cache unit of the first cache group or any cache group in the previous first memory is the 1st address, if i + 1 ≤ n, then the address of the cache unit of the first cache group or any cache group in the previous first memory is the (i + 1)-th address.

[0068] Taking n equal to 4 as an example for illustration, asFigure 6 As shown, the address of the cache unit way1-S2 in the cache group way1 in the second first memory S2 is the fourth address, and 4 + 1 > 4. Then, the address of the cache unit way1-S1 in the cache group way1 in the previous first memory, i.e., the first first memory S1, is the first address, and 4 - 1 > 0. Then, the address of the cache unit way1-S3 in the cache group way1 in the next first memory, i.e., the third first memory S3, is the third address. The addresses of the cache units in other cache groups can be deduced by analogy and will not be elaborated here.

[0069] In some alternative examples, the addresses of the n cache units in the first memory are the first address to the nth address respectively, and the n cache groups are the first cache group to the nth cache group respectively. Assume that the first cache group or any cache group is the jth cache group, and the address of the cache unit in the jth cache group in any first memory is the ith address. Both j and i are any integers between 1 and n, including the endpoint values 1 and n. When the addresses of the n cache units in the first cache group or any cache group are different, if j is even, and if i - 1 > 0, then the address of the cache unit in the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit in the jth cache group in the previous first memory is the first address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the previous first memory is the (i + 1)th address. If j is odd, and if i + 1 > n, then the address of the cache unit in the jth cache group in the next first memory is the first address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache unit in the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the previous first memory is the nth address.

[0070] Taking n equal to 4 as an example for illustration, as Figure 8As shown, the address of the cache unit way1-S2 in the first cache group way1 in the second first memory S2 is the second address. Since 1 is odd and 2 + 1 ≤ 4, the address of the cache unit way1-S3 in the next first memory, i.e., the third first memory S3, of the first cache group way1 is the third address. And since 2 - 1 > 0, the address of the cache unit way1-S1 in the previous first memory, i.e., the first first memory S1, of the first cache group way1 is the first address. The address of the cache unit way2-S2 in the second cache group way2 in the second first memory S2 is the first address. Since 2 is even and 1 + 1 ≤ 4, the address of the cache unit way2-S1 in the previous first memory, i.e., the first first memory S1, of the second cache group way2 is the second address. And since 1 - 1 = 0, the address of the cache unit way2-S3 in the next first memory, i.e., the third first memory S3, of the second cache group way2 is the fourth address. The addresses of the cache units in other cache groups can be deduced by analogy and will not be elaborated here.

[0071] It should be noted that making the addresses of the n cache units in the first cache group different from each other and arranging the addresses of the n cache units in the first cache group in a Figures 6 to 8 spiral arrangement as shown can make the structural design of the cache easier to implement and can relatively save resource consumption, etc.

[0072] Of course, the present invention is not limited to this. In some other embodiments, the addresses of the n cache units in the first cache group are the same, or rather, the addresses of the n cache units in each cache group are the same. In some embodiments, the addresses of the n cache units in the first memory are the first address to the nth address respectively, and the n cache groups are the first cache group to the nth cache group respectively. Assuming the first cache group is the jth cache group, then when the addresses of the n cache units in the first cache group are the same, the address of the cache unit in the jth cache group in any first memory is the jth address, where j is any integer between 1 and n, including the endpoint values 1 and n.

[0073] As Figure 9 shown, taking n equal to 4 as an example for illustration, the addresses of the 4 cache units in the cache group way1 are the same, such as all being the first address; the addresses of the 4 cache units in the cache group way2 are the same, such as all being the second address; the addresses of the 4 cache units in the cache group way3 are the same, such as all being the third address; the addresses of the 4 cache units in the cache group way4 are the same, such as all being the fourth address.

[0074] In some embodiments of the present invention, the first cache access request carries first data, a write address, and an identifier of a first cache group. After the cache control module responds to the first cache access request, it selects the first cache group from the n cache groups according to the identifier of the first cache group, encodes the addresses of the n cache units in the first cache group according to the write address, and makes the addresses of the n cache units in the first cache group different or the same. According to the addresses of the n cache units in the first cache group obtained by encoding, the n first sub-data are respectively written into the n cache units in the first cache group.

[0075] In some embodiments, the cache control module compares the identifier of the first cache group with the identifiers of the n cache groups respectively. If the identifier of one of the cache groups is the same as the identifier of the first cache group, then this one cache group is selected as the first cache group. In some embodiments, the identifier of the first cache group may be the common address (tag) in the access address carried by the first cache access request.

[0076] In some embodiments, the cache control module can encode according to the write address to obtain the addresses of the n cache units in the first cache group, and after writing the n first sub-data into the n cache units in the first cache group respectively, store the addresses of the n cache units in the first cache group, so as to read out the n first sub-data according to the addresses of the n cache units in the first cache group. Wherein, the write address is the address of the first data in the memory.

[0077] In some embodiments of the present invention, as Figure 10 shown, the cache access method further includes:

[0078] S103: Receive a second cache access request, where the second cache access request is used to read out second data of a second cache group.

[0079] Wherein, the second cache group is any one of the n cache groups of the n first memories disclosed in the embodiments of the present invention, and the width of the second data is equal to the width of the data of m memory blocks.

[0080] S104: In response to the second cache access request, according to the read address carried by the second cache access request, read out the data of the n cache units with the same byte segment corresponding to the read address from the n first memories respectively. The data of the n cache units with the same byte segment are respectively the data of the n cache groups, and select the data of the cache unit of the second cache group from the data of the n cache units with the same byte segment as the second data.

[0081] After the cache control module receives the second cache access request sent by the processor or the processor core, in response to the second cache access request, it reads out the data of n cache units whose byte segments are the same as the byte segment corresponding to the read address from n first memories respectively, and selects the data of the cache units of the second cache group from the data of the n cache units with the same byte segment to obtain the second data.

[0082] Taking the data in the cache unit of way3-S3 as the second data as an example, the cache control module reads out the data of n cache units of way1-S1, way2-S2, way3-S3... wayn-Sn from the n first memories of S1 to Sn respectively. Among them, the byte segments of the data of the n cache units of way1-S1, way2-S2, way3-S3... wayn-Sn are all the same as the byte segment corresponding to the read address. The data of the cache unit of way3-S3 is selected from the data of the n cache units of way1-S1, way2-S2, way3-S3... wayn-Sn to obtain the second data.

[0083] Because different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories, so the data of n cache units with the same byte segment can be read out in one clock cycle. And because the data of each cache unit is the data of m memory blocks, so the data of m×n memory blocks can be read out in one clock cycle, which can improve the data reading rate of the cache, and further improve the data processing rate of the cache.

[0084] In some embodiments of the present invention, the second cache access request also carries the identifier of the second cache group. The cache control module can select the data of the cache units of the second cache group from the data of the n cache units with the same byte segment according to the identifier of the second cache group to obtain the second data.

[0085] In some embodiments, the cache control module compares the cache group identifier of the data of n cache units with the same byte segment with the identifier of the second cache group. If the cache group identifier of a cache unit is the same as the identifier of the second cache group, then the cache unit is the cache unit of the second cache group, and the data of the cache unit is the second data.

[0086] In some embodiments, the byte segment to be read can be obtained according to the offset address (i.e., the read address) in the access address carried by the second cache access request. In some embodiments, the identifier of the second cache group can be the common address (tag) in the access address carried by the second cache access request.

[0087] In some embodiments of the present invention, such asFigure 5 As shown, the addresses of n cache units with the same data byte segment are the same. Or rather, the byte segments of the data of n cache units that belong to different cache groups but have the same address are the same. For example, the byte segments of the data of n cache units way1-S1, way2-S2, way3-S3... wayn-Sn that belong to n cache groups way1 to wayn respectively are the same and the addresses are the same.

[0088] Moreover, the addresses of n cache units that belong to the same cache group but have different data byte segments are different. As Figure 5 shown, the byte segments of the data of n cache units way1-S1, way1-S2, way1-S3... way1-Sn that belong to cache group way1 are different from each other and the addresses are different. The byte segments of the data of n cache units way2-S1, way2-S2, way2-S3... way2-Sn that belong to cache group way2 are different from each other and the addresses are different.

[0089] Of course, the present invention is not limited thereto. In some other embodiments, as Figure 11 shown, the addresses of n cache units with the same data byte segment are different. Or rather, the addresses of n cache units that belong to different cache groups but have the same data byte segment are different. For example, the byte segments of the data of n cache units way1-S1, way1-S2, way1-S3... way1-Sn that belong to cache group way1 are different from each other but the addresses are the same. However, the addresses of n cache units way1-S1, way2-S2, way3-S3... wayn-Sn that belong to different cache groups and have the same data byte segment are different from each other.

[0090] Moreover, the addresses of n cache units that belong to the same cache group but have different data byte segments are the same. As Figure 11 shown, the addresses of n cache units way1-S1, way1-S2, way1-S3... way1-Sn that belong to cache group way1 are the same. The addresses of n cache units way2-S1, way2-S2, way2-S3... way2-Sn that belong to cache group way2 respectively are the same.

[0091] As another alternative implementation of the disclosed content of the present invention, an embodiment of the present invention also discloses a cache control module, which is applied to a processor, and the processor includes a cache, as Figure 3As shown, the cache includes n first memories. The n first memories include n cache groups. Each cache group includes n cache units. The n cache units are respectively located in the n first memories. And each cache unit is used to store data of m memory blocks. n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1. For example, Figure 12 As shown, the cache control module includes a first address encoding unit 101.

[0092] The first address encoding unit 101 is configured to receive a first cache access request. The first cache access request is used to write first data into a first cache group. The first cache group is any one of the n cache groups. The width of the first data is equal to the width of data of m×n memory blocks. In response to the first cache access request, the first data is divided into n first sub-data with different byte segments. The width of each first sub-data is equal to the width of data of m memory blocks. The n first sub-data are respectively written into the n cache units of the first cache group. Among them, different first data are stored in the cache units of different cache groups. And the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

[0093] In some embodiments of the present invention, the first cache access request carries the first data, a write address, and an identifier of the first cache group. The first address encoding unit 101 is configured to select the first cache group from the n cache groups according to the identifier of the first cache group, perform address encoding on the n cache units of the first cache group according to the write address, and make the addresses of the n cache units of the first cache group different or the same. According to the addresses of the n cache units of the first cache group obtained by encoding, the n first sub-data are respectively written into the n cache units of the first cache group.

[0094] In some embodiments, for example, Figure 12As shown, after the first address encoding unit 101 receives a first cache access request sent by a processor or a processor core, in response to the first cache access request, it divides the first data into n first sub-data with different byte segments. These n first sub-data are data1 to datan respectively. According to the identifier Wn of the first cache group, it selects the first cache group from n cache groups, performs address encoding on the n cache units of the first cache group according to the write address Wadress, and makes the addresses of the n cache units of the first cache group different or the same. For example, it makes the addresses of the n cache units of the first cache group be address1 to addressn respectively. According to the addresses address1 to addressn of the n cache units of the first cache group obtained by encoding, it writes the n first sub-data data1 to datan into the n cache units of the first cache group respectively, and stores the addresses of the n cache units of the first cache group, so as to read out the n first sub-data according to the addresses of the n cache units of the first cache group.

[0095] In some embodiments of the present invention, the addresses of the n cache units of the first cache group are different from each other, or in other words, the addresses of the n cache units in any cache group of the n first memories are different from each other. For example, it makes the addresses of the n cache units way3-S1, way3-S2, way3-S3... way3-Sn different from each other. In some embodiments, the addresses of the n cache units of any first memory are the same as the addresses of the n cache units of another first memory respectively. For example, it makes the addresses of the n cache units of the first memory S1 the same as the addresses of the n cache units of the first memory S2 respectively, and makes the addresses of the n cache units of the first memory S2 the same as the addresses of the n cache units of the first memory S3 respectively.

[0096] In some embodiments, the addresses of the n cache units of the first cache group decrease in sequence. As Figure 6 shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way4 are arranged in sequence from left to right. Among them, the addresses increase in sequence from right to left, and the addresses of the cache units in the same column are the same. In some other embodiments, the addresses of the n cache units of the first cache group increase in sequence. As Figure 7 shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way4 are arranged in sequence from right to left.

[0097] In some other embodiments, the addresses of the n cache units of the first cache group increase first and then decrease. As Figure 6As shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way1 are arranged from right to left first and then from left to right. In some other embodiments, the addresses of the n cache units of the first cache group first decrease and then increase. As Figure 6 shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way3 are arranged from left to right first and then from right to left.

[0098] In some other embodiments, the addresses of the n cache units of the first cache group first decrease, then increase, and then decrease. As Figure 6 shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way2 are arranged from left to right first, then from right to left, and then from left to right. In some other embodiments, the addresses of the n cache units of the first cache group first increase, then decrease, and then increase. As Figure 7 shown, taking n equal to 4 as an example for illustration, the 4 cache units of the cache group way2 are arranged from right to left first, then from left to right, and then from right to left.

[0099] In addition, in some embodiments, the addresses of the n cache units of the first memory are the 1st address to the nth address respectively. Assuming that the address of the cache unit in the first cache group or any cache group in any first memory is the i-th address, where i is any integer between 1 and n, including the endpoint values 1 and n. When the addresses of the n cache units in the first cache group or any cache group are different, if i - 1 > 0, then the address of the cache unit in the first cache group or any cache group in the next first memory is the (i - 1)-th address; if i - 1 ≤ 0, then the address of the cache unit in the first cache group or any cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit in the first cache group or any cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the first cache group or any cache group in the previous first memory is the (i + 1)-th address.

[0100] Taking n equal to 4 as an example for illustration, as Figure 6 shown, the address of the cache unit way1-S2 of the cache group way1 in the 2nd first memory S2 is the 4th address, and 4 + 1 > 4, then the address of the cache unit way1-S1 of the cache group way1 in the previous first memory, i.e., the 1st first memory S1, is the 1st address, and 4 - 1 > 0, then the address of the cache unit way1-S3 of the cache group way1 in the next first memory, i.e., the 3rd first memory S3, is the 3rd address. The addresses of the cache units of other cache groups can be deduced by analogy and will not be elaborated here.

[0101] In some alternative examples, the addresses of the n cache units in the first memory are the 1st address to the nth address respectively, and the n cache groups are the 1st cache group to the nth cache group respectively. Suppose the first cache group or any cache group is the jth cache group, and the address of the cache unit in the jth cache group in any first memory is the ith address. Both j and i are any integers between 1 and n, including the endpoint values 1 and n. When the addresses of the n cache units in the first cache group or any cache group are different, if j is an even number and if i - 1 > 0, then the address of the cache unit in the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit in the jth cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the previous first memory is the (i + 1)th address. If j is an odd number and if i + 1 > n, then the address of the cache unit in the jth cache group in the next first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache unit in the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the previous first memory is the nth address.

[0102] Taking n equal to 4 as an example for illustration, as Figure 8 shown, the address of the cache unit way1 - S2 in the 1st cache group way1 in the 2nd first memory S2 is the 2nd address. 1 is an odd number and 2 + 1 ≤ 4, so the address of the cache unit way1 - S3 in the 1st cache group way1 in the next first memory, i.e., the 3rd first memory S3, is the 3rd address. And 2 - 1 > 0, so the address of the cache unit way1 - S1 in the 1st cache group way1 in the previous first memory, i.e., the 1st first memory S1, is the 1st address. The address of the cache unit way2 - S2 in the 2nd cache group way2 in the 2nd first memory S2 is the 1st address. 2 is an even number and 1 + 1 ≤ 4, so the address of the cache unit way2 - S1 in the 2nd cache group way2 in the previous first memory, i.e., the 1st first memory S1, is the 2nd address. 1 - 1 = 0, so the address of the cache unit way2 - S3 in the 2nd cache group way2 in the next first memory, i.e., the 3rd first memory S3, is the 4th address. The addresses of the cache units in other cache groups can be deduced by analogy and will not be elaborated here.

[0103] Of course, the present invention is not limited thereto. In some other embodiments, the addresses of the n cache units in the first cache group are the same, or rather, the addresses of the n cache units in each cache group are the same. In some embodiments, the addresses of the n cache units in the first memory are the first address to the nth address respectively, and the n cache groups are the first cache group to the nth cache group respectively. Assuming that the first cache group is the jth cache group, when the addresses of the n cache units in the first cache group are the same, the addresses of the cache units in the jth cache group in any first memory are all the jth address, where j is any integer between 1 and n, including the endpoint values 1 and n.

[0104] As Figure 9 shown, taking n equal to 4 as an example for illustration, the addresses of the 4 cache units in the cache group way1 are the same, such as all being the first address; the addresses of the 4 cache units in the cache group way2 are the same, such as all being the second address; the addresses of the 4 cache units in the cache group way3 are the same, such as all being the third address; the addresses of the 4 cache units in the cache group way4 are the same, such as all being the fourth address.

[0105] In some embodiments of the present invention, as Figure 12 shown, the cache control module further includes a second address encoding unit 102 and a multiplexing unit 103. The second address encoding unit 102 is configured to receive a second cache access request, where the second cache access request is used to read out second data of a second cache group, the second cache group being any one of the n cache groups, and the width of the second data is equal to the width of the data of m memory blocks. In response to the second cache access request, according to the read address carried in the second cache access request, data of n cache units corresponding to the same byte segment as the read address are respectively read out from the n first memories. The data of the n cache units with the same byte segment are respectively the data of the n cache groups, and the multiplexing unit 103 is controlled to select the data of the cache units in the second cache group from the data of the n cache units with the same byte segment to obtain the second data.

[0106] In some embodiments of the present invention, the second cache access request further carries an identifier of the second cache group, and the second address encoding unit 102 is configured to control the multiplexing unit 103 to select the data of the cache units in the second cache group from the data of the n cache units with the same byte segment according to the identifier of the second cache group to obtain the second data.

[0107] In some embodiments, as Figure 12As shown in the figure, the second address encoding unit 102 reads out the data of n cache units from n first memories respectively according to the read address Radress. The byte segments of the data of these n cache units are the same as the byte segment corresponding to the read address Radress. The data of these n cache units with the same byte segment will be output to the multiplexing unit 104. The second address encoding unit 103 will send the read address Radress and the identifier Wm of the second cache group to the multiplexing unit 103 to control the multiplexing unit 103 to select the data of the cache unit of the second cache group from the data of n cache units with the same byte segment. Based on this, in the embodiment of the present invention, only one multiplexing unit 103 can be used to implement the selection of data, and the structure is relatively simple and easy to implement.

[0108] Taking the data in the cache unit way3-S3 as the second data as an example, the second address encoding unit 102 reads out the data of n cache units such as way1-S1, way2-S2, way3-S3... wayn-Sn from n first memories S1 to Sn respectively. Among them, the byte segments of the data of these n cache units such as way1-S1, way2-S2, way3-S3... wayn-Sn are the same as the byte segment corresponding to the read address Radress. At the same time, the second address encoding unit 102 sends the identifier of the second cache group way3 and the read address Radress to the multiplexing unit 103 to control the multiplexing unit 103 to select the data of the cache unit way3-S3 from the data of n cache units such as way1-S1, way2-S2, way3-S3... wayn-Sn.

[0109] In some embodiments of the present invention, such as Figure 12 shown in the figure, the addresses of n cache units with the same data byte segment are the same, or in other words, the byte segments of the data of n cache units belonging to different cache groups but having the same address are the same. For example, the byte segments of the data of n cache units such as way1-S1, way2-S2, way3-S3... wayn-Sn belonging to n cache groups way1 to wayn are the same and the addresses are the same.

[0110] Moreover, the addresses of n cache units belonging to the same cache group but having different data byte segments are different. As Figure 12 shown in the figure, the byte segments of the data of n cache units such as way1-S1, way1-S2, way1-S3... way1-Sn belonging to the cache group way1 are different from each other and the addresses are different. The byte segments of the data of n cache units such as way2-S1, way2-S2, way2-S3... way2-Sn belonging to the cache group way2 are different from each other and the addresses are different.

[0111] Of course, the present invention is not limited to this. In some other embodiments, such as Figure 13 shown, the addresses of n cache units with the same data byte segment are different. Or rather, the addresses of n cache units belonging to different cache groups but having the same data byte segment are different. For example, the data byte segments of the n cache units way1-S1, way1-S2, way1-S3... way1-Sn belonging to the cache group way1 are different but their addresses are the same. However, the addresses of the n cache units way1-S1, way2-S2, way3-S3... wayn-Sn belonging to different cache groups and having the same data byte segment are different.

[0112] Moreover, the addresses of n cache units belonging to the same cache group but having different data byte segments are the same. As Figure 13 shown, the addresses of the n cache units way1-S1, way1-S2, way1-S3... way1-Sn belonging to the cache group way1 are the same, and the addresses of the n cache units way2-S1, way2-S2, way2-S3... way2-Sn belonging to the cache group way2 are the same.

[0113] As another alternative implementation of the disclosure of the present application, an embodiment of the present application also discloses a processor, which includes a cache and a cache control module disclosed in any of the foregoing embodiments. Or, the processor includes a cache control module and a cache, and the cache control module is configured to execute the cache access method disclosed in any of the foregoing embodiments.

[0114] As another alternative implementation of the disclosure of the present application, an embodiment of the present application also discloses a computer-readable storage medium, on which is stored a program for executing the cache access method disclosed in any of the foregoing embodiments.

[0115] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this specification can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0116] As another alternative implementation of the disclosure of the present application, embodiments of the present application also disclose an electronic device, which includes a processor disclosed in any of the above embodiments. The electronic device may include one or more processors and one or more memories. It can be understood that the electronic device may include other components as needed.

[0117] The electronic device can load and thus include one or more applications. These applications are instruction sets (e.g., computer program code), which control the operation of the electronic device when read by one or more processors. To this end, one or more memories may include instructions / data executable by one or more processors, whereby the electronic device can execute the methods disclosed in at least one embodiment of the present disclosure.

[0118] As another alternative implementation of the disclosure of the present application, embodiments of the present application also disclose a computer program product, which includes computer program instructions that cause a processor to execute the cache access method disclosed in any of the above embodiments when the computer program instructions are run by the processor.

[0119] A computer program product may be written in any combination of one or more programming languages for executing the program code of the operations of the embodiments of the present application. The programming languages include object-oriented programming languages such as Python, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0120] The technical features of the above embodiments may be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0121] The above embodiments only represent several implementation manners of this specification, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several deformations and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A cache access method, characterized in that, Applied to a processor, the processor includes a cache control module and a cache. The cache includes n first memories. The n first memories include n cache groups. Each cache group includes n cache units. The n cache units are respectively located in the n first memories. And each cache unit is used to store data of m memory blocks. n is an integer greater than or equal to 2, and m is an integer greater than or equal to 1. The cache access method includes the following operations performed by the cache control module: Receiving a first cache access request, the first cache access request is used to write first data into a first cache group, the first cache group is any one of the n cache groups, and the width of the first data is equal to the width of data of m×n memory blocks; In response to the first cache access request, dividing the first data into n first sub-data with different byte segments. The width of each first sub-data is equal to the width of data of m memory blocks, and writing the n first sub-data into the n cache units of the first cache group respectively. Among them, different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

2. The cache access method according to claim 1, wherein The addresses of the n cache units of the first cache group are different from each other; Or, the addresses of the n cache units of the first cache group are the same.

3. The cache access method according to claim 2, wherein The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. Assuming that the address of the cache unit of the first cache group in any first memory is the ith address, where i is any integer between 1 and n. In the case where the addresses of the n cache units of the first cache group are different from each other, if i - 1 > 0, then the address of the cache unit of the first cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit of the first cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit of the first cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit of the first cache group in the previous first memory is the (i + 1)th address.

4. The cache access method according to claim 2, wherein The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. The n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group, and the address of the cache unit in any first memory of the jth cache group is the ith address. Both j and i are any integers between 1 and n. When the addresses of the n cache units in the first cache group are different from each other, if j is an even number and if i - 1 > 0, then the address of the cache unit in the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache unit in the jth cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the previous first memory is the (i + 1)th address; if j is an odd number and if i + 1 > n, then the address of the cache unit in the jth cache group in the next first memory is the 1st address; if i + 1 ≤ n, then the address of the cache unit in the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache unit in the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache unit in the jth cache group in the previous first memory is the nth address.

5. The cache access method according to claim 2, wherein The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. The n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group. Then, when the addresses of the n cache units in the first cache group are the same, the address of the cache unit in the jth cache group in any first memory is the jth address, where j is any integer between 1 and n.

6. The cache access method according to claim 2, characterized in that, The first cache access request carries a write address and an identifier of the first cache group. The writing of the n first sub - data into the n cache units of the first cache group respectively includes: Selecting the first cache group from the n cache groups according to the identifier of the first cache group; Performing address encoding on the n cache units of the first cache group according to the write address, and making the addresses of the n cache units of the first cache group different from each other or the same; Writing the n first sub - data into the n cache units of the first cache group respectively according to the addresses of the n cache units of the first cache group obtained by encoding.

7. The cache access method according to claim 1, wherein It further includes: Receiving a second cache access request, which is used to read out second data of a second cache group. The second cache group is any one of the n cache groups, and the width of the second data is equal to the width of the data of m memory blocks; In response to the second cache access request, according to the read address carried in the second cache access request, data of n cache units that are the same as the byte segments corresponding to the read address are respectively read out from the n first memories. The data of the n cache units with the same byte segments are respectively the data of the n cache groups, and the data of the cache units of the second cache group are selected from the data of the n cache units with the same byte segments to obtain the second data.

8. The cache access method according to claim 7, wherein The second cache access request carries an identifier of the second cache group, and the selecting the data of the cache units of the second cache group from the data of the n cache units with the same byte segments includes: According to the identifier of the second cache group, the data of the cache units of the second cache group are selected from the data of the n cache units with the same byte segments to obtain the second data.

9. The cache access method according to claim 7 or 8, characterized in that, The addresses of the n cache units with the same data byte segments are the same, or the addresses of the n cache units with the same data byte segments are different from each other.

10. A cache control module, characterized in that, Applied to a processor, the processor includes a cache, the cache includes n first memories, the n first memories include n cache groups, each cache group includes n cache units, the n cache units are respectively located in the n first memories, and each cache unit is used to store data of m memory blocks. n is an integer greater than or equal to 2, m is an integer greater than or equal to 1, and the cache control module includes a first address encoding unit; The first address encoding unit is configured to receive a first cache access request for writing first data into a first cache group, where the first cache group is any one of the n cache groups, the width of the first data is equal to the width of data of m×n memory blocks. In response to the first cache access request, the first data is divided into n first sub-data with different byte segments, the width of each first sub-data is equal to the width of data of m memory blocks, and the n first sub-data are respectively written into the n cache units of the first cache group. Among them, different first data are stored in the cache units of different cache groups, and the first sub-data of the same byte segment of different first data are stored in the cache units of different first memories.

11. The cache control module according to claim 10, wherein The addresses of the n cache units of the first cache group are different from each other; Or, the addresses of the n cache units of the first cache group are the same.

12. The cache control module according to claim 11, characterized in that, The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. Assume that the address of the cache units of the first cache group in any first memory is the ith address, where i is any integer between 1 and n. When the addresses of the n cache units of the first cache group are different from each other, if i - 1 > 0, then the address of the cache units of the first cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache units of the first cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache units of the first cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache units of the first cache group in the previous first memory is the (i + 1)th address.

13. The cache control module according to claim 11, characterized in that, The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. The n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group, and the address of the cache units of the jth cache group in any first memory is the ith address, where both j and i are any integers between 1 and n. When the addresses of the n cache units of the first cache group are different from each other, if j is an even number and if i - 1 > 0, then the address of the cache units of the jth cache group in the next first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache units of the jth cache group in the next first memory is the nth address; if i + 1 > n, then the address of the cache units of the jth cache group in the previous first memory is the 1st address; if i + 1 ≤ n, then the address of the cache units of the jth cache group in the previous first memory is the (i + 1)th address; if j is an odd number and if i + 1 > n, then the address of the cache units of the jth cache group in the next first memory is the 1st address; if i + 1 ≤ n, then the address of the cache units of the jth cache group in the next first memory is the (i + 1)th address; if i - 1 > 0, then the address of the cache units of the jth cache group in the previous first memory is the (i - 1)th address; if i - 1 ≤ 0, then the address of the cache units of the jth cache group in the previous first memory is the nth address.

14. The cache control module according to claim 11, wherein The addresses of the n cache units of the first memory are the 1st address to the nth address respectively. The n cache groups are the 1st cache group to the nth cache group respectively. Assume that the first cache group is the jth cache group. Then when the addresses of the n cache units of the first cache group are the same, the address of the cache units of the jth cache group in any first memory is the jth address, where j is any integer between 1 and n.

15. The cache control module according to claim 11, wherein The first cache access request carries a write address and an identifier of the first cache group. The first address encoding unit is configured to select the first cache group from the n cache groups according to the identifier of the first cache group, perform address encoding on the n cache units of the first cache group according to the write address, and make the addresses of the n cache units of the first cache group different from or the same as each other. According to the addresses of the n cache units of the first cache group obtained by encoding, write the n first sub-data into the n cache units of the first cache group respectively.

16. The cache control module according to claim 10, wherein The cache control module further includes a second address encoding unit and a multiplexing unit; The second address encoding unit is configured to receive a second cache access request for reading second data of a second cache group. The second cache group is any one of the n cache groups, and the width of the second data is equal to the width of data of m memory blocks. In response to the second cache access request, according to the read address carried in the second cache access request, read data of n cache units with the same byte segment corresponding to the read address from the n first memories respectively. The data of the n cache units with the same byte segment are respectively the data of the n cache groups. Control the multiplexing unit to select the data of the cache unit of the second cache group from the data of the n cache units with the same byte segment to obtain the second data.

17. The cache control module according to claim 16, wherein The second cache access request carries an identifier of the second cache group. The second address encoding unit is configured to control the multiplexing unit to select the data of the cache unit of the second cache group from the data of the n cache units with the same byte segment according to the identifier of the second cache group to obtain the second data.

18. The cache control module according to claim 16 or 17, characterized in that, The addresses of the n cache units with the same byte segment of data are the same, or the addresses of the n cache units with the same byte segment of data are different from each other.

19. A processor, characterized in that, Comprising a cache and the cache control module according to any one of claims 10 to 18; or, the processor comprises a cache control module and a cache, and the cache control module is configured to execute the cache access method according to any one of claims 1 to 9.

20. An electronic device, characterized in that, Comprising the processor according to claim 19.

21. A computer-readable storage medium, characterized in that, Stored thereon are instructions for executing the cache access method according to any one of claims 1 to 9.

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