Monitoring circuit, refresh method and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a monitoring circuit, a refreshing method and a memory. The monitoring circuit comprises: a sampling module, which samples an initial address to obtain a monitoring address; a first counting module, which adjusts a counting value of a first counter corresponding to the monitoring address based on the received monitoring address; a processing module, which compares the counting value of the first counter corresponding to each monitoring address in the first counting module with a corresponding first preset value based on an update signal, and determines whether to transmit the monitoring address to a second counting module based on a comparison result; compares a counting value of a second counter corresponding to each monitoring address in the second counting module with a corresponding second preset value based on the update signal, and determines whether to retain the monitoring address based on a comparison result; and the second counting module adjusts the counting value of the second counter corresponding to the monitoring address based on the received monitoring address, so as to monitor a slow and continuously enabled word line address.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a refresh method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) stores data through a structure (1T1C) where a transistor is connected to a memory area. The transistor is controlled by a word line (WL). When the WL is turned on, the charge in the memory area is shared with the charge of the bit line (BL) to read data from or write data to the target memory area.

[0003] Frequent activation of word lines can lead to charge loss in adjacent memory areas, potentially causing errors in the stored data. Currently, a common approach is to refresh the memory areas adjacent to the word line address that is activated most frequently within a refresh cycle, based on the refresh period as the time unit, thus preventing data errors. However, this method requires counting all activated word line addresses, driving a large number of counters, resulting in significant power consumption and making it impractical for real-world applications. Furthermore, slowly and continuously activated word line addresses can be masked by word line addresses activated multiple times in a short period, compromising the accuracy of the stored data.

[0004] How to complete the supplementary refresh of the storage area with low power consumption, and detect the word line address that is slowly and continuously enabled, so as to ensure the accuracy of the stored data in each storage area, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a monitoring circuit, a refresh method, and a memory that achieves supplementary refresh of specific rows in the memory area with low power consumption, and monitors word line addresses that are slowly and continuously enabled. This ensures the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0006] One embodiment of this disclosure provides a monitoring circuit, including: a sampling module configured to sample an initial address to obtain a monitoring address and output the monitoring address, wherein the initial address is an enabled word line address in the memory where the monitoring circuit is located; a first counting module connected to the sampling module, configured to adjust the count value of a first counter corresponding to the received monitoring address based on the received monitoring address; a processing module connected to the first counting module and a second counting module, configured to compare the count value of the first counter corresponding to each monitoring address in the first counting module with a corresponding first preset value based on an update signal, and determine whether to transmit the monitoring address to the second counting module based on the comparison result of the count value of the first counter and the first preset value; compare the count value of the second counter corresponding to each monitoring address in the second counting module with a corresponding second preset value based on an update signal, and determine whether to retain the monitoring address based on the comparison result of the count value of the second counter and the second preset value; and a second counting module connected to the sampling module and the first counting module, configured to adjust the count value of the second counter corresponding to the received monitoring address based on the received monitoring address, wherein the second preset value is less than the first preset value.

[0007] In the monitoring circuit provided in this embodiment, the processing module continuously releases monitoring addresses whose count values ​​in the first counting module are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the first counting module, so that the first counting module can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the second counting module continues to count the addresses released by the first counting module to continue monitoring word line addresses that are slowly and continuously enabled, avoiding the word line addresses that are slowly and continuously enabled being masked by word line addresses that are enabled multiple times in a short period of time, so as to ensure the accuracy of the stored data in each memory area.

[0008] Additionally, the processing module includes: a first processing unit connected to the first counting module, configured to compare the count value of the first counter corresponding to each monitoring address in the first counting module with a first preset value based on an update signal; wherein, if the count value of the first counter is greater than or equal to the first preset value, the monitoring address is retained; if the count value of the first counter is less than the first preset value, the monitoring address is transmitted to the second counting module, and the first counter and the first preset value corresponding to the monitoring address are reset; and a second processing unit connected to the second counting module, configured to compare the count value of the second counter corresponding to each monitoring address in the second counting module with a second preset value based on an update signal; wherein, if the count value of the second counter is greater than or equal to the second preset value, the monitoring address is retained; if the count value of the second counter is less than the second preset value, the monitoring address is released, and the second counter and the second preset value corresponding to the monitoring address are reset.

[0009] In addition, the monitoring circuit further includes: a judgment module, connected to the sampling module, configured to determine whether the acquired monitoring address is stored based on the acquired monitoring address and the stored monitoring address; if the monitoring address is stored by the first counting module, a first control signal is generated; if the monitoring address is stored by the second counting module, a second control signal is generated; if the monitoring address is not stored, a third control signal is generated; the first counting module includes: a first counting unit, connected to the sampling module and the judgment module, configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on the first control signal, or configure a corresponding first counter for the newly added monitoring address and set the count value of the first counter to 1 based on the third control signal; and a first reference unit, connected to the first counting unit and the judgment module. The system is configured to: configure a first preset value for the monitoring address based on a third control signal, and store the configured first preset value in a first counting unit, and adjust the first preset value based on an update signal; the second counting module includes: a second counting unit connected to the first counting unit, a sampling module, and a judgment module, configured to: increment the count value of the second counter corresponding to the monitoring address by 1 based on a second control signal, configure a corresponding second counter for the monitoring address transmitted by the first counting unit, and set the count value of the second counter; a second reference unit connected to the first counting unit and the second counting unit, configured to: configure a second preset value for the monitoring address transmitted by the first counting unit, and store the configured second preset value in the second counting unit, and adjust the second preset value based on an update signal.

[0010] In addition, setting the count value of the second counter includes: setting the count value of the second counter based on the count value of the first counter corresponding to the monitoring address; or, setting the count value of the second counter to 0.

[0011] In addition, the magnitude of the first preset value is positively correlated with the number of first update cycles retained in the first counting module for the monitoring address, and the magnitude of the second preset value is positively correlated with the number of second update cycles retained in the second counting module for the monitoring address, or the sum of the number of first update cycles and the number of second update cycles retained. The first update cycle and the second update cycle are the interval time between adjacent update signals. By setting the first preset value and the second preset value as variables related to the update cycle, that is, by increasing the retention standard for word line addresses that have been counted for a long time, the word line addresses that may cause errors in the data stored in the memory area are obtained are more accurate, thereby further ensuring the accuracy of memory refresh.

[0012] Additionally, the first reference unit includes: a first setting subunit connected to the first counting unit and the judgment module, configured to, in response to a third control signal, set a first preset value corresponding to the monitoring address based on a first initial value; and a first adjustment subunit configured to receive an update signal and adjust the first preset value corresponding to the monitoring address retained in the first counting unit based on the update signal. The second reference unit includes: a second setting subunit connected to the first counting unit and the second counting unit, configured to, based on a second initial value, set a second preset value corresponding to the monitoring address transmitted by the first counting unit; and a second adjustment subunit configured to receive an update signal and adjust the second preset value corresponding to the monitoring address retained in the second counting unit based on the update signal.

[0013] In addition, the first preset value is the counting result of the third counter in the first counting unit; adjusting the first preset value corresponding to the monitoring address retained in the first counting unit based on the update signal includes: based on the update signal, accumulating the third initial value to the third counter corresponding to the monitoring address retained in the first counting unit; the second preset value is the counting result of the fourth counter in the second counting unit; adjusting the second preset value corresponding to the monitoring address retained in the second counting unit based on the update signal includes: based on the update signal, accumulating the fourth initial value to the fourth counter corresponding to the monitoring address retained in the second counting unit.

[0014] In addition, the first initial value is set to 2. n The second initial value is set to 2. m The third initial value is set to 2. p The fourth initial value is set to 2. q m, n, p, and q are positive integers greater than or equal to 1, and m > n, p > q.

[0015] In addition, the sampling module obtains the monitoring address based on a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. By setting the sampling probability for the sampling module, the number of word line addresses that the sampling module needs to obtain is reduced, that is, the power consumption of the monitoring circuit is further reduced by sampling detection.

[0016] Additionally, x is a positive integer less than or equal to 16.

[0017] In addition, the update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, and the count adjustment signal is provided in the interval between two adjacent refresh signals. By using the refresh signal and the count adjustment signal together as the update signal, the frequency at which the processing module releases the monitored addresses in the first and second counting modules is increased, thereby further reducing the number of counters that the monitoring circuit needs to drive. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line addresses is increased, preventing the sudden multiple enabling of certain enabled word line addresses in a short period of time.

[0018] In addition, the memory refresh operation also includes: refreshing the adjacent rows of the monitoring addresses with the highest count values ​​corresponding to the first counter in the monitoring addresses retained in the first counting module, and refreshing the adjacent rows of the monitoring addresses with the highest count values ​​corresponding to the second counter in the monitoring addresses retained in the second counting module, where y and z are positive integers greater than or equal to 1; after refreshing, releasing the monitoring addresses corresponding to the refreshed adjacent rows in the first and second counting modules, and resetting the first counter and the first preset value corresponding to the monitoring addresses corresponding to the refreshed adjacent rows, or the second counter and the second preset value corresponding to the refreshed monitoring addresses.

[0019] In addition, the first counting unit is configured to discard newly added monitoring addresses based on a third control signal when each first counter in the first counting unit has a corresponding monitoring address; the second counting unit is configured to discard monitoring addresses transmitted by the first counting unit when each second counter in the second counting unit has a corresponding monitoring address.

[0020] Another embodiment of this disclosure provides a refresh method applied to the monitoring circuit provided in the above embodiments, including: Step S1: Obtaining a monitoring address and detecting whether the monitoring address is stored; if the monitoring address has been stored, then proceeding to Step S2; if the monitoring address has not been stored, then proceeding to Step S3; Step S2: Incrementing the count value of the first counter corresponding to the monitoring address by 1, or incrementing the count value of the second counter corresponding to the monitoring address by 1; Step S3: Using a new first counter to count the monitoring address, setting the count value of the first counter to 1, and setting a corresponding first preset value for the monitoring address; Step S4: Adjusting the first preset value corresponding to the retained monitoring address based on the update signal. Set a value and compare the count value of the first counter corresponding to each monitoring address with the first preset value. If the count value of the first counter is greater than or equal to the first preset value, proceed to step S5. If the count value of the first counter is less than the first preset value, proceed to step S6. Step S5: Retain the count value of the first counter corresponding to the monitoring address and the first preset value, and continue to proceed to step S1. Step S6: Use a new second counter to count the monitoring address. The count value of the second counter is the same as the count value of the first counter corresponding to the monitoring address. Set the corresponding second preset value for the monitoring address and reset the first counter and the first preset value corresponding to the monitoring address. Continue to proceed to step S1.

[0021] Additionally, step S4 further includes: adjusting the second preset value corresponding to the retained monitoring address based on the update signal, and comparing the count value of the second counter corresponding to each monitoring address with the second preset value. If the count value of the second counter is greater than or equal to the second preset value, then step S7 is executed; if the count value of the second counter is less than the second preset value, then step S8 is executed. Step S7: retain the monitoring address, the count value of the second counter corresponding to the monitoring address, and the second preset value, and continue executing step S1. Step S8: release the monitoring address, reset the second counter corresponding to the monitoring address, and continue executing step S1.

[0022] In addition, setting a corresponding first preset value for the monitoring address includes: acquiring a newly added monitoring address and setting a first preset value corresponding to the newly added monitoring address based on a first initial value; adjusting the first preset value corresponding to the retained monitoring address based on the update signal, including: accumulating the first preset value corresponding to the retained monitoring address based on a third initial value; setting a corresponding second preset value for the monitoring address includes: acquiring the monitoring address and setting a second preset value corresponding to the monitoring address based on a second initial value; adjusting the second preset value corresponding to the retained monitoring address based on the update signal, including: accumulating the second preset value corresponding to the retained monitoring address based on a fourth initial value.

[0023] Another embodiment of this disclosure also provides a memory that obtains the word line address to be refreshed based on the monitoring circuit provided in the above embodiments; it achieves supplementary refresh of specific rows in the memory area with low power consumption, and monitors word line addresses that are slowly and continuously enabled, ensuring the accuracy of stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a monitoring circuit provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of the structure of a processing module provided in an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of the structure of a first counting module and a second counting module provided in an embodiment of the present disclosure;

[0028] Figure 4 A schematic diagram of the structure of a first reference unit and a second reference unit provided in an embodiment of this disclosure;

[0029] Figures 5-8 A schematic diagram illustrating the principle of a monitoring circuit for reserving and releasing monitoring addresses according to an embodiment of this disclosure;

[0030] Figure 9 This is a flowchart illustrating each step in a refresh method provided in another embodiment of the present disclosure. Detailed Implementation

[0031] As the background technology shows, frequent activation of word lines can lead to charge loss in adjacent memory areas, potentially causing errors in the stored data. Currently, the common approach to address this is to refresh the memory areas adjacent to the word line address that is activated most frequently within a refresh cycle, based on the refresh cycle as the time unit, thereby preventing data errors. However, this method requires counting all activated word line addresses, driving a large number of counters, resulting in significant power consumption, which is impractical. Furthermore, slowly and continuously activated word line addresses can be masked by word line addresses activated multiple times in a short period, compromising the accuracy of the stored data.

[0032] One embodiment of this disclosure provides a monitoring circuit that achieves supplementary refresh of specific rows in the memory area with low power consumption, and monitors word line addresses that are slowly and continuously enabled. This ensures the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0033] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0034] Figure 1 This is a schematic diagram of the monitoring circuit provided in this embodiment. Figure 2 This is a schematic diagram of the processing module provided in this embodiment. Figure 3 This is a schematic diagram of the structure of the first counting module and the second counting module provided in this embodiment. Figure 4 This is a schematic diagram of the structure of the first reference unit and the second reference unit provided in this embodiment. Figures 5-8 This is a schematic diagram illustrating the principle of the monitoring circuit in this embodiment for reserving and releasing monitoring addresses. The monitoring circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0035] refer to Figure 1 Monitoring circuit, including:

[0036] The sampling module 101 is configured to sample the initial address to obtain the monitoring address and output the monitoring address. The initial address is the word line address that is enabled in the memory where the monitoring circuit is located.

[0037] The first counting module 110, connected to the sampling module 101, is configured to adjust the count value of the first counter corresponding to the received monitoring address based on the received monitoring address.

[0038] The processing module 102, connected to the first counting module 110 and the second counting module 120, is configured to: compare the count value of the first counter corresponding to each monitoring address in the first counting module 110 with the corresponding first preset value based on the update signal; and determine whether to transmit the monitoring address to the second counting module based on the comparison result of the count value of the first counter and the first preset value; and compare the count value of the second counter corresponding to each monitoring address in the second counting module with the corresponding second preset value based on the update signal; and determine whether to retain the monitoring address if the second preset value is less than the first preset value based on the comparison result of the count value of the second counter and the second preset value.

[0039] The second counting module 120, connected to the sampling module 101 and the first counting module 110, is configured to adjust the count value of the second counter corresponding to the received monitoring address based on the received monitoring address.

[0040] In the monitoring circuit provided in this embodiment, the processing module 102 continuously releases monitoring addresses whose count values ​​in the first counting module 110 are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the first counting module 110, so that the first counting module 110 can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters required by the monitoring circuit is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module 102 continues to count the addresses released by the first counting module 110 through the second counting module 120, so as to continue to monitor word line addresses that are slowly and continuously enabled, and avoid the word line addresses that are slowly and continuously enabled being masked by word line addresses that are enabled multiple times in a short period of time, so as to ensure the accuracy of the stored data in each memory area.

[0041] In some embodiments, the first counting module 110 is further configured to configure a first preset value for the monitored address, and the magnitude of the configured first preset value is positively correlated with the duration of the monitored address in the first counting module 110. The second counting module 120 is further configured to configure a second preset value for the monitored address, and the magnitude of the configured second preset value is positively correlated with the duration of the monitored address in the second counting module 120. Specifically, the longer the monitoring address exists in the first counting module 110 or the second counting module 120, the larger the preset value corresponding to the monitoring address; the shorter the time the monitoring address exists in the first counting module 110 or the second counting module 120, the smaller the preset value corresponding to the monitoring address. In other embodiments, the second preset value configured in the second counting module 120 is positively correlated with the sum of the durations the monitoring address exists in the first counting module 110 and the second counting module 120. Specifically, the longer the monitoring address exists in the first counting module 110 and the second counting module 120, the larger the second preset value corresponding to the monitoring address; the shorter the time the monitoring address exists in the first counting module 110 and the second counting module 120, the smaller the second preset value corresponding to the monitoring address.

[0042] In some embodiments, the sampling module 101 provided in this embodiment obtains the monitoring address by sampling at a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. That is, the sampling module 101 samples the monitoring address once every x word lines of memory are enabled. By setting the sampling probability for the sampling module 101, the number of word lines the sampling module 101 needs to obtain is reduced, thus further reducing the power consumption of the monitoring circuit through sampling detection. In some embodiments, x can be a positive integer less than or equal to 16; in a specific example, x can be a positive integer less than or equal to 8, for example, x can be a positive integer such as 8, 6, 4, or 2.

[0043] Regarding the processing module 102 provided in this embodiment, in some embodiments, refer to Figure 2 Processing module 102 includes:

[0044] The first processing unit 201, connected to the first counting module 110, is configured to compare the count value of the first counter corresponding to each monitoring address in the first counting module 110 with a first preset value based on the update signal; wherein, if the count value of the first counter is greater than or equal to the first preset value, the monitoring address is retained; if the count value of the first counter is less than the first preset value, the monitoring address is transmitted to the second counting module 120, and the first counter and the first preset value corresponding to the monitoring address are reset.

[0045] The second processing unit 202, connected to the second counting module 120, is configured to compare the count value of the second counter corresponding to each monitoring address in the second counting module 120 with the second preset value based on the update signal; wherein, if the count value of the second counter is greater than or equal to the second preset value, the monitoring address is retained; if the count value of the second counter is less than the second preset value, the monitoring address is released, and the second counter and the second preset value corresponding to the monitoring address are reset.

[0046] Specifically, for the first processing unit 201, in some embodiments, the first processing unit 201 includes: a first processing subunit (not shown), connected to the first counting module, configured to receive the count value of the first counter corresponding to each monitoring address and a first preset value, and based on the control of the update signal, latch the count value of the first counter and the first preset value and transmit them to the comparison subunit (not shown); the comparison subunit (not shown) is connected to the first processing subunit (not shown), configured to compare the count value of the first counter and the first preset value, and when the count value of the first counter is less than the first preset value, generate and output a release control signal; a second processing subunit (not shown), connected to the comparison subunit (not shown) and the first counting module 110, configured to, based on the release control signal, transmit the corresponding monitoring address in the first counting module 110 to the second counting module 120, and reset the first counter and the first preset value corresponding to the monitoring address.

[0047] It should be noted that the above description of the structure of the first processing unit 201 is only for those skilled in the art to understand the working principle of the first processing unit 201 provided in this embodiment, and does not constitute a limitation on the first processing unit 201; in addition, the working principle of the second processing unit 202 is similar to that of the first processing unit 201, and will not be described again in this embodiment.

[0048] In this embodiment, if the monitoring address is transmitted from the first counting module 110 to the second counting module 120, the second counter in the second counting module 120 inherits the value of the first counter in the first counting module 110. The second counting module 120 also inherits the duration of the monitoring address in the first counting module 110, thereby configuring a second preset value accordingly to continue monitoring the monitoring address, thereby monitoring word line addresses that are slowly and continuously enabled.

[0049] In other embodiments, the second counting module 120 may also be configured such that the monitoring address is transmitted from the first counting module 110 to the second counting module 120, the second counter corresponding to the monitoring address transmitted to the second counting module 120 restarts counting, and the second counting module 120 configures a second preset value for the monitoring address based on the duration (initial value is 0) of the monitoring address existing in the second counting module 120.

[0050] refer to Figure 3 In some embodiments, the monitoring circuit further includes:

[0051] The judgment module 301, connected to the sampling module 101, is configured to determine whether the acquired monitoring address has been stored based on the acquired monitoring address and the stored monitoring address. If the monitoring address is stored by the first counting module 110, a first control signal is generated; if the monitoring address is stored by the second counting module 120, a second control signal is generated; if the monitoring address is not stored, a third control signal is generated.

[0052] In some embodiments, the first counting module 110 and the second counting module 120 provided in this embodiment include: a first counting unit 302, connected to the sampling module 101 and the judgment module 301, configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on a first control signal, or configure a corresponding first counter for the newly added monitoring address based on a third control signal and set the count value of the first counter to 1; and a first reference unit 303, connected to the first counting unit 302 and the judgment module 301, configured to configure a first preset value for the monitoring address based on a third control signal, wherein the configured first preset value is stored in the first counting unit 302 and the first preset value is adjusted based on an update signal. The second counting module 120 includes: a second counting unit 304 connected to the first counting unit 302, the sampling module 101, and the judgment module 301, configured to increment the count value of the second counter corresponding to the monitoring address by 1 based on the second control signal, configure the corresponding second counter for the monitoring address transmitted by the first counting unit, and set the count value of the second counter; and a second reference unit 305 connected to the first counting unit 302 and the second counting unit 304, configured to configure a second preset value for the monitoring address transmitted by the first counting unit 302, and store the configured second preset value in the second counting unit 304, and adjust the second preset value based on the update signal.

[0053] It should be noted that if the monitoring address is transmitted from the first counting module 110 to the second counting module 120, the value of the first counter in the first counting module 110 can be inherited by the second counter in the second counting module 120, or the count value of the second counter corresponding to the monitoring address can be set to 0, that is, the counting of the monitoring address transmitted from the first counting module to the second counting module 120 can start again. Specifically, in some embodiments, the second counting unit 304 is further configured to configure a corresponding second counter for the monitoring address transmitted by the first counting unit 302, and set the count value of the second counter based on the count value of the first counter corresponding to the monitoring address; in other embodiments, the second counting unit 302 is configured to configure a corresponding second counter for the monitoring address transmitted by the first counting unit 302, and set the count value of the second counter corresponding to the monitoring address to 0.

[0054] In other embodiments, a judgment module 301 can be set in both the first counting module 110 and the second counting module 120, so that the first counting module 110 and the second counting module 120 respectively compare the acquired monitoring address and the stored monitoring address to determine whether the acquired monitoring address has been stored.

[0055] In other embodiments, the first preset value can also be stored in the first reference unit, and the second preset value can also be stored in the second reference unit. It should be noted that in the following description of this embodiment, the first preset value is set in the first counting unit 302 and the second preset value is set in the second counting unit 304 as an example for detailed explanation.

[0056] It should be noted that the capacities of the first and second counters are based on the refresh command reception interval, the preset sampling interval, and the word line enable interval in the memory. Specifically, in the DDR4 standard, under normal operating temperature, for a 16GB memory in 1X refresh mode, the word line enable interval tRC = 45ns, the preset sampling interval tREFC = 550ns, and the refresh command reception interval tREFI = 7.8us. At this time, in the burst transfer mode of the memory, the number of word line addresses that can be enabled by 9*tREFI is 9*(tREFI-tREFC) / tRC = 161. If the capacities of the first and second counters are b, it is necessary to ensure 2 b >161, meaning b is at least 8. In this example, the capacity of the first counter and the second counter is set to 8 bits. It should be noted that the numerical examples in this example are only for those skilled in the art to understand the capacity setting method of the first counter and the second counter, and do not constitute a limitation on this embodiment.

[0057] In practical applications, the number of first counters in the first counting unit 302 is limited. The first counting unit 302 is also configured to discard newly added monitoring addresses based on the second control signal when each first counter in the first counting unit 302 has a corresponding monitoring address, that is, when all the first counters in the first counting unit 302 have started counting and the monitoring addresses stored in the first counting unit 302 are full. Correspondingly, the number of second counters in the second counting unit 304 is limited. The second counting unit 304 is also configured to discard monitoring addresses transmitted by the first counting unit 302 when each second counter in the second counting unit 304 has a corresponding monitoring address, that is, when all the second counters in the second counting unit 304 have started counting and the monitoring addresses stored in the second counting unit 304 are full. In some scenarios, the monitoring addresses discarded by the second counting unit 304 can be set to monitoring addresses with smaller second counter values.

[0058] In some embodiments, the number of the second counters in the second counting unit 304 is greater than the number of the first counters in the first counting unit 302. By setting the number of the second counters in the second counting unit 304 to be greater than that in the first counting unit 302, more address changes can be monitored, resulting in better monitoring of word line addresses where the memory is enabled.

[0059] In some embodiments, the first preset value and the second preset value are configured such that the magnitude of the first preset value is positively correlated with the number of first update cycles in which the monitoring address is retained in the first counting module 110, and the magnitude of the second preset value is positively correlated with the number of second update cycles in which the monitoring address is retained in the second counting module 120 or the sum of the number of first update cycles and the number of second update cycles retained. The first update cycle and the second update cycle are the interval time between two adjacent update signals.

[0060] Specifically, refer to Figure 4The first reference unit 303 includes: a first setting subunit 401, connected to the first counting unit 302 and the judgment module 301, configured to, in response to a third control signal, set a first preset value corresponding to the monitoring address based on a first initial value; and a first adjustment subunit 402, configured to receive an update signal and adjust the first preset value corresponding to the monitoring address retained in the first counting unit 302 based on the update signal, thereby achieving a positive correlation between the magnitude of the set first preset value and the number of first update cycles retained by the monitoring address in the first counting module 110. The second reference unit 305 includes: a second setting subunit 403, connected to the first counting unit 302 and the second counting unit 304, configured to, based on a second initial value, set a second preset value corresponding to the monitoring address transmitted by the first counting unit; and a second adjustment subunit 404, configured to receive an update signal and adjust the second preset value corresponding to the monitoring address retained in the second counting unit 304 based on the update signal, thereby achieving a positive correlation between the magnitude of the set second preset value and the number of second update cycles retained by the monitoring address in the second counting module 120.

[0061] In some embodiments, the second preset value set by the second setting subunit 403 for the monitoring address transmitted by the first counting unit 302 is the second initial value, that is, the monitoring address is not retained in the first counting module 110 for a certain duration, and the corresponding second preset value is set accordingly. In other embodiments, the second preset value set by the second setting subunit 403 for the monitoring address transmitted by the first counting unit 302 is the sum of the second initial value and the cumulative duration value, where the cumulative duration value is a parameter related to the number of first update cycles in which the monitoring address is retained in the first counting unit 302, that is, the monitoring address is retained in the first counting module 110 for a certain duration, and the corresponding second preset value is set accordingly.

[0062] In a specific example, the first preset value is the counting result of the third counter in the first counting unit 302. The first adjustment subunit 402 is configured to accumulate the third initial value to the third counter corresponding to the monitoring address retained in the first counting unit 302 based on the update signal. Correspondingly, the second preset value is the counting result of the fourth counter in the second counting unit 304. The second adjustment subunit 404 is configured to accumulate the fourth initial value to the fourth counter corresponding to the monitoring address retained in the second counting unit 304 based on the update signal.

[0063] refer to Figure 5For the first counting unit, the count value is the counting result of the first counter, used to represent the number of times the corresponding monitoring address is counted. The preset value, i.e., the first preset value, is the counting result of the third counter, used to represent the first record reference value of the corresponding monitoring address. Here, c represents the first initial value set by the first setting subunit 401, y represents the step size of each adjustment by the first adjustment subunit 402, and t1 to t5 represent the number of first update cycles in which the corresponding monitoring address exists. For monitoring addresses with a count value greater than or equal to the first preset value, i.e., word line addresses in the memory that have been opened a preset number of times, there is a risk of being maliciously attacked. It is necessary to refresh the adjacent rows of the corresponding monitoring address. The adjacent rows can be adjacent address rows such as +1 / -1, +2 / -2, etc. of the monitoring address. In addition, word line addresses that are continuously opened are more likely to cause data errors in adjacent storage areas. In this embodiment, the preset value corresponding to the monitoring address is gradually increased as the retention time of the monitoring address increases. That is, only word line addresses that are continuously opened have a higher probability of causing errors in the stored data of adjacent storage areas. They are the addresses that deserve more attention and should be retained and their adjacent rows refreshed. For the second counting unit, the count value is the counting result of the second counter, used to characterize the number of times the corresponding monitoring address is counted. The preset value, i.e., the second preset value, is the counting structure of the fourth counter, used to characterize the second record reference value of the corresponding monitoring address. Here, d represents the second initial value set by the second setting subunit 403, z represents the step size of each adjustment by the second adjustment subunit 404, and T6 to T12 represent the number of second update cycles existing for the corresponding monitoring address. For monitoring addresses with count values ​​less than the first preset value, i.e., the speed at which word line addresses are opened does not reach the standard of the first preset value, but may belong to word line addresses whose number of openings is continuously and slowly increasing, there is also a risk of being attacked. In this embodiment, the monitoring addresses released by the first counter are continued to be monitored by the second counter, and a second preset value less than the first preset value is set for the corresponding monitoring address, thereby monitoring word line addresses that are continuously and slowly opened, ensuring the accuracy of the stored data in each storage area.

[0064] It should be noted that there are multiple ways to perform supplementary refresh as mentioned above. It can be based on each update signal to perform supplementary refresh on the adjacent rows of the monitoring address corresponding to the first counter with the maximum count value stored in the first counting unit 302 and the monitoring address corresponding to the second counter with the maximum count value stored in the second counting unit 304; it can also be set to perform supplementary refresh on the adjacent rows of the monitoring address with the maximum count value every n update signals; it can also be set to refresh the adjacent rows of multiple monitoring addresses in a single supplementary refresh.

[0065] More specifically, the first initial value is set to 2. n The second initial value is set to 2. mThe third initial value is set to 2. p The fourth initial value is set to 2. q m, n, p, and q are positive integers greater than or equal to 1, and m > n, p > q; in a specific example, m and n can be set to 2, 3, 4, or 5, and p and q can be set to 1, 2, 3, or 4; correspondingly, the values ​​of m and n, p and q can be set to the same value or different values.

[0066] The working principle of the first counting module 110 and the second counting module 120 provided above is as follows: Figure 6 It should be noted that, Figure 6 The specific values ​​shown are only for those skilled in the art to understand the working principle of the first counting module 110 and the second counting module 120 provided in this embodiment, and do not constitute a limitation on this embodiment.

[0067] refer to Figure 6 and combined Figures 2-4When the judgment module 301 receives the monitoring address Address1 sampled by the sampling module 101, it generates a first control signal, and the first counting unit 302 controls the count value of the first counter corresponding to the monitoring address Address1 to increase by 1 (from 10 to 11); when the judgment module 301 receives the monitoring address Address6 sampled by the sampling module 101, it generates a second control signal, and the second counting unit 304 controls the count value of the first counter corresponding to the monitoring address Address6 to increase by 1 (from 12 to 13); when the first reference unit 303 and the second reference unit 305 receive the update signal, it indicates that the recorded monitoring address has existed for one more update cycle. The first reference unit 303 adjusts the first preset value configured for the monitoring address in the first counting unit 302, wherein the preset value of the monitoring address Address1 changes from 4+4*1 to 4+4*2, the preset value of the monitoring address Address2 changes from 4+4*0 to 4+4*1, and the preset value of the monitoring address Address3 changes from 4+4*0 to 4+4*1. The preset value of monitoring address Address4 changes from 4+4*0 to 4+4*1, and the preset value of monitoring address Address5 changes from 4+4*2 to 4+4*3. The second reference unit 305 adjusts the second preset value configured for the monitoring address in the second counting unit 304. The preset value of monitoring address Address6 changes from 2+2*3 to 2+2*4, the preset value of monitoring address Address7 changes from 2+2*0 to 2+2*1, the preset value of monitoring address Address8 changes from 2+2*7 to 2+2*8, and the preset value of monitoring address Address9 changes from 2+2*4 to 2+2*5. The preset value of monitoring address Address9 changes from 2+2*5 to 2+2*6. Word line addresses that are continuously enabled are more likely to cause data errors in adjacent memory areas. By setting the preset value corresponding to the monitoring address to gradually increase as the retention time of the monitoring address increases, only the adjacent rows of word line addresses that are continuously enabled have a greater probability of being retained and refreshed.Then, the processing module 102 compares the count value of each monitoring address with the preset value, retaining the monitoring addresses whose count value is greater than or equal to the preset value. For the first counting unit, the monitoring addresses whose count value is less than the preset value are transmitted to the second counting unit. For the second counting unit, the monitoring addresses whose count value is less than the preset value are released. After comparison, monitoring address Address5 in the first counting unit 302 is retained, and other monitoring addresses are transmitted to the second counting unit. The corresponding first counter and first preset value are reset. Monitoring address Address6 in the second counting unit 304 is retained, and other monitoring addresses are released. The corresponding second counter and second preset value are reset. In this embodiment, the corresponding count value and existence period of the monitoring address transmitted to the second counting unit are retained. That is, the count value 11 and existence period 2 corresponding to monitoring address Address1 are retained in the second counter unit. The second counting unit resets the second preset value to 2+2*2 based on period 2. 5 and the existence period 1 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*1 based on period 1. The count value 19 and the existence period 6 corresponding to the monitoring address Address3 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*6 based on period 6. The count value 1 and the existence period 1 corresponding to the monitoring address Address4 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*1 based on period 1. When the judgment module 301 receives the monitoring address Address7 sampled by the sampling module 101, since the monitoring address Address7 does not exist in the first counting module 110, the judgment module 301 generates a third control signal. At this time, the first counting module 110 adds the monitoring address Address7 and sets the count value of the first count value corresponding to the monitoring address Address7 to 1. The first reference unit 303 sets the preset value 4+4*0 for the monitoring address Address7.

[0068] In some embodiments, reference Figure 7The corresponding count value and existence period of the monitoring address transmitted to the second counting unit are reset to 0. That is, the count value 11 and existence period 2 corresponding to the monitoring address Address1 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 5 and existence period 1 corresponding to the monitoring address Address2 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 19 and existence period 6 corresponding to the monitoring address Address3 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 1 and existence period 1 corresponding to the monitoring address Address4 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0.

[0069] It should also be noted that, in the above example, after the first counting unit and the second counting unit simultaneously complete the comparison of the monitoring address based on the update signal, the first counting unit releases the monitoring address to the second counting unit, and the second counting unit releases the monitoring address at the same time; in some embodiments, it can be set that the first counting unit first completes the comparison of the monitoring address based on the update signal, releases the monitoring address to the second counting unit, and then the second counting unit releases the monitoring address based on the updated monitoring address and the update signal.

[0070] In the above implementation, the first initial value of the preset value of the monitoring address stored in the first counting module 110 is set to 4, and the third initial value for accumulation based on the update signal is set to 4. The second initial value of the preset value of the monitoring address stored in the second counting module 120 is set to 2, and the fourth initial value for accumulation based on the update signal is set to 2. When the update signal is received, the preset value of the retained monitoring address is first accumulated, and then the count value is compared with the preset value. In other implementations, when the update signal is received, the system can also be configured to first compare the count value with the preset value, and then accumulate the preset value of the retained monitoring address, so as to reduce the number of the third and fourth counters that the monitoring circuit needs to adjust, thereby reducing the power consumption of the monitoring circuit.

[0071] refer to Figure 8 , Figure 8 The upper diagram illustrates the monitoring data for the monitored address when the first counting module 110 and the second counter module 120 are present. The lower diagram illustrates the monitoring data for the monitored address when only the second counting module 110 is present. Solid lines represent the monitored addresses in the first counting module 110, and dashed lines represent the monitored addresses in the second counting module 120. Figure 8The example is used to count the number of times monitoring addresses A, B, C, D, E, P, Q, R, and S are recorded. Referring to the diagram below, in the first refresh cycle, the count value of monitoring addresses AB is greater than the first preset value for one cycle and is retained, with the count value corresponding to monitoring address A being the largest. At this time, the adjacent row of monitoring address A is refreshed, and the count value of monitoring address DEP is less than the first preset value for one cycle and is released. In the second refresh cycle, since monitoring address B has been retained for two cycles, the first preset value corresponding to monitoring address B is the first preset value for two cycles. The count value of monitoring address B is still greater than the first preset value for two cycles and is retained, and monitoring address B... When the corresponding count value is the largest, the adjacent row of monitoring address B is refreshed. The count value of the newly appearing monitoring address Q is less than the first count value of 1 cycle and is released. In the third refresh cycle, the count value of the newly appearing monitoring address C is greater than the first count value of 1 cycle and is retained. The count value corresponding to monitoring address C is the largest, and the adjacent row of monitoring address C is refreshed. The count value of the newly appearing monitoring address R is less than the first count value of 1 cycle and is released. In the fourth refresh cycle, the count value of the newly appearing monitoring address S is greater than the first preset value of 1 cycle and is retained. The count value corresponding to monitoring address S is the largest, and the adjacent row of monitoring address S is refreshed.Referring to the diagram above, in the first refresh cycle, the count value of monitored address AB in the first counting module 110 is greater than the first preset value for one cycle and is retained, and the count value corresponding to monitored address A is the largest. At this time, the adjacent row of monitored address A is refreshed, and the count value of monitored address DEP is less than the first preset value for one cycle and is released to the second counting module 120. In the second refresh cycle, since monitored address BDEP has been retained for two cycles, the first preset value corresponding to monitored address B in the first counting module 110 is the first preset value for two cycles. The count value of monitored address B is still greater than the first preset value for two cycles and is retained. The count value corresponding to monitoring address B is the largest, and the adjacent row of monitoring address B is refreshed. The count value of the newly appearing monitoring address Q is less than the first count value of 1 cycle and is released to the second counting module 120. In the second counting module 120, the second preset value corresponding to monitoring address DEP is the second preset value of 2 cycles. The count value of monitoring address DE is still greater than the second preset value of 2 cycles and is retained. The count value of monitoring address P is less than the second preset value of 2 cycles and is released. In the third refresh cycle, since monitoring address DE has been retained for 3 cycles and monitoring address Q has been retained for 2 cycles, the newly appearing row in the first counting module 110... The count value of monitoring address C is greater than the first count value of 1 cycle and is retained. The count value corresponding to monitoring address C is also the largest. The adjacent row of monitoring address C is refreshed. The count value of the newly appearing monitoring address R is less than the first count value of 1 cycle and is released to the second counting module 120. In the second counting module 120, the second preset value corresponding to monitoring address DE is the second preset value of 3 cycles. The count value of monitoring address DE is still greater than the second preset value of 3 cycles and is retained. The count value of monitoring address Q is less than the second preset value of 2 cycles and is released. In the fourth refresh cycle, since monitoring address DE has been retained for 4 cycles, the monitoring address... R has been retained for 2 cycles. In the first counting module 110, the count value of the newly appearing monitoring address S is greater than the first preset value of 1 cycle and is retained. In the second counting module 120, the second preset value corresponding to the monitoring address DE is the second preset value of 4 cycles. The count value of the monitoring address D is still greater than the second preset value of 4 cycles and is retained. Moreover, the count value corresponding to the monitoring address D is the largest. The adjacent row of the monitoring address S is refreshed. The count value of the monitoring address E is less than the second preset value of 4 cycles and is released. The second preset value corresponding to the monitoring address R is the second preset value of 2 cycles and is released. In this embodiment, by setting the second counting module 120, the word line address that is slowly and continuously increased in the number of times it is opened is monitored, so as to avoid the word line address that is slowly and continuously opened being masked by the word line address that is opened multiple times in a short period of time, thus ensuring the accuracy of the stored data in the storage area.

[0072] for Figure 8For example, the release of the monitored address in the second counter is delayed by one refresh cycle compared to the release of the monitored address by the first counter. That is, after the first and second counting units simultaneously complete the comparison of the monitored address based on the update signal, the first counting unit releases the monitored address to the second counting unit at the same time as the second counting unit releases the monitored address. In some embodiments, it can be set that the first counting unit first completes the comparison of the monitored address based on the update signal and then releases the monitored address to the second counting unit. Then, the second counting unit compares and releases the monitored address based on the updated monitored address and the update signal. In this case, the release of the monitored address in the second counter is performed synchronously with the release of the monitored address by the first counter. Based on the above discussion, it can be seen that the second counting module 120 is used to count word line addresses that are slowly and continuously increased in the number of times they are enabled. The count value of the corresponding monitored address needs to grow to the maximum after a certain number of cycles. Figure 8 In this example, the monitoring address in the first counting module 110 is refreshed three times before the monitoring address in the second counting module 120 is refreshed once, meaning the refresh ratio of the first counting module 110 and the second counting module 120 is 3:1. It should be noted that the refresh ratio setting of the first counting module 110 and the second counting module 120 in the above example does not constitute a limitation on this embodiment. In other embodiments, the refresh ratio of the first counting module 120 and the second counting module 120 can be set to 5:1, 7:1, or 10:1.

[0073] In addition, in some embodiments, the first preset value and the second preset value also correspond to a maximum value. The values ​​of the third counter and the fourth counter will not continue to accumulate after reaching the maximum value. When the count value of the first counter or the second counter corresponding to the monitoring address is greater than or equal to the maximum value, it proves that the data in the storage area adjacent to the monitoring address is prone to errors and needs to be refreshed. At this time, there is no need to accumulate the preset value again, so as to avoid unnecessary value updates of the third counter and the fourth counter.

[0074] Regarding the update signal described above, in some embodiments, the update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, i.e., the original signal of the memory. The count adjustment signal is provided within the interval between two adjacent refresh signals. The count adjustment signal is a newly defined signal within the refresh cycle, used to update the monitoring addresses reserved in the first counting module 110 and the second counting module 120 based on the count value and a preset value. By using the refresh signal and the count adjustment signal together as update signals, the frequency at which the processing module 102 adjusts the monitoring addresses in the first counting module 110 and the second counting module 120 is increased, thereby further reducing the number of counters required to drive the monitoring circuit. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line addresses is increased, preventing sudden multiple enablements of certain enabled word line addresses within a short period of time. It should be noted that, in addition to the refresh signal, the memory can also perform refresh operations on the monitoring addresses based on other special refresh commands, such as the refresh command RFM.

[0075] In addition, for the count adjustment signal within the same refresh cycle, the number of count adjustment signals can be appropriately adjusted according to the application scenario required by the memory, thereby adaptively adjusting the frequency at which the processing module 102 releases the monitored address in the first count module 110.

[0076] For the memory to which the monitoring circuit provided in this embodiment belongs, the memory refresh operation further includes: refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the first counter among the monitoring addresses stored in the first counting module 110, and refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the second counter among the monitoring addresses stored in the second counting module 120, where y and z are positive integers greater than or equal to 1. After refreshing, the refreshed monitoring addresses in the first counting module 110 and the second counting module 120 are released, and the first counter and the first preset value (third counter) corresponding to the monitoring address corresponding to the refreshed adjacent row are reset, or the second counter and the second preset value (fourth counter) corresponding to the monitoring address corresponding to the refreshed adjacent row are reset.

[0077] In the monitoring circuit provided in this embodiment, the processing module 102 continuously releases monitoring addresses whose count values ​​in the first counting module 110 are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the first counting module 110, so that the first counting module 110 can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters required by the monitoring circuit is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module 102 continues to count the addresses released by the first counting module 110 through the second counting module 120, so as to continue to monitor word line addresses that are slowly and continuously enabled, and avoid the word line addresses that are slowly and continuously enabled being masked by word line addresses that are enabled multiple times in a short period of time, so as to ensure the accuracy of the stored data in each memory area.

[0078] It should be noted that the features disclosed in the monitoring circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new monitoring circuit embodiments.

[0079] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0080] Another embodiment of this disclosure provides a refresh method applied to the monitoring circuit provided in the above embodiments. This method achieves supplementary refresh of specific rows in the storage area with lower power consumption, ensuring the accuracy of the stored data in each storage area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0081] Figure 9 This is a flowchart illustrating each step of the refresh method provided in this embodiment. The refresh method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0082] refer to Figure 9 Refresh methods include:

[0083] Step S1: Obtain the monitoring address and check whether the monitoring address has been stored; if the monitoring address has been stored, proceed to step S2; if the monitoring address has not been stored, proceed to step S3.

[0084] The monitoring address is the address of the enabled word line in the memory. If the monitoring address has been stored, it proves that the currently enabled word line address has been counted, and counting needs to continue based on step S2. If the monitoring address has not been stored, it proves that the currently enabled word line address has not been counted, and the first counter needs to be configured to start counting based on step S3, and the corresponding preset value needs to be configured. It should be noted that the count value of the first counter and the preset value are both initially set to 0. After the count value of the first counter and the preset value are reset, they are also reset to 0. Therefore, after adding a monitoring address, the first counter, the count value, and the preset value need to be assigned values.

[0085] In some embodiments, step S1 obtains the monitoring address based on sampling at a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. That is, the sampling module 101 samples the monitoring address once every x word lines of memory are enabled. By setting the sampling probability, the number of word lines to be obtained is reduced, thus further reducing the power consumption required for refresh through sampling detection. In some embodiments, x is a positive integer less than or equal to 16; in a specific example, x can be set to a positive integer such as 14, 12, 10, 8, 6, 4, or 2.

[0086] Step S2: Increment the count value of the first counter corresponding to the monitoring address by 1, or increment the count value of the second counter corresponding to the monitoring address by 1, and then execute step S4.

[0087] For the first and second counters, their capacities are set based on the refresh command reception interval, the preset sampling interval, and the word line enable interval in the memory. Specifically, in the DDR4 standard, under normal operating temperature, for a 16GB memory in 1X refresh mode, the word line enable interval tRC = 45ns, the preset sampling interval tREFC = 550ns, and the refresh command reception interval tREFI = 7.8us. At this time, in the burst transfer mode of the memory, the number of word line addresses that can be enabled by 9*tREFI is 9*(tREFI-tREFC) / tRC = 161. If the capacities of the first and second counters are b, it is necessary to ensure 2 b >161, meaning b is at least 8. In this example, the capacity of the first counter and the second counter is set to 8 bits. It should be noted that the numerical examples in this example are only for those skilled in the art to understand how the capacity of the first counter is set, and do not constitute a limitation on this embodiment.

[0088] Step S3: Use a new first counter to count the monitoring address, set the count value of the first counter to 1, and set the corresponding first preset value for the monitoring address, then execute step S4.

[0089] Specifically, the newly added monitoring address is obtained, and the preset value corresponding to the monitoring address is set based on the first initial value.

[0090] For steps S1 to S3, in one example, refer to Figure 6 and combined Figures 2-4 When the judgment module 301 receives the monitoring address Address1 sampled by the sampling module 101, it generates a first control signal, and the first counting unit 302 controls the count value of the first counter corresponding to the monitoring address Address1 to increase by 1 (from 10 to 11); when the judgment module 301 receives the monitoring address Address6 sampled by the sampling module 101, it generates a second control signal, and the second counting unit 304 controls the count value of the first counter corresponding to the monitoring address Address6 to increase by 1 (from 12 to 13); when the judgment module 301 receives the monitoring address Address7 sampled by the sampling module 101, since the monitoring address Address7 does not exist in the first counting module 110, the judgment module 301 generates a third control signal. At this time, the first counting module 110 adds the monitoring address Address7 and sets the count value of the first counter corresponding to the monitoring address Address7 to 1. The first reference unit 303 sets a preset value of 4+4*0 for the monitoring address Address7.

[0091] Step S4: Adjust the first preset value corresponding to the retained monitoring address based on the update signal, and compare the count value of the first counter corresponding to each monitoring address with the first preset value. If the count value of the first counter is greater than or equal to the first preset value, then proceed to step S5. If the count value of the first counter is less than the first preset value, then proceed to step S6.

[0092] In a specific example, refer to Figure 5For the first counting unit, the count value is the counting result of the first counter, used to represent the number of times the corresponding monitoring address is counted. The preset value, i.e., the first preset value, is the counting result of the third counter, used to represent the first record reference value of the corresponding monitoring address. Here, c represents the first initial value set by the first setting subunit 401, y represents the step size of each adjustment by the first adjustment subunit 402, and t1 to t5 represent the number of first update cycles in which the corresponding monitoring address exists. For monitoring addresses with a count value greater than or equal to the first preset value, i.e., word line addresses in the memory that have been opened a preset number of times, there is a risk of being maliciously attacked. It is necessary to refresh the adjacent rows of the corresponding monitoring address. The adjacent rows can be adjacent address rows such as +1 / -1, +2 / -2, etc. of the monitoring address. In addition, word line addresses that are continuously opened are more likely to cause data errors in adjacent storage areas. In this embodiment, the preset value corresponding to the monitoring address is gradually increased as the retention time of the monitoring address increases. That is, only word line addresses that are continuously opened have a higher probability of causing errors in the stored data of adjacent storage areas. They are the addresses that deserve more attention and should be retained and their adjacent rows refreshed. For the second counting unit, the count value is the counting result of the second counter, used to characterize the number of times the corresponding monitoring address is counted. The preset value, i.e., the second preset value, is the counting structure of the fourth counter, used to characterize the second record reference value of the corresponding monitoring address. Here, d represents the second initial value set by the second setting subunit 403, z represents the step size of each adjustment by the second adjustment subunit 404, and T6 to T12 represent the number of second update cycles existing for the corresponding monitoring address. For monitoring addresses with count values ​​less than the first preset value, i.e., the speed at which word line addresses are opened does not reach the standard of the first preset value, but may belong to word line addresses whose number of openings is continuously and slowly increasing, there is also a risk of being attacked. In this embodiment, the monitoring addresses released by the first counter are continued to be monitored by the second counter, and a second preset value less than the first preset value is set for the corresponding monitoring address, thereby monitoring word line addresses that are continuously and slowly opened, ensuring the accuracy of the stored data in each storage area.

[0093] More specifically, the first initial value is set to 2. n The second initial value is set to 2. m The third initial value is set to 2. p The fourth initial value is set to 2. q m, n, p, and q are positive integers greater than or equal to 1, and m > n, p > q; in a specific example, m and n can be set to 2, 3, 4, or 5, and p and q can be set to 1, 2, 3, or 4; correspondingly, the values ​​of m and n, p and q can be set to the same value or different values.

[0094] Step S5: Retain the monitoring address, the count value of the first counter corresponding to the monitoring address, and the first preset value, and continue to execute step S1.

[0095] Specifically, for the retained monitoring address, the third counter corresponding to the retained monitoring address is accumulated based on the third initial value, that is, the retained monitoring address after adjustment based on the update signal is obtained, and the third counter corresponding to the corresponding monitoring address is accumulated based on the third initial value.

[0096] Step S6: Use a new second counter to count the monitoring address, set a corresponding second preset value for the monitoring address, reset the first counter and preset value corresponding to the monitoring address, and continue to execute step S1.

[0097] In some embodiments, step S4 further includes: adjusting the second preset value corresponding to the retained monitoring address based on the update signal, and comparing the count value of the second counter corresponding to each monitoring address with the second preset value. If the count value of the second counter is greater than or equal to the second preset value, then step S7 is executed; if the count value of the second counter is less than the second preset value, then step S8 is executed.

[0098] Step S7: Retain the monitoring address, the count value of the second counter corresponding to the monitoring address, and the second preset value, and continue to execute step S1.

[0099] Specifically, for the retained monitoring address, the fourth counter corresponding to the retained monitoring address is accumulated based on the fourth initial value, that is, the retained monitoring address after adjustment based on the update signal is obtained, and the fourth counter corresponding to the corresponding monitoring address is accumulated based on the fourth initial value.

[0100] Step S8: Release the monitoring address and reset the second counter corresponding to the monitoring address, then continue to execute step S1.

[0101] For steps S4 to S8, in one example, refer to... Figure 6 and combined Figures 2-4When the first reference unit 303 and the second reference unit 305 receive the update signal, it indicates that the recorded monitoring address has been updated for one more cycle. The first reference unit 303 adjusts the first preset value configured for the monitoring address in the first counting unit 302. Specifically, the preset value of monitoring address Address1 changes from 4+4*1 to 4+4*2, the preset value of monitoring address Address2 changes from 4+4*0 to 4+4*1, the preset value of monitoring address Address3 changes from 4+4*5 to 4+4*6, the preset value of monitoring address Address4 changes from 4+4*0 to 4+4*1, and the preset value of monitoring address Address5 changes from 4+4*2 to 4+4*3. The second reference unit 305 adjusts the second counting unit 302. 4. The second preset value is configured for the monitoring address. The preset value of monitoring address Address6 changes from 2+2*3 to 2+2*4, the preset value of monitoring address Address7 changes from 2+2*0 to 2+2*1, the preset value of monitoring address Address8 changes from 2+2*7 to 2+2*8, the preset value of monitoring address Address9 changes from 2+2*4 to 2+2*5, and the preset value of monitoring address Address9 changes from 2+2*5 to 2+2*6. A continuously enabled word line address is more likely to cause data errors in adjacent memory areas. By setting the preset value of the monitoring address to gradually increase as the retention time of the monitoring address increases, only the adjacent rows of a continuously enabled word line address have a greater probability of being retained and refreshed.Then, the processing module 102 compares the count value of each monitoring address with a preset value, retaining monitoring addresses whose count value is greater than or equal to the preset value. For the first counting unit, monitoring addresses whose count value is less than the preset value are transmitted to the second counting unit. For the second counting unit, monitoring addresses whose count value is less than the preset value are released. After comparison, monitoring address Address5 in the first counting unit 302 is retained, and other monitoring addresses are transmitted to the second counting unit. The corresponding first counter and first preset value are reset. Monitoring address Address6 in the second counting unit 304 is retained, and other monitoring addresses are released. The corresponding second counter and second preset value are also reset. In this embodiment, the corresponding count value and existence period of the monitoring address transmitted to the second counting unit are retained. The count value 11 and existence period 2 corresponding to monitoring address Address1 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*2 based on period 2. The count value 5 and existence period 1 corresponding to monitoring address Address2 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*1 based on period 1. The count value 19 and existence period 6 corresponding to monitoring address Address3 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*6 based on period 6. The count value 1 and existence period 1 corresponding to monitoring address Address4 are retained in the second counter unit. The second counter unit resets the second preset value to 2+2*1 based on period 1.

[0102] In some embodiments, reference Figure 7 The corresponding count value and existence period of the monitoring address transmitted to the second counting unit are reset to 0. That is, the count value 11 and existence period 2 corresponding to the monitoring address Address1 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 5 and existence period 1 corresponding to the monitoring address Address2 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 19 and existence period 6 corresponding to the monitoring address Address3 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0. The count value 1 and existence period 1 corresponding to the monitoring address Address4 are not retained in the second counter unit. The second counting unit resets the second preset value to 2+2*0 based on period 0.

[0103] It should also be noted that, in the above example, after the first counting unit and the second counting unit simultaneously complete the comparison of the monitoring address based on the update signal, the first counting unit releases the monitoring address to the second counting unit, and the second counting unit releases the monitoring address at the same time; in some embodiments, it can be set that the first counting unit first completes the comparison of the monitoring address based on the update signal, releases the monitoring address to the second counting unit, and then the second counting unit releases the monitoring address based on the updated monitoring address and the update signal.

[0104] In the above implementation, the first initial value for the first preset value is set to 4, the third initial value for accumulation based on the update signal is set to 4, the second initial value for the second preset value is set to 2, and the fourth initial value for accumulation based on the update signal is set to 2. When the update signal is received, the preset value of the reserved monitoring address is first accumulated, and then the count value is compared with the preset value. In other implementations, when the update signal is received, the count value can also be compared with the preset value first, and then the preset value of the reserved monitoring address is accumulated, so as to reduce the number of the third and fourth counters that the monitoring circuit needs to adjust, thereby reducing the power consumption of the monitoring circuit.

[0105] In addition, in some embodiments, the first preset value and the second preset value also correspond to a maximum value. The values ​​of the third counter and the fourth counter will not continue to accumulate after reaching the maximum value. When the count value of the first counter or the second counter corresponding to the monitoring address is greater than or equal to the maximum value, it proves that the data in the storage area adjacent to the monitoring address is prone to errors and needs to be refreshed. At this time, there is no need to accumulate the preset value again, so as to avoid unnecessary value updates of the third counter and the fourth counter.

[0106] Regarding the update signal described above, in some embodiments, the update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, i.e., the original signal of the memory. The count adjustment signal is provided between two adjacent refresh signals. The count adjustment signal is a newly defined signal within the refresh cycle, used to update the reserved monitoring address based on the count value and a preset value. By using the refresh signal and the count adjustment signal together as the update signal, the frequency of releasing the monitoring address is increased, thereby further reducing the number of counters that the monitoring circuit needs to drive. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line address is increased, preventing the sudden multiple enabling of certain enabled word line addresses in a short period of time. It should be noted that, in addition to the refresh signal, the memory can also perform the refresh operation of the monitoring address based on other special refresh commands, such as the refresh command RFM.

[0107] In addition, for the count adjustment signal within the same refresh cycle, the number of count adjustment signals can be appropriately adjusted according to the application scenario required by the memory, thereby adaptively adjusting the frequency of releasing the monitoring address.

[0108] The refresh method provided in this embodiment continuously releases monitoring addresses with count values ​​less than a preset value based on the update signal, that is, continuously releases recorded noise addresses. This allows the counting module to record new monitoring addresses. By avoiding the waste of counter resources caused by continuous recording of noise addresses, the number of first counters required to drive the monitoring circuit is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, by continuing to count the released addresses, the slow and continuously enabled word line addresses are monitored, preventing the slow and continuously enabled word line addresses from being masked by word line addresses that are enabled multiple times in a short period of time, thus ensuring the accuracy of the stored data in each memory area.

[0109] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0110] It should be noted that the features disclosed in the refresh method provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh method embodiments.

[0111] Another embodiment of this disclosure provides a memory that obtains the word line address to be refreshed based on the monitoring circuit provided in the above embodiments, and realizes supplementary refresh of a specific row in the memory area with low power consumption. It also monitors word line addresses that are slowly and continuously enabled, ensuring the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0112] Specifically, for the monitoring circuit, the processing module continuously releases monitoring addresses whose count values ​​in the first counting module are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the first counting module, so that the first counting module can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module continues to count the addresses released by the first counting module through the second counting module, so as to continue to monitor word line addresses that are slowly and continuously enabled, and avoid the word line addresses that are slowly and continuously enabled being masked by word line addresses that are enabled multiple times in a short period of time, so as to ensure the accuracy of the stored data in each memory area.

[0113] In some embodiments, the memory can be a storage cell or device based on a semiconductor device or component. For example, the memory device can be volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate type fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it can be non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0114] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A monitoring circuit, characterized in that, include: The sampling module is configured to sample the initial address to obtain the monitoring address and output the monitoring address, wherein the initial address is the word line address that is enabled in the memory where the monitoring circuit is located; The first counting module, connected to the sampling module, is configured to adjust the count value of the first counter corresponding to the received monitoring address based on the received monitoring address. The second counting module, connected to the sampling module and the first counting module, is configured to adjust the count value of the second counter corresponding to the received monitoring address based on the received monitoring address. The processing module, connected to the first counting module and the second counting module, is configured to compare the count value of the first counter corresponding to each monitoring address in the first counting module with the corresponding first preset value based on the update signal, and determine whether to transmit the monitoring address to the second counting module based on the comparison result of the count value of the first counter and the first preset value. Based on the update signal, the count value of the second counter corresponding to each monitoring address in the second counting module is compared with the corresponding second preset value, and based on the comparison result of the count value of the second counter and the second preset value, it is determined whether to retain the monitoring address; Wherein, the second preset value is less than the first preset value.

2. The monitoring circuit according to claim 1, characterized in that, The processing module includes: A first processing unit, connected to the first counting module, is configured to compare the count value of a first counter corresponding to each monitoring address in the first counting module with a first preset value based on an update signal; wherein, if the count value of the first counter is greater than or equal to the first preset value, the monitoring address is retained; if the count value of the first counter is less than the first preset value, the monitoring address is transmitted to the second counting module, and the first counter and the first preset value corresponding to the monitoring address are reset. The second processing unit, connected to the second counting module, is configured to compare the count value of the second counter corresponding to each monitoring address in the second counting module with the second preset value based on the update signal; wherein, if the count value of the second counter is greater than or equal to the second preset value, the monitoring address is retained; if the count value of the second counter is less than the second preset value, the monitoring address is released, and the second counter and the second preset value corresponding to the monitoring address are reset.

3. The monitoring circuit according to claim 1, characterized in that, Also includes: The judgment module, connected to the sampling module, is configured to determine whether the acquired monitoring address is stored based on the acquired monitoring address and the stored monitoring address. If the monitoring address is stored by the first counting module, a first control signal is generated; if the monitoring address is stored by the second counting module, a second control signal is generated; if the monitoring address is not stored, a third control signal is generated. The first counting module includes: The first counting unit, connected to the sampling module and the judgment module, is configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on the first control signal, or configure a corresponding first counter for the monitoring address and set the count value of the first counter to 1 based on the third control signal. The first reference unit, connected to the first counting unit and the judgment module, is configured to configure the first preset value for the monitoring address based on the third control signal, and the configured preset value is stored in the first counting unit, and the first preset value is adjusted based on the update signal. The second counting module includes: The second counting unit, connected to the first counting unit, the sampling module, and the judgment module, is configured to increment the count value of the second counter corresponding to the monitoring address by 1 based on the second control signal, configure a corresponding second counter for the monitoring address transmitted by the first counting unit, and set the count value of the second counter. The second reference unit, connected to the first counting unit and the second counting unit, is configured to configure the second preset value for the monitoring address transmitted by the first counting unit, and the configured second preset value is stored in the second counting unit, and the second preset value is adjusted based on the update signal.

4. The monitoring circuit according to claim 3, characterized in that, Setting the count value of the second counter includes: The count value of the second counter is set based on the count value of the first counter corresponding to the monitoring address; Alternatively, the count value of the second counter corresponding to the monitoring address can be set to 0.

5. The monitoring circuit according to claim 3, characterized in that, The value of the first preset value is positively correlated with the number of first update cycles in which the monitoring address is retained in the first counting module; The value of the second preset value is positively correlated with the number of second update cycles in which the monitoring address is retained in the second counting module, or with the sum of the number of first update cycles and the number of second update cycles in which the monitoring address is retained. Wherein, the first update period and the second update period are the interval time between adjacent update signals.

6. The monitoring circuit according to claim 5, characterized in that, include: The first reference unit includes: The first setting subunit, connected to the first counting unit and the judgment module, is configured to, in response to the third control signal, set the first preset value corresponding to the monitoring address based on the first initial value; The first adjustment subunit is configured to receive the update signal and adjust the first preset value corresponding to the monitoring address retained in the first counting unit based on the update signal. The second reference unit includes: The second setting subunit, connected to the first counting unit and the second counting unit, is configured to set the second preset value corresponding to the monitoring address transmitted by the first counting unit based on the second initial value; The second adjustment subunit is configured to receive the update signal and adjust the second preset value corresponding to the monitoring address retained in the second counting unit based on the update signal.

7. The monitoring circuit according to claim 6, characterized in that, include: The first preset value is the counting result of the third counter in the first counting unit; The step of adjusting the first preset value corresponding to the monitoring address retained in the first counting unit based on the update signal includes: based on the update signal, accumulating the third initial value to the third counter corresponding to the monitoring address retained in the first counting unit; The second preset value is the counting result of the fourth counter in the second counting unit; The step of adjusting the second preset value corresponding to the monitoring address retained in the second counting unit based on the update signal includes: based on the update signal, accumulating the fourth initial value to the fourth counter corresponding to the monitoring address retained in the second counting unit.

8. The monitoring circuit according to claim 7, characterized in that, The first initial value is set to 2n, the second initial value is set to 2m, the third initial value is set to 2p, and the fourth initial value is set to 2q, where m, n, p, and q are positive integers greater than or equal to 1, and m > n and p > q.

9. The monitoring circuit according to claim 1, characterized in that, The sampling module obtains the monitoring address based on a preset interval, wherein the preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer.

10. The monitoring circuit according to claim 9, characterized in that, x is a positive integer less than or equal to 16.

11. The monitoring circuit according to claim 1, characterized in that, include: The update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, and the count adjustment signal is provided within the interval between two adjacent refresh signals.

12. The monitoring circuit according to claim 1, characterized in that, include: The refresh operation of the memory further includes: refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the first counter in the monitoring addresses retained in the first counting module, and refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the second counter in the monitoring addresses retained in the second counting module, where y and z are positive integers greater than or equal to 1; After refreshing, the monitoring addresses corresponding to the refreshed adjacent rows in the first and second counting modules are released, and the first counter and the first preset value corresponding to the monitoring address corresponding to the refreshed adjacent row, or the second counter and the second preset value corresponding to the refreshed monitoring address are reset.

13. The monitoring circuit according to claim 3, characterized in that, include: The first counting unit is further configured to discard newly added monitoring addresses based on the third control signal when each of the first counters in the first counting unit has a corresponding monitoring address. The second counting unit is further configured to discard the monitoring address transmitted by the first counting unit when each of the second counters in the second counting unit has a corresponding monitoring address.

14. A refresh method, applied to the monitoring circuit according to any one of claims 1 to 13, characterized in that, include: Step S1: Obtain the monitoring address and check whether the monitoring address has been stored. If the monitoring address has been stored, proceed to step S2. If the monitoring address has not been stored, proceed to step S3. Step S2: Increment the count value of the first counter corresponding to the monitoring address by 1, or increment the count value of the second counter corresponding to the monitoring address by 1; Step S3: Use a new first counter to count the monitored address, set the count value of the first counter to 1, and set a corresponding first preset value for the monitored address; Step S4: Adjust the first preset value corresponding to the retained monitoring address based on the update signal, and compare the count value of the first counter corresponding to each monitoring address with the first preset value. If the count value of the first counter is greater than or equal to the first preset value, then proceed to step S5. If the count value of the first counter is less than the first preset value, then proceed to step S6. Step S5: Retain the monitoring address, the count value of the first counter corresponding to the monitoring address, and the first preset value, and continue to execute step S1; Step S6: Use a new second counter to count the monitoring address. The count value of the second counter is the same as the count value of the first counter corresponding to the monitoring address. Set a corresponding second preset value for the monitoring address, reset the first counter and the first preset value corresponding to the monitoring address, and continue to execute step S1.

15. The refresh method according to claim 14, characterized in that, include: Step S4 further includes: adjusting the second preset value corresponding to the retained monitoring address based on the update signal, and comparing the count value of the second counter corresponding to each monitoring address with the second preset value. If the count value of the second counter is greater than or equal to the second preset value, then step S7 is executed; if the count value of the second counter is less than the second preset value, then step S8 is executed. Step S7: Retain the monitoring address, the count value of the second counter corresponding to the monitoring address, and the second preset value, and continue to execute step S1; Step S8: Release the monitoring address and reset the second counter corresponding to the monitoring address, then continue executing step S1.

16. The refresh method according to claim 14, characterized in that, include: Setting a corresponding first preset value for the monitoring address includes: obtaining a newly added monitoring address and setting a first preset value corresponding to the newly added monitoring address based on a first initial value; The first preset value corresponding to the monitoring address that is adjusted and retained based on the update signal includes: the first preset value corresponding to the monitoring address that is accumulated and retained based on the third initial value; Setting a corresponding second preset value for the monitoring address includes: obtaining the monitoring address and setting a second preset value corresponding to the monitoring address based on a second initial value; The second preset value corresponding to the monitoring address that is adjusted and retained based on the update signal includes: the second preset value corresponding to the monitoring address that is accumulated and retained based on the fourth initial value.

17. A memory, characterized in that, The word line address to be refreshed is obtained based on the monitoring circuit according to any one of claims 1 to 13.

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