Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a source-drain recess in a channel stack on both sides of a dummy gate structure of a first region and a second region; removing a partial thickness of a sacrificial layer exposed by a sidewall of the source-drain recess in a length direction of the channel layer, so as to form a groove between an adjacent channel layer and a remaining sacrificial layer, or between a protruding portion and the adjacent channel layer and the remaining sacrificial layer; forming an inner sidewall in the groove of the first region and the second region; forming a first source-drain doped layer in the source-drain recess of the first region, the first source-drain doped layer being in contact with a sidewall of the inner sidewall; and forming a second source-drain doped layer in the source-drain recess of the second region, the second source-drain doped layer being in contact with the sidewall of the inner sidewall. The embodiment simplifies the process flow and improves the process integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects.

[0004] However, the current process for forming fully enclosed gate transistors is quite complex. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which simplifies the process flow.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, wherein the first type MOS transistor and the second type MOS transistor have different channel conductivity types; the substrate includes a substrate and a protrusion protruding from the substrate, wherein one or more channel stacks are formed on the protrusions in a bottom-up manner, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure spanning the channel stacks; and in the first region... Source / drain grooves are formed in the channel stacks on both sides of the pseudo-gate structure in the first and second regions. Along the length of the channel layer, a portion of the exposed thickness of the sacrificial layer on the sidewall of the source / drain groove is removed, so that a trench is formed between the adjacent channel layer and the remaining sacrificial layer, or between the protrusion and the adjacent channel layer and the remaining sacrificial layer. Inner sidewalls are formed in the trenches of the first and second regions. A first source / drain doped layer is formed in the source / drain groove of the first region, and the first source / drain doped layer is in contact with the sidewall of the inner sidewall. A second source / drain doped layer is formed in the source / drain groove of the second region, and the second source / drain doped layer is in contact with the sidewall of the inner sidewall.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by the embodiments of the present invention, source and drain grooves are formed in the channel stack on both sides of the pseudo-gate structure of the first region and the second region. Then, along the length of the channel layer, a portion of the exposed thickness of the sacrificial layer of the source and drain groove sidewalls is removed to form a trench. Afterward, an inner sidewall is formed in the trench of the first region and the second region, thereby integrating the process of forming the inner sidewall of the first region and the second region together. Compared with the scheme of forming the trench and inner sidewall of the first region and the trench and inner sidewall of the second region separately in different process steps, the embodiments of the present invention simplify the process flow and improve the process integration. Attached Figure Description

[0009] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] As the background technology shows, the current process for forming fully enclosed gate transistors is quite complex. This paper analyzes the reasons for this complexity by combining a semiconductor structure formation method.

[0012] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 The substrate includes a first region I for forming a first type MOS transistor and a second region II for forming a second type MOS transistor, wherein the first type MOS transistor and the second type MOS transistor have different channel conductivity types; the substrate includes a substrate 1 and a protrusion 2 protruding from the substrate 1, wherein one or more channel stacks 5 are formed on the protrusion 2 in a bottom-up manner, and each channel stack 5 includes a sacrificial layer 3 and a channel layer 4 located on the sacrificial layer 3; a pseudo-gate structure 6 is formed across the channel stacks 5.

[0014] refer to Figure 2 A first source / drain groove 7 is formed in the channel stack 5 on both sides of the pseudo-gate structure 6 in the first region I.

[0015] refer to Figure 3Along the length of the channel layer 4, a portion of the thickness of the sacrificial layer 3 exposed on the sidewall of the first source drain groove 7 is removed, so that the adjacent channel layer 4 and the remaining sacrificial layer 3, or the protrusion 2 and the adjacent channel layer 4 and the remaining sacrificial layer 3, form a first groove (not shown); a first inner sidewall 71 is formed in the first groove.

[0016] refer to Figure 4 After the first inner sidewall 71 is formed, the first source / drain doped layer 72 is formed in the first source / drain groove 7.

[0017] Reference Figure 5 After the first source / drain doped layer 72 is formed, a second source / drain groove 8 is formed in the channel stack 5 on both sides of the pseudo-gate structure 6 in the second region II.

[0018] refer to Figure 6 Along the length of the channel layer 4, a portion of the thickness of the sacrificial layer 3 exposed on the sidewall of the second source drain groove 8 is removed, so that the adjacent channel layer 4 and the remaining sacrificial layer 3, or the protrusion 2 and the adjacent channel layer 4 and the remaining sacrificial layer 3, form a second groove (not shown in the figure); a second inner sidewall 81 is formed in the second groove.

[0019] Reference Figure 7 After the second inner sidewall 81 is formed, a second source / drain doped layer 82 is formed in the second source / drain groove 8.

[0020] The above-mentioned semiconductor structure formation method involves forming the first source / drain groove 7, the first trench and the first inner sidewall 71, and forming the second source / drain groove 8, the second trench and the second inner sidewall 81, which requires multiple photolithography, etching and deposition processes, making the process flow complex.

[0021] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, wherein the first type MOS transistor and the second type MOS transistor have different channel conductivity types; the substrate includes a substrate and a protrusion protruding from the substrate, wherein one or more channel stacks are formed on the protrusions in a bottom-to-top manner, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure spanning the channel stacks; and in the first region... Source / drain grooves are formed in the channel stacks on both sides of the pseudo-gate structure in the first and second regions. Along the length of the channel layer, a portion of the exposed thickness of the sacrificial layer on the sidewall of the source / drain groove is removed, so that a trench is formed between the adjacent channel layer and the remaining sacrificial layer, or between the protrusion and the adjacent channel layer and the remaining sacrificial layer. Inner sidewalls are formed in the trenches of the first and second regions. A first source / drain doped layer is formed in the source / drain groove of the first region, and the first source / drain doped layer is in contact with the sidewall of the inner sidewall. A second source / drain doped layer is formed in the source / drain groove of the second region, and the second source / drain doped layer is in contact with the sidewall of the inner sidewall.

[0022] In the semiconductor structure formation method provided by the embodiments of the present invention, source and drain grooves are formed in the channel stack on both sides of the pseudo-gate structure of the first region and the second region. Then, along the length of the channel layer, a portion of the exposed thickness of the sacrificial layer of the source and drain groove sidewalls is removed to form a trench. Afterward, an inner sidewall is formed in the trench of the first region and the second region, thereby integrating the process of forming the inner sidewall of the first region and the second region together. Compared with the scheme of forming the trench and inner sidewall of the first region and the trench and inner sidewall of the second region separately in different process steps, the embodiments of the present invention simplify the process flow and improve the process integration.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0025] refer to Figure 8 The substrate includes a first region I for forming a first type MOS transistor and a second region II for forming a second type MOS transistor, wherein the first type MOS transistor and the second type MOS transistor have different channel conductivity types; the substrate includes a substrate 100 and a protrusion 110 protruding from the substrate 100, and one or more channel stacks 210 are formed on the protrusion 110 in a bottom-up manner, each channel stack 210 including a sacrificial layer 20 and a channel layer 30 located on the sacrificial layer 20.

[0026] The substrate serves as a process platform for subsequent fabrication processes. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0027] As an example, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor. In other embodiments, the first type of MOS transistor may also be an NMOS transistor, and the second type of MOS transistor may be a PMOS transistor accordingly.

[0028] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0029] In this embodiment, the protrusion 110 and the substrate 100 are an integral structure, and the material of the protrusion 110 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0030] In this embodiment, the protrusion 110 is a fin-like structure that extends laterally.

[0031] Among them, the channel stack 210 provides a process basis for the subsequent formation of the channel layer 30 with suspended space partition.

[0032] Specifically, the channel layer 30 provides a conductive channel for the field-effect transistor, and the sacrificial layer 20 supports the second channel layer 30, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the channel layer 30. The sacrificial layer 20 also occupies space for the subsequent formation of the gate structure.

[0033] In this embodiment, the channel layer 30 of the first region I and the channel layer 30 of the second region II are made of the same material, and the sacrificial layer 20 of the first region I and the sacrificial layer 20 of the second region II are made of the same material.

[0034] As an example, the material of the channel layer 30 is Si, and the material of the sacrificial layer 20 is SiGe. In the subsequent removal of the sacrificial layer 20, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 20 to SiGe and the material of the channel layer 30 to Si, the impact of the removal process of the sacrificial layer 20 on the channel layer 30 can be effectively reduced, thereby improving the quality of the channel layer 30 and thus helping to improve device performance.

[0035] In other embodiments, the channel layer may also be made of SiGe, and the sacrificial layer may be made of Si.

[0036] In other embodiments, the material of the channel layer in the first region may be different from the material of the channel layer in the second region, and correspondingly, the material of the sacrificial layer in the first region may be different from the material of the sacrificial layer in the second region.

[0037] As an example, the number of channel stacks 210 is three. In other embodiments, the number of channel stacks may also be other.

[0038] In this embodiment, an isolation layer 105 is also formed on the substrate 100 surrounding the protrusion 110.

[0039] The isolation layer 105 serves to isolate adjacent protrusions 110 and also to isolate the substrate 100 from the subsequent gate structure. In this embodiment, the isolation layer 105 is made of silicon oxide. The isolation layer 105 can also be made of other insulating materials.

[0040] Continue to refer to Figure 8 This forms a pseudo-gate structure 120 that spans the channel stack 210.

[0041] The pseudo-gate structure 120 is used to pre-occupy space for the subsequent formation of the gate structure.

[0042] Specifically, the pseudo-gate structure 120 is located on the isolation layer 105 and covers part of the top and part of the sidewalls of the channel stack 210. The extension direction of the pseudo-gate structure 120 is perpendicular to the extension direction of the channel stack.

[0043] The pseudo-gate structure 120 can be a stacked structure or a single-layer structure. In this embodiment, the pseudo-gate structure 120 is a stacked structure, including a pseudo-gate oxide layer (not shown) and a pseudo-gate layer (not shown) located on the pseudo-gate oxide layer.

[0044] Specifically, the material of the pseudo-gate oxide layer can be silicon oxide or silicon oxynitride, and the material of the pseudo-gate layer can be polycrystalline silicon or amorphous silicon.

[0045] In this embodiment, during the step of forming the pseudo-gate structure 120, a pseudo-gate mask layer (not shown) is also formed on the top of the pseudo-gate structure 120.

[0046] The pseudo-gate mask layer is used as an etching mask to form the pseudo-gate mask layer as a patterned pseudo-gate material layer.

[0047] As an example, the material of the pseudo-gate mask layer is silicon nitride.

[0048] Continue to refer to Figure 8 The method for forming the semiconductor structure further includes forming a gate sidewall 130 on the sidewall of the pseudo-gate structure 120.

[0049] In this embodiment, the gate sidewall 130 is used together with the dummy gate structure 120 as an etching mask for the subsequent formation of source and drain trenches to define the formation location of the source and drain doped layer. The gate sidewall 130 is also used to protect the dummy gate structure 120 and the sidewalls of the subsequent gate structure.

[0050] In this embodiment, the material of the gate sidewall 130 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 130 is a single-layer or multi-layer structure. As an example, the gate sidewall 130 is a single-layer structure, and the material of the gate sidewall 130 is silicon nitride.

[0051] refer to Figure 9 Source / drain grooves 140 are formed in the channel stack 210 on both sides of the pseudo-gate structure 120 in the first region I and the second region II.

[0052] In this embodiment, the source / drain groove 140 is used to provide spatial location for the formation of the source / drain doped layer. Specifically, the source / drain groove 140 in the first region I is used to provide spatial location for the subsequent formation of the first source / drain doped layer, and the source / drain groove 140 in the second region II is used to provide spatial location for the subsequent formation of the second source / drain doped layer.

[0053] Furthermore, the sidewall of the source / drain groove 140 exposes the channel stack 210 so that the exposed portion of the thickness sacrificial layer 20 can be removed along the length of the channel layer.

[0054] As an example, using a pseudo-gate mask layer, a pseudo-gate structure, and a gate sidewall as a mask, an anisotropic etching process is employed to etch the channel stack 210 to form source / drain recesses 140.

[0055] As an example, anisotropic etching is anisotropic dry etching.

[0056] refer to Figure 10Along the length of the channel layer 30, a portion of the exposed thickness of the sacrificial layer 20 on the sidewall of the source / drain groove 140 is removed, so that a groove 145 is formed between the adjacent channel layer 30 and the remaining sacrificial layer 20, or between the protrusion 110 and the adjacent channel layer 30 and the remaining sacrificial layer 20.

[0057] The groove 145 is used to provide space for the subsequent formation of the inner spacer.

[0058] In this embodiment, an isotropic etching process is used to remove a portion of the thickness of the sacrificial layer 20 exposed on the sidewall of the source / drain groove 140 along the length of the channel layer 30.

[0059] In this embodiment, a vapor etching process is used to etch the sacrificial layer 20, which is a portion of the sidewall thickness of the source / drain groove 140, along the length of the channel layer 30.

[0060] In the above embodiments, the vapor etching process is an isotropic etching process that can etch the sacrificial layer 20 along the length of the channel layer 30. The vapor etching process is also easy to achieve a large etching selectivity, which helps to reduce the difficulty of etching the sacrificial layer 20 and reduce the probability of damage to other film structures (e.g., the channel layer 30).

[0061] In this embodiment, the sacrificial layer 20 is made of SiGe, and the channel layer 30 is made of Si. The sacrificial layer 20 on the sidewall of the source / drain recess 140 is etched using HCl vapor. The etching rate of HCl vapor on SiGe is much higher than that on Si, which can effectively reduce the probability of damage to the channel layer 30.

[0062] In other embodiments, when the channel layer is made of SiGe and the sacrificial layer is made of Si, an isotropic dry etching process can be used to etch the sacrificial layer on the trench sidewalls in the lateral direction. The etchant used in the dry etching process can include a mixture of plasmas of CF4, O2, and N2. The difference between the etching rate of Si and the etching rate of SiGe by the plasma mixture is relatively large, which can effectively reduce the probability of channel layer damage.

[0063] refer to Figure 11 An inner wall 150 is formed within the trench 145 of the first region I and the second region II.

[0064] Subsequently, a first source / drain doped layer is formed in the source / drain groove 140 of the first region I, and a second source / drain doped layer is formed in the source / drain groove 140 of the second region II. A gate structure is formed at the location of the dummy gate structure 120 and the sacrificial layer 20. The inner wall 150 is used to achieve isolation between the first source / drain doped layer and the gate structure, as well as between the second source / drain doped layer and the gate structure. It also increases the distance between the first source / drain doped layer and the gate structure, as well as between the second source / drain doped layer and the gate structure, which helps to reduce the parasitic capacitance between the first source / drain doped layer and the gate structure, as well as between the second source / drain doped layer and the gate structure.

[0065] In this embodiment, the inner wall 150 is made of an insulating material to achieve isolation between the first source / drain doped layer and the gate structure, as well as between the second source / drain doped layer and the gate structure.

[0066] In this embodiment, the material of the inner wall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. As an example, the material of the inner wall 150 is silicon nitride.

[0067] In this embodiment, the step of forming the inner sidewall includes: forming the inner sidewall on the top and sidewalls of the pseudo-grid structure, as well as the sidewalls and bottom of the source-drain groove, and filling the groove with the inner sidewall.

[0068] In this embodiment, the process for forming the inner sidewall includes atomic layer deposition (ALD). ALD involves multiple ALD cycles. ALD offers good gap-filling performance and step coverage, thereby improving the gap-filling capacity of the inner sidewall and thus enhancing its filling ability within the trench.

[0069] refer to Figures 12 to 13 A first source / drain doped layer 170 is formed in the source / drain groove 140 of the first region I, and the first source / drain doped layer 170 is in contact with the sidewall of the inner sidewall 150.

[0070] The first source / drain doped layer 170 is used as the source or drain of the first type MOS transistor. When the first type MOS transistor is working, the first source / drain doped layer 170 is used to provide a carrier source.

[0071] In this embodiment, the first source / drain doped layer 170 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0072] Specifically, the first type of MOS transistor is a PMOS transistor, and the first source / drain doped layer includes a stress layer doped with P-type ions, the material of which is Si or SiGe. In other embodiments, when the first type of MOS transistor is an NMOS transistor, the first source / drain doped layer includes a stress layer doped with N-type ions, the material of which is Si or SiC.

[0073] It should be noted that, in this embodiment, the reference is... Figure 12 The method for forming a semiconductor structure further includes: after forming the inner sidewall 150 and before forming the first source / drain doped layer 170, removing the top and sidewalls of the dummy gate structure 120 located in the first region I, the bottom of the source / drain recess 140, and the inner sidewall 150 on the channel layer 30 of the sidewall of the source / drain recess 140.

[0074] In the above embodiment, the top and sidewalls of the pseudo-gate structure 120 located in the first region I, the bottom of the source / drain groove 140, and the inner sidewalls 150 on the channel layer 30 of the sidewall of the source / drain groove 140 are removed to expose the protrusion 110 at the bottom of the source / drain groove 140 in the first region I and the channel layer 30 on the sidewall of the source / drain groove 140, so that the first source / drain doped layer 170 subsequently formed in the source / drain groove 140 in the first region I can contact the channel layer 30.

[0075] Specifically, the method for forming the semiconductor structure further includes: after forming the inner sidewall 150 and before forming the first source / drain doped layer 170, forming a first mask layer covering the second region II, the first mask layer exposing the first region I; using the first mask layer as a mask, removing the top and sidewalls of the dummy gate structure 120 located in the first region I, the bottom of the source / drain recess 140, and the inner sidewall 150 on the channel layer 30 of the sidewall of the source / drain recess 140.

[0076] The first mask layer is used as an etching mask to remove the top and sidewalls of the pseudo gate structure 120 located in the first region I, the bottom of the source drain groove 140, and the inner sidewalls 150 on the channel layer 30 of the sidewall of the source drain groove 140.

[0077] In this embodiment, the first mask layer includes a first planarization layer 171, a first anti-reflection layer 172, and a first photoresist patterning layer 173 formed sequentially from bottom to top.

[0078] In this embodiment, the first planarization layer 171 is used to provide a flat surface for forming the first anti-reflection layer 172 and the first photoresist patterning layer 173.

[0079] As an example, the material of the first planarization layer 171 includes ODL (organic dielectric layer) or SOC (spin-coated carbon).

[0080] The first anti-reflective layer 172 is used to reduce the reflection effect during the exposure process of forming the first photoresist pattern layer 173. As an example, the material of the first anti-reflective layer 172 includes Si-ARC or BARC.

[0081] In this embodiment, the first photoresist pattern layer 173 is used as an etching mask.

[0082] In this embodiment, the material of the first photoresist pattern layer 173 is photoresist.

[0083] In this embodiment, an anisotropic etching process is used to remove the inner sidewalls 150 located on the top of the pseudo gate structure 120 and the bottom of the source / drain groove 140; an isotropic etching process is used to remove the inner sidewalls 150 located on the channel layer 30 of the sidewalls of the pseudo gate structure 120 and the sidewalls of the source / drain groove 140.

[0084] Anisotropic etching processes have the characteristics of anisotropic etching, which enables the inner sidewall 150 to be etched in a direction perpendicular to the substrate, thereby facilitating the removal of the inner sidewall 150 located at the bottom of the source / drain recess 140.

[0085] As an example, anisotropic etching is an anisotropic dry etching process.

[0086] As an example, anisotropic dry etching processes include atomic layer etching (ALE). ALE processes are characterized by low etching damage, high selectivity, accurate depth control, and low power consumption. They can etch precisely down to an atomic layer, requiring the etching process to proceed uniformly, atomically by atomic layer, and stopping at appropriate times or locations to achieve extremely high etching selectivity and precision.

[0087] Specifically, the atomic layer etching process can be capacitively coupled plasma (CCP). In other embodiments, it can also be an etching process such as inductively coupled plasma (ICP).

[0088] The isotropic etching process has the characteristics of isotropic etching, which enables the inner sidewall 150 to be etched along a direction parallel to the substrate, thereby removing the inner sidewall 150 located on the sidewall of the dummy gate structure and the channel layer of the source / drain recess sidewall.

[0089] As an example, isotropic etching is a wet etching process.

[0090] In this embodiment, the material of the inner wall 150 is silicon nitride, and the etching solution of the wet etching process includes a phosphoric acid solution.

[0091] In this embodiment, after removing the top and sidewalls of the pseudo-gate structure 120 in the first region I, the bottom of the source / drain groove 140, and the inner sidewalls 150 on the channel layer 30 of the sidewalls of the source / drain groove 140, the sidewalls and bottom of the source / drain groove 140 in the second region II are still covered by the inner sidewalls 150, so that the first source / drain doped layer 170 is formed only in the source / drain groove 140 of the first region I.

[0092] refer to Figures 14 to 15 A second source / drain doped layer 180 is formed in the source / drain groove 140 of the second region II, and the second source / drain doped layer 180 is in contact with the sidewall of the inner sidewall 150.

[0093] The second source / drain doped layer 180 is used as the source or drain of the second type MOS transistor. When the second type MOS transistor is working, the second source / drain doped layer 180 is used to provide a carrier source.

[0094] In this embodiment, the second source / drain doped layer 180 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0095] Specifically, in this embodiment, the second type MOS transistor is an NMOS transistor, and the second source / drain doped layer 180 includes a stress layer doped with N-type ions, the material of which is Si or SiC. In other embodiments, the second type MOS transistor is a PMOS transistor, and the second source / drain doped layer 180 includes a stress layer doped with P-type ions, the material of which is Si or SiGe.

[0096] In this embodiment, the method for forming the semiconductor structure further includes: referencing Figure 14 After forming the inner sidewall 150 and before forming the second source / drain doped layer 180, the top and sidewalls of the pseudo-gate structure 120 located in the second region II, the bottom of the source / drain recess 140, and the inner sidewall 150 on the channel layer 30 of the sidewall of the source / drain recess 140 are removed.

[0097] The top and sidewalls of the pseudo-gate structure 120 in the second region II, the bottom of the source / drain recess 140, and the inner sidewalls 150 on the channel layer 30 of the sidewall of the source / drain recess 140 are removed to expose the protrusion 110 at the bottom of the source / drain recess 140 in the second region II and the channel layer 30 on the sidewall of the source / drain recess 140, so that a second source / drain doped layer 180 can be formed in the source / drain recess 140 in the second region II.

[0098] In this embodiment, the method for forming the semiconductor structure further includes: after forming the inner sidewall 150 and before forming the second source / drain doped layer 180, forming a second mask layer covering the first region I, the second mask layer exposing the second region II; using the second mask layer as a mask, removing the top and sidewalls of the dummy gate structure 120 located in the second region II, the bottom of the source / drain recess 140, and the inner sidewall 150 on the channel layer of the sidewall of the source / drain recess 140.

[0099] The second mask layer is used as an etching mask to remove the top and sidewalls of the pseudo-gate structure 120 located in the second region II, the bottom of the source / drain groove 140, and the inner sidewalls 150 on the channel layer 30 of the sidewalls of the source / drain groove 140.

[0100] In this embodiment, the second mask layer includes a second planarization layer 181, a second anti-reflection layer 182, and a second photoresist patterning layer 183 formed sequentially from bottom to top.

[0101] The second planarization layer 181 is used to provide a flat surface for forming the second anti-reflection layer 182 and the second photoresist patterning layer 183.

[0102] As an example, the material of the second planarization layer 181 includes ODL (organic dielectric layer) or SOC (spin-coated carbon).

[0103] In this embodiment, the second anti-reflection layer 182 is used to reduce the reflection effect during the exposure process of forming the second photoresist pattern layer 183. As an example, the material of the second anti-reflection layer 182 includes Si-ARC or BARC.

[0104] In this embodiment, the second photoresist pattern layer 183 is used as an etching mask.

[0105] In this embodiment, the material of the second photoresist pattern layer 183 is photoresist.

[0106] In this embodiment, an anisotropic etching process is used to remove the inner sidewalls 150 located on the top of the pseudo gate structure 120 and the bottom of the source / drain groove 140; an isotropic etching process is used to remove the inner sidewalls 150 located on the channel layer 30 of the sidewalls of the pseudo gate structure 120 and the sidewalls of the source / drain groove 140.

[0107] Anisotropic etching processes have the characteristics of anisotropic etching, which enables the inner sidewall 150 to be etched in a direction perpendicular to the substrate, thereby facilitating the removal of the inner sidewall 150 located at the bottom of the source / drain recess 140.

[0108] As an example, anisotropic etching is an anisotropic dry etching process.

[0109] As an example, anisotropic dry etching processes include atomic layer etching (ALE). ALE processes are characterized by low etching damage, high selectivity, accurate depth control, and low power consumption. They can etch precisely down to an atomic layer, requiring the etching process to proceed uniformly, atomically by atomic layer, and stopping at appropriate times or locations to achieve extremely high etching selectivity and precision.

[0110] Specifically, the atomic layer etching process can be capacitively coupled plasma (CCP). In other embodiments, it can also be an etching process such as inductively coupled plasma (ICP).

[0111] The isotropic etching process has the characteristics of isotropic etching, which enables the inner sidewall 150 to be etched along a direction parallel to the substrate, thereby removing the inner sidewall 150 located on the sidewall of the dummy gate structure and the channel layer of the source / drain recess sidewall.

[0112] As an example, isotropic etching is a wet etching process.

[0113] In this embodiment, the material of the inner wall 150 is silicon nitride, and the etching solution of the wet etching process includes a phosphoric acid solution.

[0114] In this embodiment, before forming the second mask layer, a conformal protective layer (not shown) is also formed on the substrate; before removing the top and sidewalls of the pseudo gate structure 120, the bottom of the source / drain groove 140, and the inner sidewall 150 on the channel layer of the sidewall of the source / drain groove 140 located in the second region II, the protective layer located in the first region I is also removed using the second mask layer as a mask to expose the second region II.

[0115] Correspondingly, the remaining protective layer located in the first region II can protect the first region I in the subsequent step of forming the second source / drain doped layer 180, preventing the process of forming the second source / drain doped layer 180 from affecting the first region I.

[0116] It should be noted that in this embodiment, the formation of the second source / drain doped layer 180 after the formation of the first source / drain doped layer 170 is used as an example for illustration. In other embodiments, the first source / drain doped layer may be formed in the first region after the second source / drain doped layer is formed in the second region.

[0117] It should also be noted that, in this embodiment, the inner sidewalls 150 on the bottom of the source / drain recess 140 and on the channel layer 30 of the sidewall of the source / drain recess 140 are removed before the source / drain doped layers are formed. In other embodiments, the inner sidewalls located on the top and sidewalls of the dummy gate structure, the bottom of the source / drain recess, and the channel layer of the sidewall of the source / drain recess can be removed in the first and second regions after the inner sidewalls are formed and before the first and second source / drain doped layers are formed.

[0118] refer to Figure 16 After forming the first source / drain doped layer 170 and the second source / drain doped layer 180, the dummy gate structure 120 is removed to form a gate opening (not shown) and expose the channel stack 210. Through the gate opening, the sacrificial layer 20 in the channel stack 210 is removed to form a through trench (not shown). The through trench is surrounded by the protrusion 110 and the adjacent channel layer 30, or by the adjacent channel layer 30. The gate structure 190 is filled in the gate opening and the through trench, and the gate structure 190 surrounds the channel layer 30.

[0119] The gate opening provides space for forming the gate structure. The gate opening exposes the channel stack 210 to facilitate subsequent removal of the sacrificial layer 20 in the channel stack 210 through the gate opening.

[0120] Specifically, after forming the first source / drain doped layer 170 and the second source / drain doped layer 180, and before removing the dummy gate structure 120, the method further includes forming an interlayer dielectric layer 160 covering the first source / drain doped layer 170 and the second source / drain doped layer 180 on the side of the dummy gate structure 120.

[0121] Interlayer dielectric layer 160 is used to isolate adjacent devices. As an example, the material of interlayer dielectric layer 160 is silicon oxide.

[0122] It should be noted that in the step of forming the interlayer dielectric layer 160, the dummy gate mask layer is also removed.

[0123] In this embodiment, the gate opening spans the channel stack 210 and is located in the interlayer dielectric layer 160.

[0124] In this embodiment, the through-slot and the gate opening together provide space for forming the gate structure. The through-slot is connected to the gate opening.

[0125] In the above embodiment, the sacrificial layer 20 is removed after the formation of the first source / drain doped layer 170 and the second source / drain doped layer 180. Therefore, after the sacrificial layer 20 is removed, along the extension direction of the channel layer 30, the two ends of the channel layer 30 in the first region I are connected to the first source / drain doped layer 170, and the two ends of the channel layer 30 in the second region II are connected to the second source / drain doped layer 180. The channel layer 30 is suspended in the gate opening so that the subsequent gate structure can surround the channel layer.

[0126] In this embodiment, a vapor etching process is used to remove the sacrificial layer 20. Specifically, the channel layer 30 is made of Si, and the sacrificial layer 20 is made of SiGe. Therefore, the sacrificial layer 20 exposed at the gate opening is removed by HCl vapor. HCl vapor has a high etching selectivity between SiGe and Si, which is beneficial to improving the removal efficiency of the sacrificial layer 20 and reducing the probability of damage to the channel layer 30.

[0127] In this embodiment, when the device is in operation, the gate structure 190 is used to control the opening and closing of the conductive channel.

[0128] In this embodiment, the gate structure 190 is a metal gate structure, which includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through slot and gate opening.

[0129] In this embodiment, the gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0130] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0131] In this embodiment, the work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0132] In this embodiment, the gate electrode layer serves as an external electrode for electrical connection between the gate structure 190 and an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0133] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a first region for forming a first type MOS transistor and a second region for forming a second type MOS transistor, wherein the first type MOS transistor and the second type MOS transistor have different channel conductivity types; the substrate includes a substrate and a protrusion protruding from the substrate, wherein one or more channel stacks are formed on the protrusion in a bottom-up manner, and each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer; A pseudo-gate structure is formed that spans the channel stack; Source / drain grooves are formed in the channel stack on both sides of the pseudo-gate structure in the first and second regions; Along the length of the channel layer, remove a portion of the exposed thickness of the sacrificial layer on the sidewall of the source / drain groove, so that a groove is formed between the adjacent channel layer and the remaining sacrificial layer, or between the protrusion and the adjacent channel layer and the remaining sacrificial layer. Inner walls are formed within the trenches of the first and second regions; A first source / drain doped layer is formed in the source / drain groove of the first region, and the first source / drain doped layer is in contact with the sidewall of the inner sidewall; A second source / drain doped layer is formed within the source / drain groove of the second region, and the second source / drain doped layer is in contact with the sidewall of the inner sidewall.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the inner sidewall includes: forming an inner sidewall on the top and sidewalls of the pseudo-grid structure, and on the sidewalls and bottom of the source-drain groove, wherein the inner sidewall fills the groove; The method for forming the semiconductor structure further includes: after forming the inner sidewalls and before forming the first source / drain doped layer, removing the top and sidewalls of the dummy gate structure located in the first region, the bottom of the source / drain recess, and the inner sidewalls on the channel layer of the source / drain recess sidewalls; The method for forming the semiconductor structure further includes: after forming the inner sidewalls and before forming the second source / drain doped layer, removing the top and sidewalls of the dummy gate structure located in the second region, the bottom of the source / drain groove, and the inner sidewalls on the channel layer of the source / drain groove sidewalls.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the semiconductor structure further includes: after forming the inner sidewall and before forming the first source / drain doped layer, forming a first mask layer covering the second region, the first mask layer exposing the first region; using the first mask layer as a mask, removing the top and sidewalls of the pseudo-gate structure located in the first region, the bottom of the source / drain groove, and the inner sidewall on the channel layer of the sidewall of the source / drain groove.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method for forming the semiconductor structure further includes: after forming the inner sidewall and before forming the second source / drain doped layer, forming a second mask layer covering the first region, the second mask layer exposing the second region; using the second mask layer as a mask, removing the top and sidewalls of the pseudo-gate structure located in the second region, the bottom of the source / drain groove, and the inner sidewall on the channel layer of the sidewall of the source / drain groove.

5. The method for forming a semiconductor structure according to any one of claims 2 to 4, characterized in that, The step of removing the inner sidewalls located on the top and sidewalls of the dummy gate structure, the bottom of the source / drain groove, and the channel layer of the sidewall of the source / drain groove includes: using an anisotropic etching process to remove the inner sidewalls located on the top of the dummy gate structure and the bottom of the source / drain groove; and using an isotropic etching process to remove the inner sidewalls located on the sidewalls of the dummy gate structure and the channel layer of the sidewall of the source / drain groove.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The anisotropic etching process is an anisotropic dry etching process.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The dry etching process includes atomic layer etching.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, The isotropic etching process includes wet etching.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching solution used in the wet etching process includes a phosphoric acid solution.

10. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process for forming the inner sidewall includes atomic layer deposition.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, An isotropic etching process is used to remove a portion of the exposed thickness of the sacrificial layer along the length of the channel layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor; or, the first type of MOS transistor is an NMOS transistor, and the second type of MOS transistor is a PMOS transistor.

13. The method for forming a semiconductor structure according to any one of claims 1 to 4, 10 to 12, characterized in that, The method for forming the semiconductor structure further includes: after forming the first source / drain doped layer and the second source / drain doped layer, removing the dummy gate structure to form a gate opening and expose the channel stack; By removing the sacrificial layer in the channel stack through the gate opening, a through-slot is formed, which is surrounded by the protrusion and the adjacent channel layer, or by the adjacent channel layer. A gate structure is filled within the gate opening and the through-slot, and the gate structure surrounds the channel layer.

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