Intelligent grouping method and system for IO pipeline adapting to CPU multi-core

Abstract

The application discloses an IO pipeline intelligent grouping method and system suitable for CPU multicore, and the method comprises the following steps: when the driver is loaded, the number of IO pipelines is confirmed according to the smaller value between the NUMANode number of the detected CPU and the port number of the front-end interface card; the physical memory of each group of IO pipelines allocated on the NUMANode is used as a cache pool and an object pool; the thread of each group of pipelines uses the cache pool and the object pool resources of the pipeline; when the driver is started, each group of IO pipelines creates a front-end Target thread, a data processing engine thread and a preset number of back-end Initiator threads for the selected front-end interface card, and the threads on each group of IO pipelines are bound on the NUMA Node; the solid state disk storage space is divided into granules which do not cross each other, and the Target is used to export the granules to the host for access. According to the processing scheme, the IO parallel execution between different pipelines does not interfere with each other, and the performance of the storage is improved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to an intelligent grouping method and system for I / O pipelines adapted to multi-core CPUs. Background Technology

[0002] Symmetric Multiprocessor (SMP) architecture refers to a computer where multiple CPUs operate symmetrically, sharing the same physical memory and I / O resources with comparable access times. SMP architecture is quite efficient when the number of CPUs is small. However, as the number of CPUs increases, memory access conflicts increase rapidly, and memory bandwidth becomes the bottleneck for system performance. Due to the limited scalability of SMP, people have gradually shifted to NUMA architecture for building large-scale systems.

[0003] NUMA (Non-Uniform Memory Access) refers to a system with multiple CPU modules, each consisting of multiple CPUs. Each CPU module has independent local memory and I / O resources, and these CPU modules can be called Nodes. Nodes can interact through interconnect modules. Each CPU module still accesses the overall system memory, and accessing a Node's local memory is faster than accessing the memory of other Nodes. NUMA architecture offers good scalability, allowing the processor and memory resources in the system to expand on a Node-by-Node basis. NUMA architecture also offers locality of reference, with each processor having local memory and I / O resources, resulting in low access latency. NUMA architecture provides good load balancing, distributing tasks across different Nodes. NUMA architecture also offers good parallelism, with each node having memory resources, reducing memory access contention and increasing memory bandwidth.

[0004] In recent years, mechanical hard drives have been gradually replaced by solid-state drives (SSDs), and storage protocols have gradually evolved from SCSI to NVMe. Due to the efficient cooperation between SSDs and NVMe, the hardware latency of storage has been significantly reduced. However, storage software has gradually become the bottleneck of storage systems. Traditional storage software stacks have a large amount of software overhead such as memory copying, context switching, and interrupts, resulting in large read and write latency and failing to fully utilize the hardware performance of NVMe SSDs.

[0005] The storage I / O stack is typically divided into three parts: the front-end target, the data processing engine, and the back-end initiator.

[0006] The front-end Target is responsible for receiving commands and data from the host from the interface card (10 Gigabit Ethernet card, FC card, IB card), parsing the protocol, handing the commands over to the data processing engine for processing, and sending the processing results from the data processing engine back to the host. This is typically implemented by the interface device driver through an interrupt handler.

[0007] The intermediate data processing engine processes commands, implements RAID or other functions, sends read / write requests to the backend initiator, and delivers the processing results to the frontend target. It typically consists of one or more threads.

[0008] The backend initiator primarily sends received read and write requests to the NVMe SSD. This is typically achieved by a backend NVMe driver, implemented through an interrupt handler.

[0009] The existing solutions mainly include the following:

[0010] 1. After receiving a data packet from the host, the front-end interface card notifies the CPU via a hardware interrupt. The CPU handles the interrupt and disables it. The interrupt handler function completes the reception of the data packet, places it in the global ring buffer, exits the interrupt handler function, and then re-enables the interrupt. One or more data processing engine threads retrieve commands from the global ring buffer, parse the commands, allocate command objects and their required memory and other resources and objects, execute the commands, and send I / O requests to the SSD through the NVMe driver interface. After receiving the I / O, the SSD finds the corresponding command and notifies the data processing engine to execute it. After processing, the data processing engine returns the result to the host through the front-end interface card's interface. The front-end Target and back-end Initiator do not use interrupts; they receive requests and send responses using a polling mode with threads.

[0011] 2. The front-end Target, data processing engine, and back-end Initiator run in the same thread. Within this thread, the front-end Target handles data packet reception and response sending, the data processing engine parses and executes commands, and the back-end Initiator handles SSD I / O. The front-end interface card typically has multiple ports, with one thread running for each port.

[0012] In practical use, it was found that the above method still has several shortcomings, failing to achieve the best results. These shortcomings can be summarized as follows:

[0013] Disadvantages of Option 1:

[0014] 1) In this mode, the front-end and back-end frequently switch contexts due to the use of interrupt mode. The front-end Target, the middle data transmission engine, and the back-end Initiator compete for global memory and objects and therefore lock them. The front-end Target, the middle data transmission engine, and the back-end Initiator are located on different NUMA nodes. Cross-node access to global memory and objects is very slow, which will affect performance.

[0015] 2) In this mode, each thread runs all the work for one request. The work of this thread is very complex, including the work of the front-end Target, the middle data transmission engine, the back-end Initiator and other modules. The code development and maintenance work is complex. The number of threads is at most the same as the number of ports, and it cannot make full use of multi-core processors.

[0016] It is evident that the existing data storage methods described above still have inconveniences and shortcomings in use, and urgently need further improvement. Creating a new high-performance storage method has become a pressing goal for the industry. Summary of the Invention

[0017] In view of this, the present disclosure provides an intelligent grouping method for I / O pipelines adapted to multi-core CPUs, which at least partially solves the problems existing in the prior art.

[0018] In a first aspect, embodiments of this disclosure provide a method for intelligent grouping of I / O pipelines adapted to multi-core CPUs, the method comprising the following steps:

[0019] When the driver is loaded, the number of I / O pipelines is determined based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-end interface card.

[0020] The physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline.

[0021] When the driver starts, each IO pipeline creates a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for the selected front-end interface card. The threads in each IO pipeline are bound to the NUMANode.

[0022] The solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access via the Target.

[0023] According to a specific implementation of an embodiment of this disclosure, the method further includes:

[0024] When each front-end Target thread receives a request, it allocates an object from the object pool on the corresponding Node and hands it over to the request circular buffer of the data processing engine on that group.

[0025] When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group.

[0026] When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer.

[0027] Each group's data processing engine thread continues processing after polling the response in the response ring buffer of that group, and puts the result into the response ring buffer of the front-end Target of that group;

[0028] After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

[0029] According to a specific implementation of this disclosure, a queue of NVMe devices is allocated on a NUMA Node; the resources of this I / O pipeline are only dedicated to the threads of this I / O pipeline.

[0030] According to a specific implementation of an embodiment of this disclosure, the method further includes:

[0031] Resource allocation for this I / O pipeline group is directly allocated from the idle queue of this I / O pipeline group, without the need for locking.

[0032] According to one specific implementation of this disclosure, data exchange between different threads of the I / O pipeline is lock-free using a circular buffer.

[0033] Secondly, embodiments of this disclosure provide an intelligent grouping system for I / O pipelines adapted to multi-core CPUs, the system comprising:

[0034] The grouping module is configured to determine the number of I / O pipelines during driver loading based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-side interface card; and,

[0035] The physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline.

[0036] The segmentation module is configured to, during driver startup, create a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for each selected front-end interface card in each I / O pipeline group. The threads in each I / O pipeline group are bound to the NUMA Node; and...

[0037] The solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access via the Target.

[0038] According to a specific implementation of an embodiment of this disclosure, the system further includes:

[0039] The buffer module is configured to allocate objects from the object pool on the corresponding Node when each group of front-end Target threads receives a request, and then hand them over to the request circular buffer of the data processing engine on that group.

[0040] When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group.

[0041] When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer.

[0042] Each group's data processing engine thread continues processing after polling the response in the group's response circular buffer, placing the result into the response circular buffer of the front-end Target for that group; and,

[0043] After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

[0044] Thirdly, embodiments of this disclosure also provide an electronic device, the electronic device comprising:

[0045] At least one processor; and,

[0046] A memory communicatively connected to the at least one processor; wherein,

[0047] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, cause the at least one processor to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines as described in the first aspect or any implementation thereof.

[0048] Fourthly, embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one processor, cause the at least one processor to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines in the first aspect or any implementation thereof.

[0049] Fifthly, embodiments of this disclosure also provide a computer program product, the computer program product including a computing program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to execute the intelligent grouping method for I / O pipelines adapted to CPU multi-cores in the first aspect or any implementation thereof.

[0050] The intelligent grouping method for I / O pipelines adapted to multi-core CPUs in this disclosure proposes an intelligent grouping method for I / O pipelines adapted to multi-core CPUs under a NUMA architecture. Based on the smaller of the number of NUMA nodes and the number of front-end interface cards, the I / O pipeline is divided into multiple thread groups. Each thread group is bound to a CPU core on a selected Node. Threads within each group use the physical memory allocated by the Node for caching and object management, thereby avoiding cross-Node memory access. Threads within each group allocate cache and objects from the Node's cache pool and object pool, thereby reducing lock contention. The initiator of each group creates a queue of NVMe devices on the Node's CPU core. The data transfer engine of each group uses the queue of the Node's back-end initiator to process I / O requests. I / O requests only flow between threads within the Node, thereby improving storage performance. Attached Figure Description

[0051] The above is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Figure 1 A schematic flowchart of an intelligent grouping method for I / O pipelines adapted to multi-core CPUs is provided in this embodiment of the present disclosure.

[0053] Figure 2A flowchart illustrating an intelligent grouping method for I / O pipelines adapted to multi-core CPUs, provided in this embodiment of the disclosure;

[0054] Figure 3 A schematic diagram of an intelligent grouping system architecture for I / O pipelines adapted to multi-core CPUs is provided for embodiments of this disclosure; and

[0055] Figure 4 A schematic diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0056] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0057] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0058] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0059] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0060] This invention provides an intelligent grouping method for I / O pipelines adapted to multi-core CPUs, proposing a method for intelligent grouping of I / O pipelines adapted to multi-core CPUs under NUMA architecture. Based on the number of NUMA nodes, the I / O pipeline is divided into multiple thread groups. Each thread group is bound to a CPU core on a selected Node. Threads within each group use the physical memory allocated by the Node for caching and object management, thereby avoiding cross-Node memory access. Threads within each group allocate cache and objects from the Node's cache pool and object pool, thereby reducing lock contention. The initiator of each group creates a queue of NVMe devices on the Node's CPU core. The data transfer engine of each group uses the queue of the Node's backend initiator to process I / O requests. I / O requests flow only between threads within the Node, improving storage performance.

[0061] Figure 1 This is a schematic diagram of the intelligent grouping method for I / O pipelines adapted to multi-core CPUs provided in the embodiments of this disclosure.

[0062] Figure 2 To and Figure 1 The corresponding flowchart illustrates the intelligent grouping method for I / O pipelines adapted to multi-core CPUs. The system architecture of the related components of this invention is as follows: Figure 2 As shown, an I / O pipeline includes a front-end target thread, a middle data processing thread (DTE thread), and a back-end initiator thread. Each I / O pipeline's thread is bound to the CPU of its respective Node. Physical memory on the Node to which each I / O pipeline belongs is allocated as a dedicated cache pool. The storage space is divided into non-overlapping segments and exported to the host through the front-end target thread.

[0063] like Figure 1 As shown, in step S110, when the driver is loaded, the number of IO pipelines is determined based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-end interface card.

[0064] More specifically, the I / O pipeline is divided into multiple I / O pipelines based on the number of CPU NUMA nodes. Each I / O pipeline contains various threads required by that I / O pipeline, and each group of threads is bound to the CPU core on that node.

[0065] More specifically, we now proceed to step S120.

[0066] In step S120, the physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline.

[0067] Next, proceed to step S130.

[0068] In step S130, when the driver starts, each I / O pipeline creates a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for the selected front-end interface card. The threads in each I / O pipeline are bound to the NUMA Node.

[0069] Next, proceed to step S140.

[0070] In step S140, the solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access via the Target.

[0071] More specifically, the storage space is divided into non-overlapping granularities and exported to the host through the Target. The I / O of different pipelines is executed in parallel without interference, thus improving performance.

[0072] In this embodiment of the invention, the method further includes:

[0073] When each front-end Target thread receives a request, it allocates an object from the object pool on the corresponding Node and hands it over to the request ring buffer of the data processing engine on that group.

[0074] When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group.

[0075] When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer.

[0076] Each group's data processing engine thread continues processing after polling the response in the response ring buffer of that group, and puts the result into the response ring buffer of the front-end Target of that group;

[0077] After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

[0078] In this embodiment of the invention, a queue of NVMe devices is allocated on the NUMA Node; the resources of this group of IO pipelines are only dedicated to the threads of this group of IO pipelines.

[0079] More specifically, the physical memory on the NUMA node of this I / O pipeline is used as a cache pool and object pool, and a queue of NVMe devices is allocated on the NUMA node. The resources of this I / O pipeline are only dedicated to the threads of this I / O pipeline.

[0080] In this embodiment of the invention, the method further includes: the resource allocation of this group of IO pipelines is directly allocated on the idle queue of this group of IO pipelines without the need for locking.

[0081] In this embodiment of the invention, data exchange between different threads in the IO pipeline is lock-free using a circular buffer; IO uses threads, memory resources, and queue resources on the same NUMA Node to complete the entire IO pipeline operation, reducing cross-Node resource access and improving performance.

[0082] The intelligent grouping method for I / O pipelines adapted to multi-core CPUs proposed in this invention, based on the characteristics of NUMA architecture, groups threads and memory according to NUMA Nodes, and divides storage space into non-overlapping groups, allowing I / O to flow between the same NUMA Node and avoiding cross-Node access. Different I / O pipelines can work in parallel, improving storage performance.

[0083] Specifically, this invention divides the IO pipeline into multiple pipelines based on the NUMA node. Each pipeline is allocated a set of threads on the NUMA node, and each set of threads is bound to the CPU core on that node. The physical memory on the NUMA node is used as a cache pool and object pool for each pipeline, and a queue of NVMe devices is allocated on the NUMA node for each pipeline. IO uses the threads, memory resources, and queue resources on the same node to complete the entire IO pipeline, avoiding cross-core resource access and global lock contention. The storage space is divided and exported to the host in a non-overlapping manner, and the IO of different pipelines is executed in parallel without interference, thereby improving storage performance.

[0084] Figure 3 The present invention illustrates an intelligent grouping system 300 for I / O pipelines adapted to multi-core CPUs, including a grouping module 310, a splitting module 320, and a buffer module 330.

[0085] The grouping module 310 is used during driver loading to determine the number of I / O pipelines based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-side interface card; and,

[0086] The physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline.

[0087] The segmentation module 320 is used during driver startup to create a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for each selected front-end interface card in each I / O pipeline group. The threads in each I / O pipeline group are bound to the NUMA Node; and...

[0088] The solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access via the Target.

[0089] In this embodiment of the invention, the system further includes:

[0090] The buffer module 330 is used by each group of front-end Target threads to allocate objects from the object pool on the corresponding Node when a request is received, and then hand them over to the request circular buffer of the data processing engine on that group.

[0091] When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group.

[0092] When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer.

[0093] Each group's data processing engine thread continues processing after polling the response in the group's response circular buffer, placing the result into the response circular buffer of the front-end Target for that group; and,

[0094] After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

[0095] See Figure 4 This disclosure also provides an electronic device 40, which includes:

[0096] At least one processor; and,

[0097] The memory is communicatively connected to the at least one processor; wherein,

[0098] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines in the foregoing method embodiments.

[0099] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the intelligent grouping method for adapting to multi-core CPU I / O pipelines in the foregoing method embodiments.

[0100] This disclosure also provides a computer program product, which includes a computing program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines in the foregoing method embodiments.

[0101] The following is for reference. Figure 4 The diagram illustrates a structural schematic of an electronic device 40 suitable for implementing embodiments of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0102] like Figure 4 As shown, electronic device 40 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 401, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 402 or a program loaded from storage device 408 into random access memory (RAM) 403. The RAM 403 also stores various programs and data required for the operation of electronic device 40. The processing unit 401, ROM 402, and RAM 403 are interconnected via bus 404. Input / output (I / O) interface 405 is also connected to bus 404.

[0103] Typically, the following devices can be connected to I / O interface 405: input devices 406 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 407 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 408 including, for example, magnetic tapes, hard disks, etc.; and communication devices 409. Communication device 409 allows electronic device 40 to communicate wirelessly or wiredly with other devices to exchange data. Although electronic device 40 with various devices is shown in the figure, it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0104] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 409, or installed from a storage device 408, or installed from a ROM 402. When the computer program is executed by the processing device 401, it performs the functions defined in the methods of embodiments of this disclosure.

[0105] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0106] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0107] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: acquire at least two Internet Protocol (IP) addresses; send a node evaluation request including the at least two IP addresses to a node evaluation device, wherein the node evaluation device selects an IP address from the at least two IP addresses and returns it; and receive the IP address returned by the node evaluation device; wherein the acquired IP address indicates an edge node in a content delivery network.

[0108] Alternatively, the aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a node evaluation request including at least two Internet Protocol (IP) addresses; select an IP address from the at least two IP addresses; and return the selected IP address; wherein the received IP address indicates an edge node in the content delivery network.

[0109] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0111] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a unit does not necessarily limit the unit itself; for example, the first acquisition unit can also be described as "a unit that acquires at least two Internet Protocol addresses".

[0112] It should be understood that the various parts of this disclosure can be implemented in hardware, software, firmware, or a combination thereof.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An IO pipeline intelligent grouping method suitable for CPU multi-core, characterized in that, The method includes the following steps: When the driver is loaded, the number of I / O pipelines is determined based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-end interface card. The physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline. When the driver starts, each IO pipeline creates a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for the selected front-end interface card. The threads in each IO pipeline are bound to the NUMANode. The solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access through the front-end Target thread, specifically including: When each front-end Target thread receives a request, it allocates an object from the object pool on the corresponding Node and hands it over to the request circular buffer of the data processing engine on that group. When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group. When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer. Each group's data processing engine thread continues processing after polling the response in the response ring buffer of that group, and puts the result into the response ring buffer of the front-end Target thread of that group; After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

2. The method for intelligent grouping of IO pipelines adapting to CPU multi-cores according to claim 1, characterized in that, Allocate queues of NVMe devices on NUMA nodes; the resources of this I / O pipeline are reserved for the threads of this I / O pipeline only.

3. The method for intelligent grouping of IO pipelines to adapt to CPU cores according to claim 1, wherein, The method further includes: Resource allocation for this I / O pipeline group is directly allocated from the idle queue of this I / O pipeline group, without the need for locking.

4. The intelligent grouping method for I / O pipelines adapted to multi-core CPUs according to claim 3, characterized in that, Data exchange between different threads in the I / O pipeline is lock-free using a circular buffer.

5. An intelligent grouping system for I / O pipelines adapted to multi-core CPUs, characterized in that, The system includes: The grouping module is configured to determine the number of I / O pipelines during driver loading based on the smaller of the detected number of CPU NUMA Nodes and the number of ports on the front-side interface card; and, The physical memory allocated on the NUMA Node to which each I / O pipeline belongs is used as a cache pool and an object pool; the threads of each pipeline use the cache pool and object pool resources of this pipeline. The segmentation module is configured to, during driver startup, create a front-end Target thread, a data processing engine thread, and a preset number of back-end Initiator threads for each selected front-end interface card in each I / O pipeline group. The threads in each I / O pipeline group are bound to the NUMA Node; and... The solid-state drive storage space is divided into non-overlapping granularities and exported to the host for access through the front-end Target thread; The buffer module is configured to allocate objects from the object pool on the corresponding Node when each group of front-end Target threads receives a request, and then hand them over to the request circular buffer of the data processing engine on that group. When the data processing engine thread of each group polls the request ring buffer of that group, it parses the command, executes the command, allocates cache in the cache pool of that group, receives data, executes data processing algorithms, and sends the request to the request ring buffer of the backend Initiator thread of that group. When the backend initiator thread of each group polls for a request in the group's request ring buffer, it parses the request and puts it into the NVMe device's submission queue (SQ); after receiving a response from the NVMe device's completion queue (CQ), it puts the response into the group's data processing engine's response ring buffer. Each group's data processing engine thread continues processing after polling the response in the group's response circular buffer, placing the result into the response circular buffer of the front-end Target thread in that group; and, After polling the response in the response ring buffer for that group, the front-end Target thread of each group sends the result to the host.

6. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, cause the at least one processor to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines as described in any one of claims 1 to 4.

7. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions that, when executed by at least one processor, cause the at least one processor to perform the intelligent grouping method for adapting to multi-core CPU I / O pipelines as described in any one of claims 1 to 4.

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