Electronic device and control method

Abstract

The embodiment of the present application provides an electronic device and a control method. The electronic device includes: a system-on-chip SOC, a management chip and a first power management unit PMU; wherein the management chip is used to manage the first PMU; the SOC, the bus controller of the management chip, and the first PMU are connected in sequence through a first differential line; the first differential line is provided with a first switch combination in the part between the SOC and the bus controller of the management chip; wherein, when the SOC sends a signal to the first PMU, the first switch combination is in a closed state; when the management chip sends a signal to the first PMU, the first switch combination is in an open state. In this way, the connection mode of the SPMI bus can be improved, and the chips and devices of the circuit can be easily deployed; and the master-slave switching problem of the SOC chip and the PMK chip can be alleviated.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to an electronic device and a control method. Background Art

[0002] The motherboard of the electronic device is equipped with a system on chip (SOC), a management chip and a power management unit (PMU). The SOC chip can control the PMU through signals; the PMU can be used to power the devices in the electronic device. For example, the PMU can be used to power the SOC chip, and the PMU can also be used to power peripherals such as motors and cameras. In some scenarios, the system of the electronic device may be in a dormant state, and the SOC chip is not working; in this case, the management chip can control the PMU through signals. The communication between the SOC chip, the management chip, and the PMU can be implemented based on the system power management interface (SPMI) protocol.

[0003] In the related art, there are many PMUs deployed in the motherboard, and these PMUs need to be connected to the SOC chip and the management chip to maintain communication. However, when the SOC chip, the management chip and the connection wiring of these PMUs are deployed in the motherboard, the wiring is often difficult and complicated, which will also cause the signal quality of the signal sent by the SOC chip or the management chip to be poor when it is transmitted on the wiring, thereby affecting the signal transmission. Summary of the invention

[0004] The embodiments of the present application provide an electronic device and a control method, which are applied to the field of terminal technology and can provide a control method and an electronic device for improving the connection mode of an SPMI bus, reducing the requirements for the layout of the SPMI bus, and improving the efficiency of PMU receiving signals.

[0005] In a first aspect, an embodiment of the present application proposes an electronic device, which may also be referred to as a terminal, a terminal device, a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc. The terminal device may be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0006] The electronic device includes: a system-on-chip SOC, a management chip and a first power management unit PMU; wherein the management chip is used to manage the first PMU; the SOC, the bus controller of the management chip, and the first PMU are connected in sequence through a first differential line; the first differential line is provided with a first switch combination in the part between the SOC and the bus controller of the management chip; wherein when the SOC sends a signal to the first PMU, the first switch combination is in a closed state; when the management chip sends a signal to the first PMU, the first switch combination is in an open state. In this way, the connection mode of the SPMI bus can be improved, and the chips and devices of the circuit can be easily deployed; and the master-slave switching problem of the SOC chip and the PMK chip can be alleviated.

[0007] Among them, the management chip can be a PMK chip.

[0008] In a possible implementation, a second switch combination is provided in the portion of the first differential line between the bus controller of the management chip and the first PMU; wherein, when the SOC sends a signal to the first PMU, the first switch combination is in a closed state, and the second switch combination is in a closed state; when the management chip sends a signal to the first PMU, the first switch combination is in an open state, and the second switch combination is in a closed state; when the management chip sends a signal to the SOC, the first switch combination is in a closed state, and the second switch combination is in an open state. In this way, when the SOC chip communicates with the PMK chip, it is avoided that the wiring of the PMK chip and the first PMU forms a branch route, which affects the communication signal between the SOC chip and the PMK chip.

[0009] In a possible implementation, multiple PMUs are connected to the first differential line, and the multiple PMUs are connected in the direction where the first PMU is away from the SOC. The management chip also includes a signal repeater; the signal repeater is connected to the SOC through a second differential line; the management chip is used to send the target signal to the second PMU corresponding to the target signal using the bus controller of the management chip when the signal repeater receives the target signal of the SOC. In this way, when the SOC sends a signal, the PMK can share part of the load for the SOC and reduce the operating pressure of the SOC.

[0010] In a possible implementation, the SOC includes a first system power management interface SPMI and a second SPMI, and the management chip includes a third SPMI and a fourth SPMI; the SOC is connected to the first differential line through the first SPMI, and is connected to the second differential line through the second SPMI; the management chip is connected to the first differential line through the third SPMI, and is connected to the second differential line through the fourth SPMI. In this way, the electronic device can transmit signals to part of the PMU through the first differential line and the second differential line respectively. Compared with the single SPMI bus, the two SPMI buses can reduce the pressure of signal transmission on the single SPMI bus.

[0011] In a possible implementation, the delay required for the operation of the first PMU is less than or equal to the delay required for the operation of the second PMU. In this way, the SOC chip can give priority to controlling the first PMU to avoid the target signal occupying resources and ensure that the delay requirements of the first PMU are met; at the same time, the delay of transparent transmission will not affect the PMK's control of the second PMU; in addition, the PMK can share part of the load for the SOC, reducing the operating pressure of the SOC

[0012] In a possible implementation, when the SOC is in working state, the SOC sends a signal to the first PMU and / or the second PMU to control the first switch combination to be closed and the second switch combination to be closed; the management chip sends a signal to the SOC to control the first switch combination to be closed and the second switch combination to be disconnected; when the SOC is in sleep state, the management chip sends a signal to the first PMU and / or the second PMU to control the first switch combination to be disconnected and the second switch combination to be closed. In this way, the electronic device can flexibly and accurately control the first switch combination and / or the second switch combination to be turned off through the communication signals between different chips to realize signal transmission.

[0013] On the second aspect, the embodiment of the present application also proposes an electronic device, which includes: a system-on-chip SOC, a management chip, and M power management units PMU, where M is an integer greater than 1; wherein the management chip is used to manage the M PMUs; the SOC, L PMUs among the M PMUs, and the management chip are connected in sequence through a first differential line; the SOC, K PMUs among the M PMUs, and the management chip are connected in sequence through a second differential line, the sum of L and K is M, and the first differential line is not connected to the second differential line. In this way, the data transmission rate of the SPMI bus can be increased, and the delay of the signal reaching the PMU can be reduced. In addition, this method can also reduce the complexity of the SPMI bus layout in the motherboard and shorten the wiring length.

[0014] In a possible implementation, the SOC includes a first system power management interface SPMI and a second SPMI, and the management chip includes a third SPMI and a fourth SPMI; the SOC is connected to the first differential line through the first SPMI, and is connected to the second differential line through the second SPMI; the management chip is connected to the first differential line through the third SPMI, and is connected to the second differential line through the fourth SPMI. In this way, compared with a single SPMI bus, the data transmission volume of the two SPMI buses is significantly improved, effectively shortening the delay of the signal reaching the PMU, so that the SOC chip can schedule the PMU more quickly.

[0015] In a possible implementation, the delay required for the operation of L PMUs is less than or equal to the delay required for the operation of K PMUs. In this way, the scenario where K PMUs and L PMUs compete for resources can be reduced, and the delay of the signal reaching the PMU device with a smaller delay required for operation can be further shortened.

[0016] In a possible implementation, when the SOC is in working state, the SOC sends a signal to the PMU; when the SOC is in sleeping state, the management chip sends a signal to the PMU. In this way, the electronic device can control the PMU when it is sleeping or working, so that the electronic device can operate normally.

[0017] In the third aspect, the embodiment of the present application provides a control method, which can be applied to an electronic device as claimed in any one of claims 1 to 10, and the method includes: when the SOC sends a signal to the first PMU, controlling the first switch combination to be in a closed state; when the management chip sends a signal to the first PMU, controlling the first switch combination to be in an open state. In this way, the connection mode of the SPMI bus can be improved, and the chips and devices of the circuit can be easily deployed; and the master-slave switching problem between the SOC chip and the PMK chip can be alleviated.

[0018] In a possible implementation, a second switch combination is provided at a portion of the first differential line between the bus controller of the management chip and the first PMU, and the method further includes: when the SOC sends a signal to the first PMU, the first switch combination is controlled to be in a closed state, and the second switch combination is controlled to be in a closed state; when the management chip sends a signal to the first PMU, the first switch combination is controlled to be in an open state, and the second switch combination is controlled to be in a closed state; when the management chip sends a signal to the SOC, the first switch combination is controlled to be in a closed state, and the second switch combination is controlled to be in an open state. In this way, when the SOC chip communicates with the PMK chip, it is avoided that the wiring of the PMK chip and the first PMU forms a branch route, which affects the communication signal between the SOC chip and the PMK chip.

[0019] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method according to the third aspect is implemented.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the method of the third aspect.

[0021] In a sixth aspect, an embodiment of the present application provides a chip, the chip including a processor, the processor being used to call a computer program in a memory to execute the method described in the first aspect.

[0022] It should be understood that the fourth to sixth aspects of the present application correspond to the technical solutions of the third aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the SPMI bus in a possible implementation;

[0024] Figure 2 Schematic diagram of normal signal and abnormal signal in possible implementation;

[0025] Figure 3 A schematic diagram of a SPMI bus forming a branching route in a possible implementation;

[0026] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0034] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0035] Fig.13 A schematic diagram of an SPMI bus provided in an embodiment of the present application;

[0036] Fig.14 A schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of the present application;

[0037] Fig.15 A flow chart of a control method provided in an embodiment of the present application;

[0038] Fig.16 A schematic diagram of the structure of a control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to clearly describe the technical solutions of the embodiments of the present application, some terms and technologies involved in the embodiments of the present application are briefly introduced below:

[0040] 1) System Power Management Interface (SPMI): The SPMI protocol defines a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some cases, the SPMI protocol is implemented to support power management operations within a device.

[0041] 2) System on chip (SOC): Also known as system on chip, it is an integrated circuit that integrates a computing processor and other electronic systems into a single chip. SOC can process digital signals, analog signals, mixed signals, and even radio frequency signals, and is often used in embedded systems.

[0042] 3) Power management unit (PMU): It is a highly integrated power management solution for portable applications, which integrates several types of traditional discrete power management devices into a single package, thus achieving higher power conversion efficiency and lower power consumption. In some possible implementation scenarios, PMU can also be in the form of an integrated circuit, for example, PMU can also be called PMIC.

[0043] 4) Management chip: The management chip can be used to manage the power management chip. For example, the management chip can be a power clock management chip (PMK); the PMK chip can be used to manage the PMU chip (or PMIC chip) and the clock, etc. It should be noted that in the embodiment of the present application, the management chip can be a PMK chip, which will not be described in detail in the embodiment of the present application.

[0044] 5) Others

[0045] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0046] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0047] It should be noted that the "at..." in the embodiment of the present application can be the instant when a certain situation occurs, or a period of time after a certain situation occurs, and the embodiment of the present application does not specifically limit this. In addition, the display interface provided in the embodiment of the present application is only an example, and the display interface can also include more or less content.

[0048] In a possible implementation, the SPMI routing in the motherboard is relatively complex and the routing is relatively long. For example, the routing of the SOC chip, PMK chip and PMU device in the motherboard can be as follows: Figure 1 As shown. The SOC chip and the PMK chip are deployed at both ends of the routing, and multiple PMU devices are connected to the routing, such as PMU1-PMU7. In some scenarios, when the SOC chip is in working state, the SOC chip can be the master chip and the PMK chip can be the slave chip; the SOC chip can control the PMU device, for example, the signal sent by the SOC chip can communicate with PMU1, PMU2, PMU3, PMU4, PMU5, PMU6, PMU7 and PMK chip in turn through the routing.

[0049] In other scenarios, when the SOC chip is in sleep state, the PMK chip can be the master chip and the SOC chip can be the slave chip; the PMK chip can control the PMU, and the signal sent by the PMK chip can communicate with PMU7, PMU6, PMU5, PMU4, PMU3, PMU2, PMU1 and the SOC chip in sequence through routing, among which the SOC chip and the PMK chip communicate through the SPMI bus, and the routing can be understood as the SPMI bus.

[0050] It should be noted that the master and slave here can be understood as: for any node in the SPMI bus, the direction of the signal before the signal reaches the node can be the master, and the direction of the signal after the signal reaches the node can be the slave; for example, the node can be Figure 1 In the node A shown in the figure, when the PMK chip sends a signal to the PMU device, the signal passes through the node A from right to left, the PMK chip is the master, and the SOC chip is the slave; when the SOC chip sends a signal to the PMU device, the signal passes through the node A from left to right in the opposite direction, the SOC chip is the master, and the PMK chip is the slave. It can be seen that during the master-slave switching process, the direction of the signal passing through the node A is opposite.

[0051] Combine the following Figure 1 Analyze the design principles of the SPMI bus in possible implementations.

[0052] The SOC chip can send signals to the PMU device, and the PMK chip can also send signals to the PMU device. When the signal is transmitted on the SPMI bus, the integrity of the signal needs to be guaranteed. For example, a normal signal can be as follows: Figure 2 As shown in signal 1 in the figure, the abnormal signal can be Figure 2 As shown in signal 2 in the figure, it can be seen that signal 1 is a smooth square wave, and there are no grooves on the rising and falling edges of signal 1; while there may be grooves on the rising and falling edges of signal 2, resulting in poor integrity of signal 2.

[0053] Among them, the factors that affect signal integrity are related to the arrangement of the SOC chip, PMK chip and PMU on the SPMI bus. Figure 3 As shown in Figure a, the routing between the SOC chip and node A is routing 1, the routing between PMU1 and node A is routing 2, and the routing between PMU2 and node A is routing 3. The SOC chip can send a signal to PMU1, and the signal is transmitted on routing 1. When the signal is transmitted to node A, one signal will be transmitted along routing 2, and one signal will be transmitted along routing 3. Among them, when the branch line length of routing 3 is long, routing 3 is equivalent to an equivalent parasitic, thereby forming a reflection. After the signal reaches PMU2 along routing 3, it returns to the SOC chip through node A, resulting in discontinuity of the signal of the SPMI bus, and the signal has a back groove, which leads to abnormal communication between the SOC chip and PMU1. Therefore, in the process of designing the SPMI bus, it is necessary to minimize the appearance of branch lines.

[0054] In a possible implementation, the SOC chip includes an SPMI interface, which means that in the motherboard, an SPMI bus needs to connect the SOC chip, the PMK chip and all the PMUs; at the same time, it is also required that there are no branch lines in the SPMI bus as much as possible.

[0055] In summary, in a possible implementation, the SOC chip and the PMK chip on the motherboard can be set at both ends of the SPMI bus. In this way, when the SOC chip is working, the signal sent from the SOC chip can pass through multiple PMU devices in sequence before reaching the PMK chip. When the SOC chip is dormant, the signal sent from the PMK chip can pass through multiple PMU devices in sequence before reaching the SOC chip. In the above two processes, there will be no branch routes in the SPMI bus, such as Figure 1 If the SOC chip and the PMK chip are not set at both ends of the SPMI bus, the following problems may occur:

[0056] In some scenarios, such as Figure 3 As shown in Figure b, the SOC chip is not set on the end side of the SPMI bus, and the PMK chip is set on the end side of the SPMI bus. When the SOC chip is not working, the PMK chip can send signals to multiple PMUs. The signals are sent from the PMK chip through the SOC chip, PMU1, PMU2 and PMU3. There are no branch lines in the link from the PMK chip to any PMU. Therefore, when the PMK chip sends a signal, the PMK chip can communicate normally with multiple PMUs.

[0057] However, when the SOC chip is working, the SOC chip can send signals to the PMK chip or to multiple PMUs. If the SOC chip sends a signal to the PMK chip, the link from the SOC chip to PMU1, PMU2 and / or PMU3 can be regarded as a branch route; if the SOC chip sends a signal to the PMU, the link from the SOC chip to the PMK chip can also be regarded as a branch route; and the branch route will form reflections, affecting the integrity of the signal.

[0058] From the above, it can be seen that when either the SOC chip or the PMK chip is not set on the end side of the SPMI bus, the chip not set on the end side will generate a branch route when sending a signal, which will cause the signal of the SPMI bus to be incomplete, affecting the communication between the SOC chip and / or PMK chip and the PMU.

[0059] Therefore, in the switching process of the master and slave chips of the SPMI bus, it is necessary to consider the end-side design of the SOC chip and the PMK chip, and the placement of multiple PMU devices in the motherboard. Therefore, in the possible implementation, the SPMI bus still has the problem of long and complex routing.

[0060] Based on this, in a possible implementation, an embodiment of the present application provides an electronic device, in which the SOC chip and the PMK chip are connected via an SPMI bus; at the same time, the SPMI bus is no longer arranged at the other end of the SOC chip. When the SOC chip sends a signal to the PMU, the signal can be transmitted to the PMU through the PMK chip; and the PMK chip can also send a signal to the PMU, and when the PMK sends a signal to the PMU, the PMK chip is disconnected from the SOC chip to avoid forming a branch route. In this way, the control of the PMU by the SOC chip and the PMK chip can be realized, and the integrity of the signal can be ensured; at the same time, the SOC chip is not set on the end side of the SPMI bus, the layout requirements of the SPMI bus are reduced, and it is easier to layout the SPMI bus.

[0061] In another possible implementation, the embodiment of the present application further provides an electronic device, including two SPMI buses, where the two SPMI buses are two sets of differential lines between the SOC chip and the PMK chip. The PMU device is divided into two parts, where one part of the PMU is set on one set of differential lines, and the remaining PMU is set on another set of differential lines. In this way, the number of PMUs set on each SPMI bus is reduced, and the length of each SPMI bus is shortened; at the same time, the number of PMUs on each SPMI bus is reduced, which can also reduce the layout requirements of the SPMI bus, and a small number of PMU devices are easier to be laid out on the SPMI bus.

[0062] The following specific embodiments are used to describe in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following specific embodiments can be implemented independently or in combination with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0063] For example, Figure 4 An electronic device provided by an embodiment of the present application is shown. Figure 4 As shown:

[0064] The electronic device includes: a SOC 401, a PMK 402 and a first PMU 403; the SOC 401, a bus controller 404 of the PMK 402, and the first PMU 403 are connected in sequence through a first differential line; a first switch combination 405 is provided at a portion of the first differential line between the SOC 401 and the bus controller 404 of the PMK 402; wherein, when the SOC 401 sends a signal to the first PMU 403, the first switch combination 405 is in a closed state; when the PMK 402 sends a signal to the first PMU 403, the first switch combination 405 is in an open state.

[0065] The bus controller 404 may be an SPMI bus controller of a PMK chip, for example, the bus controller 404 may be an SPMI controller. The first differential line may be two parallel lines of equal length, wherein one of the first differential lines transmits a positive signal and the other transmits a negative signal, and the signal difference between the two lines may include a valid signal with twice the strength and does not include an interference signal. In the embodiment of the present application, the chips may be connected via differential lines or other lines, and the embodiment of the present application does not limit this.

[0066] The first switch combination 405 may be two switch elements respectively disposed on the first differential line, and the switch elements in the first switch combination 405 may be switch elements such as diodes, triodes, and metal-oxide-semiconductor (MOS) transistors, etc. This embodiment of the application does not limit this.

[0067] In the electronic device, the SOC 401 is connected to the first switch combination 405 through a first differential line, and the bus controller 404 of the PMK 402 is connected to the first switch combination 405 and the first PMU 403 through the first differential line.

[0068] In the embodiment of the present application, the electronic device can control the first switch combination to be turned off according to the state of the SOC 401. For example, when the SOC 401 is in the working state, the SOC 401 sends a signal to the first PMU 403 to control the first switch combination to be in the closed state; when the SOC chip is in the sleep state, the PMK 402 sends a signal to the first PMU 403 to control the first switch combination to be in the open state.

[0069] Specifically, when the SOC 401 of the electronic device is in a working state, the SOC 401 may control the first PMU 403, such as Figure 5 As shown in Figure a of FIG. 1 . The first switch combination is in a closed state, and the bus controller 404 does not work. After the SOC 401 sends a signal, the signal can reach the first PMU 403 through the first differential line to achieve communication between the SOC 401 and the first PMU 403.

[0070] When the SOC 401 of the electronic device is in a sleep state, the PMK 402 can control the first PMU 403, such as Figure 5 As shown in FIG. b in FIG. 401 , the first switch combination 405 is in the disconnected state, and the SOC 401 does not work. After the bus controller 404 of the PMK 402 sends a signal, the signal can reach the first PMU 403 through the first differential line to achieve communication between the PMK 402 and the first PMU 403.

[0071] In some embodiments, the first switch combination can also switch between an open state and a closed state through the PMK chip. For example, when the PMK chip needs to send a signal to the first PMU device, the PMK chip can send a signal to the first switch combination for disconnecting the first switch combination; after the first switch combination is disconnected, the PMK chip can send a signal to the first PMU device. For another example, when the SOC chip needs to send a signal to the first PMU device, the PMK chip can send a signal to the first switch combination for closing the first switch combination; after the first switch combination is closed, the SOC chip can send a signal to the first PMU device.

[0072] In the embodiment of the present application, the SOC 401 may include the SPMI0 407 , and the PMK 402 may include the SPMI1 408 ; the SOC 401 is connected to the first differential line through the SPMI0 407 , and the PMK 402 is connected to the first differential line through the SPMI1 408 .

[0073] Among them, SPMI0 407 may correspond to the first SPMI, and SPMI1 408 may correspond to the second SPMI. Specifically, SPMI0 407 may be a pin of the SPMI routing in the SOC chip, and SPMI1 408 may be a pin of the SPMI bus in the PMK chip. When the SOC 401 of the electronic device is in a working state, the SOC 401 may send a signal to the SPMI1 408 of the PMK 402 through SPMI0 407, the PMK 402 receives the signal, the first combination switch 405 is in a closed state, and the signal is transmitted to the first PMU 403 through the PMK 402.

[0074] It should be noted that the number of the first PMU can be one or more; in the embodiment of the present application, the SOC chip and the PMK chip are connected in the electronic device so that the PMK chip does not need to be deployed on the end side of the SPMI bus. In this way, when the circuit is actually deployed, the circuit can reduce the layout restrictions of the first PMU. For example, after the SOC chip and the PMK chip are connected through the first differential line, multiple first PMUs can be connected to the PMK chip in series, wherein the position of the first PMU can be placed relatively randomly. In a possible implementation, after the SPMI bus is connected to the first PMU, it is also necessary to ensure that the SOC chip is provided on the end side. It can be seen that the electronic device in the embodiment of the present application can improve the connection method of the SPMI bus, making it easier to deploy the SOC chip, the PMK chip and the first PMU.

[0075] In addition, the electronic device provided in the embodiment of the present application can also avoid the master-slave switching problem between the PMK chip and the SOC chip. Figure 5 The node A shown in a in Figure 5 Node B shown in b in the figure is a node at the same position in the SPMI bus as an example; illustratively, when the first switch combination is closed, the signal sent by the SOC chip passes through node A from left to right to reach the first PMU; when the first switch combination is disconnected, the signal sent by the PMK chip passes through node B from left to right to reach the first PMU. For this node, the flow direction of the signal is always from left to right. In this way, the problem of the PMK chip and the SOC chip transmitting the signal in the forward direction and / or reverse direction on the SPMI bus during the master-slave switching process is avoided.

[0076] An electronic device provided by an embodiment of the present application includes: a SOC, a PMK, and a first PMU; the bus controllers of the SOC and the PMK, and the first PMU are connected in sequence through a first differential line; a first switch combination is provided in the portion of the first differential line between the bus controller of the SOC and the PMK; wherein, when the SOC sends a signal to the first PMU, the first switch combination is in a closed state; when the PMK sends a signal to the first PMU, the first switch combination is in an open state. In this way, the connection mode of the SPMI bus can be improved, and the chips and devices of the circuit can be easily deployed; and the master-slave switching problem of the SOC chip and the PMK chip can be alleviated.

[0077] In the above embodiment, the PMK chip may include a first switch combination. In some other embodiments, the PMK chip may not include the first switch combination, wherein the first differential line is provided with the first switch combination in the portion between the SOC chip and the PMK chip, such as Figure 6 As shown:

[0078] The electronic device includes: SOC 401, a first switch combination 405, PMK 402, and a first PMU 403; SOC 401, the first switch combination 405, a bus controller 404 of PMK 402, and the first PMU 403 are sequentially connected through a first differential line. When the SOC sends a signal to the first PMU, the first switch combination is in a closed state; when the PMK sends a signal to the first PMU, the first switch combination is in an open state.

[0079] When the SOC 401 of the electronic device is in working state, the SOC 401 can control the first PMU 403. The first switch combination is in a closed state, and the bus controller 404 is not working. After the SOC 401 sends a signal, the signal can reach the first PMU 403 through the first differential line to achieve communication between the SOC 401 and the first PMU 403.

[0080] When the SOC 401 of the electronic device is in a dormant state, the PMK 402 can control the first PMU 403. The first switch combination 405 is in an off state, and the SOC 401 does not work. After the PMK 402 sends a signal, the signal can reach the first PMU 403 through the first differential line to achieve communication between the PMK 402 and the first PMU 403.

[0081] The embodiments of the present application Figure 4 and Figure 5 The principles of the illustrated embodiments are similar and will not be described in detail here.

[0082] In the above embodiment, all or part of the PMUs in the mainboard need to be connected in series with the PMK chip, wherein each PMU will have certain delay requirements during operation. When the delay requirements of the PMU are high, the problem of insufficient SPMI bus transmission capacity may occur.

[0083] The required delay of the PMU device is first described below.

[0084] The motherboard of an electronic device may be provided with a PMU with multiple functions, and these PMUs often have certain requirements for signal delay. Among them, some PMUs have higher requirements for delay, which requires that the PMU device can quickly receive and respond to the signal after the SOC chip sends a signal. The PMU device with higher delay requirements may be a PMU device whose delay required for PMU operation is less than or equal to the preset delay threshold, and the PMU device whose delay required for PMU operation is less than or equal to the preset delay threshold may be a PMU device controlled by the SOC chip, for example: a PMU device for powering the SOC chip and a PMU device for voltage regulation, etc. Specifically, the PMU with higher delay requirements may be PM8550, PM8550VS, PM8550VE, etc.

[0085] PMU devices with higher latency requirements can be used in the following scenarios: for example, an electronic device receives a trigger operation from a user to start an application, and in response to the trigger operation, the electronic device starts the application. During the application startup process, PMU devices with higher latency requirements need to quickly receive the signal sent by the SOC and adjust the voltage. This is because: when an electronic device starts an application, the related devices in the electronic device require additional voltage to support the startup and operation of the application. The electronic device starting the application can be understood as an overload. At this time, the electronic device needs to increase the frequency by frequency modulation; on the one hand, the SOC chip in the electronic device needs to increase its own control voltage to ensure that the SOC chip can quickly control multiple PMUs for power supply; on the other hand, the SOC chip also needs to increase the power supply voltage of the PMU; the SOC chip and the PMU need to have the ability to quickly increase the voltage. Therefore, this part of the PMU often has higher latency requirements.

[0086] In the PMU, there are also some devices with lower requirements for latency. When the electronic device controls this part of the PMU based on the SOC chip, it may not be necessary to limit the latency required for the PMU operation to within the preset latency threshold. In some scenarios, PMU devices with lower latency requirements can be PMU devices where the latency required for the PMU operation is greater than the preset latency threshold. PMU devices with lower latency requirements can be used to power peripherals in electronic devices. For example, PMU devices can power input devices and output devices in electronic devices. Specifically, PMUs with lower latency requirements can be PM8550B and PM8010, among which PM8550B can be used for fast charging, powering motors, etc., and PM8010 is a power management unit that powers cameras.

[0087] The required delay of the PMU device is described above. In order to solve the load problem and delay problem on the SPMI bus, the embodiment of the present application also provides a power control circuit. Figure 7 A circuit control circuit provided by an embodiment of the present application is shown. Figure 7 As shown:

[0088] Exemplarily, the electronic device includes: SOC 401, PMK 402, a first PMU 403 and a second PMU 414; SOC 401, a bus controller 404 of PMK 402, a first PMU 403, and a second PMU 414 are connected in sequence through a first differential line; SOC 401 and a signal repeater 406 of PMK 402 are connected through a second differential line; a first switch combination 405 is provided in a portion of the first differential line between the first SOC 401 and the bus controller 404 of PMK 402; wherein, when SOC 401 sends a signal to PMU 403, the first switch combination 405 is in a closed state; when PMK 402 sends a signal to PMU 403, the first switch combination 405 is in an open state.

[0089] The signal repeater 406 is used to resend the signal, for example, the signal repeater 406 may be a repeater device. The PMK 402 may be used to send the target signal to the second PMU 414 corresponding to the target signal using the bus controller 404 of the PMK 402 when the signal repeater 406 receives the target signal of the SOC 401. The target signal may be a signal for controlling the second PMU.

[0090] In the electronic device, two SPMI buses may be set between the SOC 401 and the PMK 402, for example, a first differential line and a second differential line. The first differential line and the second differential line may pass different signals. For example, when the SOC chip sends a signal to the first PMU, the signal may reach the first PMU through the first differential line. When the SOC chip sends a target signal to the second PMU, the target signal may reach the PMK chip through the second differential line, and then the PMK chip transmits the target signal to the second PMU through the first differential line.

[0091] Multiple PMUs may also be connected to the first differential line, and the multiple PMUs are all connected in a direction away from the SOC from the first PMU. Figure 7 In the embodiment, the SPMI bus is first connected to the first PMU and then to the second PMU, and the SOC chip is not directly connected to the PMU. In the embodiment of the present application, the second PMU can also be connected between the first PMU and the PMK, and the embodiment of the present application does not limit this.

[0092] In the embodiment of the present application, the electronic device can control the first switch combination to be turned off according to the state of the SOC. For example, when the SOC chip is in the working state, the SOC 401 sends a signal to the first PMU 403 to control the first switch combination to be in the closed state; when the SOC chip is in the sleep state, the PMK 402 sends a signal to the first PMU 403 to control the first switch combination to be in the open state.

[0093] Specifically, when the SOC 401 of the electronic device is in a dormant state, the PMK 402 may control the first PMU 403 and the second PMU 414, such as Figure 8 As shown in a in FIG. 4 . The first switch combination 405 is in the off state, and the SOC 401 does not work. The PMK 402 can send a signal to the first PMU 403 through the bus controller 404, and the signal can reach the first PMU 403 through the first differential line, thereby realizing communication between the PMK 402 and the first PMU 403. Alternatively, the PMK 402 can send a signal to the second PMU 414 through the bus controller 404, and the signal can reach the second PMU 414 through the first differential line, thereby realizing communication between the PMK 402 and the second PMU 414.

[0094] When the SOC 401 of the electronic device is in working state, the SOC 401 can control the first PMU 403 and the second PMU 414, such as Figure 8 As shown in FIG. b in FIG. 401 , the first switch combination 405 is in a closed state. The SOC 401 can send a signal to the first PMU 403 through the first differential line, and the SOC 401 can also send a signal to the second PMU 414 through the second differential line.

[0095] After the SOC 401 sends a signal to the first PMU 403 through the first differential line, the signal can reach the first PMU 403 through the first switch combination 405 based on the first differential line.

[0096] After the SOC 401 sends the target signal through the second differential line, the target signal reaches the signal repeater 406 based on the second differential line; the signal repeater 406 resends the target signal, and the signal repeater 406 can pass the target signal to the bus controller 404 in the PMK 402; the bus controller 404 then passes the target signal to the second PMU 414 corresponding to the target signal.

[0097] It can be seen from the above process that the first PMU 403 and the second PMU 414 can be different PMU devices. When the SOC chip is working, the SOC chip of the electronic device can control part of the PMU through the first differential line, and the PMK chip of the electronic device can receive the signal from the second differential line and control another part of the PMU. In this way, the load pressure of the SOC controlling all the PMUs can be reduced.

[0098] In a possible implementation, a delay required for the operation of the first PMU is less than or equal to a delay required for the operation of the second PMU.

[0099] The delay required for the operation of the first PMU 403 is less than or equal to the preset delay threshold. The delay required for the operation of the second PMU 414 is greater than the preset delay threshold. For example, the first PMU may be a PMU with a higher delay requirement, and the second PMU may be a PMU with a lower delay requirement.

[0100] It can be understood that the target signal retransmission process and the target signal transmission process between the signal repeater 406 and the bus controller 404 can be regarded as a transparent transmission process. The electronic device can control the delay of transparent transmission, for example, the delay required for transparent transmission is relatively high. In this way, since the target signal is used to control the second PMU device whose delay required for operation is greater than the preset delay threshold, the second PMU device has a relatively low delay requirement. The high delay in the transparent transmission process will not have much impact on the PMU device with lower delay requirements. Therefore, in this way, the electronic device can control the PMU device with higher delay requirements based on the SOC chip when the SOC chip sends a signal. For example, the SOC chip can control the PMU that powers the SOC chip and the PMU used for voltage regulation, etc.; and control the PMU device with lower delay requirements based on the PMK chip. For example, the PMK can control the PMU that powers the peripherals.

[0101] In an embodiment of the present application, when the SOC chip is in working state, the electronic device divides the PMU that originally needs the SOC chip to control into two parts. One part of the PMU devices with higher latency requirements is controlled by the SOC chip, for example, the signal used to control the PMU with higher latency requirements goes through the first differential line to reach the PMU; the other part of the PMU devices with lower latency requirements is controlled by the PMK, for example, the target signal sent by the SOC chip first goes through the second differential line to reach the PMK, and after the signal is retransmitted by the PMK signal repeater, it is transmitted by the bus controller to the PMU device with lower latency requirements. In this way, the two SPMI bus method can reduce the pressure of signal transmission on a single SPMI bus compared to the single SPMI bus method.

[0102] It should be noted that in the embodiment of the present application, the SOC chip may have a scenario in which it sends out a signal for controlling the first PMU and a target signal at the same time. The signal for controlling the first PMU can quickly reach the first PMU device through the first differential line. However, the target signal has a high latency after transparent transmission, and the time when the target signal arrives at the second PMU device may be later than the time when the signal for controlling the first PMU arrives at the first PMU. In this way, the electronic device can give priority to controlling the first PMU to avoid the target signal occupying resources and ensure that the latency requirements of the first PMU are met; at the same time, the latency of transparent transmission will not affect the PMK's control of the second PMU; in addition, the PMK can share part of the load for the SOC and reduce the operating pressure of the SOC.

[0103] It is understandable that in the embodiment of the present application, when the SPC chip is working, the load of the electronic device may be heavy. When the SOC chip is dormant, the load of the electronic device is often low, and the pressure of the PMK controlling the PMU is low. Therefore, the electronic device in the embodiment of the present application may not adjust the control process of the PMK chip. The embodiment of the present application is not limited to this.

[0104] In a possible implementation, two SPMI interfaces may be provided in the SOC chip, for example, Figure 7 As shown, SOC 401 includes SPMI0 407 and SPMI2 409. Correspondingly, two SPMI interfaces are also provided in the PMK chip, for example, Figure 7 As shown, PMK 402 includes SPMI1 408 and SPMI3 410 .

[0105] The SOC is connected to the first differential line through SPMI0 407 and to the second differential line through SPMI2 409 ; the PMK is connected to the first differential line through SPMI1 408 and to the second differential line through SPMI3 410 .

[0106] Among them, SPMI0 407 may also be referred to as a first SPMI, SPMI2 409 may also be referred to as a second SPMI, SPMI1 408 may also be referred to as a third SPMI, and SPMI3 410 may also be referred to as a fourth SPMI.

[0107] The above embodiments illustrate the electronic device provided by the embodiments of the present application. The SOC chip can communicate with the PMU, and the PMK chip can also communicate with the PMU. In addition, in some scenarios, the SOC chip can also communicate with the PMK chip. For example, Figures 4 to 7 In the electronic device shown, when the SOC chip can communicate with the PMK chip, the first switch combination can be in a closed state, and the signal of the PMK chip can be received by the SOC chip. However, in actual applications, the path between the bus controller and the PMU can form a branch route, resulting in a back-channel in the signal transmitted between the SOC chip and the PMK chip, affecting the communication between the SOC chip and the PMK chip. To solve the above problem, the embodiment of the present application also provides an electronic device. Fig. 9 An electronic device provided by an embodiment of the present application is shown, such as Fig. 9 As shown:

[0108] Exemplarily, the electronic device includes: SOC 401, PMK 402 and first PMU 403; SOC 401, bus controller 404 of PMK 402, and first PMU 403 are connected in sequence through a first differential line; a first switch combination 405 is provided at a portion of the first differential line between SOC 401 and bus controller 404 of PMK 402; a second switch combination 411 is provided at a portion of the first differential line between bus controller 404 of PMK 402 and first PMU 403; wherein, when SOC 401 sends a signal to first PMU 403, first switch combination 405 is in a closed state, and second switch combination 411 is in a closed state; when PMK 402 sends a signal to first PMU 403, first switch combination 405 is in an open state, and second switch combination 411 is in a closed state; when PMK 402 sends a signal to SOC When 401 sends a signal, the first switch combination 405 is in a closed state, and the second switch combination 411 is in an open state.

[0109] The second switch combination 411 may be two switch elements disposed on the first differential line, and the switch elements in the second switch combination 405 may be switch elements such as diodes, triodes, and metal-oxide-semiconductor (MOS) transistors, etc. This embodiment of the application does not limit this.

[0110] In the embodiment of the present application, the electronic device can control the shut-down of the first switch combination and / or the second switch combination according to the communication process between the SOC chip, the PMK chip and the PMU.

[0111] Exemplarily, when the SOC 401 is in the working state, the SOC 401 sends a signal to the first PMU 403 to control the first switch combination 405 to be closed and the second switch combination 411 to be closed; or, the PMK 402 sends a signal to the SOC 401 to control the first switch combination 405 to be closed and the second switch combination 411 to be opened. When the SOC 401 is in the sleep state, the PMK 402 sends a signal to the first PMU 403 to control the first switch combination 405 to be opened and the second switch combination 411 to be closed.

[0112] Specifically, when the SOC 401 sends a signal to the first PMU 403, the first switch combination 405 is in a closed state, and the second switch combination 411 is in a closed state, such as Fig.10 After the SOC 401 sends a signal, the signal can reach the first PMU 403 through the first differential line to achieve communication between the SOC 401 and the first PMU 403.

[0113] When the PMK 402 sends a signal to the first PMU 403, the first switch combination 405 is in an open state, and the second switch combination 411 is in a closed state, such as Fig.10 After the PMK 402 sends a signal through the bus controller 404 , the signal can reach the first PMU 403 through the first differential line to achieve communication between the PMK 402 and the first PMU 403 .

[0114] The above two processes can refer to Figure 4 The relevant description in the embodiments of the present invention will not be repeated here.

[0115] When PMK 402 sends a signal to SOC 401, the first switch combination 405 is in a closed state, and the second switch combination 411 is in an open state, such as Fig.10 After PMK 402 sends a signal through bus controller 404, the signal can reach SOC 401 through the first differential line to achieve communication between PMK 402 and SOC 401.

[0116] In the embodiment of the present application, the electronic device can realize the communication between the SOC chip and the PMK chip by closing the first switch combination and opening the second switch combination. In this way, when the SOC chip communicates with the PMK chip, it is avoided that the wiring of the PMK chip and the first PMU forms a branch route, which affects the communication signal between the SOC chip and the PMK chip.

[0117] exist Figure 7 and Fig. 9 Based on the shown embodiment, Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. Fig.11 As shown:

[0118] Exemplarily, the electronic device includes: SOC 401, PMK 402, a first PMU 403 and a second PMU 414; SOC 401, a bus controller 404 of PMK 402, a first PMU 403 and a second PMU 414 are connected in sequence through a first differential line; SOC 401 and a signal repeater 406 of PMK 402 are connected through a second differential line; a first switch combination 405 is provided at a portion of the first differential line between SOC 401 and the bus controller 404 of PMK 402; a second switch combination 411 is provided at a portion of the first differential line between the bus controller 404 of PMK 402 and the first PMU 403.

[0119] Among them, when SOC 401 sends a signal to the first PMU 403 and / or the second PMU 414, the first switch combination 405 is in a closed state, and the second switch combination 411 is in a closed state; when PMK 402 sends a signal to the first PMU 403 and / or the second PMU 414, the first switch combination 405 is in an open state, and the second switch combination 411 is in a closed state; when PMK 402 sends a signal to SOC 401, the first switch combination 405 is in a closed state, and the second switch combination 411 is in an open state.

[0120] In the embodiment of the present application, the electronic device can control the shut-down of the first switch combination and / or the second switch combination according to the communication process between the SOC chip, the PMK chip and the PMU.

[0121] Exemplarily, when the SOC is in the working state, the SOC sends a signal to the first PMU and / or the second PMU to control the first switch combination to be closed and the second switch combination to be closed; and / or the bus controller of the PMK sends a signal to the second PMU; the PMK sends a signal to the SOC to control the first switch combination to be closed and the second switch to be opened. When the SOC is in the dormant state, the PMK sends a signal to the first PMU and / or the second PMU to control the first switch combination to be opened and the second switch combination to be closed.

[0122] Specifically, in a possible implementation, when PMK 402 sends a signal to the first PMU 403 and / or the second PMU 414, the first switch combination 405 is in an open state, and the second switch combination 411 is in a closed state. After PMK 402 sends a signal through bus controller 404, the signal can reach the first PMU 403 and / or the second PMU 414 through the first differential line, so as to realize communication between PMK 402 and the first PMU 403 and / or the second PMU 414.

[0123] In another possible implementation, when the SOC 401 of the electronic device is in working state, the SOC 401 can control the PMU 403, the first switch combination 405 is in a closed state, and the second switch combination 411 is in a closed state. The SOC 401 can send a signal to the first PMU 403, and the SOC 401 can also send a signal to the second PMU 414.

[0124] For example, after SOC 401 sends a signal to first PMU 403, the signal can reach first PMU 403 through first switch combination 405 and second switch combination 414 based on the first differential line, wherein the delay required for operation of first PMU 403 is less than or equal to a preset delay threshold.

[0125] For another example, after the SOC 401 sends a signal to the second PMU 414, the signal reaches the signal repeater 406 based on the second differential line; the signal repeater 406 resends the signal, and the signal repeater 406 can pass the signal to the bus controller 404 in the PMK 402; the bus controller 404 then transmits the signal to the second PMU 414 through the first differential line, wherein the delay required for the operation of the second PMU 414 is greater than the preset delay threshold.

[0126] The principles of the above two processes can be referred to Figure 7 The relevant description in the embodiments of the present invention will not be repeated here.

[0127] In another possible implementation, when PMK 402 sends a signal to SOC 401, first switch combination 405 is in a closed state, and second switch combination 411 is in an open state. After PMK 402 sends a signal through bus controller 404, the signal can reach SOC 401 through the first differential line to achieve communication between PMK 402 and SOC 401.

[0128] In the embodiment of the present application, the electronic device can realize the communication between the SOC chip and the PMK chip by closing the first switch combination and opening the second switch combination. In this way, when the SOC chip communicates with the PMK chip, it is avoided that the wiring of the PMK chip and the first PMU forms a branch route, which affects the communication signal between the SOC chip and the PMK chip.

[0129] In the embodiment of the present application, the first switch combination and the second switch combination can be respectively set in the PMK chip, and the first switch combination and the second switch combination can also be respectively set on the routing between the SOC chip and the PMK chip and the routing between the SOC chip and the PMU. The embodiment of the present application is not limited to this.

[0130] It should be noted that in Figure 4-Figure 11 In the embodiment shown, the positions of the SOC chip and the PMK chip can be connected in sequence by a differential line. In the embodiment of the present application, the positions of the SOC chip and the PMK chip can also be connected in sequence by a differential line, and the embodiment of the present application will not elaborate on this implementation method.

[0131] The above embodiments illustrate the structures of four electronic devices that improve the SPMI bus connection mode in the embodiments of the present application. The embodiments of the present application also provide an electronic device that can reduce the delay and increase the data transmission volume of the SPMI bus, such as Fig.12 As shown:

[0132] Exemplarily, the electronic device may include: SOC 401, PMK 402, M PMUs, M is an integer greater than 1; SOC 401, L PMUs 412 among the M PMUs, and PMK 402 are connected in sequence through a first differential line; SOC 401, K PMUs 413 among the M PMUs, and PMK 402 are connected in sequence through a second differential line, the sum of L and K is M, and the first differential line is not connected to the second differential line.

[0133] Among them, the SPMI interface of SOC 401 includes SPMI0 407 and SPMI2 409, and the SPMI interface of PMK 402 includes SPMI1 408 and SPMI3 410; SOC 401 is connected to the first differential line through SPMI0 407, and is connected to the second differential line through SPMI2 409; PMK 402 is connected to the first differential line through SPMI1 408, and is connected to the second differential line through SPMI3 410.

[0134] SPMI0 407 may correspond to a first SPMI, SPMI2 409 may correspond to a second SPMI, SPMI1 408 may correspond to a third SPMI, and SPMI3 410 may correspond to a fourth SPMI.

[0135] When the SOC 401 is in the working state, the SOC 401 can send a signal to the L PMUs 412 through the first differential line, and / or send a signal to the K PMUs 413 through the second differential line. When the SOC 401 is in the sleeping state, the PMK 402 can send a signal to the L PMUs 412 through the first differential line, and / or send a signal to the K PMUs 413 through the second differential line.

[0136] It is understandable that in a possible implementation, a large number of PMUs are deployed in the motherboard, for example, the number of PMUs may be 10. However, the SOC chip is only provided with one SPMI interface, and only one SPMI bus is provided between the SOC chip and the PMK chip. Figure 1 As shown. Therefore, in a possible implementation, many PMU devices need to be set on the SPMI bus. The data transmission volume of the signal in this method is low and the latency is high. This is because: taking the SOC chip transmitting signal as an example, when the SOC chip controls multiple PMUs, the SOC chip can send multiple signals for controlling the corresponding PMU devices. According to the SPMI protocol, these signals will be pushed into the Buffer first, and then the data will be transmitted in sequence according to the order of the signals in the Buffer. For example, after one data is pushed out of the Buffer, the next data will be pushed out. When the amount of data is large, the SPMI bus will be very busy and the transmission pressure will be high, which may lead to a scenario where a PMU with higher requirements cannot receive the signal within the preset latency threshold.

[0137] To address the above problem, the SOC 401 in the embodiment of the present application is provided with two SPMI interfaces, so that the signal between the SOC 401 and the PMK 402 can be transmitted through two SPMI buses. For example, the two SPMI buses are respectively a first differential line and a second differential line.

[0138] The signals sent to the L PMUs 412 can be transmitted via the first differential line, and the signals sent to the K PMUs 413 can be transmitted via the second differential line. In this way, compared with a single SPMI bus, the data transmission volume of the two SPMI buses is significantly increased, effectively shortening the delay of the signal reaching the PMU, so that the SOC chip can schedule the PMU more quickly.

[0139] In one possible implementation, the L PMUs 412 and the K PMUs 413 may be different PMU devices. The electronic device does not restrict the PMU devices connected to the first differential line and the PMU devices connected to the second differential line. For example, 10 PMU devices are deployed in the motherboard, of which any 6 PMU devices can be connected to the first differential line, and the remaining 4 PMU devices can be connected to the second differential line. The embodiment of the present application does not restrict the total number M of PMUs and the number L and K of PMUs connected to each SPMI bus.

[0140] In the embodiment of the present application, the electronic device can increase the data transmission volume of the SPMI bus and reduce the delay of the signal reaching the PMU by setting two SPMI buses. In addition, this method can also reduce the complexity of the SPMI bus layout in the motherboard and shorten the wiring length.

[0141] For example, Fig.13 As shown, the mainboard of the electronic device may include two SPMI buses, wherein the line marked with a solid line may be a first differential line, and the line marked with a dotted line may be a second differential line. It can be seen that the length of any SPMI bus is less than Figure 1 The length of the SPMI bus shown in b shortens the length of the wiring that the signal sent by the SOC chip or PMK chip passes through when reaching the PMU, which can effectively reduce the delay and increase the data transmission volume.

[0142] In addition, since the number of PMUs connected to any SPMI bus in the embodiment of the present application is less than Figure 1 The number of PMUs connected to the SPMI bus is shown in b in the figure, so the embodiment of the present application can reduce the complexity of the SPMI bus and simplify the deployment of PMUs. Fig.13 The number of PMUs connected to the third SPMI bus shown is 4, and Figure 1 The number of PMUs connected to the SPMI bus shown in b is 7. In the process of deploying the PMUs on the mainboard, the embodiment of the present application only needs to consider the placement of 4 PMUs in the mainboard, thereby reducing the difficulty of the SPMI bus layout.

[0143] exist Fig.12 Based on the illustrated embodiment, the embodiment of the present application further provides a solution for dividing PMU1 412 and PMU2 413 .

[0144] Exemplarily, in one possible implementation, the delay required for the operation of L PMUs is less than or equal to the delay required for the operation of K PMUs; for example, the delay required for the operation of L PMUs 412 may be less than or equal to a preset delay threshold, and the delay required for the operation of K PMUs 413 is greater than the preset delay threshold.

[0145] In the embodiment of the present application, the electronic device can classify the PMUs according to the delay required for operation, connect the PMUs whose delay required for operation is less than or equal to the preset delay threshold to the first differential line, and connect the PMUs whose delay required for operation is greater than the preset delay threshold to the second differential line. Alternatively, the electronic device can connect the PMUs whose delay required for operation is less than or equal to the preset delay threshold to the second differential line, and connect the PMUs whose delay required for operation is greater than the preset delay threshold to the first differential line.

[0146] For example, the first differential line can access one PM8550, four 8550VS and one PM8550VE; the second differential line can access one PM8550B and multiple PM8010. The embodiment of the present application only provides an exemplary method for multiple PMUs to access two SPMI buses according to latency requirements. The embodiment of the present application does not limit the number of PMUs on each bus and the specific chip form of the PMU.

[0147] In the embodiment of the present application, the electronic device divides the PMU devices into PMU devices with higher delay requirements and PMU devices with lower delay requirements according to the relationship between the delay required for the operation of the PMU and the preset delay threshold. It can be understood that when a PMU with higher delay requirements and a PMU with lower delay requirements exist on an SPMI bus at the same time, the PMU with lower delay requirements may increase the delay on the bus, resulting in the delay being unable to meet the delay required for the operation of the PMU with higher delay requirements, resulting in the SOC chip or PMK chip being unable to quickly control the PMU with higher delay requirements. Therefore, the embodiment of the present application can be classified according to the delay requirements of the PMU, with one SPMI bus used to transmit the signal sent by the chip to the PMU with higher delay requirements, and one SPMI bus used to transmit the signal sent by the chip to the PMU with lower delay requirements, so as to further shorten the delay.

[0148] The present application embodiment takes the SOC chip having two SPMI buses as an example to explain the power control circuit. In the present application embodiment, the SOC chip may also be provided with multiple SPMI interfaces, and multiple SPMI buses may be provided between the SOC chip and the PMK chip. The present application embodiment does not limit this.

[0149] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0150] The electronic device provided in the embodiment of the present application may also satisfy the following structure, such as Fig.14 As shown:

[0151] For example, electronic devices can also be called terminals, terminal equipment, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. Terminal equipment can be mobile phones, smart TVs, wearable devices, tablet computers, computers with wireless transceiver functions, virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0152] Among them, wearable devices can also be called wearable smart devices, which are a general term for the intelligent design and development of wearable devices for daily wear using wearable technology, such as glasses, gloves, watches, clothing and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also realize powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include full-featured, large-sized, and independent of smartphones to achieve complete or partial functions, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0153] In addition, in the embodiments of the present application, the terminal device may also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection. The embodiments of the present application do not limit the specific technology and specific device form adopted by the terminal device.

[0154] In an embodiment of the present application, the terminal device may include a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and a memory (also called main memory). The operating system may be any one or more computer operating systems that implement business processing through processes, such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a Windows operating system. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0155] Fig.14 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. Fig.14 As shown: the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0156] Among them, the sensor module 180 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

[0157] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0158] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and / or a neural network processor (neural-network processing unit, NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. In the embodiment of the present application, the processor 110 may also be a SOC.

[0159] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0160] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0161] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device. In an embodiment of the present application, the power management module may include a PMK chip and a PMU chip. Among them, the PMU chip is used to manage power, and the PMK chip can be used to manage the PMU chip and clock, etc.

[0162] The above embodiments illustrate the structure of the electronic device provided in the embodiments of the present application. Fig.15 A control method provided in an embodiment of the present application is shown, and the control method can be applied to the electronic device described in the above embodiment. The control method includes:

[0163] S1501 . When the SOC sends a signal to the first PMU, control the first switch combination to be in a closed state.

[0164] S1502: When the PMK sends a signal to the first PMU, control the first switch combination to be in an off state.

[0165] Among them, steps S1501-S1502 can refer to Figure 4 The relevant descriptions in the illustrated embodiments are not repeated in the embodiments of the present application.

[0166] The control method provided in the embodiment of the present application controls the first switch combination to be in a closed state when the SOC sends a signal to the first PMU; and controls the first switch combination to be in an open state when the management chip sends a signal to the first PMU. In this way, the connection mode of the SPMI bus can be improved, and the chips and devices of the circuit can be easily deployed; and the master-slave switching problem between the SOC chip and the PMK chip can be alleviated.

[0167] Optionally, a second switch combination is provided in a portion of the first differential line between the bus controller of the PMK and the first PMU, and the method further includes: when the SOC sends a signal to the first PMU, controlling the first switch combination to be in a closed state, and controlling the second switch combination to be in a closed state; when the PMK sends a signal to the first PMU, controlling the first switch combination to be in an open state, and controlling the second switch combination to be in a closed state; when the PMK sends a signal to the SOC, controlling the first switch combination to be in a closed state, and controlling the second switch combination to be in an open state.

[0168] Among them, the control method can refer to Fig. 9 The relevant descriptions in the illustrated embodiments will not be repeated in the embodiments of the present application.

[0169] Combined with the above Fig.15 , the control method provided in the embodiment of the present application is described, and the device for executing the above control method provided in the embodiment of the present application is described below. Fig.16 As shown, Fig.16 A schematic diagram of the structure of a control device provided in an embodiment of the present application. The control device may be an electronic device in an embodiment of the present application, or a chip or chip system in an electronic device.

[0170] like Fig.16 As shown, the control device 1600 can be used in a communication device, a circuit, a hardware component or a chip, and the control device includes: a display unit 1601 and a processing unit 1602. The display unit 1601 is used to support the display step performed by the control device 1600; the processing unit 1602 is used to support the control device 1600 to perform the information processing step.

[0171] In a possible implementation, the control device 1600 may also include a communication unit 1603. Specifically, the communication unit is used to support the control device 1600 to execute the steps of sending and receiving data. The communication unit 1603 may be an input or output interface, a pin or a circuit.

[0172] In some embodiments, the control device 1600 may further include: a storage unit 1604. The processing unit 1602 and the storage unit 1604 are connected via a line. The storage unit 1604 may include one or more memories, and the memory may be a device used to store programs or data in one or more devices or circuits. The storage unit 1604 may exist independently and be connected to the processing unit 1602 of the control device via a communication line. The storage unit 1604 may also be integrated with the processing unit 1602.

[0173] The storage unit 1604 may store computer-executable instructions of the method in the terminal device so that the processing unit 1602 executes the method in the above embodiment. The storage unit 1604 may be a register, a cache, or a RAM, etc. The storage unit 1604 may be integrated with the processing unit 1602. The storage unit 1604 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, and the storage unit 1604 may be independent of the processing unit 1602.

[0174] The control method provided in the embodiment of the present application can be applied to electronic devices with communication functions. The electronic devices include terminal devices, and the specific device form of the terminal devices can refer to the above related descriptions, which will not be repeated here.

[0175] An embodiment of the present application provides a terminal device, which includes: a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, so that the terminal device executes the above method.

[0176] The embodiment of the present application provides a chip. The chip includes a processor, and the processor is used to call a computer program in a memory to execute the technical solution in the above embodiment. Its implementation principle and technical effect are similar to those of the above related embodiments, and will not be repeated here.

[0177] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program. The above method is implemented when the computer program is executed by the processor. The method described in the above embodiment can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium that can be accessed by a computer.

[0178] In one possible implementation, a computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that is intended to carry or store the required program code in the form of instructions or data structures and can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of medium. Disks and optical disks as used herein include optical disks, laser disks, optical disks, digital versatile disks (DVD), floppy disks and Blu-ray disks, where disks usually reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included in the scope of computer-readable media.

[0179] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above method.

[0180] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0181] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. An electronic device, characterized in that: include: A system-on-chip (SOC), a management chip and a first power management unit; wherein the management chip is used to manage the first power management unit; The SOC, the bus controller of the management chip, and the first power management unit are connected in sequence via a first differential line; A first switch combination is provided at a portion of the first differential line between the SOC and the bus controller of the management chip; When the SOC sends a signal to the first power management unit, the first switch combination is in a closed state; when the management chip sends a signal to the first power management unit, the first switch combination is in an open state.

2. The electronic device according to claim 1, characterized in that: A second switch combination is provided at a portion of the first differential line between the bus controller of the management chip and the first power management unit; Among them, when the SOC sends a signal to the first power management unit, the first switch combination is in a closed state, and the second switch combination is in a closed state; when the management chip sends a signal to the first power management unit, the first switch combination is in an open state, and the second switch combination is in a closed state; when the management chip sends a signal to the SOC, the first switch combination is in a closed state, and the second switch combination is in an open state.

3. The electronic device according to claim 1, characterized in that: A plurality of power management units are also connected in series on the first differential line, and the plurality of power management units are all connected in a direction in which the first power management unit is away from the SOC, and the management chip further includes a signal repeater; The signal repeater is connected to the SOC via a second differential line; The management chip is used for, when the signal repeater receives the target signal of the SOC, using the bus controller of the management chip to send the target signal to the second power management unit corresponding to the target signal.

4. The electronic device according to claim 3, characterized in that: The SOC includes a first system power management interface and a second system power management interface, and the management chip includes a third system power management interface and a fourth system power management interface; The SOC is connected to the first differential line through the first system power management interface, and is connected to the second differential line through the second system power management interface; the management chip is connected to the first differential line through the third system power management interface, and is connected to the second differential line through the fourth system power management interface.

5. The electronic device according to claim 4, characterized in that: The delay required for the first power management unit to operate is less than or equal to the delay required for the second power management unit to operate.

6. The electronic device according to any one of claims 1 to 5, characterized in that: When the SOC is in a working state, the SOC sends a signal to the first power management unit and / or the second power management unit to control the first switch combination to be closed and the second switch combination to be closed; the management chip sends a signal to the SOC to control the first switch combination to be closed and the second switch to be opened; When the SOC is in a dormant state, the management chip sends a signal to the first power management unit and / or the second power management unit to control the first switch combination to be opened and the second switch combination to be closed.

7. An electronic device, characterized in that: include: A system-on-chip (SOC), a management chip, and M power management units, where M is an integer greater than 1; wherein the management chip is used to manage the M power management units; The SOC, L power management units among the M power management units, and the management chip are connected in sequence through a first differential line; The SOC, K power management units among the M power management units, and the management chip are sequentially connected through a second differential line, the sum of L and K is M, and the first differential line is not connected to the second differential line; When the SOC is in a working state, the SOC sends a signal to a power management unit among the M power management units; When the SOC is in a dormant state, the management chip sends a signal to a power management unit among the M power management units.

8. The electronic device according to claim 7, characterized in that: The SOC includes a first system power management interface and a second system power management interface, and the management chip includes a third system power management interface and a fourth system power management interface; The SOC is connected to the first differential line through the first system power management interface, and is connected to the second differential line through the second system power management interface; the management chip is connected to the first differential line through the third system power management interface, and is connected to the second differential line through the fourth system power management interface.

9. The electronic device according to claim 8, characterized in that: The delay required for the L power management units to operate is less than or equal to the delay required for the K power management units to operate.

10. A control method, characterized in that: Applied to the electronic device according to any one of claims 1 to 9, the method comprises: When the SOC sends a signal to the first power management unit, the first switch combination is controlled to be in a closed state; When the management chip sends a signal to the first power management unit, the first switch combination is controlled to be in an off state.

11. The method according to claim 10, characterized in that A second switch combination is provided on a portion of the first differential line between the bus controller of the management chip and the first power management unit, and the method further includes: When the SOC sends a signal to the first power management unit, control the first switch combination to be in a closed state, and control the second switch combination to be in a closed state; When the management chip sends a signal to the first power management unit, the first switch combination is controlled to be in an open state, and the second switch combination is controlled to be in a closed state; When the management chip sends a signal to the SOC, the first switch combination is controlled to be in a closed state, and the second switch combination is controlled to be in an open state.

12. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to claim 10 or 11 is implemented.

13. A computer program product, characterized in that It comprises a computer program which, when being executed, causes a computer to execute the method as claimed in claim 10 or 11.

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