IIR digital filter with accelerated settling time in engineering

Abstract

The invention is an IIR digital filter that accelerates the stabilization time in engineering. The invention designs an initial value feedforward circuit in the IIR filter, assigns the estimated result to the register in the filter as the initial value according to the sampling data of the corresponding filter output unstable data when the IIR filter circuit starts working, reduces the distortion of the output signal after the IIR filter starts working, and reduces the time from starting to stable working of the IIR filter. In addition, the initial value feedforward circuit only includes simple multiplication and addition operations, and has relatively small impact on the area consumption and timing of the hardware circuit.

Description

Technical Field

[0001] The invention relates to the technical field of digital signal processing, and in particular to an IIR digital filter for accelerating stabilization time in engineering. Background Art

[0002] In the field of digital signal processing, IIR filters are often used to filter interference signals due to their good frequency screening characteristics. In the field of digital signal processing, IIR filters are often used to filter interference signals due to their good frequency screening characteristics. Taking the classic second-order digital filter as an example, its logical structure is as follows: Figure 1 shown.

[0003] In a typical application, the initial value of the D flip-flop in the circuit is generally 0x0. When the target frequency to be screened is simulated and input into the IIR filter circuit, it can be seen that the output of the IIR filter takes a certain amount of time to reach a stable state. Refer to the following simulation example, the sampling rate is 640kHz, and the target screening frequency is 10KHz: The parameters related to the zero point in the figure are b(0), b(1) and b(2), and the parameters related to the pole are a(1) and a(2). By designing reasonable parameters, the characteristic frequency can be screened. Taking the design of a bandpass IIR digital filter as an example, in a specific application, assuming that the sampling frequency is 640KHz and the target frequency to be screened is 10KHz, after completing the design of the specific parameters, the frequency response curve and phase response curve of the filter may be as follows: Figure 2 As shown. Figure 2 It can be seen that after the target frequency signal to be screened passes through the IIR filter, its phase and amplitude may change to a certain extent. The more the interference signal deviates from the target frequency to be screened, the higher the attenuation degree will be.

[0004] Generally, the IIR filter is implemented by four groups of D flip-flops. -1 Delay, 5 multipliers realize the multiplication operation of the input discrete signal and the coefficient, two adders realize the addition and subtraction operation, and the five coefficients of a(1)a(2)b(0)b(1)b(2) come from the configuration register of the circuit and are configured by software according to the specific application scenario.

[0005] In typical applications, the initial value of the D flip-flop in the circuit is generally 0x0. When the target frequency to be screened is simulated and input into the IIR filter circuit, it can be seen that the output of the IIR filter takes a certain amount of time to reach a stable state. Refer to the following simulation example, the sampling rate is 640kHz, and the target screening frequency is 10KHz: adc_in is the input data of the IIR filter, adc_out is the output data of the IIR filter, when the iir_en signal is enabled, the output of the IIR filter is severely distorted at the beginning, and then the IIR filter will become stable after more than 100 sampling data. In actual use, it means that the data for a period of time after the IIR filter is enabled is unavailable. In some cases where the equipment needs to be started and stopped repeatedly, the data for a period of time after each restart of the IIR filter needs to be discarded. Through the above introduction to the basic principles of IIR, it can be known that the main reason for this process is that when the IIR is just started, the initial value of the two D flip-flops on the right side of the circuit diagram is 0. These two D flip-flops need to go through a certain period of iteration before they can be almost the same as the normal output. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an IIR digital filter with accelerated settling time in engineering, so as to solve the above technical problems in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides an IIR digital filter for accelerating the stabilization time in engineering, wherein the filter comprises: a first calculation circuit, a second calculation circuit and a total calculation circuit which are jointly constituted by four groups of D flip-flops, five multipliers and two adders; the filter further comprises: a selection device and an initial value feedforward circuit which uses S parameters for calculation; wherein the input signal of the current target frequency to be screened is sequentially input into the first calculation circuit and the initial value feedforward circuit, and the first calculation circuit and the initial value feedforward circuit respectively output a first calculation signal and an initial value calculation signal corresponding to the input signal of the current target frequency to be screened; the input signal corresponding to the previous target frequency to be screened output by the total calculation circuit, which is selected by the selection device based on judging whether the input signal of the current target frequency to be screened corresponds to the unstable signal output by the filter, is input into the first calculation circuit and the initial value feedforward circuit in sequence, and the first calculation circuit and the initial value feedforward circuit respectively output a first calculation signal and an initial value calculation signal corresponding to the input signal of the current target frequency to be screened The output signal of the initial value feedforward circuit or the initial value calculation signal of the input signal of the current target frequency to be screened outputted by the initial value feedforward circuit is inputted into the second calculation circuit, and the second calculation circuit outputs the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened; the first calculation signal, the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened are inputted into the total calculation circuit, and the total calculation circuit outputs the output signal corresponding to the input signal of the current target frequency to be screened; wherein, the output signal and the initial value calculation signal corresponding to the input signal of the current target frequency to be screened are inputted into the selection device for selection, so that the output signal selected by the selection device or the initial value calculation signal outputted by the initial value feedforward circuit is inputted into the second calculation circuit to output the second calculation signal corresponding to the input signal of the next target frequency to be screened.

[0008] In one embodiment of the present invention, the first calculation circuit is composed of two groups of D flip-flops, three multipliers and an adder; wherein, the first calculation circuit includes: a first D flip-flop, a second D flip-flop, a first multiplier, a second multiplier, a third multiplier and a first adder; and wherein, the Q port of the first D flip-flop is connected to the initial value feedforward circuit, the first D flip-flop and the D port of the second D flip-flop; the Q port of the second D flip-flop is connected to the third multiplier; the first adder is connected to the first multiplier, the second multiplier and the third multiplier; the input signal of the current target frequency to be screened is input into the first multiplier, and the calculation is performed based on the set first parameter related to the zero point, and the output is the first a calculation sub-signal; at the same time, the input signal of the current target frequency to be screened is input into the first D flip-flop for delay, and the signal delayed by the first D flip-flop is output to the second multiplier, the second D flip-flop and the initial value feedforward circuit respectively, the second multiplier calculates and outputs the second calculation sub-signal based on the set second parameter related to the zero point, and the second D flip-flop is delayed, and the third multiplier calculates and outputs the delayed signal output from the Q port of the second D flip-flop based on the set third parameter related to the zero point; the first adder calculates and obtains the first calculation signal based on the first calculation sub-signal, the second calculation sub-signal and the third calculation sub-signal.

[0009] In one embodiment of the present invention, the second calculation circuit is composed of two groups of D flip-flops and two multipliers; wherein the second calculation circuit includes: a third D flip-flop, a fourth D flip-flop, a fourth multiplier and a fifth multiplier; and wherein the D port of the third D flip-flop is connected to the selection device, the Q port of the third D flip-flop is connected to the fourth multiplier and the D port of the fourth D flip-flop; the Q port of the fourth D flip-flop is connected to the fifth multiplier; the output signal corresponding to the input signal of the previous target frequency to be screened or the initial value calculation signal of the input signal corresponding to the current target frequency to be screened selected by the selection device is input to the third D flip-flop for delay, the signal delayed by the third D flip-flop is input to the fourth multiplier and the fourth D flip-flop respectively, the fourth multiplier is used to calculate based on the set first parameter related to the pole to obtain the second calculation signal, and the fourth D flip-flop is used to delay, and the fifth multiplier is used to calculate based on the set second parameter related to the pole to obtain the third calculation signal.

[0010] In one embodiment of the present invention, the initial value feedforward circuit is composed of two adders and a multiplier.

[0011] In one embodiment of the present invention, the initial value feedforward circuit includes: a first initial feedforward adder, a second initial feedforward adder and an initial feedforward multiplier; and wherein the second initial feedforward adder is connected to the first initial feedforward adder and the initial feedforward multiplier respectively; the first initial feedforward adder is connected to the Q port of the first D flip-flop; the input signal of the current target frequency to be screened and the signal delayed by the first D flip-flop are input to the first initial feedforward adder for calculation to obtain a fourth calculation sub-signal; the fourth calculation sub-signal is input to the initial feedforward multiplier for calculation based on the S parameter to obtain a fifth calculation sub-signal; the input signal of the current target frequency to be screened and the fifth calculation sub-signal are input to the second initial feedforward adder for calculation to obtain an initial value calculation signal.

[0012] In one embodiment of the present invention, the S parameters are related to the phase delay introduced by the filter, the amplification factor, the target frequency to be screened, the sampling frequency of the signal, and the phase of the input signal of the current target frequency to be screened; wherein, the phase delay, the amplification factor, and the target frequency to be screened introduced by the filter are related to the set first parameter, the second parameter, and the third parameter related to the zero point, and the first parameter and the second parameter related to the pole.

[0013] In one embodiment of the present invention, the selection device adopts a selection strategy to select the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit or the initial value calculation signal corresponding to the input signal of the current target frequency to be screened output by the initial value feedforward circuit to input into the second calculation circuit based on judging whether the input signal of the current target frequency to be screened corresponds to the output unstable signal; wherein the selection strategy includes: when the input signal of the current target frequency to be screened is the input signal of the target frequency to be screened for the first set number of times the filter is enabled each time, it is judged that the input signal of the current target frequency to be screened is the corresponding filter output unstable signal, and the initial value calculation signal corresponding to the input signal of the current target frequency to be screened is selected to be input into the second calculation circuit; when the input signal of the current target frequency to be screened is not the input signal of the target frequency to be screened for the first set number of times the filter is enabled each time, it is judged that the input signal of the current target frequency to be screened is not the corresponding filter output unstable signal, and the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit is selected to be input into the second calculation circuit.

[0014] In one embodiment of the present invention, the set number is no less than 3.

[0015] In one embodiment of the present invention, the total calculation circuit is composed of an adder; the total calculation circuit includes: a second adder; wherein the second adder is connected to the first adder, the fourth multiplier and the fifth multiplier; the first calculation signal output by the first adder, the second calculation signal output by the fourth multiplier and the second calculation signal output by the fifth multiplier are input to the second adder for calculation to obtain an output signal corresponding to the input signal of the current target frequency to be screened.

[0016] In one embodiment of the present invention, the selection device is a two-to-one multiplexer.

[0017] As described above, the present invention is an IIR digital filter that accelerates the stabilization time in engineering, and has the following beneficial effects: the present invention designs an initial value feedforward circuit in the IIR filter, and assigns the estimated result to the register in the filter as the initial value according to the sampling data of the corresponding filter output unstable data when the IIR filter circuit starts working, thereby reducing the distortion of the output signal after the IIR filter starts working, and reducing the time from the start-up to the stable operation of the IIR filter. In addition, the initial value feedforward circuit only includes simple multiplication and addition operations, and has relatively small impact on the area consumption and timing of the hardware circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of the logic structure of a classic second-order digital filter in an embodiment of the present invention.

[0019] Figure 2 Shown is a schematic diagram of a frequency response curve and a phase response curve of a classic second-order digital filter in an embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of the structure of an IIR digital filter for accelerating the settling time in engineering according to an embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the structure of an IIR digital filter for accelerating the settling time in engineering according to an embodiment of the present invention.

[0022] Figure 5 Shown is a schematic diagram of the fitting of an S-parameter curve in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0025] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0026] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0027] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0028] The present invention provides an IIR digital filter that accelerates the stabilization time in engineering. An initial value feedforward circuit is designed in the IIR filter. According to the sampling data of the corresponding filter output unstable data when the IIR filter circuit is started, the estimated result is assigned to the register in the filter as the initial value, thereby reducing the distortion of the output signal after the IIR filter is started, and reducing the time from the start to the stable operation of the IIR filter. In addition, the initial value feedforward circuit only includes simple multiplication and addition operations, and has relatively small impact on the area consumption and timing of the hardware circuit.

[0029] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0030] like Figure 3 A schematic diagram of the structure of an IIR digital filter for accelerating the settling time in engineering according to an embodiment of the present invention is shown.

[0031] The filter comprises:

[0032] A first calculation circuit 1, a second calculation circuit 2 and a total calculation circuit 3 composed of four groups of D flip-flops, five multipliers and two adders;

[0033] The filter further comprises: a selection device 4 and an initial value feedforward circuit 5 that uses S parameters for calculation;

[0034] The input signal x(n) of the current target frequency to be screened is sequentially input into the first calculation circuit 1 and the initial value feedforward circuit 5, and the first calculation circuit 1 and the initial value feedforward circuit 5 respectively output a first calculation signal and an initial value calculation signal corresponding to the input signal of the current target frequency to be screened;

[0035] The output signal y(n-1) corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit 3 or the initial value calculation signal corresponding to the input signal of the current target frequency to be screened output by the initial value feedforward circuit 5, which is selected by the selection device 4 based on whether the input signal of the current target frequency to be screened corresponds to the unstable signal output by the filter, is input into the second calculation circuit 2, and the second calculation circuit 2 outputs the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened; the first calculation signal, the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened are input into the total calculation circuit 3, and the total calculation circuit 3 outputs the output signal y(n) corresponding to the input signal of the current target frequency to be screened;

[0036] Among them, the output signal corresponding to the input signal of the current target frequency to be screened and the initial value calculation signal are input to the selection device 4 for selection, so that the output signal selected by the selection device 4 or the initial value calculation signal output by the initial value feedforward circuit 5 is input to the second calculation circuit 2 to output the second calculation signal corresponding to the input signal x(n+1) of the next target frequency to be screened.

[0037] In one embodiment, the first calculation circuit is composed of two groups of D flip-flops, three multipliers and an adder; wherein, Figure 4 , the first calculation circuit includes: a first D flip-flop 11, a second D flip-flop 12, a first multiplier 13, a second multiplier 14, a third multiplier 15 and a first adder 16;

[0038] And wherein, the Q port of the first D flip-flop 11 is connected to the initial value feedforward circuit 5, the first D flip-flop 11 and the D port of the second D flip-flop 12; the Q port of the second D flip-flop 12 is connected to the third multiplier 15; the first adder 16 is connected to the first multiplier 13, the second multiplier 14 and the third multiplier 15;

[0039] The input signal x(n) of the current target frequency to be screened is input into the first multiplier 13 for calculation based on the set first parameter b(0) related to the zero point, and a first calculation sub-signal is output; at the same time, the input signal x(n) of the current target frequency to be screened is input into the first D flip-flop 11 for delay, and the signal delayed by the first D flip-flop 11 is output to the second multiplier 14, the second D flip-flop 12 and the initial value feedforward circuit 5 respectively, the second multiplier 14 calculates and outputs the second calculation sub-signal based on the set second parameter b(1) related to the zero point, and the second D flip-flop 12 delays, and the third multiplier 15 calculates and outputs the third calculation sub-signal on the delayed signal output from the Q port of the second D flip-flop 12 based on the set third parameter b(2) related to the zero point; the first adder 16 calculates and obtains the first calculation signal based on the first calculation sub-signal, the second calculation sub-signal and the third calculation sub-signal.

[0040] In one embodiment, the second calculation circuit is composed of two groups of D flip-flops and two multipliers; wherein the second calculation circuit includes: a third D flip-flop 21, a fourth D flip-flop 22, a fourth multiplier 23 and a fifth multiplier 24;

[0041] And wherein, the D port of the third D flip-flop 21 is connected to the selection device, the Q port of the third D flip-flop 21 is connected to the fourth multiplier 23 and the D port of the fourth D flip-flop 22; the Q port of the fourth D flip-flop 22 is connected to the fifth multiplier 24;

[0042] The output signal y(n-1) corresponding to the input signal of the previous target frequency to be screened or the initial value calculation signal of the input signal of the current target frequency to be screened selected by the selection device is input into the third D flip-flop 21 for delay, and the signal delayed by the third D flip-flop 21 is input into the fourth multiplier 23 and the fourth D flip-flop 22 respectively, and the fourth multiplier 23 calculates based on the set first parameter a(1) related to the pole to obtain the second calculation signal, and the fourth D flip-flop 22 delays, and the fifth multiplier 24 calculates based on the set second parameter a(2) related to the pole to obtain the third calculation signal.

[0043] In one embodiment, the total calculation circuit is composed of an adder; the total calculation circuit includes: a second adder 31; wherein the second adder 31 is connected to the first adder 16, the fourth multiplier 23 and the fifth multiplier 24; the first calculation signal output by the first adder 16, the second calculation signal output by the fourth multiplier 23 and the second calculation signal output by the fifth multiplier 24 are input to the second adder 31 for calculation to obtain the output signal y(n) corresponding to the input signal of the current target frequency to be screened.

[0044] In order to better describe the implementation of the initial value feedforward circuit, a specific description is now given in conjunction with the following embodiments.

[0045] First, the idea and principle of setting up the initial value feedforward circuit are explained. This scheme can quickly and roughly estimate the initial values ​​of the two D flip-flops mentioned earlier in engineering, so that their values ​​are close to the output of the IIR filter in the initial state, thereby reducing the time it takes for the IIR filter to enter a stable state.

[0046] Assume that the input signal of the target frequency to be screened is expressed as:

[0047] x=sin(θ); Formula (1)

[0048] Wherein, θ is the phase of the input signal of the target frequency to be screened;

[0049] The output signal after the IIR filter can be expressed as:

[0050]

[0051] in, is the phase delay introduced by the IIR filter, and A is the amplification factor.

[0052] The difference between the output signal and the input signal is calculated as:

[0053]

[0054] The difference between two adjacent input signals is calculated as:

[0055] x`=sin(θ)-sin(θ-τ); Formula (4)

[0056] Among them, τ represents the phase difference between two adjacent sampling points, and:

[0057]

[0058] Among them, f0 represents the target frequency to be screened, f s Indicates the sampling frequency.

[0059] Then calculate according to the following formula:

[0060]

[0061] Simplifying the above formula, we get:

[0062]

[0063] Therefore, the S parameter is related to the phase delay introduced by the filter, the amplification factor, the target frequency to be screened, the sampling frequency of the signal, and the phase of the input signal of the current target frequency to be screened; since the phase delay, the amplification factor, and the target frequency to be screened introduced by the filter are related to the set first parameter related to the zero point, the second parameter and the third parameter, and the first parameter and the second parameter related to the pole, they are fixed values; when the sampling frequency, the target frequency, and the coefficients of the IIR filter are configured, τ and The value of is a fixed value, and s is a function with θ as a variable.

[0064] When f0 is set to 10KHz, fs is set to 64KHz, and A is set to 1, after completing the IIR filter coefficient configuration, the shape of the s function can be as follows: Figure 5 As shown in the lower line (the upper line is the input signal with frequency f0), Figure 5 It can be seen that s is relatively flat in most areas, with extreme values ​​only appearing in some places (near 90 degrees and 270 degrees). Fitting the s curve can approximate a horizontal line, so in engineering classes, s is roughly regarded as a constant.

[0065] Therefore, the output value of the IIR filter can be estimated as:

[0066] y≈s*x`+x; Formula (8)

[0067] According to the above theoretical analysis, an initial value feedforward circuit with s-parameter configuration can be added to the IIR filter circuit.

[0068] In one embodiment, the initial value feedforward circuit is composed of two adders and a multiplier.

[0069] In one embodiment, if Figure 4 , the initial value feedforward circuit comprises: a first initial feedforward adder 51, a second initial feedforward adder 52 and an initial feedforward multiplier 53;

[0070] And wherein, the second initial feedforward adder 52 is connected to the first initial feedforward adder 51 and the initial feedforward multiplier 53 respectively; the first initial feedforward adder 51 is connected to the Q port of the first D flip-flop 11;

[0071] The input signal x(n) of the current target frequency to be screened and the signal delayed by the first D flip-flop 11 are input into the first initial feedforward adder 51 for calculation to obtain the fourth calculation sub-signal; the fourth calculation sub-signal is input into the initial feedforward multiplier 53 for calculation based on the S parameter to obtain the fifth calculation sub-signal; the input signal of the current target frequency to be screened and the fifth calculation sub-signal are input into the second initial feedforward adder 52 for calculation to obtain the initial value calculation signal.

[0072] In one embodiment, the S parameters are related to the phase delay introduced by the filter, the amplification factor, the target frequency to be screened, the sampling frequency of the signal, and the phase of the input signal of the current target frequency to be screened; wherein, the phase delay, the amplification factor, and the target frequency to be screened introduced by the filter are related to the set first parameter related to the zero point, the second parameter and the third parameter, and the first parameter and the second parameter related to the pole.

[0073] In order to better describe the implementation of the selection device, a specific description is now given in conjunction with the following embodiments.

[0074] In one embodiment, the selection device adopts a selection strategy based on judging whether the input signal of the current target frequency to be screened corresponds to the output unstable signal to select the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit or the initial value calculation signal corresponding to the input signal of the current target frequency to be screened output by the initial value feedforward circuit to be input into the second calculation circuit;

[0075] The selection strategy includes:

[0076] When the input signal of the current target frequency to be screened is the input signal of the target frequency to be screened for the first set number of times each filter is enabled, it is determined that the input signal of the current target frequency to be screened is an unstable signal output by the corresponding filter, and the initial value calculation signal corresponding to the input signal of the current target frequency to be screened is selected and input into the second calculation circuit;

[0077] When the input signal of the current target frequency to be screened is not the input signal of the target frequency to be screened that is set in the previous number at the beginning of each filter enabling, it is determined that the input signal of the current target frequency to be screened is not the corresponding filter output unstable signal, and the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit is selected and input into the second calculation circuit.

[0078] In a specific embodiment, the set number is no less than 3.

[0079] For example, if Figure 4 , an initial value feedforward circuit in the dotted box is added above the original IIR filter, which consists of a multiplier and two adders. When the first three data are input each time the IIR filter is enabled, the calculated initial value is stored in the two D flip-flops 21 and 22, and then the IIR filter circuit enters the normal working state.

[0080] In a specific embodiment, the selection device is a two-to-one multiplexer.

[0081] In summary, the IIR digital filter of the present invention accelerates the stabilization time in engineering. The present invention designs an initial value feedforward circuit in the IIR filter, and assigns the estimated result to the register in the filter as the initial value according to the sampling data of the corresponding filter output unstable data when the IIR filter circuit starts working, thereby reducing the distortion of the output signal after the IIR filter is started, and reducing the time from the start to the stable operation of the IIR filter. In addition, the initial value feedforward circuit only includes simple multiplication and addition operations, and has relatively small impact on the area consumption and timing of the hardware circuit. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An IIR digital filter with accelerated settling time in engineering, characterized in that: The filter comprises: A first calculation circuit, a second calculation circuit and a total calculation circuit composed of four groups of D flip-flops, five multipliers and two adders; The first calculation circuit is composed of two groups of D flip-flops, three multipliers and an adder; wherein the first calculation circuit includes: a first D flip-flop, a second D flip-flop, a first multiplier, a second multiplier, a third multiplier and a first adder; and wherein the Q port of the first D flip-flop is connected to the initial value feedforward circuit, the first D flip-flop and the D port of the second D flip-flop; the Q port of the second D flip-flop is connected to the third multiplier; the first adder is connected to the first multiplier, the second multiplier and the third multiplier; The second calculation circuit is composed of two groups of D flip-flops and two multipliers; wherein the second calculation circuit includes: a third D flip-flop, a fourth D flip-flop, a fourth multiplier and a fifth multiplier; and wherein the D port of the third D flip-flop is connected to the selection device, the Q port of the third D flip-flop is connected to the fourth multiplier and the D port of the fourth D flip-flop; the Q port of the fourth D flip-flop is connected to the fifth multiplier; The total calculation circuit is composed of an adder; the total calculation circuit includes: a second adder; wherein the second adder is connected to the first adder, the fourth multiplier and the fifth multiplier; The filter also includes: a selection device and an initial value feedforward circuit that uses S parameters for calculation; The initial value feedforward circuit is composed of two adders and a multiplier, and the initial value feedforward circuit includes: a first initial feedforward adder, a second initial feedforward adder and an initial feedforward multiplier; and wherein the second initial feedforward adder is connected to the first initial feedforward adder and the initial feedforward multiplier respectively; the first initial feedforward adder is connected to the Q port of the first D flip-flop; The input signal of the current target frequency to be screened is sequentially input into the first calculation circuit and the initial value feedforward circuit, and the first calculation circuit and the initial value feedforward circuit respectively output a first calculation signal and an initial value calculation signal corresponding to the input signal of the current target frequency to be screened; The output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit or the initial value calculation signal corresponding to the input signal of the current target frequency to be screened output by the initial value feedforward circuit, which is selected by the selection device based on whether the input signal of the current target frequency to be screened corresponds to the unstable signal output by the filter, is input into the second calculation circuit, and the second calculation circuit outputs the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened; the first calculation signal, the second calculation signal and the third calculation signal corresponding to the input signal of the current target frequency to be screened are input into the total calculation circuit, and the total calculation circuit outputs the output signal corresponding to the input signal of the current target frequency to be screened; The output signal and the initial value calculation signal corresponding to the input signal of the current target frequency to be screened are input to the selection device for selection, so that the output signal selected by the selection device or the initial value calculation signal output by the initial value feedforward circuit is input to the second calculation circuit to output the second calculation signal corresponding to the input signal of the next target frequency to be screened; The selection device adopts a selection strategy to select the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit or the initial value calculation signal corresponding to the input signal of the current target frequency to be screened output by the initial value feedforward circuit based on judging whether the input signal of the current target frequency to be screened corresponds to the output unstable signal, and inputs it into the second calculation circuit; wherein the selection strategy includes: When the input signal of the current target frequency to be screened is the input signal of the target frequency to be screened for the first set number of times each filter is enabled, it is determined that the input signal of the current target frequency to be screened is an unstable signal output by the corresponding filter, and the initial value calculation signal corresponding to the input signal of the current target frequency to be screened is selected and input into the second calculation circuit; When the input signal of the current target frequency to be screened is not the input signal of the target frequency to be screened that is set in the previous number at the beginning of each filter enabling, it is determined that the input signal of the current target frequency to be screened is not the corresponding filter output unstable signal, and the output signal corresponding to the input signal of the previous target frequency to be screened output by the total calculation circuit is selected and input into the second calculation circuit.

2. The IIR digital filter with accelerated settling time in engineering according to claim 1, characterized in that: The input signal of the current target frequency to be screened is input into the first multiplier for calculation based on the set first parameter related to the zero point, and a first calculation sub-signal is output; at the same time, the input signal of the current target frequency to be screened is input into the first D flip-flop for delay, and the signal delayed by the first D flip-flop is output to the second multiplier, the second D flip-flop and the initial value feedforward circuit respectively, the second multiplier calculates and outputs the second calculation sub-signal based on the set second parameter related to the zero point, and the second D flip-flop is delayed, and the third multiplier calculates and outputs the delayed signal output from the Q port of the second D flip-flop based on the set third parameter related to the zero point; the first adder calculates and obtains the first calculation signal based on the first calculation sub-signal, the second calculation sub-signal and the third calculation sub-signal.

3. The IIR digital filter with accelerated settling time in engineering according to claim 2, characterized in that: The output signal corresponding to the input signal of the previous target frequency to be screened selected by the selection device or the initial value calculation signal of the input signal corresponding to the current target frequency to be screened is input into the third D flip-flop for delay, and the signal delayed by the third D flip-flop is respectively input into the fourth multiplier and the fourth D flip-flop, and the fourth multiplier calculates based on the set first parameter related to the pole to obtain the second calculation signal, and the fourth D flip-flop is delayed, and the fifth multiplier calculates based on the set second parameter related to the pole to obtain the third calculation signal.

4. The IIR digital filter with accelerated settling time in engineering according to claim 1, characterized in that: Inputting the input signal of the current target frequency to be screened and the signal delayed by the first D flip-flop into the first initial feedforward adder for calculation to obtain a fourth calculation sub-signal; Inputting the fourth calculation sub-signal into the initial feedforward multiplier to perform calculation based on the S parameter to obtain a fifth calculation sub-signal; The input signal of the current target frequency to be screened and the fifth calculation sub-signal are input to the second initial feedforward adder for calculation to obtain an initial value calculation signal.

5. The IIR digital filter with accelerated settling time in engineering according to claim 4, characterized in that: The S parameters are related to the phase delay introduced by the filter, the amplification factor, the target frequency to be screened, the sampling frequency of the signal, and the phase of the input signal of the current target frequency to be screened; wherein, the phase delay, the amplification factor, and the target frequency to be screened introduced by the filter are related to the set first parameter related to the zero point, the second parameter and the third parameter, and the first parameter and the second parameter related to the pole.

6. The IIR digital filter with accelerated settling time in engineering according to claim 1, characterized in that: The set number is no less than 3.

7. The IIR digital filter with accelerated settling time in engineering according to claim 4, characterized in that: The first calculation signal output by the first adder, the second calculation signal output by the fourth multiplier and the second calculation signal output by the fifth multiplier are input to the second adder for calculation to obtain an output signal corresponding to the input signal of the current target frequency to be screened.

8. The IIR digital filter with accelerated settling time in engineering according to claim 1, characterized in that: The selection device is a two-to-one multiplexer.

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